CA1260135A - Deriving frame interval signals - Google Patents
Deriving frame interval signalsInfo
- Publication number
- CA1260135A CA1260135A CA000507483A CA507483A CA1260135A CA 1260135 A CA1260135 A CA 1260135A CA 000507483 A CA000507483 A CA 000507483A CA 507483 A CA507483 A CA 507483A CA 1260135 A CA1260135 A CA 1260135A
- Authority
- CA
- Canada
- Prior art keywords
- line
- outputs
- signals
- errors
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
- H04N7/083—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical and the horizontal blanking interval, e.g. MAC data signals
Abstract
ABSTRACT:
Deriving frame internal signals.
Serial data from a C-MAC, D-MAC or D2-MAC
television signal is applied over line (1) to a serial data to error conversion unit (2) which produces a 3-bit error signal when the applied data is compared with a W1 sync. word. The error signal is applied to comparators (6 and 7) whose other inputs receive a maximum or minimum error dependent signal to produce an output when the number of errors lies within certain requirements. These outputs are latched in a 2-bit latch (8) to produce line pulses on receipt of an acceptable sync word at an appropriate time, the outputs of the latch (8) being applied to two shift registers (9 and 10). The shift registers (9 and 10) produce outputs P1, P2, P3 and P4 over four line periods with the P3, P4 outputs of shift register (10) and the P1, P2 outputs of shift register (9) being applied to respective inputs of a first AND-gate (11) whilst the remaining outputs are applied to respective inputs of a second AND-gate (12) which gates produce an output when there is coincidence alternately at the end of each frame period. The outputs are applied to respective inputs of an OR-gate (13) to derive a frame flywheel and sync.
acquisition unit (14) at frame frequency.
Deriving frame internal signals.
Serial data from a C-MAC, D-MAC or D2-MAC
television signal is applied over line (1) to a serial data to error conversion unit (2) which produces a 3-bit error signal when the applied data is compared with a W1 sync. word. The error signal is applied to comparators (6 and 7) whose other inputs receive a maximum or minimum error dependent signal to produce an output when the number of errors lies within certain requirements. These outputs are latched in a 2-bit latch (8) to produce line pulses on receipt of an acceptable sync word at an appropriate time, the outputs of the latch (8) being applied to two shift registers (9 and 10). The shift registers (9 and 10) produce outputs P1, P2, P3 and P4 over four line periods with the P3, P4 outputs of shift register (10) and the P1, P2 outputs of shift register (9) being applied to respective inputs of a first AND-gate (11) whilst the remaining outputs are applied to respective inputs of a second AND-gate (12) which gates produce an output when there is coincidence alternately at the end of each frame period. The outputs are applied to respective inputs of an OR-gate (13) to derive a frame flywheel and sync.
acquisition unit (14) at frame frequency.
Description
Deriving frame interval signals.
The invention relates to a method of deriving signals at frame intervals from a received television signal whlch has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television siynal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said method comprising the steps of comparing portions of each line period with one of the digital words and producing therefrom an error signal representing the number of bits in said portions which differ from said one digital word and using said error signals to produce signals at frame intervals. The inven~ion also relates to apparatus for use with this method.
The European Broadcasting Union documents "Television Standards for the Broadcasting Satellite Service Specification of the C-MAC/Packet System" SPB 284, 3rd revised edition dated December 198~, and "Methods of Conveying C-MAC/Packet Signals in Small and Large Community Antenna and Cable Network Installations"
SPB 352, dated December 1984, and both of which are incorporated therein by way of reference, describe three forms of television signal which are referred to as C-MAC, D-MAC and D2-MAC. For synchronising purposes each line of these s~gnals carries one of the two digital sync. words W1 or W2 where W1 is of the form 001011 and W2 is the inverse, namely 110100. For a system having a frame comprising 625 lines, the sync. words alternate line-by-line for lines 1 to 621 whilst lines 622 and 623 both convey one sync. word whilst lines 624 and 625 both convey the other sync.
-`` 3L;2~35i word, this change in sync. word pattern indicating the end of a frame. For an odd frame line 1, and hence line 621 will convey the W2 sync. word whilst lines 622 and 623 will convey the Wl sync. word and lines 624 and 625 the ~2 sync. word. This situa-tion is the inve~se for even frames such that line 1 conveys the Wl sync. word as will lines 624 and 625 whilst lines 622 and 623 will convey the ~2 sync. word. Published PCT Patent Application W084/022~2 published June 7, 19~4 (Independent Broadcasting Authority) describes apparatus for obtaining line and frame synchronising signals from alternating digital sync. words but this is based on an earlier version of a specification for a C-MAC
television signal where the two sync. words each had 7 bits whilst the pairs of lines using the same sync. words straddled the boundary between odd and even frames.
It is an object of the present invention to provide a different method and apparatus for obtaining signals at frame intervals which effectively requires less logic.
The present invention provides a method of deriving signals at frame intervals from a received television signal which ~0 has two predetermined digital words which alterna-te line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said method comprising the steps of comparing portions of each line period with one of the digital words and producing therefrom an error signal representing the number of bits in said portions which differ from said one digital word and using said error signals to produce ~2~ 3S
signals at frame intervals, characterized in that in order to produce said signals at frame intervals from said error signals the method further comprises comparing said error si~nals with a maximum number of permitted errors for each digital word and produciny therefrom first and second detection signals for said first and second digital words when said errors are equal to or less than that permitted during a specified time in each line period, recording the resulting first and second detection signals over ~our line periods and de~ecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce said signals at frame intervals.
The comparison of the error signal with a maximum of permitted errors for each digital word may be achieved by comparing the error signal with a maxlmum number of permitted errors for the said one digital word and with a maximum number of permit~ed errors for the other digital word, the latter being performed as a comparison with a minimum number of errors for the said one digital word. This avoids the need for the inversion of certain error signals.
The comparisons may be performed throughout each line period to produce indicatlons that the maximum or less errors are present in the two digital words and which are then latched at said specified time in a line period when a true digital word should be present.
The invention also provides apparatus for deriviny signals at frame intervals from a received television signal which has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said apparatus comprising means for comparing portions of each line period received in said television signal with one of said digital words to produce an error signal representing the number of bits in said portions whi~h differ from said one digital word, characterized in that said apparatus further comprises means for comparing said error signal with a maximum number of permitted ~ errors for one of said digital words and with a maximum number of : permitted errors for the other digital word and for producing a first detection signal if at a specified time in a line period the number of errors is equal to or less than that for said one diyital word and a second detection signal if at said specified time the number of errors is equal to or less than that for said other digital word, means for recording said first and second detection signals over four line periods, and means for detecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce signals at frame intervals.
The means for comparing said error signal with a maximum number of permikted errors of the digital words may 3a ~2~ 3S
PHB.33-166 4 25.2.86 comprise first and second comparators whose respective first inputs receive the error signal specifying the number of errors when compared with said one digital word, the second input of said first comparator receiving a number corresponding to the maximum number of permitted errors in said one digital word and whose output produces said first detection signal, the second input of the second comparator receiving a number corresponding -to a minimum number of permitted errors in said one digital word which corresponds to the maximum number of permitted errors in the other digital word, the output of the second comparator producing the second detection signal.
The first and second detection signals may be applied to respective inputs of a 2-bit latch which is enabled at said specified time in a line period to produce first and second latched outputs which are respectively applied to first and second shift registers each of which is capable of producing outputs over four line periods.
The outputs for first and second line periods of said first shift register and for third and fourth line periods of said second shift register may be applied to respective inputs of a first AND gate whilst the outputs for third and fourth line periods of said first shift register and for first and second line periods of said second shift register are applied to respective inputs of a second AND-gate, the first and second AND-gates alternately producing output signals at frame intervals. The first and second AND-gates may be applied to respective inputs of an OR-gate whose output is applied to control the operation of a frame frequency synchronising circuit.
The above and other features of the invention will be more readily understood from the following description and the accompanying drawings in which:-Figure 1 is a block diagram of apparatus for use with the present invention, and ~ igures 2 and 3 are timing diagrams for theoperation of the apparatus of Figure 1.
~2~ 35 PHB.33-166 5 25.2.86 In Figure 1 the reference 1 indicates a serial data line over which, in the case of the C-M~C television system, the whole of the C-MAC television signal is applied in serial data form and which may be obtained from a re-ceived C-MAC transmission after limiting and demodulation in a 2-4 PSK demodulator stage (not shown). The serial binary data present on the line 1 will contain line-by_line the sync. word, the data burst and in addition what might be termed pseudo-random data due to the limited analogue compressed vision components. This serial data is applied to a serial datato an error conversion unit 2 in which the applied data is compared with one of the sync. words (in this case W1 - 001011) and an error signal produced as a 3-bit binary number which indicates -the number of errors present when six bits of the incoming serial data are compared with the fixed and chosen 6 bit sync. word. In the arrangement shown the unit 2 comprises a series-to-parallel converter in the form of a shift register 3 where the serial data from the line 1 is applied to a data input D which is clocked through the shift register under -the control of a 20.25 MHz clock signal applied to a clock input C (which corresponds to the bit rate of the data in the C-MAC signal) to produce at the parallel outputs P a 6 bit data word which can change at the data bit rate. The changing 6-bit data is applied to the address input A of a 6l~ x 3 bit read only memory (ROM) 4 to produce at its output E the 3-bit error signal which represents the number of differences betwcen that address and the chosen sync. word and again can change at the da-ta bit rate. This error signal is applied to a line sync. word detection and acquisition unit 5 which from the error signal produces line synchronising signals for use in a television receiver in which the present arrangement may be included and may be of a number of forms including those shown and described in published PC~
patent application w08l~/02242.
The 3-bit error signal is additionally applied to respective firs-t inputs X of a W1 comparator 6 and a W2 3~
PHB.33-166 6 25.2.86 comparator 7. The second inpu-t Y of the Wl comparator 6 receives in parallel binary form a number corresponding to the maximum number of tolerable errors that may be present in a 6-bit word when compared with the Wl sync. word.
The best value for this has been found to be two (binary 010) but a lower number of errors may be allowed during the initial lock-up procedure and a higher number thereafter.
The second input Y of the W2 comparator 7 also receives a number in parallel binary forms for comparing the number of tolerable errors in a W2 sync. word with a 6-bit word but as the error conversion unit acts on Wl sync. words only (which is the inverse of the W2 sync. word) the parallel binary number applied to the second input of the W2 comparator 7 corresponds to the minimum number of tolerable errors that may be present in a 6-bit word when compared with the ~1 sync. word. The best value for this has been found to be four (binary 100) but it may be varied as described in relation to the Wl comparator. The W1 comparator 6 only produces alogic '1~ outpu-t on each occasion when the 20 number of errors at its first input X is less than or equal to 2 and similarly the W2 comparator 7 only produces a logic '1~ output on each occasion when the number of errors at its first input X is greater than or equal to L~.
The outputs from the Wl and W2 comparators 6 and 7 form line sync. word detection signals which are applied to respective inputs of a 2-bit latch 8 whose enable input EN receives at line rate a pulse one bit (50nS) wide from the line sync. word unit 5, -this pulse appearing (ignoring transmission delays) such that it coincides with the last bit of each true line sync. word present on the serial data line 1 at which time the output of the unit 2 indicates the number of errors in that sync. word (W1 or W2).
The latch 8 has two outputs Q1 and Q2 respectively asso-ciated with the outputs of the W1 and W2 comparators 6 and 7, the output Q1 la-tching to the same state as the output from W1 compara-tor 6 on the occurrence of the enable pulse.
The Q2 output si~ilarly latches to -thesame ]ogic state as '~2~ 3S
PHB.33-166 7 24.2.86 the output of the W2 cornparator 7 Thus in the presence of a true W1 line sync. word at the input line 1 which has two or less errors in it the Q1 output latches to logic ~1~ and stays in that state until at a line interval or intervals later the number of errors is greater than 2 i.e. on the appearance of a true W2 sync. word or a W1 sync.
word which has more than two errors. In a similar manner the Q2 OUtp1lt latches to the logic ~1~ state in the presence of a true W2 sync. word with two or less errors and stays 10 in that sta-te until a true W1 s~nc. word or a corrupted W2 sync. word appears.
The Q1 and Q2 outputs from the latch ~ are applied to respective data inputs D of 4-bit shift registers 9 and 10 in which the logic states present at these inputs during 15 consecutive line periods are shifted through the shift register at line rate under the control of line frequency cloc~ pulses applied to clock inputs C from the line sync.
word unit 5 to successively appear one line apart at outputs P1, P2, P3, P4. The outputs P1, P2 of shift register 20 9 and the outputs P3, P4 of shift regis-ter 10 are applied to respective inputs of a first AND-gate 11 whilst the outputs P3, P4 of shift register 9 and the outputs P1, P2 of shift register 10 are applied to respective inputs of a second AND~gate 12. At the boundary between frames the 25 alternate W1, W2 line sync. word pattern is changed such that for lines 622, 623 9 624 and 625 in odd frames the sync. word pattern is W1, W1, W2, W2 whilst the pattern for the corresponding lines in even frames is W2, W2, W1, Wl o Thus at the end of an odd frame the logic states of the 30 outputs P1, P2, P3, P4 of shift register 9 will be respectively O, O~ 1. 1, whilst those for the corresponding outputs of shift register 10 will be respectively, 1, 1, O,O.
Under these conditions the output of AND-gate 11 will be in the logic state 'O' whilst the output of the AND-gate 12 35 will be inthe logic state '1' for a line period coincident with the first line of the following even frame. At the end of an even frame -the logic states for the outputs of the P~B.33-'166 8 25 2.86 shift registers 9 and 10 will be opposite -to -that at the end of an odd frame, namely, for shift register 9 the out-puts Pl, P2, P3, P4 will be respectively 1, 1, 0~ 0 whilst for shift register 10 the corresponding outputs will be respectively 0, 0~ 1,'1. A-t such time the output of ~ND-gate 11 will go to -the logic s-tate ~1' for a line period coincident with the first line of the following odd frame, whilst that of AND-gate 12 will remain in the logic state ~0~. The OlltpUts of the AND-gates 11 and 12 which may 'be respectively used to signal the end of an even or odd frame, are applied to respective inputs of an OR-gate 13 which gives the logic state '1' at the end of each frame period which is applied to the input of a frame flywheel and sync. acquisition circuit 14 for the generation of frame lS sync. pulses for use within the receiver.
The operation of the arrangement of Figure 1 will be betteY~ seen from the diagrams in Figures 2 and 3.
Figure 2a shows the input on line 1 containing data in serial form, this figure showing data present in two line 20 periods and in particular around the start of the line periods.Of -the two lines shown that on the left contains the Wl sync. word (001011) whils-t that on the right contains the W2 sync. word (110100). The outputs from the Wl and W2 comparators 6 and 7 are shown respectively in Figures 2b and 2c for the receipt of sync. words with 2 or less errors~
that from comparator 6 producing a single 50nS pulse concident with the last bit of a Wl sync. word whilst that from comparator 7 produces a comparable pulse coincident with the last bit of a W2 sync. word. This output may also contain pulses at other times (not shown) when false line sync. words are detected in the serial data on line 1.
Figure 2d shows the line rate 50nS pulses applied to -the enable input EN of the latch 8 whilst the result' of the latching action to produce pulses of line length is shown in Figures 2e and 2f where the Figure 2e shows the output Ql produced as a result of a true Wl sync. word and Figure 2f the output Q2 as a result of a true W2 sync. word. These Ql ~Z~ 35 PHB.33-166 9 25.2.~6 and Q2 outputs are shown over a ten line period in FigureS3b and 3c respectively~ the line numbers being indicated in Figure 3a from which it will be seen that the ten line periods are the five before the end and the five following -the commencement of a frame. The outputs shown in Figure 3b and 3c are for the situation which occurs at -the end of an odd frame where lines 622, 6239 62L~ and 625 respectively contain the sync. word sequence W1, W1, W2, W2. At the end of an even frame this sequence is W2, W2, W1, W1 and $he lO output from Q1 would then be that of Figure 3c and that from Q2 as in Figure 3b, as indicated by the legends in brackets on the left of this Figure. The line rate clock pulses applied to the clock inputs C of shift registers 9 and 10 are shown in Figure 3d whilst the time shifted outputs P1 7 15 P2 9 P3 and P4 from shift register 9 are respectively shown in Figures 3e, 3-f, 3g and 3h and the corresponding outputs from shift register 10 are respectively shown in Figures 3i, 3j, 3k and 31. The outputs shown in Figures 3e to 31 are for the end of an odd frame whilst those for the end of an 20 even frame are as indicated in the legends in brackets on the left hand side of these Figures. For an odd frame the only time that the outputs P3~ P4 of shift register 9 and the outputs P1, P2 of shift register 10 are coincident with logic '1' is during line 1 of the following even frame 25 whilst for an even frame the outputs P1, P2, of shift register 9 and P3, P4 of shift register 10 are coincident with logic '1' during line 1 of the following odd frame.
These two conditions are respectively indicated in Figures 3m and 3n as the outputs of AND-gates 12 and 11 which each 30 produce an output once every two frames. These outputs are applied to the OR-gate 13 to produce an output during each frame as shown in Figure 30.
In the above description the serial data applied to the input line 1 is that of a C-MAC television signal.
35 The operation would be exactly the same if the applied data was from a D-MAC television signal. If the applied data were however derived from a D2-MAC television ~Z~ 3~;
PHB.33-166 10 24.2.86 signal in which the data rate is half that of a C-MAC
signal then the manner of operation would be the same save that the applied data on line l, the error signal at the output E of ROM 4 and the outputs of the comparators 6 and 7 would be at the bi-t rate of 10.125 Mbits/s with a pulse width of approximately 100nS and the line rate clock pulse to the enable input EN of latch 8 could have this pulse duration.
.
The invention relates to a method of deriving signals at frame intervals from a received television signal whlch has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television siynal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said method comprising the steps of comparing portions of each line period with one of the digital words and producing therefrom an error signal representing the number of bits in said portions which differ from said one digital word and using said error signals to produce signals at frame intervals. The inven~ion also relates to apparatus for use with this method.
The European Broadcasting Union documents "Television Standards for the Broadcasting Satellite Service Specification of the C-MAC/Packet System" SPB 284, 3rd revised edition dated December 198~, and "Methods of Conveying C-MAC/Packet Signals in Small and Large Community Antenna and Cable Network Installations"
SPB 352, dated December 1984, and both of which are incorporated therein by way of reference, describe three forms of television signal which are referred to as C-MAC, D-MAC and D2-MAC. For synchronising purposes each line of these s~gnals carries one of the two digital sync. words W1 or W2 where W1 is of the form 001011 and W2 is the inverse, namely 110100. For a system having a frame comprising 625 lines, the sync. words alternate line-by-line for lines 1 to 621 whilst lines 622 and 623 both convey one sync. word whilst lines 624 and 625 both convey the other sync.
-`` 3L;2~35i word, this change in sync. word pattern indicating the end of a frame. For an odd frame line 1, and hence line 621 will convey the W2 sync. word whilst lines 622 and 623 will convey the Wl sync. word and lines 624 and 625 the ~2 sync. word. This situa-tion is the inve~se for even frames such that line 1 conveys the Wl sync. word as will lines 624 and 625 whilst lines 622 and 623 will convey the ~2 sync. word. Published PCT Patent Application W084/022~2 published June 7, 19~4 (Independent Broadcasting Authority) describes apparatus for obtaining line and frame synchronising signals from alternating digital sync. words but this is based on an earlier version of a specification for a C-MAC
television signal where the two sync. words each had 7 bits whilst the pairs of lines using the same sync. words straddled the boundary between odd and even frames.
It is an object of the present invention to provide a different method and apparatus for obtaining signals at frame intervals which effectively requires less logic.
The present invention provides a method of deriving signals at frame intervals from a received television signal which ~0 has two predetermined digital words which alterna-te line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said method comprising the steps of comparing portions of each line period with one of the digital words and producing therefrom an error signal representing the number of bits in said portions which differ from said one digital word and using said error signals to produce ~2~ 3S
signals at frame intervals, characterized in that in order to produce said signals at frame intervals from said error signals the method further comprises comparing said error si~nals with a maximum number of permitted errors for each digital word and produciny therefrom first and second detection signals for said first and second digital words when said errors are equal to or less than that permitted during a specified time in each line period, recording the resulting first and second detection signals over ~our line periods and de~ecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce said signals at frame intervals.
The comparison of the error signal with a maximum of permitted errors for each digital word may be achieved by comparing the error signal with a maxlmum number of permitted errors for the said one digital word and with a maximum number of permit~ed errors for the other digital word, the latter being performed as a comparison with a minimum number of errors for the said one digital word. This avoids the need for the inversion of certain error signals.
The comparisons may be performed throughout each line period to produce indicatlons that the maximum or less errors are present in the two digital words and which are then latched at said specified time in a line period when a true digital word should be present.
The invention also provides apparatus for deriviny signals at frame intervals from a received television signal which has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said apparatus comprising means for comparing portions of each line period received in said television signal with one of said digital words to produce an error signal representing the number of bits in said portions whi~h differ from said one digital word, characterized in that said apparatus further comprises means for comparing said error signal with a maximum number of permitted ~ errors for one of said digital words and with a maximum number of : permitted errors for the other digital word and for producing a first detection signal if at a specified time in a line period the number of errors is equal to or less than that for said one diyital word and a second detection signal if at said specified time the number of errors is equal to or less than that for said other digital word, means for recording said first and second detection signals over four line periods, and means for detecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce signals at frame intervals.
The means for comparing said error signal with a maximum number of permikted errors of the digital words may 3a ~2~ 3S
PHB.33-166 4 25.2.86 comprise first and second comparators whose respective first inputs receive the error signal specifying the number of errors when compared with said one digital word, the second input of said first comparator receiving a number corresponding to the maximum number of permitted errors in said one digital word and whose output produces said first detection signal, the second input of the second comparator receiving a number corresponding -to a minimum number of permitted errors in said one digital word which corresponds to the maximum number of permitted errors in the other digital word, the output of the second comparator producing the second detection signal.
The first and second detection signals may be applied to respective inputs of a 2-bit latch which is enabled at said specified time in a line period to produce first and second latched outputs which are respectively applied to first and second shift registers each of which is capable of producing outputs over four line periods.
The outputs for first and second line periods of said first shift register and for third and fourth line periods of said second shift register may be applied to respective inputs of a first AND gate whilst the outputs for third and fourth line periods of said first shift register and for first and second line periods of said second shift register are applied to respective inputs of a second AND-gate, the first and second AND-gates alternately producing output signals at frame intervals. The first and second AND-gates may be applied to respective inputs of an OR-gate whose output is applied to control the operation of a frame frequency synchronising circuit.
The above and other features of the invention will be more readily understood from the following description and the accompanying drawings in which:-Figure 1 is a block diagram of apparatus for use with the present invention, and ~ igures 2 and 3 are timing diagrams for theoperation of the apparatus of Figure 1.
~2~ 35 PHB.33-166 5 25.2.86 In Figure 1 the reference 1 indicates a serial data line over which, in the case of the C-M~C television system, the whole of the C-MAC television signal is applied in serial data form and which may be obtained from a re-ceived C-MAC transmission after limiting and demodulation in a 2-4 PSK demodulator stage (not shown). The serial binary data present on the line 1 will contain line-by_line the sync. word, the data burst and in addition what might be termed pseudo-random data due to the limited analogue compressed vision components. This serial data is applied to a serial datato an error conversion unit 2 in which the applied data is compared with one of the sync. words (in this case W1 - 001011) and an error signal produced as a 3-bit binary number which indicates -the number of errors present when six bits of the incoming serial data are compared with the fixed and chosen 6 bit sync. word. In the arrangement shown the unit 2 comprises a series-to-parallel converter in the form of a shift register 3 where the serial data from the line 1 is applied to a data input D which is clocked through the shift register under -the control of a 20.25 MHz clock signal applied to a clock input C (which corresponds to the bit rate of the data in the C-MAC signal) to produce at the parallel outputs P a 6 bit data word which can change at the data bit rate. The changing 6-bit data is applied to the address input A of a 6l~ x 3 bit read only memory (ROM) 4 to produce at its output E the 3-bit error signal which represents the number of differences betwcen that address and the chosen sync. word and again can change at the da-ta bit rate. This error signal is applied to a line sync. word detection and acquisition unit 5 which from the error signal produces line synchronising signals for use in a television receiver in which the present arrangement may be included and may be of a number of forms including those shown and described in published PC~
patent application w08l~/02242.
The 3-bit error signal is additionally applied to respective firs-t inputs X of a W1 comparator 6 and a W2 3~
PHB.33-166 6 25.2.86 comparator 7. The second inpu-t Y of the Wl comparator 6 receives in parallel binary form a number corresponding to the maximum number of tolerable errors that may be present in a 6-bit word when compared with the Wl sync. word.
The best value for this has been found to be two (binary 010) but a lower number of errors may be allowed during the initial lock-up procedure and a higher number thereafter.
The second input Y of the W2 comparator 7 also receives a number in parallel binary forms for comparing the number of tolerable errors in a W2 sync. word with a 6-bit word but as the error conversion unit acts on Wl sync. words only (which is the inverse of the W2 sync. word) the parallel binary number applied to the second input of the W2 comparator 7 corresponds to the minimum number of tolerable errors that may be present in a 6-bit word when compared with the ~1 sync. word. The best value for this has been found to be four (binary 100) but it may be varied as described in relation to the Wl comparator. The W1 comparator 6 only produces alogic '1~ outpu-t on each occasion when the 20 number of errors at its first input X is less than or equal to 2 and similarly the W2 comparator 7 only produces a logic '1~ output on each occasion when the number of errors at its first input X is greater than or equal to L~.
The outputs from the Wl and W2 comparators 6 and 7 form line sync. word detection signals which are applied to respective inputs of a 2-bit latch 8 whose enable input EN receives at line rate a pulse one bit (50nS) wide from the line sync. word unit 5, -this pulse appearing (ignoring transmission delays) such that it coincides with the last bit of each true line sync. word present on the serial data line 1 at which time the output of the unit 2 indicates the number of errors in that sync. word (W1 or W2).
The latch 8 has two outputs Q1 and Q2 respectively asso-ciated with the outputs of the W1 and W2 comparators 6 and 7, the output Q1 la-tching to the same state as the output from W1 compara-tor 6 on the occurrence of the enable pulse.
The Q2 output si~ilarly latches to -thesame ]ogic state as '~2~ 3S
PHB.33-166 7 24.2.86 the output of the W2 cornparator 7 Thus in the presence of a true W1 line sync. word at the input line 1 which has two or less errors in it the Q1 output latches to logic ~1~ and stays in that state until at a line interval or intervals later the number of errors is greater than 2 i.e. on the appearance of a true W2 sync. word or a W1 sync.
word which has more than two errors. In a similar manner the Q2 OUtp1lt latches to the logic ~1~ state in the presence of a true W2 sync. word with two or less errors and stays 10 in that sta-te until a true W1 s~nc. word or a corrupted W2 sync. word appears.
The Q1 and Q2 outputs from the latch ~ are applied to respective data inputs D of 4-bit shift registers 9 and 10 in which the logic states present at these inputs during 15 consecutive line periods are shifted through the shift register at line rate under the control of line frequency cloc~ pulses applied to clock inputs C from the line sync.
word unit 5 to successively appear one line apart at outputs P1, P2, P3, P4. The outputs P1, P2 of shift register 20 9 and the outputs P3, P4 of shift regis-ter 10 are applied to respective inputs of a first AND-gate 11 whilst the outputs P3, P4 of shift register 9 and the outputs P1, P2 of shift register 10 are applied to respective inputs of a second AND~gate 12. At the boundary between frames the 25 alternate W1, W2 line sync. word pattern is changed such that for lines 622, 623 9 624 and 625 in odd frames the sync. word pattern is W1, W1, W2, W2 whilst the pattern for the corresponding lines in even frames is W2, W2, W1, Wl o Thus at the end of an odd frame the logic states of the 30 outputs P1, P2, P3, P4 of shift register 9 will be respectively O, O~ 1. 1, whilst those for the corresponding outputs of shift register 10 will be respectively, 1, 1, O,O.
Under these conditions the output of AND-gate 11 will be in the logic state 'O' whilst the output of the AND-gate 12 35 will be inthe logic state '1' for a line period coincident with the first line of the following even frame. At the end of an even frame -the logic states for the outputs of the P~B.33-'166 8 25 2.86 shift registers 9 and 10 will be opposite -to -that at the end of an odd frame, namely, for shift register 9 the out-puts Pl, P2, P3, P4 will be respectively 1, 1, 0~ 0 whilst for shift register 10 the corresponding outputs will be respectively 0, 0~ 1,'1. A-t such time the output of ~ND-gate 11 will go to -the logic s-tate ~1' for a line period coincident with the first line of the following odd frame, whilst that of AND-gate 12 will remain in the logic state ~0~. The OlltpUts of the AND-gates 11 and 12 which may 'be respectively used to signal the end of an even or odd frame, are applied to respective inputs of an OR-gate 13 which gives the logic state '1' at the end of each frame period which is applied to the input of a frame flywheel and sync. acquisition circuit 14 for the generation of frame lS sync. pulses for use within the receiver.
The operation of the arrangement of Figure 1 will be betteY~ seen from the diagrams in Figures 2 and 3.
Figure 2a shows the input on line 1 containing data in serial form, this figure showing data present in two line 20 periods and in particular around the start of the line periods.Of -the two lines shown that on the left contains the Wl sync. word (001011) whils-t that on the right contains the W2 sync. word (110100). The outputs from the Wl and W2 comparators 6 and 7 are shown respectively in Figures 2b and 2c for the receipt of sync. words with 2 or less errors~
that from comparator 6 producing a single 50nS pulse concident with the last bit of a Wl sync. word whilst that from comparator 7 produces a comparable pulse coincident with the last bit of a W2 sync. word. This output may also contain pulses at other times (not shown) when false line sync. words are detected in the serial data on line 1.
Figure 2d shows the line rate 50nS pulses applied to -the enable input EN of the latch 8 whilst the result' of the latching action to produce pulses of line length is shown in Figures 2e and 2f where the Figure 2e shows the output Ql produced as a result of a true Wl sync. word and Figure 2f the output Q2 as a result of a true W2 sync. word. These Ql ~Z~ 35 PHB.33-166 9 25.2.~6 and Q2 outputs are shown over a ten line period in FigureS3b and 3c respectively~ the line numbers being indicated in Figure 3a from which it will be seen that the ten line periods are the five before the end and the five following -the commencement of a frame. The outputs shown in Figure 3b and 3c are for the situation which occurs at -the end of an odd frame where lines 622, 6239 62L~ and 625 respectively contain the sync. word sequence W1, W1, W2, W2. At the end of an even frame this sequence is W2, W2, W1, W1 and $he lO output from Q1 would then be that of Figure 3c and that from Q2 as in Figure 3b, as indicated by the legends in brackets on the left of this Figure. The line rate clock pulses applied to the clock inputs C of shift registers 9 and 10 are shown in Figure 3d whilst the time shifted outputs P1 7 15 P2 9 P3 and P4 from shift register 9 are respectively shown in Figures 3e, 3-f, 3g and 3h and the corresponding outputs from shift register 10 are respectively shown in Figures 3i, 3j, 3k and 31. The outputs shown in Figures 3e to 31 are for the end of an odd frame whilst those for the end of an 20 even frame are as indicated in the legends in brackets on the left hand side of these Figures. For an odd frame the only time that the outputs P3~ P4 of shift register 9 and the outputs P1, P2 of shift register 10 are coincident with logic '1' is during line 1 of the following even frame 25 whilst for an even frame the outputs P1, P2, of shift register 9 and P3, P4 of shift register 10 are coincident with logic '1' during line 1 of the following odd frame.
These two conditions are respectively indicated in Figures 3m and 3n as the outputs of AND-gates 12 and 11 which each 30 produce an output once every two frames. These outputs are applied to the OR-gate 13 to produce an output during each frame as shown in Figure 30.
In the above description the serial data applied to the input line 1 is that of a C-MAC television signal.
35 The operation would be exactly the same if the applied data was from a D-MAC television signal. If the applied data were however derived from a D2-MAC television ~Z~ 3~;
PHB.33-166 10 24.2.86 signal in which the data rate is half that of a C-MAC
signal then the manner of operation would be the same save that the applied data on line l, the error signal at the output E of ROM 4 and the outputs of the comparators 6 and 7 would be at the bi-t rate of 10.125 Mbits/s with a pulse width of approximately 100nS and the line rate clock pulse to the enable input EN of latch 8 could have this pulse duration.
.
Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of deriving signals at frame intervals from a received television signal which has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said method comprising the steps of comparing portions of each line period with one of the digital words and producing therefrom an error signal representing the number of bits in said portions which differ from said one digital word and using said error signals to produce signals at frame intervals, characterized in that in order to produce said signals at frame intervals from said error signals the method further comprises comparing said error signals with a maximum number of permitted errors for each digital word and producing therefrom first and second detection signals for said first and second digital words when said errors are equal to or less than that permitted during a specified time in each line period, recording the resulting first and second detection signals over four line periods and detecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce said signals at frame intervals.
2. A method as claimed in claim 1, characterized in that the step of comparing the error signals with a maximum of permitted errors for each digital word is achieved by comparing the error signals with a maximum number of permitted errors for said one digital word and with a maximum number of permitted errors for the other digital word, the latter being performed as a comparison with a minimum number of errors permitted for said one digital word.
3. A method as claimed in claim 2, characterized in that said comparing steps are performed throughout each line period to produce said first and second detection signals which are then latched at said specified time in a line period when a true digital word should be present.
4. Apparatus for deriving signals at frame intervals from a received television signal which has two predetermined digital words which alternate line-by-line for a substantial part of a frame period of the television signal but which are each repeated in a respective pair of adjacent lines in the remaining part of the frame period, said apparatus comprising means for comparing portions of each line period received in said television signal with one of said digital words to produce an error signal representing the number of bits in said portions which differ from said one digital word, characterized in that said apparatus further comprises means for comparing said error signal with a maximum number of permitted errors for one of said digital words and with a maximum number of permitted errors for the other digital word and for producing a first detection signal if at a specified time in a line period the number of errors is equal to or less than that for said one digital word and a second detection signal if at said specified time the number of errors is equal to or less than that for said other digital word, means for recording said first and second detection signals over four line periods, and means for detecting correspondence between a first pair out of said four line periods of said first detection signal with a different pair out of said four line periods of said second detection signal and also between the remaining ones out of the four line periods of said first and second detection signals to produce signals at frame intervals.
5. Apparatus as claimed in claim 4, characterized in that the means for comparing said error signal with a maximum number of permitted errors of the digital words comprises first and second comparators whose respective first inputs receive the error signal specifying the number of errors when compared with said one digital word, the second input of said first comparator receiving a number corresponding to the maximum number of permitted errors in said one digital word and whose output produces said first detection signal, the second input of the second comparator receiving a number corresponding to a minimum number of permitted errors in said one digital word which corresponds to the maximum number of permitted errors in the other digital word, the output of the second comparator producing the second detection signal.
6. Apparatus as claimed in claim 4, characterized in that said first and second detection signals are applied to respective inputs of a 2-bit latch which is enabled at said specified time in a line period to produce first and second latched outputs which are respectively applied to first and second shift registers each of which is capable of producing outputs over four line periods.
7. Apparatus as claimed in claim 6, characterized in that the outputs for first and second line periods of said first shift register and for third and fourth line periods of said second shift register are applied to respective inputs of a first AND-gate while the outputs for third and fourth line periods of said first shift register and for first and second line periods of said second shift register are applied to respective inputs of a second AND-gate, the first and second AND-gates alternately producing output signals at frame intervals.
8. Apparatus as claimed in claim 7, characterized in that the outputs of the first and second AND-gates are applied to respective inputs of an OR-gate whose output is applied to control the operation of a frame frequency synchronizing circuit.
9. Apparatus as claimed in claim 5, characterized in that said first and second detection signals are applied to respective inputs of a 2-bit latch which is enabled at said specified time in a line period to produce first and second latched outputs which are respectively applied to first and second shift registers each of which is capable of producing outputs over four line periods.
10. Apparatus as claimed in claim 9, characterized in that the outputs for first and second line periods of said first shift register and for third and fourth line periods of said second shift register are applied to respective inputs of a first AND-gate while the outputs for third and fourth line periods of said first shift register and for first and second line periods of said second shift register are applied to respective inputs of a second AND-gate, the first and second AND-gates alternately producing output signals at frame intervals.
11. Apparatus as claimed in claim 10, characterized in that the outputs of the first and second AND-gates are applied to respective inputs of an OR-gate whose output is applied to control the operation of a frame frequency synchronizing circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8510862 | 1985-04-29 | ||
| GB08510862A GB2174567A (en) | 1985-04-29 | 1985-04-29 | Deriving frame interval signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1260135A true CA1260135A (en) | 1989-09-26 |
Family
ID=10578380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000507483A Expired CA1260135A (en) | 1985-04-29 | 1986-04-24 | Deriving frame interval signals |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4713692A (en) |
| EP (1) | EP0200269B1 (en) |
| JP (1) | JPS61258591A (en) |
| AU (1) | AU579547B2 (en) |
| CA (1) | CA1260135A (en) |
| DE (1) | DE3681328D1 (en) |
| ES (1) | ES8707836A1 (en) |
| FI (1) | FI80179C (en) |
| GB (1) | GB2174567A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2605479B1 (en) * | 1986-10-17 | 1989-04-07 | Telediffusion Fse | SYSTEM FOR EXTRACTING FRAME SYNCHRONIZATION SIGNALS FROM PACKET SYNCHRONIZATION SIGNALS |
| US4807230A (en) * | 1987-05-29 | 1989-02-21 | Racal Data Communications Inc. | Frame synchronization |
| GB8715597D0 (en) * | 1987-07-02 | 1987-08-12 | Indep Broadcasting Authority | Digital synchronisation |
| KR0160279B1 (en) * | 1988-12-20 | 1998-12-01 | 이우에 사또시 | Wireless communication apparatus |
| GB8901200D0 (en) * | 1989-01-19 | 1989-03-15 | Eev Ltd | Camera using imaging array |
| US4998264A (en) * | 1989-09-20 | 1991-03-05 | Data Broadcasting Corporation | Method and apparatus for recovering data, such as teletext data encoded into television signals |
| US5742265A (en) * | 1990-12-17 | 1998-04-21 | Photonics Systems Corporation | AC plasma gas discharge gray scale graphic, including color and video display drive system |
| KR950006358B1 (en) * | 1992-01-31 | 1995-06-14 | 삼성전자주식회사 | Apparatus and method for detecting frame sync signal |
| US5921505A (en) * | 1996-12-02 | 1999-07-13 | Trw Inc. | System and method for reducing mechanical disturbances from energy storage flywheels |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1599157A (en) * | 1976-12-24 | 1981-09-30 | Indep Broadcasting Authority | Digital recognition circuits |
| JPS53819A (en) * | 1977-04-18 | 1978-01-07 | Tokyo Keidenki Kk | Method of insulating transformer coil |
| DE2740997C2 (en) * | 1977-09-12 | 1979-09-13 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Method for time-division multiplex frame synchronization with the aid of variable synchronization words |
| US4344180A (en) * | 1980-06-19 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Redundant word frame synchronization circuit |
| US4414676A (en) * | 1981-03-31 | 1983-11-08 | Motorola, Inc. | Signal synchronization system |
| NL8104533A (en) * | 1981-10-06 | 1983-05-02 | Philips Nv | SYNCHRONIZER CIRCUIT FOR DERIVING AND PROCESSING A SYNCHRONIZER SIGNAL PRESENT IN AN INCOMING VIDEO SIGNAL. |
| WO1984002242A1 (en) * | 1982-12-02 | 1984-06-07 | Indep Broadcasting Authority | Apparatus for deriving synchronisation signals for component television video signal reception |
| JPS59105789A (en) * | 1982-12-10 | 1984-06-19 | Hitachi Ltd | Code signal detecting circuit |
| EP0128921B1 (en) * | 1982-12-14 | 1987-04-01 | Independent Broadcasting Authority | Apparatus for deriving information signals for component television video signal reception |
-
1985
- 1985-04-29 GB GB08510862A patent/GB2174567A/en not_active Withdrawn
-
1986
- 1986-04-11 US US06/850,634 patent/US4713692A/en not_active Expired - Fee Related
- 1986-04-24 CA CA000507483A patent/CA1260135A/en not_active Expired
- 1986-04-25 EP EP19860200709 patent/EP0200269B1/en not_active Expired - Lifetime
- 1986-04-25 FI FI861756A patent/FI80179C/en not_active IP Right Cessation
- 1986-04-25 ES ES554367A patent/ES8707836A1/en not_active Expired
- 1986-04-25 DE DE8686200709T patent/DE3681328D1/en not_active Expired - Lifetime
- 1986-04-28 JP JP61099270A patent/JPS61258591A/en active Pending
- 1986-04-28 AU AU56770/86A patent/AU579547B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61258591A (en) | 1986-11-15 |
| FI861756A (en) | 1986-10-30 |
| EP0200269B1 (en) | 1991-09-11 |
| ES554367A0 (en) | 1987-08-16 |
| EP0200269A3 (en) | 1988-03-30 |
| GB8510862D0 (en) | 1985-06-05 |
| FI80179B (en) | 1989-12-29 |
| FI80179C (en) | 1990-04-10 |
| EP0200269A2 (en) | 1986-11-05 |
| FI861756A0 (en) | 1986-04-25 |
| DE3681328D1 (en) | 1991-10-17 |
| US4713692A (en) | 1987-12-15 |
| GB2174567A (en) | 1986-11-05 |
| ES8707836A1 (en) | 1987-08-16 |
| AU579547B2 (en) | 1988-11-24 |
| AU5677086A (en) | 1986-11-06 |
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