CA1255364A

CA1255364A - Configurable logic element

Info

Publication number: CA1255364A
Application number: CA000502720A
Authority: CA
Inventors: William S. Carter
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 1985-02-27
Filing date: 1986-02-26
Publication date: 1989-06-06
Also published as: GB8604761D0; DE3645221C2; JPH0446488B2; US4706216A; DE3645224C2; GB2171546A; GB2171546B; JPH0645912A; US4758985A; DE3606406A1; JPS61224520A

Abstract

CONFIGURABLE LOGIC ELEMENT
William S. Carter ABSTRACT
A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunc-tion with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.

Description

~LZ~53~4 FIELD OF THE INVENTION
This inventlon relates to a configurable logic element in general and in particular, to a configurable logic element which is composed of a configurable combinational logic element, a configurable storage element and a configurable output select logic. The output signals of the configurable storage element serve as input signals to both the configurable combina-tional logic and the output select logic. The output signals of the output select logic are selected from the output signals of the combinational logic element and the output signals of the ~;~ storage element.
~ACKGROUND OF THE INVENTION
In Canadian patent application Serial No. 478,752, filed April 10, 1985 by Ross H. Freeman and entitled "CONFIGURABLE
LOGIC ARRAY", a structure is described which allows changing the conflguration of a finished integrated circuit from time to time (even when the integrated circuit is installed in a system) `; to provide any one of a plurality of logical func-tions from ; the same integrated circuit. This is accomplished by providing a number of "configurable logical elements" (herein referred -to - as "configurable logic elements") each of which is capable of being configured to implement any one of a plurality of logic functions depending on the task which it is called upon to per-form. By configurable logic element is mean-t a combination of devices which are capable of being electrically interconnected by switches operated in response to control bits stored on the , ~

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-la- 70128-110 chip (or transmitted to the chip) to perform any one of a plurality of logical functions. The configurable logic element disclosed in application No. 478,752 may include all of ~25~
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l the circuit elements necessary to provide one or more of

2 -the functions provided by, for example, an AND gate,

3 flip-flop, inverter, NOR gate, exclusive OR gate, and

4 combinations of these functions to orm more complex functions. The particular function to be carried out by a configurable logic element is determined by control 7 signals applied to the configurable logic element from 8 control logic. Depending on the control signals, a 9 configurable logic element can function as an AND gate, an OR gate, a NOR gate, a NAND gate, or an exclusive OR
11 gate or any one of a number of other logic functions 12 without change in physical structure. Structure is 13 provided on chip to allow any one of a plurality of 14 functions to be implemented by the configurable logic element. This is done by providing control logic to 16 store and generate control signals which control the 17 configuration of the configurable logic element.
18 In one embodiment, the control signals are stored 19 and transmitted by control logic formed integrally with and as part of the integrated circuit chip containing the 21 configurable logic elements. ~owever, if desired, the 22 control information can be stored and/or generated outside 23 the integrated circuit and transmitted through pins to 24 the configurable logic element.
In general, a given set of control signals in the 26 form of control bits is transmitted from the control 27 logic to a configurable logic element to control the 28 configuration of that configurable logic element. The 29 actual sèt of control bits ~rovided to the configurable 30 logic element on the integrated circuit chip depends on 31 the function to be carried out by the configurable logic 32 element on the chip.

34 S~MARY OF THE INVENTION
A configurable logic element is disclosed which 36 provides great versatility in the selection of the func-37 tion it is capable of implementing. The configura~le ~ ~ `''`

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-~ 53 70128-110 locJlc element includes a combinational logic element, a storage element, and an OUtpllt select logi.c, each of which is configured by control hits. Selected input si~nals to the configurable logic element toge~her wi~h selected "feedback" signals from the storage element are the input signals to the comb:Lnational logic elemenk.
The input signals to the con:Eigurable logic element together wlth the output signals of the combinational logic element provide input signals to the configurable storage element. The output select logic provicles output signals which are selected from the output signals of the combinational :Logic element and the storage ~ element.
; In accordance ~ith a broad aspect of the invention there is provided a conficJurable logic element comprising: means for receiving a first plurality of N binary illpUt signals; means for receiving a second plurality of M binary feedback signals; means : for selec:ting K of said M-~N binary signals (where K~N-~M~;
; combinational logic means for receiving said K binary signals from said means for selecting, said combinational logic means having a plurality of configurations including at least a first ~ 20 configuration in which said combinational logic means generates a first set of binary output signals, each of which represents a function of some of said K binary signals and a second configuration in which said configurahle combinational logic means generates a second set of binary output signals, each of which represents a function of some of said K binary signals, wherein the set of functions represented by said first set of binary signals i5 not the same as ~he set of functions represented by 3 ;
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said second set of binary signals; a configurable storage circuit comprising: a pluxa:lity of input leads for receiving a plurality of input signals, said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said binary output signals of said combinational logic means and selec~ed ones of said N binary input signals, memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead; first means having a first configuration in which said first means provides a first selected one of said inpllt signals of said con-figurable storage circuit to said first input lead of said memory means; second means having a first and a second configuration in which said second means provides a second and a third selected, one, respectively, of said input signals of sa.id configurable storage circuit to saicl second input lead of said memory means, said memory means generating said second plurality of M binary ~ signals i.n response ~o said signals provided by said first and ; said second means; and a configurable select logic comprising:
means for receiving said output signals generated by said com-20 binational logic means and said M binary signals generated by said configurable storage circuit, and means for selecting output signals from among the signals received by said select logic.
In accordance with another broad aspect of the invention there is provided a configurable logic element comprising: means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals;
means for selecting K of said M+N binary signals of said first and ; ' ~
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3l :2S~64 701~8-110 saicl secorld plurality ~1here KsN~I); configurable combinational logic means comprising: first configurahle means for receiving said K binary input signals, said first configurable means having at least a first configu.ration in which said $irst configurable means generates a first set of output si~nals said first set being a first subset of saicl K input'signals, and a second configuration in which said first configurable means generates a second set of output signals said seconcl set being a second subset of said K
input signals! wherein said first set is not equal to said second set; first memory means having a plurality of storage locations, each of said sto~age locations for storing a binary bit; first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first conflgurable means and for providing a ~irst output signal representing the binary bit stored in said selected storage location within said first memory; a configurable storage clrcuit ~omprising, a plurality of input leads for receiving a plurality ::
of input signals said input siynals corresponding to said input leads on a one-to-one basisj said input signals comprising selected ones o~ said output signals of said first location selection means and selected ones of said N binary input signals;
memory,~eans for storing data, said memory means having at least a first~and a second input lead~and at least one output lead; first . ~ : :
means,having a first configuration in which said first means provides a first selected one of sald input slgnals of said con-fi~rable storage circuit to said:first input lead of said memory i~ ~
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means; second means having a first and a second configuration in whi~h said second means provides a second and a third selected one, respectively, of said input signals of said configurable storage clrcuit to said second input lead of said memory means r said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and a configurable select logic comprising:
means for receiving the output signals produced by said first location selection means of said~combinational logic and said M
binary signals; and means for selecting output signals from among the signals received by said select logic.

In accordance with another broad aspect of the invention there is provided a configurable combinational logic circuit comprising: flrst configurable means for receiving K binary input signals, said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said ` ~ ~
~ first configurable means generates a second set of out signals : : :
~ 20 said second set being a second subse~ of said K input signals :: : : :
wherein said firs~t set is not equal to said second set; first ~membry means having a plurality o f storage locations, each of said , : : :::::~: ;~ storage locations for storing a:binary bit; first location s~elect1on means for receivtng~said~output signals of said first con$1~urable means and for selecting a storage location within said first memor~ mean.s in response to said output si~nals of said first configurable means and for providing a first output signal :
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~255364 representing ~he binary ~it stored in said selected storaqe location within said first memory.
In accordance with another broad aspect of the invention there is provided a configurable storage circuit comprising:
memory means for storing lata, said memory means having at least a first and a second inpu~ lead; a first set o~ one or more input :Leads corresponding to said first input lead, each input lead of said first set for receiving a corresponding input signal; a second set of one or more input leads corresponding to said second input lead, each input lead of said second set for receiving a corresponding input signal; first means which, for each given lead in said first setr has a corresponding conflguration in which said first means provides the input signal on said giv~n lead to said first input lead; second means which, for each given lead in said second set, has a corresponding first configuration in which said second means provides the input signal on said given lead to said :
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second lead; said memory means generating one or more output signals in response to said signals provided:by said first means and sald second means.
~ In accordance with~another broad aspect of the invention thers lS provided a con~l~gurable logic~element~comprising: means for receiving a first plurality of N binary input signals; means or~receiving a second plurallty of M binary feedhack signals;
means~for selecting~K of said M~N~binary signals ~where K5N+M)~;
combinational logic means for receiving said K binary signals from said means for seleating, ssld ~onfigurable combinational loglc mesns having a plurality of conigurations ~or generating binary 3d:

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,, ,'' ''`,` , ~553~i4 output signals; a configurable storage circuit for receiving selected ones of saicl binary output signals of said configurable combinational logic means ancl selected ones of said N binary input signals and for generati.ny said M hinary feedback signals, said ~onfigurable storage circuit having a plurality of conflgura~ions;
and a configurable select logic comprising means for receiving said output signals qenerated by said combinational logic means and said M binary signals generat0d by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic.
This invention will be more fully understood with reference to the following detailed description and accompanyinq ;~ drawings.
,. ~ ~ens~
Figure 1 illustrates some of the various logic functions capable of being implemen~ed by a configurable logic element in a co~nfigurahle logic array;
Figure 2 illustrates the internal logic structure of one possible configurable logic element capable of implementing a number of useful functions of two variables A and B;

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~ ~ Figure 3A illustrates a 16 bit RAM circuit wherein any :, one of sixteen possible input states is capable of being ide~ntified~and 2l6 functlons are capable of being implemented.

Figure 3B illustra~es a selection structure for ; selecting any one of sixteen bits capable of implementing 2~6 . .:
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Eigure 3~ illustrates the logic gates represented by placing a binary one in the Karnaugh map o~ Figure 3C at the intersections of the first and second rows and the first column.

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Figure 4A illustrates a plurality of configurable logic elements (shown as nine logic elements) formed on an integrated circuit chip together with programmable interconnects formed between selected leads to yield desired logic functions and with selected input/output pads and interconnections of the leads between logic element;
Figure 4B shows the key to the cross-connections between crossing conductive leads in Figure 4A;
Figure 5 represents a portion of the circuitry of a novel combination static and dynamic shift register appropriate for use with the configurable logic array of this invention;

Figures 6A through 6H represent wave forms of use in `
explaining the operation of the structure of Figure 5;
Figure 7 shows a configurable logic element according to the present invention;
' Figure 8 shows one embodiment of the configurable logic element of Figure 7; and Figure 9 shows one embodiment of the storage element 121 of Figure 8.
`~ 20 DETAILED DESCRIPTION
, The following detailed description of this invention i ~ ls meant to be illustrative only and not limiting. Other ~ embodiments of this invention will be o~vious to those skiIled in `~ the art in view of the following disclosure.

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-4a- 70128-110 array descri.bed in copending Canadian Patent Application Serial No. 478,752, filed April 10, 1985 on an invention of Ross H.~. Freeman, entitled "Configurable Logic Array" is helpful to understand the present invention.
Figure 1 illustrates certain logic functions capable of being implemented by a configurable logic element. The ~:i :' ,' ',', ~ :

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~` 5 ~-l 28 functions shown in Figure 1 are merely illustrative and 2 other elements not shown can, if desired, be implemented 3 by a configurable logic element. The following functions 4 are shown:
Element Function 6 1 AND gate 7 2 NAND gate 8 3 AND gate with inverted input 9 4 NAND gate with inverted input OR gate ll 6 NOR gate 12 7 exclusive OR gate 13 8 : exclusive NOR gate 14 9 3 input AND gate 3 input NAND gate 16 11 3 input OR gate 17 12 3 input NOR gate 18 13 OR gate with one input comprising AND gate lg 14 NOR gate with one input comprising AND gate AND gate with one input comprising OR gate 21 16 NAND gate with one input com~rising OR gate 22 17 3 input AND gate with one input inverted 23 18 3 input NAND gate with one inverted inpu-t 24 19 3 input OR gate with one inverted input 3 ~ NOR gate with one inverted input 26 21 one of two inputs multiplexer 27 22 inverting one of~ two inputs multiplexer 28 23 "D" flip flop with reset 29 2~ Set-Reset latch . : :
"D" flip-flop with reset and inverted 31 ~ output 32 26 Set-reset latch with:reset and inverted 33 ~ output 34 27 "D" fllp-flop with~set 35~ 28 'iD" flip-flop~with set and inverted output 36 Of:course, other logic functions can also be imple-37 mented in a configurable logic element.
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1 Figure 2 illustrates the internal logic structure of 2 one possible configurable logic element which is capable of implementing all useful basic functions of the two 4 variables A and B, with the functions being selected by configuration control signals CO, CO, C1, C1, ... through 6 C5 on control leads CO, CO, ... through C5. (In this 7 example, all control leads are connected to the gates of 8 N channel enhancement mode pass -transistors.) To implement 9 an AND gate function using the structure shown in Figure 2, the input leads labeled A and B are shunted past invert-11 ers 21 and 22, respectively, to AND gate 25 by high level 12 signals on the C1 and CO configuration control leads 13 which, being connected to the gates of N channel enhance-14 ment mode pass transistors 29c and 29d, causé pass tran-sistors 29c and 29d to turn on.
16 Low level signals are applied to the configuration 17 control leads C0 and C1, thus blocking the output signals 18 of inverters 21 and 22 from AND gate 25. In addition, a 19 high level signal on lead C5 is applied to enable AND
gate 25. Thus three input AND gate 25 functions as a 21 two-input AND gate with respect to the signals A and B.
22 The output signal of AND gate 25 provides one input 23 signal to NOR gate 26. A second input signal to NOR gate 24 26 is provided by the output signal of AND gate 24. The output signal of AND gate 24 is held at a logical O by 26 applying a logical O to configuration control lead C4.
27 Thus the control signals C2 and C3 are "don't cares", 28 that is, these signals can be high or low without affect-29 ing the output signal of AN~ gate 24. Since the output sianal of AND gate 24 is a logical 0, and since the r ' ~ ~tR~e L ~ ~e control input signal to NOR gate 26 is a logi-32 cal 0, it is easy to see that AND gate 25, AND gate 24 33 and NOR gate 26 function together as a NAND gate with 34 respect to input signals A and B. Since the tri-state control signal input to NOR gate 27 is a logical O (except 36 during reset), NOR gate 27 serves as an inverter with 37 respect to the output signal of NOR gate 26. The output . . : , :
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ii53~4 ,, ( signal of NOR gate 26 is applied to the gate of N channel transistor 29a (the source of which is grounded and the drain of which is connected to output lead 28) and the 4 complement of the output signal o~ NOR gate 26 is applied to the gate of N channel transistor 29b (the source of 6 which is connected to a power supply and the drain of 7 which is connected to both the output lead 28 and the 8 drain of N channel transistor 29a). Thus, transistors 9 29a and 29b function as an inverter with respect to the output signal of NOR gate 26. Thus, the structure of 11 Figure 2 configured as described above performs the 12 function of an AND gate with respect to the signals A and 13 B. Other logic functions can also be produced by appro-1~ priate selection of the control signals to be supplied to the configuration control leads CO through C5 to activate 16 the appropriate pass transistors and gates within the 17 strUcture-18 Figure 3A illustrates a 16 bit RAM capable of producing 19 an output signal in response to any one of sixteen possible combinations of input signals. Thus input signals A and 21 B control the X decoder to select any one of the four 22 columns in the 16 bit RAM. Input signals C and D control 23 the Y decoder to select any one of the four rows in the 2~ 16 bit RAM. The 16 bit RAM produces an output signal representative of the bit at the intersection of the 26 selected row and column. There are 16 such intersections 27 and thus sixteen such bits. There are 216 possible 28 combinations of functions capable of being represented by 29 16 bits. T~us, if a NOR gate is to b~ simulated by the 16 bits in the R~, the Karnough map for the RAM would be 31 as shown in ;Figure 3C. In Figure 3C all bits are "O"32 except the bit at the intersection of the first row 33 (representing ~=O, B=O) and the first column (representing 34 C=0, D=0). Should a less frequently used function be desired to be generated by the 16 bit RAM, (for example, 36 should a "1" output signal be desired for A=1, B=O, C=O
37 and D=O~ then a binary "1" is stored at the intersection o :
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1 of the second row and the first column. Should a binary ~ "1" be desired both when A=0, B=0, C=0 and D=0 and also 3 when A=l, B=0, C=0 and D=0, then a binary "1" is stored 4 at each of the intersections of the first column with the first row and the second row. The logic circuit repre-6 sented by this loading of the RAM is as shown in Figure 7 3D. Thus the RAM of Figure 3A represents an elegant and 8 simple implementation of any one of 216 logic functions.
9 Figure 3B shows another structure for yielding any ~, one of sixteen select bits. Each of registers 0-15 in 1~. the vertical column to the left labeled "16 Select Bits", 12 contains a selected signal, either a binary 1 or 0. By 13 selecting the proper combination of A, B, C, and D, a 14 particular bi-t stored in a particular one of the sixteen locations in the 16 Select Bits register is transmitted 16 to the output lead. Thus, for example, to transmit -the 17 bit in the "1" register to the output lead, the signal A, 18 B, C, D is applied to the leads so labeled. To transmit 19 the signal labeled "lS" in the sixteenth location in the 16 Select Bits register to the output lead, the signal A, 21 B, 2, and D is applied to the appropriate columns.
22 Again, any one of 216 logic functions can be implemented 23 using this structure.
24 Figures 4A illustrates a configurable logic array containing nine configurable logical elements. As shown 26 in Figure 4a, each CLE of the nine CLEs 40-1 through 40-9 27 has a plurality of input leads and one or more output 28 leads. Each input lead has a plurality of access junctions 29 each connécting a selected general interconnect lead to the input lead. The access junctions for inpu-t lead 2 of 31 CLE 40-7 are labeled Al through A4 in Figure 4a. The 32 access junctions for the other input leads are indicated 33 schematically but are not labeled for the sake of clarity.
34 Similarly, each output lead of each CI.E has a plurality of access junctions each connecting the output lead to a 36 corresponding one of the general interconnect leads. The 37 access junctions are indicated schematically for each -, , :. , :
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1 output lead of each CLE in Figure 4a. The access junc-2 tions for the output lead of CLE 40-7 are labeled B1 ~ through B5. Tlle leads in Figure 4a which are neither 4 input leads nor output leads are called general inter-connect leads and the junctions in Figure 4a which are 6 not access junctions for input and output leads are 7 called general interconnect junctions. As shown in 8 Figure 4A, nine logic elements are placed on an integrated 9 circuit chip together with programmable access junctions , and a general interconnect structure which comprises 11 general interconnect leads and programmable general 12 interconnect junctions for connecting various leads to 13 other leads. The general interconnect structure includes 1~ a set of general interconnect leads and of programmable junctions interconnecting the general interconnect leads 16 having the property that for each general interconnect 17 lead in the general interconnect structure there is a 18 programming of the general interconnect junctions which 19 connects the given general interconnect lead to one or more o-ther leads in the general interconnect structure.
21 Moreover, there is a programming of the junctions (both 22 access and general interconnect) such that for any given 23 output lead of any CLE in the CLA, and for any given 24 input lead of any other CLE in the CLA, there is a pro-gramming of the junctions such that the given output lead 26 is connected to the given inpu-t lead. An electrical path 27 from a given output lead to a given input lead always 28 contains at least two access junctions and at least a 29 portion of a general interconnect lead. For example, one electrical path from the output lead of CLE 40-8 to the 31 second input lead of CLE 40-9 contains access junctions 32 A7 and B7 and the marked portion P of a general intercon-33 nect lead. Typicallyj an electrical path from an output 34 lead of one CLE to an input lead of another CLE will also contain one or more general interconnect junctions. Each 36 of logic elements 40-l through 40-9 represents a collection 37 of circuitry such as that shown in Figure 2 or some - . : .,~ ....
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. : : , : -:~ ~ . , , . :: , . . -~25i5364 -lo-1 similar structure capable of being configured as described above in Figure 2 to perform any one of a number of logic - functions. To program the circuitry (both the configurable 4 interconnect switches and the configurable logic elements), selected signals are applied to input leads identified as 6 configuration control input leads thereby to generate a 7 desired logical function in each of the logic elements 8 and to interconnect the logic elements as desired. In 9 Figure 4A, no specific lead has been identified as an input lead for the configuration control signals. However, 11 any particular I/O pad can be selected for this purpose.
12 The configuration control bits can be input into the 13 configurable logic array either in series or in parallel 14 depending upon design considerations where they are typically stored in a programming register (shown in 16 Figure 5). Alternatively, the configuration control bits 17 may be stored in a memory on chip. In addition, another 18 I/O pad will be used for an input clock signal which is 19 used, inter alia, for the loading of the configuration control signals into the programming register. When the 21 configurable logic array shown in Figure 4A has been 22 configured, selected output signals of logic elements 23 40-1 through 40-9 are provided to selected I/O pads.
24 Figure 4B illustrates the meaning of the junction symbols used in Figure 4A.
26 To configure a logic element such as logic element 27 40-1 ~Figure 4A), a number of bits must be applied to the 28 configuration controI leads such as leads C0 through CS, 29 as shown, for example, in Figure 2. To do this a shift register, for example, is utilized as part of each configu-31 rable logic element. Figure 5 illustrates a shift register 32 which may be~used. The shift register of Figure 5 is 33 illustrated showin~ two basic storage celIs. Each storage 3~ cell is capable of storing one bit of information. of course, an actual shift register will contain as many 36 storage cells as required to configure the logic element 37 of which the shift register is a part, to its desired . ~
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, 1 configuration. In operation, an input signal is applied 2 to input lead 58. This input signal (shown in Figure 6D) 3 contains bit stream to be stored ln the shift register as ~ configuration control bits to configure the configurable logic element to perform a desired logic function or to 6 configure (program) an access junction or a general 7 interconnect junction between general interconnect leads 8 in a manner to be described shortly. Thus the sequence 9 of pulses applied to input lead 58 represents those pulses which when stored in the storage cells of the 11 shift register will activate the configuration control 12 bits in the proper manner to achieve the desired functional 13 and/or interconnection result. For example, if the 14 circuit of Figure 2 is to be configured to form an AND
gate, the pulses C0, Cl, C2, C3, C4, and C5 would be 16 represented by 1,l,~,X, 0,1.
17 The sequence of pulses applied to input lead 58 is 18 synchronized with clocking pulses ~1 and ~2 applied to 19 leads 57 and 59 respectively. Thus in the first period of operation clocking pulse ~1 goes high (Fig. 6A), 21 clocking pulse ~2 is low (Fig. 6B), the hold signal lFig.
22 6C) is low during shifting thereby facilitating the 23 passage of data through sequentially connected cells 5-1, 24 5-2 et al. of the shift register. To shift the pattern 01010 into the shift register, the following operations 26 occur: The input signal on lead 58 is low during approx-27 imately the first half cycle of the clocking period tl.
28 The output signal Ql of inverter 51-1 goes to a high 29 level in response to the low level input signal and ~1 high to enable pass transistor 53-1. Some time through 31 the first clocking period tl, the clock signal ~1 goes 32 low (Fiq. 6A) and the clock~signal ~2 shortly thereafter 33 goes hlgh ~Fig. 6B) to enable pass transistor 55-1.
34 Consequently, the high level output signal Ql is trans-mitted to the input lead of~inverter 52-1 by enabled pass 36 transistor 55-1 and thereby produces a low level output 37 signal Ql on the output lead of inverter 52-1. Thus at ::-: ~ : ~ . ::, -: . -:~, : , : . :. : . : ,.:

-.~ : :.:, ;. ; ,,, ~25~i364 the end of period tl, the output signal Q1 (Figure 6F) from inverter 52-1 is low level. The output signals Q2 and Q2 from inverters 51-2 and 52-2 in the second cell are still indeterminate because no known signal has yet propagated to the second storage cell 5-2 to change the signals of these inverters to a known ; state.
. At the beginning of the second period (labelle~. I't2ll in :
Figure 6A), ~1 goes high (Figure 6A) and ~2 is low (Figure 6B) ; having gone low before period tl ended. The input signal . 10 (Figure 6D) now has risen to a high level representing a `.~ binary 1 and thus the output signal Ql of inverter 51-1 has gone low. The outputsignal Ql of lnverter 52-1 remains low because : ;
::: pass transistor 55-1 is held off by the low level ~2 signal.
Some time through the second period ~1 goes low followed a fraction of t.ime.later ~y ~2 going high. At this time, the output sig-.~' :
nal Ql is transmitted through pass transistor 55-1 to inverter :: ~ 52-1 thereby driving the output signal Q1 from inventer 52-1 to high level. Meanwile, during period t2 the previous low ~; level signal on Ql has driven the output signal Q2 of inverter ::.
51-2~to a high level when Ql was at a high level to enable pass transistor 53-2 and the change in ~2 from a low level to a high level in the second half of per1od t2 to enable pass transis-tor : 55-2 drives the output signal Q2 from:inverter 52-2 to a low level. In this manner,~ the~;input slgnal on lead 58 (Figure 6D) is transmitted through each. of the cells 5-1, 5-2, 5--3 et al. in the shift register. Upon the transfer into the shift register of ~255364 -12a- 70128-110 the de~ired information, the hold sLgnal (Figure 5C) is enakled (i.e., driven to a high level) therebv to connect the feedback leads 50-1, 50-2, and 50-3 et al. from the output leads of inverters 52 to the input leads of inverters 51 so as to hold the lnformation then in each cell indefinitely. In operation, the signal stored in a given cell e.g. 5-1 is connected to a configuration control or to an interconnect pass device such as devices 60-1 and 60-2; illustrated schematically in Figure 5.

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~2S~364 ( -13-2 The output signals Ql~ Q1~ Q2' Q2' etc-~ of the shif-t register are directly connected to the (configuration) control inputs of a logic element or the pass devices of 4 the general interconnect junctions.
When ~1 is low, ~2 and hold may be brought high, 6 thus holding the data indefinitely. The entire shift 7 register may be set or cleared by setting or clearing the 8 input with ~1 and ~2 both high and HOLD low. Enough 9 set/reset time must be allowed for the signal to propagate ~, the entire length of the shift register to clear the 11 shift register in this manner. Naturally this time is 12 dependent upon the length of the shift register.
13 The shift register operates in its dynamic phase by 14 storing the information being shifted as charge on the lS gates of the transistors (not shown in Figure 5 but 16 well-known) comprising innc~ne~c~r~ 551-1, 52-1, 51-2, 52-2 17 et al. of the shift register. These inverters are of 18 well-known design and will not be described in detail.
19 The use of~dynamic shift register is important because a dynamic shift register uses six transistors and thus 27 takes up very little area. The dynamic shift register is 22 converted to a static latch by adding only one transistor.
23 Thus the dynamic shift register lstatic latch) can be 24 easily fabricated as part of a configurable logic element without adding significant complexi~y to the circuit or 26 consuming significant semiconductor area. Because of the 27 "hold" signal, the dynamic shift register can become a 28 static latch because placing the shift register on hold 29 automatically refreshes the data. Thu~ a separate refresh circuit is not needed.
31 It is apparent from the above description that the 32 dynamic shift register (static latch) circuit does not 33 need refreshing once it has been latched into a hold 34 state. This is accomplished by use of the feedback circuit comprising lead 50-1 and pass transistor 54-1 in 36 cell 5-l, for example.

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~;~5S364 Figure 7 shows a hlock diagram of the configurable lo~ic element 99 of ~he present invention which includes configurable combina~ional logic 100, configurable storage circuit 120 and conflgurable output select logic 140. The combinational logic 100 re~eives the N binary input signals to the configurable logic element 99 and ~ ~inary "feedback" signals from storage circuit 120. Combinational logic 100 is configurable into a plurality of configurations. ~ach confiyuration implements one or more selected combinational logic functions of one or more selected subsets of the input si~nals to the combinational logic. Since combinational logic 100 is confiyurable, i~ can he employed to implement a variety of dif~erent functions~ Moreover, two or more selected functions may be implemented simultaneously, appearing on separate output leads of the configurable logic element 100. In more cletail, combinational lo~ic 100 selects K binary input . :
signals from among its M~N binary input slgnals (K~M-~N).
Combinational logic circuit 100 is responsive to a plurality of sets of values of a first set of configuration signals including at least a first set of values for which confiyurable combinational logic 100 implements a first set of functions, each o~ which is a function of some of said K binary signals, and a second set of values for which configurable combinational logic lOO~:implements a sçcond set of functions, each of which is a :function of some of said ~ binary signals, where said first set of functions is not the same as said second set of functions. In one embocliment combin~ational iogic 100 has a first configuration which implements a selectable 1 of 2 binary valued functions of these 3.4 -~5536~

7012~-110 K binary signals and a second configuration which implements both (K~l) a selectable 1 of the Z binary valued functions of a first (K-l) of the K selected binary input signals and a selectable 1 of ~ K-l) the 2 binary value functions of a second selected tK-l) f the K sele~ted binary input signals. (The second set ~, ::;
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: , , ( ~25~3~ -15-1 of K-1 signals need not be distinct from the first set.) 2 The operation of combinational logic 100 will be more ~ readily understood after a consideration of the specific 4 embodiment described in Fig. 8 which is explained hereafter.
Storage circuit 120 is also configurable and may be 6 programmed to implement, depending on the configuration, 7 one or more storage elements each of which may be, for 8 example, a transparent la-tch with set and reset, a D
9 flip-flop with set and reset, an edge detector, a stage , of a shift register, or a stage of a counter. Configurable ll storage circuit 120 receives the output signals of combina-12 tional logic 100 on bus 161 as well as a clock signal and 13 selected ones of the N input signals of combinational 14 logic 100 on input bus 160. Output select logic 140 is configured to provide output signals which are selected 16 from among the out~ut signals of the combinational logic 17 element and the storage circuit.
18 Fig. 8 shows the details of one e~ odiment of the 19 configurable logic element 99 in Fig. ~. In Fig. 8, the four input signals to the configurable logic element 99 21 are denoted by A, B, C, D (i.e., N=4). Since the storage 22 circuit 120 provides only a single feedback signal Q to 23 switch 107, M=1. In Fig. 8, K=4 since the signals A, B;
24 C and either D or Q are selected from among the five signals A, B, C, D, and Q. Configurable combinational 26 logic element 100 includes configurable switches lO1 27 through 107, 113, and 114, 8-bit R~s 108 and 109, one of 28 eight gelect logics 1~10 and~lll, multiplexer 112, and 29 configuration control~lead 115 to switches 113 and 114.
Each of the configurable switches is configured by control 31 bits from a programming register (not shown) on leads 32 (not shown except for lead 115) as previousl~ explained.
33~ Switch lOl may be configured to provide signal A as its 34 output signal or it may be configured to provide signal B
as its output signal. ~Simllarly, each of the switches 36 10? through 107 may be configured to provide a selected 1 37 of its two input signals as its output signal. Thus, for 3~ example, for one selection of configuration control bits, ', ~ ' ' , " ` ' ' ' :: ' ' '.',.',. :
`'' ' '' ` ~ ." ' "', ` ' ' .' "' ~ ` "' ` ~ ' ` ` ' ~L2S~364 swit~h 107 provides signa]. D and the binary signals A, C, and D
are provided to both one of eight select logic 110 and one of eight select logic 111 by switches 101 through 103 and 104 through 107, respec~ively. For each of the eight possible combinations of binary signals A, C and D, select logic 110 selects a uni~ue storage element in RAM 108 and outputs the bit stored in the selected loca~ion. One of eight select logic 111 operates similarly with respe~t to 8-~it RAM 109. Multiplexer 112 provides ei~her the output signal from select logic 110 or ~he output signal from select logic 111, depending on the state of signal B.
For ~his configuration, the control bit applied on lead 115 causes switches 113 and 114 to simultaneously pass the output signal ~rom multiplexer 112 to output leads F1 and F2 of combinational logic element 100. The two 8-bit RAMs 108 and 109 can be programmed with binary bits in 216 different ~ays. Each choice of ; programming of the 8-bik RAMs causes the combinational logic of element lOO to~ implement one of the 216=22 pos~ible logic ~20~ functions of the four binary varlables A, B, C and D. (Here K=4.) (A logic function is a binary valued function o~ binary variables.) ~ ~
For another selection of configuration control bits, swltch~107 provides feedback slgnal Q from storage circult 120 and s~71tches 101 through 103 and 104~through 107 and 113 and 114 ar~
configured as before. Then the combinational logic element 100 ; implements on~ o~ the 216722 poss1~ble~log1c functlons of the four binary var1ables ~, B, C and Q~for each choice of programm~ing of ~Z~5~i3~4~

70128~110 the two 8-bit RA~IS 108 and lO9. (Here again K=4.) For another selection of configuration control bits, switches 101 through 103 provide signals A, C and Q, and s~7itches 104 through 106 provide signals Br C, and Q, respectively, and the control signal applied to lead 115 causes switches 113 and 114 to provide ~he output signa:L of select 110 on lead F2 and the output signal of select 111 on lead F1, respectively. Thus, this con-figuration implements on lead F1 one of the 28=22 logic functions of the three binary variables A, C, and Q for each of the 28 possible programmings of 8-bit RAM 108 and on lead F2 implements one of the 2B logic functions of the three binary variables B, C

and Q for each of the 2 =2 possible programmings of RAM 109.
In cJeneral, for any first seleetion of three of the four variables A, B, C and D/Q, and for any second selection of three ;~ of the four variables A, B, C and DtQ, there is a configuration of :, :
the eombinational logic element 100 which implements one of the -~ 23 : ~ 2 logic functions of the first selection of -three variables on output Iead F2 for each of the 28 possible programmings of 8-bit RAM:108 a~d one of the 22 logic functions of ~he second selection 30 ;~ of three variables on output lead F1 for each of the 28 possible prog;ramminys of RAM 109.

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In another:embodiment (not shown), each of the 8-bit RAMs Day be "subdivided" by prov~idl~ng each with two additional one of four select logic so that any four binary functions of two of the variables A~ B. C and D/Q are implemented on four additional d~

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7312~-110 output leads of ~he eomb:Lnational logic element 100. Similarly, in another embodiment (not shown) a 32 bit RAM and the signals A, B, C, and D and the feedback signal Q are all used (so that K=5) ~ to implement in one configuration one of the 2~ binary functions ; corresponding to each programming of the 32 bit RAM (here N=4, M=1, and K=5). In another configuration (not shown) N=4, M=l, K=S, and a first binary function F1 of the variables A, B. C a second binary function F2 of the variables ~, C. D and a third binary fullction F3 of the variables B, C, D, Q are implemented.
It is important to observe that 2~ 2K2 ~ 2K3 = 2K where Ki' is the number of variables of which Fi is a function for i=l, 2, 3.
Re~urning to Figure 8, it is also important `:
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~ 25 ~36 4 ( -18-to observe that conflgurable switches 101, 102 and 103 select a subset of their input signals and provide the 3 selected subset of input signals on a one-to-one basis to 4 selected input leads of circuit 110. For example, in response to one set of values of configuxation signals, 6 configurable switches 101, 102 and 103 prcvide signal A
7 to lead 110-3, signal B to lead 110-2, and signal C to 8 lead 110-1.
9 The output signals on leads F1 and F2 are input signals to configurable storage circuit 120. Signals A, 11 C, and D are also input signals to storage circuit 120.
12 Configurable storage circuit 120 includes programmable 13 switches 122, 123, 126, 127 and 128, exclusive OR gates 14 124, 129 and 130, AND gates 125, 131 and 132, and storage element 121. Storage element 121 has a set, reset, data 16 and cloc~ input leads denoted by S, R, D and ~k, respec-17 tively, and output leads QFF and QLA-18 Switches 123, 126, 127 and 128 are each configured 19 to select one of their input signals as an output signal.
The set, clock, and reset functions associated with the 21 set, clock, and reset input leads of storage element 121 22 are all active high but each may be rendered active 10~7 " ,, '~ relative to the output signal of switches 123, 127, and 24 129 respectively by applying a logical 1 to the leads INVS, INVC, and INVR of exclusive or gates 124, 129, and 26 130 respectively. (If a logical 0 is applied to leads 27 INVS, INVC, and INVR, the polarity of the output signals 28 of the exclusive-or gates~124, 129, and 130 is the same 29 as that of the input signals. If a lo~ical l is applied to leads INVS; INVC, and INVR, the output signals of 31 exclusive-or gates 124, 129, and 130 are the inverse of 32 the input signals-) 33 The AND~ gates 125~, 131, and~132 are enabled by 34 applying a~logical 1 to the input leads ENS, ENC, and ENR
respectively (and disabled by;applying a logical 0). If 36 a~logical 0 is applied ~to~one of the input leads ENS, 37 ENC, or ENR, the output of the AND gate is a logical 0 ; ~ ~

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3L 2~iS36~ -19- f and the associated ~unction of memory circuit 121 is disabled regardless of the state of the corresponding exclusive OR gate- QFF provides a flip-flop output signal and QLA provides a latch output signal as explained later in eonjunction with Fig. 9. Configurable switch 6 122 selects one of the binary singals on leads QFF and QLA and the output signal Q of switch 122 is an input 8 signal to the output select logic 140 and to the configu-rable combinational logic 100. i, Fig. 9 shows one embodiment of memory circuit 121.
Memory element 121 comprises two "D" latches LAl and LA2 12 connected in series thereby implementing a flip-flop.
13 Latch LAl includes N chànnel pass transistors Pl and P2 14 and NOR gates Gl and G2. The gates of pass transistors Pl and P2 are controlled by the signals CK and CK, respec-16 tively. Similarly, latch LA2 ineludes N channel pass 17 transistors P3 and P4 and NOR gates G3 and G4. The gates ~8 o transistors P3 and P4 are controlled by the signals CK
19 and CK, respectively. The D input lead is the data input lead of latch LA1. The S input lead serves as the set 2L input lead of latch LA1 and as the reset input lead of 22 lateh LA2. The R input lead serves as the reset input ~3 lead of latch LA1 and as the set input lead of latch LA2.
24 The output signal~QLA of NOR gate Gl is connected to the data input lead of~latch LA2. The output lead QLA is 26 eonnected to the output lead of NOR gate G2 of latch LA1 27 and the output lead QPF is connected to the output lead of NOR gate G3 of latch LA2.
~:: :: ",~ , : ~ G~ Configurable storage circuit 120 (Fig. 8) operates as a transparent latch with s~t and reset by configuring 31 ~switch~122 to connect~output Iead Q to output lead QLA.
32 The output~signal on~lead ~QLA follows the input signal 3~3 ~while the clock signal GK is low. The output signal on 34 QLA is held when the clock signal CK goes high, turning off pass transistor Pl and~turning on pass transistor P2.
3~6 Thus, the data~slgnal 15 transmltted to output lead QLA.

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( ~5536~ -20 2 Storage circuit 120 may also be configured to operate as a D flip-flop with set and reset. In this configura-3 tion, switch 126 is configured -to select the signal on 4 lead Fl and gates 125, 131 and 132 are enabled by applying a logical 1 to leads ENS, ENC, and ENR, respectively.
6 Finally, switch 122 is configured to select the output 7 signal on lead QFF of storage element 121. Storage ~ element 120 may also be configured as a D flip-flop 9 without set and reset by modifying the above configura-tion by applying a logical zero to leads ENS and ENR.
11 Configurable storage circuit 120 may also be config-12 ured to be an RS latch by enabling AND gates 125 and 132, 13 and disabling AND gate 131 so that a logical 0 input 14 signal is provided on the Ck input lead of storage element 121. The logical 0 on lead Ck turns off pass transistor 16 P3 and turns on pass transistor P4. switch 122 is then 17 configured to select the output signal on QFF~
18 Finally, storage circuit 120 may also be configured 19 to be an edge detector. For example, to configure storage element I20 as a rising edge detector, AND gate 125 is 21 disabled to provide a logical 0 on input lead S, AND gate 22 131 is enabled to pass a clock signal to input lead Ck, 23 and switch 126 is configured to select input lead 126a so 24 that a logical 1 is provided to input lead D. AND gate 132 is enabled. A logical 1 reset signal forces the 26 output signal on QFF to a logical 0. A low clock signal 27 turns off pass transistor P2 and P3 and turns on pass Z~ transistor Pl, permitting NOR gate G1 to invert the 29 logical 1 on lead D, thus providing a logical 0 on node QLA. When the clock signal rises, transistors Pl and P4 31 are ~urned off, transistors P2~ and P3 are turned on, and 32 the logical 0 on node QLA is inverted by NOR gate 23, 33 thus providing a logical 1 on output lead QFF which 34 signals that a rising~edge has been detected. QFF is 3$ then reset to 0 using the reset input and the edge detector 36 is then ready to detect;the next rising edge. (Note that 37 when the clock signal falls, transistors P2 and P3 are . .

( ~25536~ -21-1 turned off and transistor P4 is turned on, and the signal 2 on QFF remains a logical 0 and does not change state 3 until the next rising edge.) 4 Similarly, storage circuit 120 may be configured as a falling edge detector by applying a logical one signal 6 to lead INVC of exclusive-or gate 129. Clearly, storage 7 circuit 120 may also serve as a stage of a shift register 8 or a stage of a counter.
9 The output select logic 140 includes configurable switches 141 and 142 which are each configured to select 11 an output signal from among the output signals on leads 12 F1 and F2 from the combinational logic lO0 and the output 13 signal of storage element 120.
14 The above embodiments are intended to be exemplary and not limiting. It will be obvious in view of the 16 disclosures made above that various substitutions and 17 modifications may be made without departing from the 18 spirit and scope of the invention.
19 In the claims which follow, the phase "means having a configuration in which said means'! performs a particular 21 function is used in place of the detailed wording "means 22 which are capable of being configured in response to a 23 selected set of values of a set of configuration signals 24 and which, when configured by said selected set of values,"
performs a particular function.

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Claims

-22- I claim:

1. A configurable logic element comprising:
means for receiving a first plurality of N
binary input signals;
means for receiving a second plurality of M
binary feedback signals;
means for selecting K of said M+N binary signals (where K?N+M);
combinational logic means for receiving said K
binary signals from said means for selecting, said combinational logic means having a plurality of configurations including at least a first configuration in which said combi-national logic means generates a first set of binary output signals, each of which represents a function of some of said K binary signals and a second configuration in which said configurable combinational logic means generates a second set of binary output signals, each of which represents a function of some of said K
binary signals, wherein the set of functions represented by said first set of binary signals is not the same as the set of functions repre-sented by said second set of binary signals;
a configurable storage circuit comprising:
a plurality of input leads for receiving a plurality of input signals, said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said binary output signals of said combinational logic means and selected ones of said N binary input signals, memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead;

first means having a first configuration in which said first means provides a first selected one of said input signals of said con-figurable storage circuit to said first input lead of said memory means;
second means having a first and a second configuration in which said second means provides a second and a third selected one, respectively, of said input signals of said configurable storage circuit to said second input lead of said memory means, said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and a configurable select logic comprising:
means for receiving said output signals gener-ated by said combinational logic means and said M
binary signals generated by said configurable storage circuit, and means for selecting output signals from among the signals received by said select logic.

2. A configurable logic element as in Claim 1 wherein said second means of said configurable storage circuit has a third configuration in which said second means provides the complement of said second selected one of said input signals to said second input lead of said memory means.

3. A configurable logic element comprising:
means for receiving a first plurality of N
binary input signals;
means for receiving a second plurality of M
binary feedback signals;
means for selecting K of said M+N binary signals of said first and said second plurality (where K?N+M);

configurable combinational logic means com-prising:
first configurable means for receiving said K binary input signals, said first config-urable means having at least a first configura-tion in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of output signals said second set being a second subset of said K input signals, wherein said first set is not equal to said second set;
first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;
first location selection means for receiving said output signals of said first configurable means and for selecting a storage location within said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory;
a configurable storage circuit comprising:
a plurality of input leads for receiv-ing a plurality of input signals said input signals corresponding to said input leads on a one-to-one basis, said input signals comprising selected ones of said output signals of said first location selection means and selected ones of said N binary input signals, memory means for storing data, said memory means having at least a first and a second input lead and at least one output lead;
first means having a first configura-tion in which said first means provides a first selected one of said input signals of said configurable storage circuit to said first input lead of said memory means;
second means having a first and a second configuration in which said second means provides a second and a third selected one, respectively, of said input signals of said configurable storage circuit to said second input lead of said memory means, said memory means generating said second plurality of M binary signals in response to said signals provided by said first and said second means; and a configurable select logic comprising:
means for receiving the output signals produced by said first location selection means of said combinational logic and said M binary signals; and means for selecting output signals from among the signals received by said select logic.

4. A configurable logic element as in Claim 3 wherein said configurable combinational logic means further comprises:
second configurable means for receiving said K
binary input signals, said second configurable means having at least a first configuration in which said second configurable means generates a third set of output signals, said third set being a third subset of said K input signals, and a second configuration in which said second configurable means generates a fourth set of output signals, said fourth set being a fourth subset of said K
input signals, wherein said third set is not equal to said fourth set;
second memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;
second location selection means for receiving said output signals of said second configurable means and for selecting a storage location within said second memory means in response to said output signals of said second configurable means, said second location selection means providing a second output signal representing the data bit stored in said selected storage location within said second memory;
steering logic means for receiving said first and said second output signals of said first and said second location selection means, said steering logic means having a first configuration in which said steering logic means provides a first output signal equal to said first output signal of said first location selection means and a second output signal equal to said second output signal of said second location selection means, said steering logic means having a second configuration in which said steering logic means provides an output signal equal to a selected one of said first and said second output signals of said first and said second location selection means, wherein said input signals of said configurable storage circuit further comprise selected ones of said output signals of said steering logic means, and wherein said means for receiving the output signals in said configurable select logic receives said output signals of said steering logic means.

26a

5. A configurable logic element as in Claim 4 wherein said second means of said configurable storage circuit has a third configuration in which said second means provides the complement of said second selected one of said input signals to said second input lead of said memory means.

6. A configurable logic element as in Claim 4 wherein the number of signals in each of said first, said second, said third and said fourth sets of output signals of said first and second configurable means of said configurable combinational logic means is L where L is a selected positive integer less than or equal to K.

7. A configurable logic element as in Claim 6 wherein L = K - 1.

8. A configurable logic element as in Claim 7 wherein said first memory means comprises 2K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed and wherein said second memory means comprises 2K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed.

9. A configurable logic element as in Claim 1 or 2, wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead.

10. A configurable logic element as in Claim 1 or 2, wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead and wherein said first means of said configurable storage circuit includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a second and a third configuration in which it provides said second and said third constant signal, respectively, to said first input lead.

11. A configurable logic element as in Claim 1 or 2, wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead and wherein said first means of said configurable storage circuit includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a second and a third configuration in which it provides said second and said third constant signal, respectively, to said first input lead and wherein said first input lead of said memory means of said configurable storage circuit is a data input lead, said second input lead of said memory means of said configurable storage circuit is a clock input lead, and wherein said memory means further comprises a set and a reset input lead.

-28a- 70128-110

12. A configurable combinational logic circuit comprising:
first configurable means for receiving K binary input signals, said first configurable means having at least a first configuration in which said first configurable means generates a first set of output signals said first set being a first subset of said K input signals, and a second configuration in which said first configurable means generates a second set of out signals said second set being a second subset of said K
input signals wherein said first set is not equal to said second set;
first memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;
first location selection means for receiving said output signals of said first configurable means and for selecting a storage location whithin said first memory means in response to said output signals of said first configurable means and for providing a first output signal representing the binary bit stored in said selected storage location within said first memory.

13. A configurable combinational logic circuit as in Claim 12 further including:
second configurable means for receiving said K
binary input signals, said second configurable means having at least a first configuration in which said second configurable means generates a third set of output signals, said third set being a third subset of said K input signals, and a second configuration in which said second configurable means generates a fourth set of output signals, said fourth set being a fourth subset of said K input signals, wherein said third set is not equal to said fourth set;
second memory means having a plurality of storage locations, each of said storage locations for storing a binary bit;
second location selection means for receiving said output signals of said second configurable means and for selecting a storage location within said second memory means in response to said output signals of said second configurable means, said second location selection means providing a second output signal representing the data bit stored in said selected storage location within said second memory;
steering logic means for receiving said first and said second output signals of said first and said second location selection means, said steering logic means having a first configuration in which said steering logic means provides a first output signal equal to said first output signal of said first location selection means and a second output signal equal to said second output signal of said second location selection means, said steering logic means having a second configuration in which said steering logic means provides an output signal equal to a selected one of said first and said second output signals of said first and said second location selection means;

14. A configurable logic element as in Claim 13 wherein the number of signals in each of said first, said second, said third and said fourth sets of output signals is L where L is a selected positive integer less than or equal to K.

15. A configurable logic circuit as in Claim 14 wherein L = K - 1.

16. A configurable logic element as in Claim 15 wherein said first memory means comprises 2K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed and wherein said second memory means comprises 2K-1 storage locations, each of said storage locations being capable of being programmed and reprogrammed.

17. A configurable storage circuit comprising:
memory means for storing data, said memory means having at least a first and a second input lead;
a first set of one or more input leads corres-ponding to said first input lead, each input lead of said first set for receiving a corresponding input signal;
a second set of one or more input leads corres-ponding to said second input lead, each input lead of said second set for receiving a corresponding input signal;
first means which, for each given lead in said first set, has a corresponding configuration in which said first means provides the input signal on said given lead to said first input lead;
second means which, for each given lead in said second set, has a corresponding first configuration in which said second means provides the input signal on said given lead to said second lead;

said memory means generating one or more output signals in response to said signals provided by said first means and said second means.

18. A configurable storage circuit as in Claim 17 wherein said second means, for some given lead in said second set, has a corresponding second configuration for providing the complement of the signal on said some given lead to said second lead.

19. A configurable storage circuit as in Claim 17 wherein said second means includes means for generating a first constant signal and has a configuration in which said second means provides said first constant signal to said second lead.

20. A configurable storage circuit as in Claim 19 wherein said first means includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a first and a second additional configuration in which it provides said second and said third constant signals, respectively, to said first input lead.

21. A configurable logic element comprising:
means for receiving a first plurality of N
binary input signals;
means for receiving a second plurality of M
binary feedback signals;
means for selecting K of said M+N binary signals (where K?N+M);
combinational logic means for receiving said K
binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating binary output signals;

a configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; and a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic.

22. A configurable logic element as in Claim 6, 7, or 8 wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead.

23. A configurable logic element as in Claim 6, 7, or 8 wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead and wherein said first means of said configurable storage circuit includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a second and a third configuration in which it provides said second and said third constant signal, respectively, to said first input lead.

24. A configurable logic element as in Claim 6, 7, or 8 wherein said second means of said configurable storage circuit includes means for generating a first constant signal and has a fourth configuration in which said second means provides said first constant signal to said second lead and wherein said first means of said configurable storage circuit includes means for generating a second constant signal and means for generating a third constant signal and wherein said first means has a second and a third configuration in which it provides said second and said third constant signal, respectively, to said first input lead and wherein said first input lead of said memory means of said configurable storage circuit is a data input lead, said second input lead of said memory means of said configurable storage circuit is a clock input lead, and wherein said memory means further comprises a set and a reset input lead.