CA1251555A - High efficiency technique for coding a digital video signal - Google Patents
High efficiency technique for coding a digital video signalInfo
- Publication number
- CA1251555A CA1251555A CA000497763A CA497763A CA1251555A CA 1251555 A CA1251555 A CA 1251555A CA 000497763 A CA000497763 A CA 000497763A CA 497763 A CA497763 A CA 497763A CA 1251555 A CA1251555 A CA 1251555A
- Authority
- CA
- Canada
- Prior art keywords
- digital video
- data
- dynamic range
- video data
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/98—Adaptive-dynamic-range coding [ADRC]
Abstract
ABSTRACT OF THE DISCLOSURE
An an apparatus for coding digital video data in the form of a blocks thereof, dynamic range information is generated from maximum and minimum values of the digital video data representing plural picture elements in each block, the minimum value is subtracted from each of the digital data to generate modified digital video data, the modified digital video data is encoded with a fixed digitized bit number less than that of the original digital video data, and the encoded data and an additional code for each block are transmitted, with such additional code being formed of at least two of the maximum and minimum values for the respective block and a signal corresponding to the dynamic range information for each block.
An an apparatus for coding digital video data in the form of a blocks thereof, dynamic range information is generated from maximum and minimum values of the digital video data representing plural picture elements in each block, the minimum value is subtracted from each of the digital data to generate modified digital video data, the modified digital video data is encoded with a fixed digitized bit number less than that of the original digital video data, and the encoded data and an additional code for each block are transmitted, with such additional code being formed of at least two of the maximum and minimum values for the respective block and a signal corresponding to the dynamic range information for each block.
Description
~s~s~
TITLE OF THE INVENTION
HIGH EFFICIENCY TECHNIQVE FOR CODING A DIGITAL VIDEO
SIGNAL
BACKGROUND OF T~E INVENTION
Field of the Invention - The present invention relates to a highly efficient technique for coding digital video signals and, in particular, to a highly efficient coding apparatus for compressing the data of digital video signals by dividing the data in each picture field into many blocks and processing each block separately.
Description of the Prior Art There are several known methods which effectively compress the data of the video signal by either directly reducing the number of bits per picture element, or reducing sampling frequency with each picture frame.
One known technique reduces the amount of data to 1/2 its original level by subsampling the image data in each field; that is, alternating picture elements are transmitted for the entire picuture field. At the receiver, the value of each non-transmitted picture eler,lent is approximately computed by performing an interpolation using the transmitted picture elements. Thus, the ;s effective sampling frequency is reduced by 50~.
Another technique, called DPCM (Differential Pulse Code Modulation), reduces the average number of bits per picture element. This technique takes advantage of the high level of correlation between adjacent picture elements. Basically, since the correlation between picture elements is high, the difference between adjacent picture elements is small. Thus, this difference between adjacent picture elements is transmitted, rather than the actual value of each picture element.
A third technique which reduces the average number of bits per picture element also capitali2es on the high level of correlation between adjacent picture elements. The picture is divided into many blocks.
In each block, a representative picture element is selected. Then, for each element in the block, a value corresponding to the deviation of this element's value from the representative value is transmitted.
The technique which uses sub-sampling (every other picture element is transmitted) is highly susceptible to aliasing because the sampling frequency has been effectively reduced by 50%.
In the DPCM method, coding errors tend to have serious consequences for subsequent coding.
The method which divides each picture field into ~s~
many blocks has a serious drawback in that block distortion occurs at the boundary between blocks.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly efficient coding apparatus which avoids the problems of the foregoing conventional technology, such as the occurrence of aliasing distortion, the propagation of coding error, and the occurrence of block distortion.
According to an aspect of this invention, each picture field is divided into a plurality of blocks.
Each block is then processed separately. First, the block's dynamic range (difference between the maximum and minimum picture element levels within the` block) and the minimum level are obtained. The block's dynamic range is now divided into equally spaced levels, and each picture element within the block is assigned to the nearest level. These levels are now assigned a digital value. For example, if there were 8 levels, then each level would be represented by a 3-bit number.
For transmission, the level assigned to a given picture element is transmitted, rather than the original picture element value. Also, for each block, the block's dynamic range and minimum level are transmitted. With this information, each picture element can be reconstructed at the receiver.
Since picture elements of a gi~en picture field are highly correlated ~oth spatially (in the horizontal and vertical directions~ and tempo~ally ~along the *ime base~, tAe dynamic range of t~e plcture element data included in a ~lock of one, two, or th~ee dimensions is small in non-moving portions of the picture field.
Since the dynamic range is s~all, then e~en if the num~er of new le~els used to di~ide tne dynamic range is smaller than tne sriginal num~er of le~els~ ~n the dynamic range, the digitizat~on disto~ion ~ill ~e ~ery small.
T~e ~ove ~nd o~ex o~ects, ~eatures ~nd advantages of t~e present in~ent~on-w~ ecome apparent from the ~ollo~,ng det~iled desc~ption ~h~ch ~s to ~e ~ead with ~eference to t~e acc~mpanying dra~ings.
.. . . .
B~IEF DESCRIPTION OF THE DR~N6~
-Fig. 1 is a block diagram of an em~odiment of the present invention;
Fig. 2 is a schematic diagram for explaining a ~lock as a uni,t ~nic~ i5 su~jecte~ to a co~ing proce~s;
Figs. 3A-3C are sc~ematic diagr~ms for explaining a plurality of examples of arrangements of transmission data;
Fig. 4 is a schemqtic di,agram for explaining the level distri~ution of the plcture element data in one ~lock;
5~5 Fig. 5 is a block diagram showing an example of an encoder block;
Fig. 6 is a schematic diagram for explaining the encoder block;
Fig. 7 i~ a block diagram showing another example of an encoder block;
Fig. 8 is a schematic diagram for explaining another coding method of an encoder block;
Fig. 9 is a block diagram showing still another example of an encoder block;
Fig. 10 is a schematic diagram for explaining a coding method of the encoder block of Fig. 9;
Fig. 11 is a block diagram showing another embodiment of the invention;
Fig. 12 is a schematic diagram for explaining a block as a unit which is subjected to a coding process in Fig. 11;
Fig. 13 is a block diagram showing an arrangement of the reception side;
Fig. 14 is a block diagram of a decoder; --Fig. 15 is a block diagram of an example of a decoderblock;
Fig. 16 is a block diagram of another example of a decoder block; and Fig. 17 is a block diagram of still another example ~1555 of a decoder block.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the present invention will now be described hereinbelow with reference to the drawings.
In Fig. 1, a digital video signal of eight bits is inputted in parallel to an input terminal 1. This input digital video signal is supplied to a subtracter 4 through a delay circuit 3.
A sampling clock synchronized with the input digital video signal is supplied to an input terminal 2. This sampling clock is supplied as a clock pulse to a counter 9 and registers 10 and 11. The counter 9 is a hexadecimal counter and a block clocksignal is generated as an output of this counter for every sixteen picture elements.
This block clock is supplied as a pulse for the initialization of registers 10 and 11. The block clock is also supplied as a latch pulse to latches 15 and 16.
Registers 10 and 11 can input and output 8-bit parallel data. An output data from register 10 is supplied to one input terminal of a selecting circuit 12. An output data of register 11 is supplied to one input terminal of a selecting circuit 13. The input digital video signal is supplied to the other input terminals of the selecting circuits 12 and 13.
The selecting circuit 12 is configured as a digital level comparator for selecting and outputting t~e larger-level of t~e two input data. T~e selecting circuit 13 is configured as a d~gital level comparator for selecting and ~utputting tne smaller-level of the two input data.
T~e digital output data of the selecting circuit 12 is supplied to one ~nput terminal of a su~tracter 14 and to the input terminal of t~e ~egister lQ. A digital output data of tne selecting ci~cuit 13 is supplied to tne otner input terminal of tne suBt~acter 14 and to the input terminal of tne register ll.
As shown ~n Fig. 2, in t~ts em~odiment, one hlock consists of data represent~ng 16 continuous picture elements of the same line, T~e ~lock clock from the counter 9 is generated at t~e first pos~ition of eac~ ~lock to in~tialize registers l~ and ll. All the ~its of register lO are initial~zed to ~on. ~ll o~ t~e ~lts of xegistex 11 are in~tialized to ~
The picture element data at the first position of one ~lock is select~d ~y the selecting circuits 12 and 13 and stored into tne registers lG and 11. Tne next picture element data is compared ~it~ tne picture element data stored in tne ~egisters l~ and ll and the data of the larger level ~s se~ected ~nd ~tp~ted rQm t~e selecting circuit 12. The data o~ t~e smaller lerel is selected and outputted ~rom t~e selecting c~xcuit ~S~ 5;
13. In a similar manner, all of the picture element data in one block are sequentially compared. Upon completion of this comparison, the Maximum level (MAX) of these 16 picture elements is selected and outputted at the output terminal of the selecting circuit 12.
The Minimum level (MIN) of these 16 picture elements is selected and outputted at the output terminal of the selecting circuit 13.
The subtracter 14 subtracts the minimum level MIN from the maximum level MAX, so that the dynamic range DR of the block is supplied at an output terminal of the subtracter 14. The dynamic range DR which is outputted from the subtracter 14 is latched in the latch 15. The minimum level MIN which is outputted from the selecting circuit 13 is latched in the latch 16. The dynamic ran~e DR stored in the latch 15 is taken out at an outpu~ terminal 6 and also supplied to an encoder block 5. The minimum level MIN stored in the latch 16 is taken out at output terminal 7 and also supplied to .he other input terminal of the subtracter 4. --The picture element data PD from the delay circuit3 is supplied to the subtracter 4. Thus, the data DTI
from which the minimum level MIN was removed is generated at the output terminal of the subtracter 4. The data DTI is supplied to the encoder block 5. As will be explained hereinafter, encoder ~loc~ 5 divides the dynamic range DR into sixteen equal levels~ The data DTI is no~
assigned to one of tH.ese 16 levels Sw~icHe~er is closest to the original ~aluel. This newly asslgned value determines to whicH.orig~nal DTI data value tHe picture element Belongs. THe fou~it DT code correspondlng to the appropr;ate le~el speci~ied in t~is manner is taken out at output terminal 8 o~ tne encoder Dloc~ 5.
As descri~ed aBo~e, tne dynam~c range D~ and the ~inimum le~el MIN are oBtained as additional data at tHe output term~nals 6 and 7 of tHe encoder s~own ~n Fig. 1. T~e compres~sed code of ~ou~ Bits is o~tained at t~e output terminal 8, One ~loc~ of tH.e original d~gital ~ideo s~gnal consists of 128 Bits C16 x 8 aitS~. In t~s em~odiment, one Block in the DT code is constituted ~y 8Q Bits C~ 16 x 4 Pits ~
16 ~itsI: tHus, the nu~e~ Xts to ~e transmitted ~as aeen r~duced. ~lt~o~g~ not sHown, tHe code DT and t~e additional data DR and MIN are s~jected to an error correction cod~ng process and transmitted Cor recorded in a recording mediumI as seriai data.
Figs. 3~-3C s~ow three examples o~ fo~mats for the transmission data. Fig. 3A sHow$ tHe case w~ere 64 Dits consisting o~ tHe mini~u~ level ~IN, dynamic ~ange DR, _ g ._ ~ S~S
and DT code are su~jected to the coding processes of independent error correction, and the parities of tne respective error correctlon codes are added to those data and the resultant data ls transmitted. ~ig. 3B
sho~s the case w~ere the ~ini~um le~el M~N and dynamic range DR are su~ected t~ tRe coding processes of independent error correction, and the pa~ities of the xespective error co~rection codes are added to the~
Fig. 3C shows the case wnexe ~oth of t~e ~inimum level M~ and dynamic range DR are sub~e~ted to t~e coding processes of common e~rQ~ cor~ection, and the parity of t~is er~or cor~ection code is added to t~em.
It is prefera~le t~at the num~er of digitaized ~itS
of the DT code is as s~al~ as possi~le to suppress redundancy. To prevent an ~ncxease in quantization distoxtion, ~owever, lt is undesira~le to overly reduce the num~er of digitized ~its. ~or ~ideo signals, t~e respecti~e p~cture elements in one Dloc~ ~ave ~igh correlation, so that the dynamic range DR in the non-moving portion of the picture i5 not so large, and it is sufficient to set the numDer of digitized ~its to a~out 128 as the maxi~um value.
~ s show~ ~n Fig. 4, in the case where the num~er of digitized ~lts is eight, a total of 256 (O to 255~ kinds of levels of the video sig~al can ~e presented. Ho~ever, in the non-motion portion of the picture, excluding the transient portion such as the contour of an object, the distribution of the levels of the picture elements of one block is concentrated in a fairly narrow range as shown in Fig. 4. Therefore, an increase of the digitization distortion can be prevented by setting the number of bits of the DT code to four, as in this embodiment.
For example, the number of digitized bits of the dynamic range DR becomes 128 in the worst case. Even in this case, when the number of digitized bits is four, the number of picture element levels within each DT level is 8, so the maximum digitization distortion becomes four. Such a degree of digitization distortion cannot be visually distinguished.
Fig. 5 shows one possible configuration of the encoder block 5. To simplify the explanation, the number of digitized bits is set to two instead of four, so the dynamic range is divided into four equal parts rather than sixteen.
In Fig. 5, the dynamic range DR is supplied to input terminal 21 and the data DTI from which ~he minimum level was removed is supplied to input terminal 22. The dynamic range DR is divided by 4 by divider 23 (consisting of a bit shifter to shift the input data by two bits).
~s~
An output of divider 23 is supplied to multipliers 24 and 25. Multiplier 24 triples the output of divider 23 and supplies this value to one input terminal of level comparator 26. Multiplier 25 doubles the output of divider 23 and supplies this value to one input terminal of level comparator 27. The output of the divider 23 is supplied to one input terminal of level comparator 28. The data DTI from which the minimum level was removed is supplied to the other input terminals of level comparators 26, 27, and 28, respectively.
Assuming that respective outputs of the level comparators 26 to 28 are Cl, C2, and C3, these outputs change as shown below in accordance with tie Level of the data DTI.
51) When (3/4).DR - DTI _ DR, Cl = 1 , C2 = 1 , C3 = 1 .
TITLE OF THE INVENTION
HIGH EFFICIENCY TECHNIQVE FOR CODING A DIGITAL VIDEO
SIGNAL
BACKGROUND OF T~E INVENTION
Field of the Invention - The present invention relates to a highly efficient technique for coding digital video signals and, in particular, to a highly efficient coding apparatus for compressing the data of digital video signals by dividing the data in each picture field into many blocks and processing each block separately.
Description of the Prior Art There are several known methods which effectively compress the data of the video signal by either directly reducing the number of bits per picture element, or reducing sampling frequency with each picture frame.
One known technique reduces the amount of data to 1/2 its original level by subsampling the image data in each field; that is, alternating picture elements are transmitted for the entire picuture field. At the receiver, the value of each non-transmitted picture eler,lent is approximately computed by performing an interpolation using the transmitted picture elements. Thus, the ;s effective sampling frequency is reduced by 50~.
Another technique, called DPCM (Differential Pulse Code Modulation), reduces the average number of bits per picture element. This technique takes advantage of the high level of correlation between adjacent picture elements. Basically, since the correlation between picture elements is high, the difference between adjacent picture elements is small. Thus, this difference between adjacent picture elements is transmitted, rather than the actual value of each picture element.
A third technique which reduces the average number of bits per picture element also capitali2es on the high level of correlation between adjacent picture elements. The picture is divided into many blocks.
In each block, a representative picture element is selected. Then, for each element in the block, a value corresponding to the deviation of this element's value from the representative value is transmitted.
The technique which uses sub-sampling (every other picture element is transmitted) is highly susceptible to aliasing because the sampling frequency has been effectively reduced by 50%.
In the DPCM method, coding errors tend to have serious consequences for subsequent coding.
The method which divides each picture field into ~s~
many blocks has a serious drawback in that block distortion occurs at the boundary between blocks.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly efficient coding apparatus which avoids the problems of the foregoing conventional technology, such as the occurrence of aliasing distortion, the propagation of coding error, and the occurrence of block distortion.
According to an aspect of this invention, each picture field is divided into a plurality of blocks.
Each block is then processed separately. First, the block's dynamic range (difference between the maximum and minimum picture element levels within the` block) and the minimum level are obtained. The block's dynamic range is now divided into equally spaced levels, and each picture element within the block is assigned to the nearest level. These levels are now assigned a digital value. For example, if there were 8 levels, then each level would be represented by a 3-bit number.
For transmission, the level assigned to a given picture element is transmitted, rather than the original picture element value. Also, for each block, the block's dynamic range and minimum level are transmitted. With this information, each picture element can be reconstructed at the receiver.
Since picture elements of a gi~en picture field are highly correlated ~oth spatially (in the horizontal and vertical directions~ and tempo~ally ~along the *ime base~, tAe dynamic range of t~e plcture element data included in a ~lock of one, two, or th~ee dimensions is small in non-moving portions of the picture field.
Since the dynamic range is s~all, then e~en if the num~er of new le~els used to di~ide tne dynamic range is smaller than tne sriginal num~er of le~els~ ~n the dynamic range, the digitizat~on disto~ion ~ill ~e ~ery small.
T~e ~ove ~nd o~ex o~ects, ~eatures ~nd advantages of t~e present in~ent~on-w~ ecome apparent from the ~ollo~,ng det~iled desc~ption ~h~ch ~s to ~e ~ead with ~eference to t~e acc~mpanying dra~ings.
.. . . .
B~IEF DESCRIPTION OF THE DR~N6~
-Fig. 1 is a block diagram of an em~odiment of the present invention;
Fig. 2 is a schematic diagram for explaining a ~lock as a uni,t ~nic~ i5 su~jecte~ to a co~ing proce~s;
Figs. 3A-3C are sc~ematic diagr~ms for explaining a plurality of examples of arrangements of transmission data;
Fig. 4 is a schemqtic di,agram for explaining the level distri~ution of the plcture element data in one ~lock;
5~5 Fig. 5 is a block diagram showing an example of an encoder block;
Fig. 6 is a schematic diagram for explaining the encoder block;
Fig. 7 i~ a block diagram showing another example of an encoder block;
Fig. 8 is a schematic diagram for explaining another coding method of an encoder block;
Fig. 9 is a block diagram showing still another example of an encoder block;
Fig. 10 is a schematic diagram for explaining a coding method of the encoder block of Fig. 9;
Fig. 11 is a block diagram showing another embodiment of the invention;
Fig. 12 is a schematic diagram for explaining a block as a unit which is subjected to a coding process in Fig. 11;
Fig. 13 is a block diagram showing an arrangement of the reception side;
Fig. 14 is a block diagram of a decoder; --Fig. 15 is a block diagram of an example of a decoderblock;
Fig. 16 is a block diagram of another example of a decoder block; and Fig. 17 is a block diagram of still another example ~1555 of a decoder block.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the present invention will now be described hereinbelow with reference to the drawings.
In Fig. 1, a digital video signal of eight bits is inputted in parallel to an input terminal 1. This input digital video signal is supplied to a subtracter 4 through a delay circuit 3.
A sampling clock synchronized with the input digital video signal is supplied to an input terminal 2. This sampling clock is supplied as a clock pulse to a counter 9 and registers 10 and 11. The counter 9 is a hexadecimal counter and a block clocksignal is generated as an output of this counter for every sixteen picture elements.
This block clock is supplied as a pulse for the initialization of registers 10 and 11. The block clock is also supplied as a latch pulse to latches 15 and 16.
Registers 10 and 11 can input and output 8-bit parallel data. An output data from register 10 is supplied to one input terminal of a selecting circuit 12. An output data of register 11 is supplied to one input terminal of a selecting circuit 13. The input digital video signal is supplied to the other input terminals of the selecting circuits 12 and 13.
The selecting circuit 12 is configured as a digital level comparator for selecting and outputting t~e larger-level of t~e two input data. T~e selecting circuit 13 is configured as a d~gital level comparator for selecting and ~utputting tne smaller-level of the two input data.
T~e digital output data of the selecting circuit 12 is supplied to one ~nput terminal of a su~tracter 14 and to the input terminal of t~e ~egister lQ. A digital output data of tne selecting ci~cuit 13 is supplied to tne otner input terminal of tne suBt~acter 14 and to the input terminal of tne register ll.
As shown ~n Fig. 2, in t~ts em~odiment, one hlock consists of data represent~ng 16 continuous picture elements of the same line, T~e ~lock clock from the counter 9 is generated at t~e first pos~ition of eac~ ~lock to in~tialize registers l~ and ll. All the ~its of register lO are initial~zed to ~on. ~ll o~ t~e ~lts of xegistex 11 are in~tialized to ~
The picture element data at the first position of one ~lock is select~d ~y the selecting circuits 12 and 13 and stored into tne registers lG and 11. Tne next picture element data is compared ~it~ tne picture element data stored in tne ~egisters l~ and ll and the data of the larger level ~s se~ected ~nd ~tp~ted rQm t~e selecting circuit 12. The data o~ t~e smaller lerel is selected and outputted ~rom t~e selecting c~xcuit ~S~ 5;
13. In a similar manner, all of the picture element data in one block are sequentially compared. Upon completion of this comparison, the Maximum level (MAX) of these 16 picture elements is selected and outputted at the output terminal of the selecting circuit 12.
The Minimum level (MIN) of these 16 picture elements is selected and outputted at the output terminal of the selecting circuit 13.
The subtracter 14 subtracts the minimum level MIN from the maximum level MAX, so that the dynamic range DR of the block is supplied at an output terminal of the subtracter 14. The dynamic range DR which is outputted from the subtracter 14 is latched in the latch 15. The minimum level MIN which is outputted from the selecting circuit 13 is latched in the latch 16. The dynamic ran~e DR stored in the latch 15 is taken out at an outpu~ terminal 6 and also supplied to an encoder block 5. The minimum level MIN stored in the latch 16 is taken out at output terminal 7 and also supplied to .he other input terminal of the subtracter 4. --The picture element data PD from the delay circuit3 is supplied to the subtracter 4. Thus, the data DTI
from which the minimum level MIN was removed is generated at the output terminal of the subtracter 4. The data DTI is supplied to the encoder block 5. As will be explained hereinafter, encoder ~loc~ 5 divides the dynamic range DR into sixteen equal levels~ The data DTI is no~
assigned to one of tH.ese 16 levels Sw~icHe~er is closest to the original ~aluel. This newly asslgned value determines to whicH.orig~nal DTI data value tHe picture element Belongs. THe fou~it DT code correspondlng to the appropr;ate le~el speci~ied in t~is manner is taken out at output terminal 8 o~ tne encoder Dloc~ 5.
As descri~ed aBo~e, tne dynam~c range D~ and the ~inimum le~el MIN are oBtained as additional data at tHe output term~nals 6 and 7 of tHe encoder s~own ~n Fig. 1. T~e compres~sed code of ~ou~ Bits is o~tained at t~e output terminal 8, One ~loc~ of tH.e original d~gital ~ideo s~gnal consists of 128 Bits C16 x 8 aitS~. In t~s em~odiment, one Block in the DT code is constituted ~y 8Q Bits C~ 16 x 4 Pits ~
16 ~itsI: tHus, the nu~e~ Xts to ~e transmitted ~as aeen r~duced. ~lt~o~g~ not sHown, tHe code DT and t~e additional data DR and MIN are s~jected to an error correction cod~ng process and transmitted Cor recorded in a recording mediumI as seriai data.
Figs. 3~-3C s~ow three examples o~ fo~mats for the transmission data. Fig. 3A sHow$ tHe case w~ere 64 Dits consisting o~ tHe mini~u~ level ~IN, dynamic ~ange DR, _ g ._ ~ S~S
and DT code are su~jected to the coding processes of independent error correction, and the parities of tne respective error correctlon codes are added to those data and the resultant data ls transmitted. ~ig. 3B
sho~s the case w~ere the ~ini~um le~el M~N and dynamic range DR are su~ected t~ tRe coding processes of independent error correction, and the pa~ities of the xespective error co~rection codes are added to the~
Fig. 3C shows the case wnexe ~oth of t~e ~inimum level M~ and dynamic range DR are sub~e~ted to t~e coding processes of common e~rQ~ cor~ection, and the parity of t~is er~or cor~ection code is added to t~em.
It is prefera~le t~at the num~er of digitaized ~itS
of the DT code is as s~al~ as possi~le to suppress redundancy. To prevent an ~ncxease in quantization distoxtion, ~owever, lt is undesira~le to overly reduce the num~er of digitized ~its. ~or ~ideo signals, t~e respecti~e p~cture elements in one Dloc~ ~ave ~igh correlation, so that the dynamic range DR in the non-moving portion of the picture i5 not so large, and it is sufficient to set the numDer of digitized ~its to a~out 128 as the maxi~um value.
~ s show~ ~n Fig. 4, in the case where the num~er of digitized ~lts is eight, a total of 256 (O to 255~ kinds of levels of the video sig~al can ~e presented. Ho~ever, in the non-motion portion of the picture, excluding the transient portion such as the contour of an object, the distribution of the levels of the picture elements of one block is concentrated in a fairly narrow range as shown in Fig. 4. Therefore, an increase of the digitization distortion can be prevented by setting the number of bits of the DT code to four, as in this embodiment.
For example, the number of digitized bits of the dynamic range DR becomes 128 in the worst case. Even in this case, when the number of digitized bits is four, the number of picture element levels within each DT level is 8, so the maximum digitization distortion becomes four. Such a degree of digitization distortion cannot be visually distinguished.
Fig. 5 shows one possible configuration of the encoder block 5. To simplify the explanation, the number of digitized bits is set to two instead of four, so the dynamic range is divided into four equal parts rather than sixteen.
In Fig. 5, the dynamic range DR is supplied to input terminal 21 and the data DTI from which ~he minimum level was removed is supplied to input terminal 22. The dynamic range DR is divided by 4 by divider 23 (consisting of a bit shifter to shift the input data by two bits).
~s~
An output of divider 23 is supplied to multipliers 24 and 25. Multiplier 24 triples the output of divider 23 and supplies this value to one input terminal of level comparator 26. Multiplier 25 doubles the output of divider 23 and supplies this value to one input terminal of level comparator 27. The output of the divider 23 is supplied to one input terminal of level comparator 28. The data DTI from which the minimum level was removed is supplied to the other input terminals of level comparators 26, 27, and 28, respectively.
Assuming that respective outputs of the level comparators 26 to 28 are Cl, C2, and C3, these outputs change as shown below in accordance with tie Level of the data DTI.
51) When (3/4).DR - DTI _ DR, Cl = 1 , C2 = 1 , C3 = 1 .
(2) When (2/4)-DR ~ DTI < (3/4)-DR, Cl = "0"~ C2 = 1 , C3
(3) When (1/4)-DR - DTI < (2/4)-DR
Cl ' C2 = " C3 = "1".
Cl ' C2 = " C3 = "1".
(4) When O _ DTI < (1/4)-DR, C1 = "O", C2 = O , C3 The outputs Cl, C2, and C3 of level comparators 26 to 28 are supplied to priority encoder 29. The two-bit code DT is obtained at the output terminal 8 of priority ~2 5~
encoder 29. The encoder 2Q generates a code of ~1 11 ln case Cll, a code of Cl 01 ~n case L21, a c~de of (a 11 in case ~3~, and a code of ~Q 01 in case C41.
~ s shown in ~ig. 6, the picture element data PD
of one ~loc~ falls wit~n tRe dynamic range DR from the minimum le~el MIN to th.e maxi~um level MAX. The divider 23 and multtpl~ers 24 and 25 divide the dynamic ~ange DR
~nto ~our equ~l parts, ComparatorS 26 to 28 determine to which of the 4 levels e~c~ data DTI ~elongs, and t~e result is con~erted to a t~o-~.t code cor~esponding to tne level xange c~osen, F~. 7 s~ows an example of anotn.0r arrangement of the encoder ~loc~ 5. T~e dy~amic range DR ~rom input terminal 21 is di~ided ~y 4 ~ d~der 31. An output signal o~ di~ider 31 ~.s supplied as t~e denominator input to digital divider 3Q. T~e dat~ DTI ~after t~e xemo~al of the minimum le~ell ~S supplied at input terminal 22 as~ tne numerator input to di~idex 3a. T~e t~o~ t code DT is taken at the output of dlv~.der 3Q. The d~ider 3Q generates a t~o-~it output co~xesponding to the value of t~e DT code.
Also, alt~oug~.not s~own~ t~e encoder ~loc~ 5 may be xealized ~y a ROM to ~hich a total of sixteen Dits Cthe digital data DTT a~tex t~e re~ov~l of ten minlmum level and the dynamic ~ange D~I ~re ~upplied as an addxess, In t~is emBodiment, as is~ evident f~om Fig. 6, t~e ~5~ S
dynatic range is divided into equal parts, and t~e central values LQ, Ll, L2, and ~3 of eac~ part are used as ~alues upon decoding. This coding~decvding method ~elps reduce digitization distortion, Howe~er~ the picture ele~ent data Havinq the min~mum level MIN and the maximum level MAX exist in eac~ Block.
Therefore, as shown in ~ig. 8, t~e ~ncrease t~e number of of codes naving no erro~, tne ~ynam~c range DR is d~ided into (2m - 1~ equal parts Cw~ere m is t~e num~er of digit~ized ~itsl. In this w~, t~e ~nimum level MIN
m~y be set to tne xepresentative le~el L~ and tne maximum le~el MAX may ~e set to t~e representati~e lerel L3.
Fig~ q sho~s an axrangement o~ s~ not~er ex~mple of encoder ~loc~ 5, ln ~ig~ ~, t~e dat~ DTI Cafter the ~emovAl of t~e minimum le~ell is s~plied to an ~nput ter~n~l 161 and stored ~nto reg~ster 162. An output of register 162 is supplied tQ an input ter~inal o~ a ~t selectlng circuit 163, The dynamic range DR ~om l~tc~ ci~cuit 15 in Fig. 1 is supplied to an input te~m~nal 164, Tne dynam~c range DR is supplied to a priorit~ encoder 165. The ~it select-ing circuit 163 is controlied ~y an output of tn~ee ~its of encoder 165, Among ~e e~g~ ts of the dat~ PTI, ~our ~its cox~esponding to tne output of tHe encode~ 165 are selected ~y tne Dit selecting ci~cu~t 163, The output data of the priority encoder 165 is taken out as a dynamic range data DR2 which are transmitted to the output terminal 6. The four-bit output data of the bit selecting circuit 163 is taken at the output terminal 8 and transmitted as the code DT.
The priority encoder 165 ~enerates the three-bit output (C2, Cl, C0) in correspondence to the bit patter~
of the high order four bits of the dyn mic range DR.
In response to the output of the encoder 165, the bit selecting circuit 163 -seleets four bits (Y3, Y2, Yl, Y0) from among eight bits (X7, X6, ..., X0) of the data DTI (after ~he removal of-the minimum level) and outputs this four-bit data as the code DT.
The relation between the output of the priority encoder 155 corresponding to the high order four bits of the dynamic range DR and the output of four bits of the bit selecting circuit 163 which are selected by-an output of the priority encoder 165 is shown in the table below.
. Outputs of the bit DR selecting circuit MSB C2 Cl C0 Y3 Y2 Yl Y0 0 1 / / 0 0 1 X6 X5 X4 X3 .. .. . .
0 0 0 1 0 1 1 X4 X3 X2 Xl 0 0 0 0 1 0 0 X3 X2 Xl X0 . _ .
The magnitude of the dynamic range DR is detected from the high order four bits and the minimum digitization unit is selected on the basis of the magnitude of the dynamic range DR. t 2' 1' CO) indicative of the digitization unit are transmitted as the dynamic range informaiton DR2.
In Fig. 10, a reference numeral 171 denotes four bits which are selected when. the most significant bit MSB of the dynamic range DR is "1". In this case, the minimum digitization unit is 16. Numeral 172 denotes four bits which are selected when .he MSB of the dynamic range DR is "O" and the second high order bit is "1".
In this case, the minimum digitization unit is 8. Numeral 173 indicates four bits which are selected when the MSB
and the second high order bit of the dynamic range DR
are "O" and the third high order bit is "1". In this case, the minimum digitization unit is 4. Numeral 174 represents four bits which are selected when the MSB
and the second and third high order bits of the dynamic range DR are "O" and the fourth high order bit is-"l".
In this case, the minimum digitization unit is 2. Numeral 175 indicates four bits which are selected when all of the high order four bits of the dynamic range are "O"
In this case, the minimum digitization unit is 1.
Another embodiment of the invention, namely, an example whereby the invention is applied to picture elements of a two-dimensional block will now be explained with reference to the drawings. Fig. 11 shows the entire arrangement of an encoder for this embodiment. A digital video signal of the NTSC system in which, for example, one sample is digitized to eight bits, is inputted to an input terminal 101. This digital video signal is supplied to a cascade connection of line delay circuits 102 and 103, and to a cascade connection of five sample delay circuits 111 to 115.
A cascade connection of five sample delay circuits 121 to 125 is connected to the connecting point of the line delay circuits 102 and 103. A cascade connection of five sample delay circuits 131 to 135 is connected to the output terminal of line delay circuit 103. Due to the line delay circuits 102 and 103 ~each having a delay amount of one line period) and the sample delay circuits 111 to 115, 121 to 125, and 131 to 135 (each having a delay amount equal to the sampling period of the input digital video signal), the picture element data of one block can be simultaneously obtained from output terminals of the respective delay circuits.
In Fig. 12, a reference numeral 100 indicates one block, solid lines denote continuous n-th, (n+l)-th, and (n+2)-th lines of the current field, and broken .. . . . . . . . .
~ r~
lines represent lines of the -next fields. One block consists of three lines. Each line contains six picture elements. When the picture element data of the (n+2)-th line is supplied to the input texminal 101, the picture element data of the tn+1)-th line is generated at an output of the line delay circuit 102, and the picture element data of the n-th line is generated at an output of the line delay circuit 103. Six picture element data from each line are accessed at the input and output terminals of each cascade connection of the sample delay circuits, as well as between each of the delay circuits.
Two of the six picture element data of the same line (taken out by the cascade connection of the sample d~lay circuits 111 to 115) are supplied to each of the three selecting circuits 116, 117, ~nd 118, respectively.
Similarly, selecting circuits 126, 127, and 128 nre each supplied with two picture element data from sample delay circuits 121 to 125. As well, selecting circuits 136, 137, and 138 are each supplied with two picture element data from sample delay circuits 131 to 135. Each of these selecting circuits is a digital level comparator which is configured to compare the levels of two picture element data inputted, and output the picture element data of larger magnitude at one output terminal and output the picture element data of smaller magnitude at the ~ s~
other output terminal.
one output terminal of each of the selecting circuits 116 and 117 is connected to an input terminal of a selecting circuit 141. The other output terminals of the selecting circuits 116 and 117 are connected to an input terminal of a selecting circuit 151. One output terminal of each of the selecting circuits 118 and 126 is connected to an input terminal of a selecting circuit 142 and the other output terminals of the selecting circuits 118 and 126 are connected to an input terminal of a selecting circuit 152. One ouput terminal of each of the selecting circuits 127 and 128 is connected to an input terminal of a selecting circuit 143 and the other output terminals of the selecting circuits 127 and 128 are connected to an input terminal of a selecting circuit 153. One output terminal of each of the selecting circuits 136 and 137 is connected to an input terminal of a selecting circuit 144 and the other output terminals of the selecting circuits 136 and 137 are connected to an input terminal of a selecting circuit 154.
Each of the selecting circuits 141 to 144 is a digital level comparator which is configured to compare the levels of two picture element data inputted and selectively output only the picture element data of larger magnitude Each of the selecting circuits 15]. to 154 is a digital -- 19 - ' level comparator which is configured to compare the levels of two picture element data inputted and selectively output only the picture element data of smaller magnitude.
The outputs of the selecting circuits 141 and 142 are supplied to a selecting circuit 145. The outputs of the selecting circuits 143 and 144 are supplied to a selecting circuit 146. The outputs of the selecting circuits 145 and 146 are supplied to a selecting circuit 147. The output of the selecting circuit 147 and the output of the larger level of the selecting circuit 138 are supplied to a selecting circuit 148. The selecting circuits 145 to 148 selectively output the picture element data of larger magnitude sim1lar to the selecting circuits 141 to 144. Therefore, the picture element data of the maximum elvel MAX among eighteen picture element data in the block 100 -is generated at an output terminal of the selecting circuit 148.
The outputs of the selecting circuits 151 and 152 are supplied to a selecting circuit 155. The outputs of the selecting circuits 153 and 154 are supplied to a selecting circuit 156. The outputs of the selecting circuits 155 and 156 are supplied to a selecting circuit 157. The output of the selecting circuit 157 and the output of the smaller level of the selecting circuit 138 are supplied to a selecting circuit 158. The ~:~5~S
selecting circuits 155 to 158 selectively output the picture element data of smaller magnitude, similar to the selecting circuits 151 to 154. Therefore, the picture element data of the minimum level MIN among eighteen picture element data in the block 100 is generated at an output terminal of the selecting circuit 158.
The outputs of the selecting circuits 148 and 153 are supplied to subtracter 149. The subtracter 149 subtracts the minimum level MIN from the maximum level MAX, so that the dynamic range DR of eight bits is obtained at an output terminal 106. The minimum level MIN is taken out at an output terminal 107 and supplied to a subtracter 150.
The picture element data PD generated at the output;
of the sample delay circuit 135 is supplied to the subtracter 150 through a delay circuit 104. The delay circuit 104 has a delay amount equal to the time lag which is caused by the detection of the maximum level MAX and minimum level MIN as mentioned above. The picture element data DTI of eight bits from which the minimum level was removed is obtained at the output of the subtracter 150.
The dynamic range DR and the picture element data DTI (after the removal of the minimum level) are supplied to an encoder block 105. The encoder block 105 divides ; ~ r~
the dynamic range DR ~nto equal parts according to the num~er of digit~zed ~its C~our ~ts in this examplel, and determines ~n ~hic~ one of tne divided areas the picture element data DTI Cafter the removal of the minimum levelL is ~ncluded, and genera~es the ~our-~t ~ode DT
to spec~iy t~e decided aea at an output terminal lQ8.
T~e ar~angement sho~n i~n Fig, 5, 7, or ~ may ~e used as a practical arrangement of encsder ~loc~ 5.
~ s descri~ed a~ove, t~e dynam~c range DR and minimum le~el MIN are o~tained as additional data, are o~tained at t~e output ter~inals la6 and ln7 of the encoder shown in ~ig. 11, TRe compressed code o~ ~our ~its is deri~ed at the output ter~inai lQ8.
One block of the original digital video signal consists of 144 bits (= 3 x 6 x 8 ~its~. According to this embodiment, one block of the transmitted signal consists of 88 bits ~= 3 x 6 x 4 ~its ~ 16 ~itsl, so that the number of ~its to ~e transmitted can De reduced ~y about one half.
Tne code DT whica is o~tained at t~e output terminal lQ8 o~ t~e encoder nas the same ~e~uence as t~e input video s~gnal. Therefore, t~e additional data M}N and DR oX eac~ Bloc~ are yenerated for eye~y t~ree l~nes with respect to tne line, and ~o~ e~ery SlX samples witA
regard to the s~mpll'ng direction. ~nen t~e transmission data is di~ided for e~ery predete~mined amount of the ~s~
code DT, an interval including no additional data occurs in the transmission process. Therefore, a buffer memory is connected to the output of the encoder and the additional data DR and MIN and the code DT of one block may be used as a unit of transmission. In this case, the length of the data portion consisting of the coded code DT in Fig. 3 becomes 64 bits (= 4 bits x 16).
Fig. 13 shows an arrangement of the reception (or reproduction) side. Reception data from an input terminal 41 is supplied to a data separating circuit 42, by which the DT code and additional codes are separated. The additional codes, namely, the minimum level MIN and dynamic range DR, are supplied to an error correcting circuit 43 to correct any transmis-sion error. An error concealing circuit 44 is connected to the error correcting circuit 43. The error concealing circuit 44 conceals (interpolates) the additional codes which could not -be corrected on the basis of an error flag from the error correcting circuit 43.
The additional codes which are outputted from the error concealing circuit 44 and the coded code DT, the timing of which was matched by a delay circuit 47, are supplied to a decoder 45. The code DT is decoded by the decoder ~5 and the original picture element data PD is taken out at an output terminal 46 of the decoder 45. The decoder 45 decodes the eight-bit picture element data PD from the additional codes DR and MIN, each consisting of eight bits, and from the 4-bit DT code.
The decoder 45 is configured as shown in Fig. 14.
In Fig. 14, the code DT, dynamic range DR, and minimum level MIN from input terminals 4B, 49, 4nd 50 are stored into latches 51, 52, and 53, respectively.
Tbe code DT from the latch 51 ~nd the dynamic range DR from the latch 52 are supplied to a decoder block 54. The data DTI tafter the removal of the minimum level) is decoded by the decoder block 54. The data DTI ~nd the minimum level MIN from th~ latch S3 are added by an adder 55, so that the picture element da~a PD is taken out at an output terminal 56 of the adder 55. The decoder block 54 decodes the representative value corresponding to the code DT.
Fig. 15 shows an arrangement of one example of the decoder block 54. In the decoder block shown in Pig.
lS and a decoder block shown in Fig. 16 which will be mentioned later,it is assumed that the number of digitized bits of the DT code is two for simplicity of explanation.
..
The decoder block of Fig. 15 has an arrangement corresponding to the encoder block shown in Fig. S.
~ 35 The dynamic range DR from an input terminal 61 is d~vided Py 4 ~y a divider 63 Cwh~c~ is comprised of a Pit shifter to shift data ~y two ~.~tsl and the resultant data is supplied to multlpliers 64 and 65. The multiplier 64 triples the output of the divlder 63, and multipl1er 65 dou~les the output of t~e d~vider 63. The outputs of the multipliers 64 and 65, the outpui of the di~ider 63, and t~e code in ~hich eig~t ~its are all "~" a~e suppiied to a selector 66~ The selecto~ 66 selects e~t~er one of tne four inpuis ~n cor~espondence to t~e code DT ~rom the input terminal 62 and outputs o~ t~e selected lnput.
When t~e code DT is CQ ~I, tne selector 66 selects the code of zer~ W~en t~e coded code DT is CO lI, the selector 66 selects t~e output a DRl of the divider 63. ~en tHe DT is Cl Ql, t~e selector 66 selects the output C2 DRI of tne multiplier 65. ~en t~e DT is (1 11, the selector 66 selects ~e output C3 DRl o~ the multiplier 64. Tne output of the selector 66 is suPplied to an adder 68, The output of th.e di~ider 63 is divided Py 2 Py a di~ider 67, ~nd tn.e resultant data is supplied to the adder 68. T~exefore, t~e data DTI after the removal of the ~inimum le~el ~s o~tained at an output terminal 6~ of the adder 68, Fig. 16 shows another example of the decoder ~lock 54. The example shown in ~ig. i6 ~as an arrangement ~ S~3~
corresponding to the encoder block shown in Fig. 7.
In Fig. 16, a digital multipller 71 multipl~es a value of Cl DRl from ~ diyider 70 and t~e code DT ~rom the input terminal 62. T~e multiplled output of t~e multiplier 71 and a data of Cl D~I f~om a divlder 72 are supplied to an adder 73. Tne data DTI a~ter the removal of t~e m~nimum le~el is taken out ~t the output terminal 6~ of t~e adder 73.
~ ig. 17 shows still ~not~er example of t~e decoder ~lock 54 and has an a~angement corresponding to t~e encoder ~lock s~o~n in P~g, Y, In ~g. 17, t~e input d~ta PT is supplied to an input ter~inal 181 and t~e dy~amic range ~nformation DR2 inputted ts supplied to an ~nput terminal 182. The minimum level M~N is supplied to an tnput term~nal 183, The data DT is supplied to ~ selecting circuit 184. T~e seiection circuit 184 generates an ou~put ~ eig~t ~i~s selected on t~e ~asis of the d~na~c ~ange info~mation DR2 from among five kinds o~ ~ig~ t data ~n ~ic~
fou~ ~0" ~its of total fou~ ~ts were ~dded to t~e ~igh order side or lo~ order side of the dat~ DT of four ~its.
TRe output dat~ of t~e select~ng ci~cuit 184 corresponds to tRe data DT~ a~ter t~e removal of the minimum le~el. T~e output of t~e selecting circu~t 184 ~ 3~
i5 supplied to one input terminal of an adder 185. The minimum level MIN is supplied to the other input terminal of the adder 185. The picture e~lement dat& PD is taken out at an output terminal 186 of the adder 185.
In the above description, three data of the code ~T, dynamlc range DR, and minimum level MIN are transmitted. However, as the additional codes, the minimum level MIN and maximum level MAX, or the dynamic range DR and maximum level MAX may be transmitted.
Further, inste~d of transmitting the dynamic range DR, the minimum digitization level which is formed by this signal may be tr~nsmitted in place of this signal.
According to the present invention, the amount of data to be transmitted can be reduced compared with the amount of original data. Thus, the transmission band can be narrowed. In addition, this invention has an ~dvantage such that in the non-moving portion of the picture where the dynamic range of picture element data is small, the original picture element data can be completely recovered from the received data with little or no deterioration of picture quality. Moreover, according to the invention, ince ~he dynamic range is evaluated separately for each block, the reconstructed pictured responds very well to motion in the moving part of the picture such as the edge where thç dynamic range ~;~5~ 5 is large.
The present invention is not limited to the foregoing embodiments but many modifications and variations are possible within the spirit and scope of the appended claims of the invention.
encoder 29. The encoder 2Q generates a code of ~1 11 ln case Cll, a code of Cl 01 ~n case L21, a c~de of (a 11 in case ~3~, and a code of ~Q 01 in case C41.
~ s shown in ~ig. 6, the picture element data PD
of one ~loc~ falls wit~n tRe dynamic range DR from the minimum le~el MIN to th.e maxi~um level MAX. The divider 23 and multtpl~ers 24 and 25 divide the dynamic ~ange DR
~nto ~our equ~l parts, ComparatorS 26 to 28 determine to which of the 4 levels e~c~ data DTI ~elongs, and t~e result is con~erted to a t~o-~.t code cor~esponding to tne level xange c~osen, F~. 7 s~ows an example of anotn.0r arrangement of the encoder ~loc~ 5. T~e dy~amic range DR ~rom input terminal 21 is di~ided ~y 4 ~ d~der 31. An output signal o~ di~ider 31 ~.s supplied as t~e denominator input to digital divider 3Q. T~e dat~ DTI ~after t~e xemo~al of the minimum le~ell ~S supplied at input terminal 22 as~ tne numerator input to di~idex 3a. T~e t~o~ t code DT is taken at the output of dlv~.der 3Q. The d~ider 3Q generates a t~o-~it output co~xesponding to the value of t~e DT code.
Also, alt~oug~.not s~own~ t~e encoder ~loc~ 5 may be xealized ~y a ROM to ~hich a total of sixteen Dits Cthe digital data DTT a~tex t~e re~ov~l of ten minlmum level and the dynamic ~ange D~I ~re ~upplied as an addxess, In t~is emBodiment, as is~ evident f~om Fig. 6, t~e ~5~ S
dynatic range is divided into equal parts, and t~e central values LQ, Ll, L2, and ~3 of eac~ part are used as ~alues upon decoding. This coding~decvding method ~elps reduce digitization distortion, Howe~er~ the picture ele~ent data Havinq the min~mum level MIN and the maximum level MAX exist in eac~ Block.
Therefore, as shown in ~ig. 8, t~e ~ncrease t~e number of of codes naving no erro~, tne ~ynam~c range DR is d~ided into (2m - 1~ equal parts Cw~ere m is t~e num~er of digit~ized ~itsl. In this w~, t~e ~nimum level MIN
m~y be set to tne xepresentative le~el L~ and tne maximum le~el MAX may ~e set to t~e representati~e lerel L3.
Fig~ q sho~s an axrangement o~ s~ not~er ex~mple of encoder ~loc~ 5, ln ~ig~ ~, t~e dat~ DTI Cafter the ~emovAl of t~e minimum le~ell is s~plied to an ~nput ter~n~l 161 and stored ~nto reg~ster 162. An output of register 162 is supplied tQ an input ter~inal o~ a ~t selectlng circuit 163, The dynamic range DR ~om l~tc~ ci~cuit 15 in Fig. 1 is supplied to an input te~m~nal 164, Tne dynam~c range DR is supplied to a priorit~ encoder 165. The ~it select-ing circuit 163 is controlied ~y an output of tn~ee ~its of encoder 165, Among ~e e~g~ ts of the dat~ PTI, ~our ~its cox~esponding to tne output of tHe encode~ 165 are selected ~y tne Dit selecting ci~cu~t 163, The output data of the priority encoder 165 is taken out as a dynamic range data DR2 which are transmitted to the output terminal 6. The four-bit output data of the bit selecting circuit 163 is taken at the output terminal 8 and transmitted as the code DT.
The priority encoder 165 ~enerates the three-bit output (C2, Cl, C0) in correspondence to the bit patter~
of the high order four bits of the dyn mic range DR.
In response to the output of the encoder 165, the bit selecting circuit 163 -seleets four bits (Y3, Y2, Yl, Y0) from among eight bits (X7, X6, ..., X0) of the data DTI (after ~he removal of-the minimum level) and outputs this four-bit data as the code DT.
The relation between the output of the priority encoder 155 corresponding to the high order four bits of the dynamic range DR and the output of four bits of the bit selecting circuit 163 which are selected by-an output of the priority encoder 165 is shown in the table below.
. Outputs of the bit DR selecting circuit MSB C2 Cl C0 Y3 Y2 Yl Y0 0 1 / / 0 0 1 X6 X5 X4 X3 .. .. . .
0 0 0 1 0 1 1 X4 X3 X2 Xl 0 0 0 0 1 0 0 X3 X2 Xl X0 . _ .
The magnitude of the dynamic range DR is detected from the high order four bits and the minimum digitization unit is selected on the basis of the magnitude of the dynamic range DR. t 2' 1' CO) indicative of the digitization unit are transmitted as the dynamic range informaiton DR2.
In Fig. 10, a reference numeral 171 denotes four bits which are selected when. the most significant bit MSB of the dynamic range DR is "1". In this case, the minimum digitization unit is 16. Numeral 172 denotes four bits which are selected when .he MSB of the dynamic range DR is "O" and the second high order bit is "1".
In this case, the minimum digitization unit is 8. Numeral 173 indicates four bits which are selected when the MSB
and the second high order bit of the dynamic range DR
are "O" and the third high order bit is "1". In this case, the minimum digitization unit is 4. Numeral 174 represents four bits which are selected when the MSB
and the second and third high order bits of the dynamic range DR are "O" and the fourth high order bit is-"l".
In this case, the minimum digitization unit is 2. Numeral 175 indicates four bits which are selected when all of the high order four bits of the dynamic range are "O"
In this case, the minimum digitization unit is 1.
Another embodiment of the invention, namely, an example whereby the invention is applied to picture elements of a two-dimensional block will now be explained with reference to the drawings. Fig. 11 shows the entire arrangement of an encoder for this embodiment. A digital video signal of the NTSC system in which, for example, one sample is digitized to eight bits, is inputted to an input terminal 101. This digital video signal is supplied to a cascade connection of line delay circuits 102 and 103, and to a cascade connection of five sample delay circuits 111 to 115.
A cascade connection of five sample delay circuits 121 to 125 is connected to the connecting point of the line delay circuits 102 and 103. A cascade connection of five sample delay circuits 131 to 135 is connected to the output terminal of line delay circuit 103. Due to the line delay circuits 102 and 103 ~each having a delay amount of one line period) and the sample delay circuits 111 to 115, 121 to 125, and 131 to 135 (each having a delay amount equal to the sampling period of the input digital video signal), the picture element data of one block can be simultaneously obtained from output terminals of the respective delay circuits.
In Fig. 12, a reference numeral 100 indicates one block, solid lines denote continuous n-th, (n+l)-th, and (n+2)-th lines of the current field, and broken .. . . . . . . . .
~ r~
lines represent lines of the -next fields. One block consists of three lines. Each line contains six picture elements. When the picture element data of the (n+2)-th line is supplied to the input texminal 101, the picture element data of the tn+1)-th line is generated at an output of the line delay circuit 102, and the picture element data of the n-th line is generated at an output of the line delay circuit 103. Six picture element data from each line are accessed at the input and output terminals of each cascade connection of the sample delay circuits, as well as between each of the delay circuits.
Two of the six picture element data of the same line (taken out by the cascade connection of the sample d~lay circuits 111 to 115) are supplied to each of the three selecting circuits 116, 117, ~nd 118, respectively.
Similarly, selecting circuits 126, 127, and 128 nre each supplied with two picture element data from sample delay circuits 121 to 125. As well, selecting circuits 136, 137, and 138 are each supplied with two picture element data from sample delay circuits 131 to 135. Each of these selecting circuits is a digital level comparator which is configured to compare the levels of two picture element data inputted, and output the picture element data of larger magnitude at one output terminal and output the picture element data of smaller magnitude at the ~ s~
other output terminal.
one output terminal of each of the selecting circuits 116 and 117 is connected to an input terminal of a selecting circuit 141. The other output terminals of the selecting circuits 116 and 117 are connected to an input terminal of a selecting circuit 151. One output terminal of each of the selecting circuits 118 and 126 is connected to an input terminal of a selecting circuit 142 and the other output terminals of the selecting circuits 118 and 126 are connected to an input terminal of a selecting circuit 152. One ouput terminal of each of the selecting circuits 127 and 128 is connected to an input terminal of a selecting circuit 143 and the other output terminals of the selecting circuits 127 and 128 are connected to an input terminal of a selecting circuit 153. One output terminal of each of the selecting circuits 136 and 137 is connected to an input terminal of a selecting circuit 144 and the other output terminals of the selecting circuits 136 and 137 are connected to an input terminal of a selecting circuit 154.
Each of the selecting circuits 141 to 144 is a digital level comparator which is configured to compare the levels of two picture element data inputted and selectively output only the picture element data of larger magnitude Each of the selecting circuits 15]. to 154 is a digital -- 19 - ' level comparator which is configured to compare the levels of two picture element data inputted and selectively output only the picture element data of smaller magnitude.
The outputs of the selecting circuits 141 and 142 are supplied to a selecting circuit 145. The outputs of the selecting circuits 143 and 144 are supplied to a selecting circuit 146. The outputs of the selecting circuits 145 and 146 are supplied to a selecting circuit 147. The output of the selecting circuit 147 and the output of the larger level of the selecting circuit 138 are supplied to a selecting circuit 148. The selecting circuits 145 to 148 selectively output the picture element data of larger magnitude sim1lar to the selecting circuits 141 to 144. Therefore, the picture element data of the maximum elvel MAX among eighteen picture element data in the block 100 -is generated at an output terminal of the selecting circuit 148.
The outputs of the selecting circuits 151 and 152 are supplied to a selecting circuit 155. The outputs of the selecting circuits 153 and 154 are supplied to a selecting circuit 156. The outputs of the selecting circuits 155 and 156 are supplied to a selecting circuit 157. The output of the selecting circuit 157 and the output of the smaller level of the selecting circuit 138 are supplied to a selecting circuit 158. The ~:~5~S
selecting circuits 155 to 158 selectively output the picture element data of smaller magnitude, similar to the selecting circuits 151 to 154. Therefore, the picture element data of the minimum level MIN among eighteen picture element data in the block 100 is generated at an output terminal of the selecting circuit 158.
The outputs of the selecting circuits 148 and 153 are supplied to subtracter 149. The subtracter 149 subtracts the minimum level MIN from the maximum level MAX, so that the dynamic range DR of eight bits is obtained at an output terminal 106. The minimum level MIN is taken out at an output terminal 107 and supplied to a subtracter 150.
The picture element data PD generated at the output;
of the sample delay circuit 135 is supplied to the subtracter 150 through a delay circuit 104. The delay circuit 104 has a delay amount equal to the time lag which is caused by the detection of the maximum level MAX and minimum level MIN as mentioned above. The picture element data DTI of eight bits from which the minimum level was removed is obtained at the output of the subtracter 150.
The dynamic range DR and the picture element data DTI (after the removal of the minimum level) are supplied to an encoder block 105. The encoder block 105 divides ; ~ r~
the dynamic range DR ~nto equal parts according to the num~er of digit~zed ~its C~our ~ts in this examplel, and determines ~n ~hic~ one of tne divided areas the picture element data DTI Cafter the removal of the minimum levelL is ~ncluded, and genera~es the ~our-~t ~ode DT
to spec~iy t~e decided aea at an output terminal lQ8.
T~e ar~angement sho~n i~n Fig, 5, 7, or ~ may ~e used as a practical arrangement of encsder ~loc~ 5.
~ s descri~ed a~ove, t~e dynam~c range DR and minimum le~el MIN are o~tained as additional data, are o~tained at t~e output ter~inals la6 and ln7 of the encoder shown in ~ig. 11, TRe compressed code o~ ~our ~its is deri~ed at the output ter~inai lQ8.
One block of the original digital video signal consists of 144 bits (= 3 x 6 x 8 ~its~. According to this embodiment, one block of the transmitted signal consists of 88 bits ~= 3 x 6 x 4 ~its ~ 16 ~itsl, so that the number of ~its to ~e transmitted can De reduced ~y about one half.
Tne code DT whica is o~tained at t~e output terminal lQ8 o~ t~e encoder nas the same ~e~uence as t~e input video s~gnal. Therefore, t~e additional data M}N and DR oX eac~ Bloc~ are yenerated for eye~y t~ree l~nes with respect to tne line, and ~o~ e~ery SlX samples witA
regard to the s~mpll'ng direction. ~nen t~e transmission data is di~ided for e~ery predete~mined amount of the ~s~
code DT, an interval including no additional data occurs in the transmission process. Therefore, a buffer memory is connected to the output of the encoder and the additional data DR and MIN and the code DT of one block may be used as a unit of transmission. In this case, the length of the data portion consisting of the coded code DT in Fig. 3 becomes 64 bits (= 4 bits x 16).
Fig. 13 shows an arrangement of the reception (or reproduction) side. Reception data from an input terminal 41 is supplied to a data separating circuit 42, by which the DT code and additional codes are separated. The additional codes, namely, the minimum level MIN and dynamic range DR, are supplied to an error correcting circuit 43 to correct any transmis-sion error. An error concealing circuit 44 is connected to the error correcting circuit 43. The error concealing circuit 44 conceals (interpolates) the additional codes which could not -be corrected on the basis of an error flag from the error correcting circuit 43.
The additional codes which are outputted from the error concealing circuit 44 and the coded code DT, the timing of which was matched by a delay circuit 47, are supplied to a decoder 45. The code DT is decoded by the decoder ~5 and the original picture element data PD is taken out at an output terminal 46 of the decoder 45. The decoder 45 decodes the eight-bit picture element data PD from the additional codes DR and MIN, each consisting of eight bits, and from the 4-bit DT code.
The decoder 45 is configured as shown in Fig. 14.
In Fig. 14, the code DT, dynamic range DR, and minimum level MIN from input terminals 4B, 49, 4nd 50 are stored into latches 51, 52, and 53, respectively.
Tbe code DT from the latch 51 ~nd the dynamic range DR from the latch 52 are supplied to a decoder block 54. The data DTI tafter the removal of the minimum level) is decoded by the decoder block 54. The data DTI ~nd the minimum level MIN from th~ latch S3 are added by an adder 55, so that the picture element da~a PD is taken out at an output terminal 56 of the adder 55. The decoder block 54 decodes the representative value corresponding to the code DT.
Fig. 15 shows an arrangement of one example of the decoder block 54. In the decoder block shown in Pig.
lS and a decoder block shown in Fig. 16 which will be mentioned later,it is assumed that the number of digitized bits of the DT code is two for simplicity of explanation.
..
The decoder block of Fig. 15 has an arrangement corresponding to the encoder block shown in Fig. S.
~ 35 The dynamic range DR from an input terminal 61 is d~vided Py 4 ~y a divider 63 Cwh~c~ is comprised of a Pit shifter to shift data ~y two ~.~tsl and the resultant data is supplied to multlpliers 64 and 65. The multiplier 64 triples the output of the divlder 63, and multipl1er 65 dou~les the output of t~e d~vider 63. The outputs of the multipliers 64 and 65, the outpui of the di~ider 63, and t~e code in ~hich eig~t ~its are all "~" a~e suppiied to a selector 66~ The selecto~ 66 selects e~t~er one of tne four inpuis ~n cor~espondence to t~e code DT ~rom the input terminal 62 and outputs o~ t~e selected lnput.
When t~e code DT is CQ ~I, tne selector 66 selects the code of zer~ W~en t~e coded code DT is CO lI, the selector 66 selects t~e output a DRl of the divider 63. ~en tHe DT is Cl Ql, t~e selector 66 selects the output C2 DRI of tne multiplier 65. ~en t~e DT is (1 11, the selector 66 selects ~e output C3 DRl o~ the multiplier 64. Tne output of the selector 66 is suPplied to an adder 68, The output of th.e di~ider 63 is divided Py 2 Py a di~ider 67, ~nd tn.e resultant data is supplied to the adder 68. T~exefore, t~e data DTI after the removal of the ~inimum le~el ~s o~tained at an output terminal 6~ of the adder 68, Fig. 16 shows another example of the decoder ~lock 54. The example shown in ~ig. i6 ~as an arrangement ~ S~3~
corresponding to the encoder block shown in Fig. 7.
In Fig. 16, a digital multipller 71 multipl~es a value of Cl DRl from ~ diyider 70 and t~e code DT ~rom the input terminal 62. T~e multiplled output of t~e multiplier 71 and a data of Cl D~I f~om a divlder 72 are supplied to an adder 73. Tne data DTI a~ter the removal of t~e m~nimum le~el is taken out ~t the output terminal 6~ of t~e adder 73.
~ ig. 17 shows still ~not~er example of t~e decoder ~lock 54 and has an a~angement corresponding to t~e encoder ~lock s~o~n in P~g, Y, In ~g. 17, t~e input d~ta PT is supplied to an input ter~inal 181 and t~e dy~amic range ~nformation DR2 inputted ts supplied to an ~nput terminal 182. The minimum level M~N is supplied to an tnput term~nal 183, The data DT is supplied to ~ selecting circuit 184. T~e seiection circuit 184 generates an ou~put ~ eig~t ~i~s selected on t~e ~asis of the d~na~c ~ange info~mation DR2 from among five kinds o~ ~ig~ t data ~n ~ic~
fou~ ~0" ~its of total fou~ ~ts were ~dded to t~e ~igh order side or lo~ order side of the dat~ DT of four ~its.
TRe output dat~ of t~e select~ng ci~cuit 184 corresponds to tRe data DT~ a~ter t~e removal of the minimum le~el. T~e output of t~e selecting circu~t 184 ~ 3~
i5 supplied to one input terminal of an adder 185. The minimum level MIN is supplied to the other input terminal of the adder 185. The picture e~lement dat& PD is taken out at an output terminal 186 of the adder 185.
In the above description, three data of the code ~T, dynamlc range DR, and minimum level MIN are transmitted. However, as the additional codes, the minimum level MIN and maximum level MAX, or the dynamic range DR and maximum level MAX may be transmitted.
Further, inste~d of transmitting the dynamic range DR, the minimum digitization level which is formed by this signal may be tr~nsmitted in place of this signal.
According to the present invention, the amount of data to be transmitted can be reduced compared with the amount of original data. Thus, the transmission band can be narrowed. In addition, this invention has an ~dvantage such that in the non-moving portion of the picture where the dynamic range of picture element data is small, the original picture element data can be completely recovered from the received data with little or no deterioration of picture quality. Moreover, according to the invention, ince ~he dynamic range is evaluated separately for each block, the reconstructed pictured responds very well to motion in the moving part of the picture such as the edge where thç dynamic range ~;~5~ 5 is large.
The present invention is not limited to the foregoing embodiments but many modifications and variations are possible within the spirit and scope of the appended claims of the invention.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A highly efficient coding apparatus for coding digital video data in the form of blocks of digital video data representing plural picture elements so as to provide compressed video data, comprising:
first and second detecting means for detecting maximum and minimum values, respectively, of the digital video data representing the plural picture elements in each of said blocks, means for generating dynamic range information for each said block from said maximum and minimum values for the respective block, means for generating modified digital video data for each said block as the difference between each of the digital video data and one of said maximum and minimum values for said respective block, means for encoding said modified digital video data with a fixed digitized bit number less than the number of bits in said original digital video data so as to provide coded data of a reduced fixed bit length, and transmitting means for transmitting the coded data of reduced fixed bit length and an additional code for each said respective block formed of at least two of said maximum and minimum values and a signal corresponding to said dynamic range information.
first and second detecting means for detecting maximum and minimum values, respectively, of the digital video data representing the plural picture elements in each of said blocks, means for generating dynamic range information for each said block from said maximum and minimum values for the respective block, means for generating modified digital video data for each said block as the difference between each of the digital video data and one of said maximum and minimum values for said respective block, means for encoding said modified digital video data with a fixed digitized bit number less than the number of bits in said original digital video data so as to provide coded data of a reduced fixed bit length, and transmitting means for transmitting the coded data of reduced fixed bit length and an additional code for each said respective block formed of at least two of said maximum and minimum values and a signal corresponding to said dynamic range information.
2. A highly efficient coding apparatus according to claim 1, wherein said means for encoding includes a reference level signal generator supplied with said dynamic range information for generating a reference level signal, comparator means for comparing said modified digital video data and said reference level signal, and priority encoding means supplied with the output of said comparator means for generating said coded data of reduced fixed bit length therefrom.
3. A highly efficient encoding apparatus according to claim 1, wherein said means for encoding includes level dividing means supplied with said dynamic range information for level dividing said dynamic range information by a number corresponding to said fixed digitized bit number, and a digital divider for dividing said modified digital video data by the output of said level dividing means and providing said coded data of reduced fixed bit length as the result thereof.
4. A highly efficient encoding apparatus according to claim 1, wherein said means for encoding includes priority encoding means supplied with said dynamic range information and generating encoded dynamic range data with a smaller number of bits than that of said dynamic range information, and a bit selector supplied with said modified digital video data and controlled by said encoded dynamic range data for selecting the predetermined number of bits of said modified digital video data which is equal to said fixed digitized bit number.
5. A highly efficient coding apparatus according to claim 4, wherein said priority encoding means generates the encoded dynamic range data in accordance with the most significant bit position containing "1" said dynamic range information.
6. A highly efficient coding apparatus according to claim 1, wherein said transmitting means adds parity data at least to said additional code.
7. A highly efficient coding apparatus according to claim 1, wherein said digital video data in each of said blocks represents a two-dimensional group of picture elements.
8. A highly efficient coding apparatus according to claim 1, wherein said digital video data in each of said blocks represents a one-dimensional group of picture elements,
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP266408/84 | 1984-12-19 | ||
| JP59266407A JPH0793723B2 (en) | 1984-12-19 | 1984-12-19 | High efficiency coding apparatus and coding method for television signal |
| JP266407/84 | 1984-12-19 | ||
| JP59266408A JP2785822B2 (en) | 1984-12-19 | 1984-12-19 | High-efficiency encoding device and decoding device for television signal |
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|---|---|---|---|
| CA000497763A Expired CA1251555A (en) | 1984-12-19 | 1985-12-16 | High efficiency technique for coding a digital video signal |
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| US (1) | US4703352A (en) |
| EP (1) | EP0185533B1 (en) |
| AU (1) | AU583078B2 (en) |
| CA (1) | CA1251555A (en) |
| DE (1) | DE3582314D1 (en) |
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-
1985
- 1985-12-16 CA CA000497763A patent/CA1251555A/en not_active Expired
- 1985-12-16 DE DE8585309127T patent/DE3582314D1/en not_active Expired - Lifetime
- 1985-12-16 EP EP85309127A patent/EP0185533B1/en not_active Expired
- 1985-12-17 US US06/809,775 patent/US4703352A/en not_active Expired - Lifetime
- 1985-12-18 AU AU51404/85A patent/AU583078B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| AU5140485A (en) | 1986-06-26 |
| EP0185533A2 (en) | 1986-06-25 |
| AU583078B2 (en) | 1989-04-20 |
| EP0185533B1 (en) | 1991-03-27 |
| EP0185533A3 (en) | 1987-07-15 |
| DE3582314D1 (en) | 1991-05-02 |
| US4703352A (en) | 1987-10-27 |
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