CA1250935A - Dynamic bandwidth allocation mechanism between circuit slots and packet bit stream in a communication network - Google Patents

Abstract

ABSTRACT

System to be used for dynamically allocating circuit slots in the frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, said frames being delimited by flags and divided into bit slots which may be devoted to synchronous circuit flow and to asynchronous packet flow. It comprises in each node means for changing the flags preceding at least one frame in which at least one slot is to be added or deleted to a value including a first number of delimiting bits and a second number of bits which are coded to indicate that slot(s) is (are) to be added or deleted and the corresponding slot number(s); means for sending call control packets which are propagated through the network nodes, comprising call control information , routing information and indicating the circuit user slot number(s) to be added or deleted on specified link interfaces, and means receiving the call control packets and the changed flags for adding or deleting circuit user slot(s) in the subsequent frames depending upon the flag value.

Figure 11

Description

1251~935 DYN~IC sAND~IDTH ALLOCATION MECHANIS21 BET~7EEN CIRCUIT SLOTS AND PACKET BIT
STREAM IN A COMMU~IICATION NETWORK

Description of the invention Field of the invention This invention relates to a mechanism to be used in a packet/circuit switched transportation system for dynamically allocating the circuit switched slots according to the circuit user activity.

Background art A telecommunication network is made of various nodes to which terminals are attached through communication controllers adapters and which are linked through multiplex links.

Due to the bursty nature of most of the data to be transported packet switching networks have been implemented to optimize the utilization of the network resources.
However packet transportation implies large and variable transit delays that cannot be suffered by some real time applications. The variation of the transit delay can only be compensated by means of additional'buffers at the end users, which is costly and implies delays.

on the other hand, circuit switch networks provide low constant transit delays, but lead to a bad utilization of the network links when bursty data or is to be transported through the network.

The ISDN network (Integrated Service Digital Metwork) described in "I" series of International Telegraph and ~ 3~ ~ ~

Telephone Consulative Cornmitee (CCITT) ~esommendations is the present approach to circuit switchiny and packet switching integration. ~-lo~ever the networks using the I~Dr~
integra-tion technique are not optimized for the data packet traffic since the bandwidth allocated to the packet traffic is channelized.

In this type of networks which integrate the transportation of asynchronous (packet) data in dedicated packet bits and synchronous data such as voice in dedicated circuit slots there is a need to optimize the bandwith use allocated to asynchronous data t~pe of users and to synchronous data type of users since circuit switched type of users are not always involved in a call.

Summary of the invention In this environment an object of the present invention is to provide a mechanism which insures a dynamic allocation of the bandwith to circuit or packet switehed bit users according to the user activity.

The system according to the invention is to be used for dynamieally alloeating cireuit slots in the frames whieh are used for exchanging bits between users eonneeted to nodes of a eommunieation network linked by means of medium links having transmit and reeeive interfaees, said frames being delimited by flags and divided into bit slots whieh may be devoted to synchronous eireuit flow and to asynchronous paeket flow.

The system eomprises in eaeh node:

- means t20, 238, 232) for ehanging the flags preeeding at least one frame in whieh at least one slot is to be added or deleted to a value ineluding a first number of delimiting bits and a seeond number of bits whieh are 7~3~5 coded to indicate that a slot[s) is (are~ to be ad~ed or deleted and the corresponding slot number(s), means (418, 404) for sending call control packets which are propagated through the network nodes, cornprising call control information, routing information and indicating the circuit user slot number~s) to be added or deleted on speeified link interfaces.

means (418, 128, 106) receiving the call control packets and the changed flags for adding or deleting a circuit user slot(s) in the subsequent frames depending upon the flag value.

Brief deseription of the drawings .

Figure 1 schematieally shows a network wherein the mechanism aeeording to -the invention may be implemented.

Figures 2-A and 2-B show a speeifie frames which can be preferably used for implementing the mechanism aceording to the invention.

Figure 3 shows the ealeulation steps to be used for building the frame aeeording to figure 2.

Figure 4 sehematieally shows two nodes of the teleeommunieation network.

Figure S shows how a eomplete paeket may be reeonstructed from the paeket bits received in eonseeutive frames.

Figure 6 shows the transmitting means for generating the frames aceording to figure 2 on the transmit interfaee of the outgoing medium link eonneeted to a node.

~ ~t7~3 Figure 7 shows the receiving means receiving the cornple~
frame from the receive interface of an inCominCJ medium link connected -to a node.

Figure 8 shows circuit 56 of the transmitting rn~ans.

Figure 9 shows circuit 128-1 of the receiving means.

Figure 10 shows t~o adjacent nodes in the network and schematically shows the protocols and interfaces defined for implementing the mechanism according to the invention.

Figure 11 shows the call set up flow which is used for dynamically allocating a circuit slot in the frame.

Detailed description of the invention The mechanism according to the invention allows circuit switched bit slots to be dynamically allocated in the frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links, said frames being delimited by f-bit flags, f being higher than four and the flags comprising at least two delimiting bits and which are divided into bits slots which may be devoted to synchronous circuit flow and to asynchronous packet flow according to the circuit user activity on a per cal basis.

For adding a new circuit slot in the frame the managing means of the originating node eonneeted to the calling user sends a call request packet using the paeket flow, said eall request packet ineluding call control information and the slot number to be alloeated to the ealling user, on the transmit interface of one of the node outgoing links to be used for reaching the destination node according to the network routing faeility and the non delimiting bits of the opening flag of at least one of the subsequent frame sent on FR 9 85 00~

the interface as de~ined in the call control inforrn~tion are set to a coded value indlcatiny that a slot is to be adde~d on said link transmit interEace and the slot number to be added and at least one circuit slot is added in the following frames.

The node receiving this call request packet and detecting the new flag configuration, if not the destination node, propagates the call request packet to a further node, said packet being updated so as to contain the slot ~umber to be allocated on a specified transmit interface of one of the node outgoing link to be used for reaching the destination node and the opening flag configuration of at least one of the subsequent frame sent on this specified interface is set to a value indicating that a slot is to be added and at least one circuit slot is added in the following frames.

When the call request packet reaches the destination node, if the call may be accepted, the managing means in said node causes a call connected packet to be sent to the originator node including call control information and the slot number to be allocated on a specified transmit interface of one of the node outgoing links to be used for reaching the originating node and the opening flag configuration of at least one of the subsequent frames sent on this interface is set to a value indicating that a slot is to be added and at least one additional slot is provided in the following frames.

The call connected packet is propagated in the network through the same nodes as the call request packet, until the originator node is reached, and slots are allocated in the transmit interfaces to be used for reachiny said originator node, as previously described by setting the flags to values specifying the slot numbers to be added and by updating of the call connected packets in the crossed nodes.

FR 9 ~5 00~

When the call connected pac~.et reaches the originator noce, a full duplex connection is established between the users which can exchanye circuit switched bits in the s]ots which have been allocated thereto in the frames on the links.

If the call request packet rnay not be prop~yated, which occurs when the maximum circuit slot number in the frame to be sent on one node outgoing link, is reached, the node sends a clear request packet to the originator node, on the transmit interfaces of the previously crossed node outgoing links, and the opening flags of the subsequent frames sent on these interfaces are set to a value indicating that the slots previously allocated have to be deleted. The clear request packet includes the slot number and the call control information as the one of the call request packet.

The originator node receiving the clear request packet sends a clear confirmation packet. The clear confirmation packet is propagated back to the originator node of the clear request packet to confirm that the clear request has been received.

When the call established according to the above procedure is to be released, a clear request packet is sent by one of the users in the same way as described above for the call request packet except that the flags are set to a value indicating that slots have to be deleted. This causes a clear confirmation packet to be sent by the other user in the same way as described above for the call connected packet, except that the flags are also set to a value indicating that slots have to be deleted.

The originator of a call request or clear request packets is responsible of retrying the action if the corresponding confirmation is not received within a pre-defined period of time.

~ r~ 5 Before describing this mecharlism, a detailed description of a speeific environment wherein i-t may be implemented will be made~

A telecommunication network, as schematicAlly shown in figure 1 comprises a plurality of nodes, four of ~,/hich 1, 2, 3, 4 are represented. A plurality of eircuit switched type users C and a plurality of packet switched type users P are attaehed to each node. The nodes are linked through medium links, the links between different nodes may operate at any speed v higher than u.64 kilobits per second, u being the number of circuit switched users. The users connected to a node share the link bandwidth in such a way that, at a given instant the circuit switched users exchange the non eharaeter coded information (NCI), such as voiee, in subehannels and the remaining bandwidth is used for paeket traffic. This is sehematieally represented in figure 1 by the hatched part of the links.

The circuit type users operates at 64 kilobits per second, whieh eorresponds to the presently conventional bit rate, i.e. 8 bits every 125 microseconds.

The transmitting adapter of each node comprises means to cause the data and non eoded information NCI bits sueh as voiee emanatiny from the paeket switehed type users and from the cireuit switehed type users eonneeted to the node to be transmitted on the medium link in eomplex frames having the structure shown in figure 2. The structure of the complex frames is determined using the method of the present invention whieh comprises the steps illustrated in figure 3.

For the sake of the explanation of the invention, the structure of the theoreatieal complex frame is shown in figure 2-A. Figure 2-B shows the eomplex frame whieh is generated by the means described in figures 6 to be sent on the medium link.

. .

i 5~ 5 The complex frame contains ~lc or Nc~l bits and has a duration equal to nT~e, T heing the conventional time division multiplex slo-t which for the present tirne is equal to 125 microseconds, n being arl integer equal or higher than 1 and e being lower than a medium link bit period, n depends upon the link speed and is calculated as will be described in reference to figure 3.

The complex frames contain n subframes, each subframe has a duration equal or less than T so as to contain an integer number Ns of bits. The Ns bits of a subframe are allocated to the transportation of a variable number of circuit switched bit slots. The number of slots depends upon the user need, two slots are represented in figure 2, and the remaining bits are allocated to the transport of packet switched bits.

The purpose of the mechanism of the invention is to dynamically allocate the circuit user bit slots to active circuit users, so that the subframe structure changes depending upon the circuit user activity, thus the number of packet data bits varies.

The complex frames are delimited through a f-bit flag which is part of the R bits remaining at the end of the complex frame with R=Nc-nNs.

In cases where R is higher than f,-the r=R-f bits are filled with asynchronous traffic bits.

The residual r bits, may be spread in given subframes to avoid jitter. This causes a variable determined number of bits Nsi to be contained in the subframes. This result in a different number Rl of residual bits at the end of the complex frame which is equal to Nc - ~ Nsi.

~ (7~

As shown in figure 2-B, the flag is genera~ed at the next medium link clock tirne following -the nT boundaries. Th~n the n subframes comprising ~1s bits and the r residual bits are sent on the medium link.

The environment of the invention ~"ill be more s~ecifically described assuming that the subframes contain a constant number of bits~ and the man skilled in the ar~ can easily adapt the means which will be described later on to provide subframes having a variable number of bits according to the above requirements.

As can be seen in the hereafter table, depending upon the link speed versus 64 kbps, the complex frames do not contain a constant number of bits, however the variation of the bit number Nc in consecutive complex frames is only equal to 1.
Thus, the complex frame limit is known by the receiving end thanks to the flag detection and bit counting. ~o implement the mechanism according to the invention, the flag comprises two delimiting 2 bits, and f-2 non-delimiting bits which are used for synchronization purposes or which are coded to indicate that cic~it slots have to be added or deleted, as will be described later on. The two delimiting bits are set to 01 or 10. When the lowest possible number Nc of bits a complex frame have been counted, the two nex~ bits are analyzed. An equality of these bits with the two delimiting bits of the flags, means that the frame contains Nc bits, if not, the frame contains Nc+1 bi-ts. This is illustrated below :
Flag 01;

..XXXXX represent the frame bits which can be equal to O or 1 XXXXXXXOl Frame contains Nc bits XXXXXXXXO1 Frame contains Nc~1 bits I->bit count Nc Consequently, when Nc bits have been counted from the beginning of the opening flag the two next bits including the first bit of the next flag and the additional bit of the FR 9 ~5 004 frame, i~ a~y, cannot sirnulate the 01 de]irrliting pattern, whatever the value of this additional framc bit ean be. ~7hen Nc bits have been counted, the detection of the 01 pattern indicates that the frame contains Nc bits.

Delimiting bits equal to 10 has also the same propert~.

The method which is used for configuring the complex frames at each transmitting ends is represented in figure 3.

The speed of the medium link and the desired approximate number of bits Na in the complex frames determine the complex frame structure. In a specific configuration of the complex frarnes which for the present time are intended to be used with medium link speed lower or equal to 2.048 megabits per second, Na is chosen equal to 256 so that the number Nc be as close as possible to 256 bits, in order to keep a flag overhead ratio f/Nc in the same range as the one used for classical TDM first order multiplex link.

The method consists in calculating the link bit time which is equal to 1/v, where v is the bit rate on the medium link.
(Step 1) Then the number of bits in the time division multiplex slot T is calculated. The number of bits Ns in each subframe is equal to the integer part of this number. Assuming that v is expressed in kiloblts per second and T is equal to 125 microseconds, Ns is the integer part of the product 125.v.10 3. (Step 2) Then the number n of subframes is calculated, this number is the integer part of the quotient Na/Ns. In the specific embodiment described in figure 3, it is the integer part of 256/Ns. (Step 3) :

i~s,335 ll Then the residual number R o~ bi~s is calculated (Step 4).
This number is equal the difference between the real number of bits comyrised in T and Ns, rnultiplied by the subfrarne number n and can be e~pressed as fol]ows:

n.(T.v.10 3-Ns) This number R is compared to f, (Step 5). If it is higher or equal to f, the number of bits in the subframes is made equal to the value of Ms calculated in step 2. If not the number of bits in the subframes is made equal to Ns calculated in step 2 minus 1. The residual number R of bits corresponding to this new subframe number is calculated.

Steps 4 and 5 are resumed as long as the residual number R
is not higher or equal to f.

This method also applies when it is desired to have the residual bits spread in the subframes. In that case the theoretical numbers Ns and R are calculated according to the above described method and the residual bits are placed in specific identified subframes and the new residual bit number R1 is calculated so that the rl bits, with rl=Rl-f, if any remaining at the end of the complex frames may be filled with asynchronous traffic bits.

The following table gives the various values which are obtained according to the above me-thod for four medium link speeds.

~t,~

T~BL~ 1 .
! ~Ie~ium ! ~Is bits !M~xirnum !~Iumb~r n ! ! ! ~iumb~r of ! link ! per !number of ! ~ ! ! ! bit~ tIc ~r !
! speed v! subfr~me!circuit user~!subframe~ ! r ! f ! ~Ic~
! kbps ! !at 64 kbps ! ! ! ! c~,mple~ !
! ! ! ! ! ! fr~ne 72 ! 8 ! 1 !28 ! 20 ! 8 ! 252 132 ! 15 ! 1 !16 ! 5 ! 8 ! 253 or 254 ' 230 ! 27 ! 3 ! 9 ! 7 ! 8 ! 256 or 257 !1.54~ ! 185 ! 23 ! 1 ~ 0 ! 8 ! 193 ! !

Figure 4 shows two nodes of the telecommunication network.
Each node comprises similar rneans, they are referenced by the same number with a suffix 1 for the means in node 1 and

2 for means in node 2. Each node comprises medium link adapters 10 and 11 made of receiver/transmitter means and including the specific means which are needed to implement the method according to the invention. The adapters are connected to medium links, each link having a specific speed, so that the complex frames on the different links have different configurations. These frames are built in the transmitter means of the adapters to be sent on the links.
The parameters n, Ns, r of the complex frames-are made known to the corresponding receiver means, in order the received bits may be processed. The complex frames are shown in a schematic way on the different links.

Two paths are provided in each node. One path CP is dedicated to the circuit switched bits (synchronous path) which have to be transmitted with constant and very short delay (<500 microseconds) and the other path PP is dedicated to the packet switched bits (asynchronous path) which are bufferized and processed in packet handling means 14.

~ ..

11 ~ ~ 7( ~ ~ ~, l S

Figure 5 shows how packets read~ to be s~Jitched co1~ld be reconstructe~ in the receiviny node from the as~nchronous flow made of packet bits.

The consecutive received complex ~rames contain circuit user slots Cl and C2 for example, assuming that two circuit users are involved in a call and packet switc~.ed bits P. Ccmple~
frame (m-l) contains packet bits P0, complex frame m contains packet bits Pl, P2, P3, P4 and comple~ frame m+l contains packet bits P5. For the purpose of illustration, it is assumed that a packet ready to be switched: i.e.
constituted of a packet header containing the information which is necessary to route and switch the packet and packet data comprising packet bits Pl, P2, P3 , P4 from complex frame m and parts of packet bits P0 and P5.

Figures 6 and 7 show the specific means which are needed in the medium link adapters to build the complex frames.

Figure 6 represents the transmitting means and figure 7 represents the receiving means. For the sake of explanation, it is assumed that figure 6 shows the transmitting means of a first transmitting node and figure 7 shows the receiving means of a second receiving node. It is to be understood that, each adapter comprises receiving and transmitting means such as shown in figures 6 and 7. The medium access manager and the finite state machine are common to the receiving and transmitting means in an adapter.

In the transmitting means, the medium link access manager 20 computes the link parameters according to the method of figure 3. It also provides event indications to finite state machine 32, E~IGl, 2, 3, and receives signal S~lG3 from finite state machine 32 as will be described later on in connection with the finite state machine diagram.

F~ 9 85 004

3~5 The medium link access manayer 20 provides throu~h output bus 21 the link parameters Ns, n and the slot allocation to registers 22 and 24 and to slot table 26, respec~ivel~.
Thus the slot table 26 contains an indicatlorl of the slots of the sub~rames which are allocated to circuit users. At each subframe generation, -the slot table is read and its output 28 is used in logic circuit 30 to generate Packet or Circuit P or C ENABLE signals.

The medium access protocol is managed through finite state machine 32 which is a logic providing control signals when specific events occur. The operation of this machine will be detailed later. It is connected to three lines 33, 34 and 35 from the associated receiving means, said lines carrying the RECEIVED IDLE PATTERN, RECEIVE SYNCHRO RE~UEST and the RECEIVE LOST SYNCHRO signals respectively and to output bus 21. Depending upon the received events it generates on its output lines 38, 39, 40, 41 control signals DISABLED, SEMD
SYNCHRO PATTER~I, SEND SYNCHRO REQUEST and OPERATION
respectively.

Bit counter 44 working under control of a clock 48 operating at the medium link speed counts the bits and the subframes.
Counter 46 counts the subframes. The contents of counters 44 and 46 are compared with the Ns and n registers 22 and 24 by comparators 47 and 49. The output 50 of comparator 47 is provided to subframe counter 46 so as to cause this counter to be incremented each time an -equality is detected by comparator 47.

Outputs 50 and 51 of the comparators, output 28 of slot table 26 are provided to logic 30 to generate the P ENABLE, C ENABLE and FLAG ENABLE signals at the correct times to build the complex frame as shown in Fig. 2-B.

Logic 30 also receives the OPER~TION control signal from finite state machine 32.

$

Flag and r sending logic control circuit 56 ~,70r~iny under control of T-pulse counter 57, mediurn lin~. bit clock 48 and outputs 50 and 51 of comparators 47 and 4g allo~ls speci~ic patterns to be sent on the medium link at yiven instants under control of thc signals on output lines 39, 40 and 41 of finite state machine 32. It also provides a reset counter signal on its output line 58. Output line 58 and output lines 50 and 51 of comparators 47 and 49 are provided to OR
circuits 52 and 54 which provide the reset signal to bit and subframe counters 44 and 46 respectivel~.

Circuit 56 also generates on output line 60, a r sending control signal which is provided to logic 30 so as to cause the r residual packet bits to be sent on the medium link in order to generate the complex frames as described in reference to figure 2-B.

The different flags are generated by circuit 56 on output lines 62, 64 and 66. As will be described later on, different flags have to be sent at given times. In a specific embodiment, 01111110 is the normal complex frames delimiter, abort flag 01111111 is used to request the synchronization and UCC flag is used for indicating to the receiving means that a circuit user is added or deleted, according to the present invention.

Consequently generator 56 generates the medium 01111110 flag under control of OPERATION and SEN~ SYNCHRO PATTERN signals on lines 41 and 39 from finite state ~achine 32.

Circuit 56 generates the specific 011111l1 flag under control of SEND SYNCHRO REQUEST line 40 from finite state machine 32.

Circuit 56 generates the USER CIRCUIT CHANGE pattern UCC
which is used for changing the user slots in the subframes.
This pattern is changed under control of the medium access 3~ 3 ~
1~
manager 20, so that circuit 56 receives the pattern to be generated on bus 21.

The flag outputs 62, 64 an~ 66 of circuit 56 are provided to OR circuit 72.

Circuit 56 also generates a flag sending control signal on line 68 which is provided to logic 30 and which is also used during the initialization period to prevent the idle 111...11 configuration from being sent on the medium link during the flag sending period as will be detailed later on.

Circuit 56 generates a next slot signal on line 70, which is provided to the slot table to cause the table to be scanned in order to have the P or C indication to be provided to loglc 30 through output line 28 of slot table 26.

The packet user bits from path PP and the circuit user bits from path CP or the specific patterns from the output of OR
clrcuit 72 are transmi.tted on medium link 96 at specific instants to build the complex frames through AND gates 74, 76 and 78 and OR gate 80. AND gate 74 receives the P ENABLE
signal from output line 84 of logic circuit 30 and the packet switched bits from PP path. AND gate 76 receives the C ENABLE signal from output line 86 of circuit 30 and the circuit switched bits from path CP. AND gate 78 receive the FLAG ENABLE signal from output line 88 of circuit 30 and the specific flag patterns from output~of OR circuit 72.

The outputs of AMD gates 74, 76 and 78 are provided to OR
circuit 80. The output of OR circuit 80 is provided to AND
gate 81 which is conditioned when the medium link clock signal is positive, for example. The output of AND gate 81 set latch 83 which is reset when the medium link clock signal is negative. Thus latch 83 provides on its output the bit to be transmitted on the medium link 96.

OR circuit 82 receiving the ~ISA~IJED signal from output lire 38 of finite state machine 32 has its output corlnected to O~
circuit 80, so that the idle configuration ll...1111 is sent on the medium link g6 through AM~ gate 81 and latch 83 when the DISABLED signal is active.

AND gate 94 receiving the OPERATION siynal from line 41 inverted by inverter 92 and the flag sending control signal from line 68 of circuit 56, has its output connected to OR
circuit 82 to send the all mark 111..111 configuration on medium link 96 during the initialization period, between flags.

An embodiment of circuit 56 will be described in reference to figure 8.

The receiving means shown in figure 7 will now be described, so that the operation of the transmitting means will be explained in connection with the operation of the receiving means.

In the receiving means which is assumed to be in the adapter of the second node to be linked to the first node comprising the transmitting means described in reference to figure 6, the adapter medium access manager 100 is represented.

The finite state machine 101 of the adapter is also schematically shown in figure 7, only OPERATION output line 103 which is needed for the receiving operation is represented.

The link parameters have to be known from the receiving means. They may be transmitted from the transmitting means or may be calculated in the receiving means. In a specific embodiment, they are found in the receiving means by consulting tables containing the correlation between Nc and the desired parameters-values Nc being the number of bits F~ 9 85 00~

? ~ r~

received between two flags duriny ~he initialization period, i.e. being an indication of the link speed.

The medium link parameters are loaded in ~s-register 102, n-register 104 and slot table 106 throuyh output bus 101.

The receiving means also comprises a bit counter 108 and a subframe counter 110. sit counter 108 works under control of medium link clock 112. Comparator 114 compares the content of counter 108 and Ns-register 102 and comparator 116 compares the content of counter 110 and n-register 104 so as to generate signals on their output lines 115 and 117 which are active when an equality is detected. Output lines 115 and 117 are connected together with the output line 119 of slot table 106 to logic circuit 118. Logic circuit 118 generates P ENAsLE or C ENABLE signal on output lines 120 and 122 respectively.

The detection of an equality by comparators 114 and 116 causes counters 108 and 110 to be reset.

The received bits on medium link 96 are provided to two AND
gates 124 and 126 by means of 8-bit shift register 127. AND
gates 124 and 126 are conditioned by the P ENABLE and the C
ENABLE signals on lines 120 and 122 respectively. Their outputs are provided to the packet switched bit handling facility of the receiver and to the circuit switched bit handling facility, where the packet and circuit switched bits are processed in the conventional way. These f~cilities are not described since they are not the subject of the invention.

The received bits are also provided to circuit 128. Circuit 128 comprises means 128-1 for detecting the flags and counting the bits in the complex frames. In normal mode of operation, i.e. after the initialization period, "r Received" output line 130 of circuit 128 is activated so as ?q~1 3 to cause the P EMABL~ sigrlal at output of logic 1]~ to be activated so that the r residual bits are provided to the packet switched bi.t handling facility thrGugh ~r~l~ gate 124.

It also detec-ts -the UCC flag~ which are transmitted to the slot table through bus 132 in order the receiving means take into account the circuit user chanye transmitted by the transmitting means and generates the RCV UCC signal on line 136 and the next slot signal on line 137 which causes the content of slot table 106 to be scanned to cause the P and C
ENABLE signals to be activated accordiny -to the subframe configurations.

Circuit 128-l generates a reset CTR signal on line 138 which is provided to OR circuits 140 and 142. The outputs of comparators 114 and 116 are also provided to OR circuits 140 and 142 whose outputs control the resetting of counters 108 and 110.

The function of shift register ].27 is to delay the received bits in such a way that the flag detection may be performed in circuit 128.

Circuit 128 detects the flags in the received bits and from this flag detection and the counting of bits, part 128-2 detects when the synchronization is lost to generate the RCV
LOST SYNCHRO and RCV SYNCHRO REQUEST on lines 35 and 34. It also detects the all mark 11~..111 received bit stream to generate the RCV IDLE signal on line 33. These three signals are sent to the transmitting means as shown in figure 6.

A specific embodiment of part 128-1 will be described in reference to figure 9.

The operation of the transmitting and receiving means will now be described. Through the framing of the medium complex frame, the adjacent medium access elements are able to exchange status information and signals.

The different states are the following:

- DISABLED: send idle pattern, i.e. 11....1111 - ENABLED: send SYNCHRO (01111110) or SYNCII~O REQUES~
(01111111) at transmitting end and SEARCH
FOR RECEIVE SYNHRO at receiviny end, - SYNCHRONIZED: receive SYNCHRO ~ithout SY~ICHRO REQUEST
~ send SYNCHRO without SYNCilP.O ~EQUEST
- OPERATIONAL: send/receive normal frame; send/receive User Circuit Change UCC

The finite state machine generates signals ~Jhich depend upon the occurence of events. There are two kinds of signals and events, namely the medium access manager events and signals and the medium link events and signals.

MANAGER EVENTS AND SIGNALS

EVENTS:
EMGl : Load transmit medium access parameters Ns, n EMG2 : Load receive medium access parameters EMG3 : Add circuit user SJGNALS:
SMGl : User Circuit Change UCC

MEDIUM EVENTS AND SIGNALS

EVENTS:
E~IDl : ~eceive idle, i.e. all mark EMD2 : Receive SYNCIIRO REQUEST, i.e. 01111111 in place of flag EMD3 : Receive LOST SYNCHRO if not 01XXXXXX every medium frame ' ..

EMD4 : Receive UCC, i.e. OlOC~X~X in place of flags where 01 are the two delirnitirlg bits of the flags and the followiny O indicates a circuit user change, C=O means delete and C=1 means add and X~XX means the user nurnher from 0000 to 1111. If there are more than 16 circuit users, the user number to be added or deleted is encoded in two consecutive frames.
In that case, in the first codiny frame UCC
value OlOC1111 indicates that the circuit user number is encoded on two consecutive frames, said number being equal to 1110 plus the value in the opening flag of the following frame.
EMD5 : receive normal frame EMD6 : receive SYNCHRO PATTERN: normal flag 01111110 with ones between the flags SIGNALS:
SMDl : Send idle SllD2 : Send SYNCHRO REQUEST
SMD3 : Send SYNCHRO PATTERN
SMD4 : Send normal frame SMD5 : Send circuit user change The medium access protocol is managed according to the following state diagram through the finite state machine.

?~ ,3 r Legend:
State I Event I signal ========================================a======================~=======
ST~TE DIAG2~
=======================================================================
DISABLED ENABLED SYNC~RONIZED OPERATIO~iAL
EMG1 . . EMD6 or EMD2 EMG2 EMD4 ______----~ ------>:: ---- --> _______-------------- > _________, SMD2 : : SMD3 SMD3 SMG1 :
. . Er~2 <-----___.
. SMD3 EMD2 . . <---__ SMD3 : : EMD1 EMD1 EMD1 <---------______. SMDl ~ SMDl ¦ SMDl < __________ _______ EMD3 EMD3 E~3 SMD2 ~ SMD2 ~ SMD2 <--------------------_____________ :
< ----------------------------------------________________. .
. _______~

. . EMG3 . . . EMD6 . . SMD~
==================================================================

:
., The operation of the transmitting means and receiving means located at both ends of a medium link between two nodes 1 and 2 will now be described.

sefore an exchange is esta~lished between ~he two nodes, an initialization period is required for synchronization purposes. This initialization period encompasses the states DISABLED, ENABLED and SYNCHRONIZED as described in the state diagram.

~rom the node power on reset, the following operations are performed:

The idle configuration corresponding to all marks i.e.
11....111 is sent by the transmitting means in node 1 and transmitting means in node 2 which are in the disabled state. In that state the disabled signal is active and OR
gate 82 provides the idle pattern to the rnedium link 96.

The medium acc~ss manager in node 1 adapter loads the medium link parameters in n and Ns registers 24 and 22 of transmitting means.

Then, the transmitting means generates through flag and r sending control circuit 56 :

1-synchro pattern without synchro request if synchro not lost, (S~3), i.e.

0111111011111111...1110111111011111...
<-flag-><--all mark--><-flag-><--all mark n.T microsec.
2-synchro pattern with synchro request if synchro lost, (SMD2), i.e.

01111111111....111111101111111111111111...11101111111 <-flag-><--all mark--><-flag-><--all mark---><-flag->

F~ 9 85 004 r 3 ~ ~ q3 ~ 5 2~
During this initialization period P EI~A~LE signal is active so that all the bits be-t~Jeen the flay; are harldled as packet switched bits. rhe number of bits between flags is an indication of the link speed which is used in the receiving means to get the Nc receiviny paraMe-ter.

The 1 at the end of the flags indicate that synchro is requested at the receiving end.

When the node 1 transmitting means detects that the SY~`7CHRO
REQUEST line 34 is no more active which means that synchro is no longer requested by receiving means in node 2 the transmitting means in node 1 stop the synchro pattern generation and may switch from continuous flag sending at n.T boundaries (SMD3) to normal or UCC flag sending (S~4&SMD5). This corresponds to the state OPERATIONAL as defined in the state diagram.

The UCC flags which are thus transmitted are used in the receiving means for loading slot table 106.

If no UCC change is received from medium access manager the normal flag is sent instead of the UCC flag.

The link parameters computed by consulting tables containing the parameters as a function of Nc, are loaded in registers 102 and 104 of receiving means in node 2.

While in operational state all marK bits are sent in the frame between the flags by nodes 1 and 2, till one of the nodes has something to transmit. At that time, the slot table 26 in the transmitting means of the node having something to transmit is loaded accordin~ to the active circuit user configuration.

In the receiving means, the slot table 106 is loaded through the UCC detection in circuit 128.

C~ #3 ~5 Then, the comple~ normal frarnes built According to ~he method of the invention are exchanged between the t~,to nodes.
Comparators 47 and 49 detect the end of the subfrarnes and of the n subframes in the comple~. frarnes. This detection and the scanning of the slot table causes Y, C ~nd F EI~ABLE
signal to be activated through yating loyic 30 to build t~le complex frames as shown in Figure 2-B.

In reference to figures 8, 9 and 2-B, it ~ill now be described how the flags and the r residual bits are generated and received.

In circuit 56, counter 57 counts the T (125 microseconds) periods, the T-pulse count at the output of counter 57 is compared with the n value provided by register 24 by comparator 200. Comparator 200 provides an active signal when an equality is detected, this active signal indicating a nT boundary. When a nT boundary is detected, latch 202 is set. The output of latch 202 and the output of medium link clock 48 are provided to AND gate 204. The output of gate 204 sets FLAG latch 206 which thus provides on its output 68 the FLAG SENDING control signal which is active at the bit clock time following a nT boundary. Latches 202 and 206 ar~
reset by the signal on line 208 at the output of comparator 210.

Comparator 210 compares the content of flay or slot bit counter 212 which counts modulo eight the medium bit clock from 48, with eight. This counter is reset at the medium link clock pulse following a nT boundary or at the eight-modulo bit boundary through OR ga-te 214 by connecting output of comparator 210 to one OR gate 214 input. The other input of OR gate 214 is connected to the output of AND gate 204 to provide the reset signal on its output 216.

Output 208 of comparator 210 is connected to the reset input of latches 202 and 206 in order to reset the latches on the i ~-,~, eight-bit boundaries so as to provide on output 6~ of la~ch 206 a FLAG SENDING control signal which is active during the eigh-t-bit flag periods.

Comparator output line 208 and F~I,AG SE~ G control line 68 are provided to ~ID gate 218 which thus provides the reset signal for Ns and n counters 22 and 24, on line 58. This signal is active at the end of the flag sending period, so that counters 22 and 24 are reset to zero in order to initiate the bit and subframe countiny from that,tirne.

The FLAG SENDING siynal on line 68 is provided to frame counter 220 which is a one-bit counter providiny an indication that the sent frame number is even or odd. This indication is required for sending normal ~lag or UCC flag alternatively.

Latch 224 is set at the n subframes boundary which is detected ~hen comparator 49 detects an equality and provides an active signal on line 51 and is reset when the flag sending period begins which is detected by comparator 200.
Thus the output of comparator 200 is provided to the reset input of latch 224, which is thus set during the r sending period and provides the r sending control signal on output 60, see Fig. 2-B for r sending period.

AN,D gate 226 is connected to the output 208 of comparator 210, to FLAG SENDING PERIOD line 68 through inverter 228 and to the output 60 of latch 224 through inverter 230.,Thus AND
gate provides an active output signal on its output 70 at the eight-bit boundaries when FLAG SENDING and r SENDING
control signals are inactive. Thus AND gate 226 provides on line 70 the NEXT SLOT control signal which is used for scanning slot table 26.

The flag patterns 01111110 and 01111111 are contained in shift registers 228 and-230 and the UCC flags are loaded in ~, ~t ~ 3~
Or~

shift register 232 from bus 21. Thc two rnost ~i~jht bi~s uf shift register 232 are set to 10 and the other hits indicates either the user ch~nge, if any, or are set to 011111 if no user change is requested.

The shifting of registers 228, 230 and 232 is performed under control of a logic circuit comprising AMD gates 234, 236 and 238. These AND gates are conditioned b~ the FL~G
SENDING signal on line 68 and by the mediu~ bit clock signals from 48.

AND gate 234 provides an active shifting output signal when its third input 240 is activated by means of OR gate 242 and AND gate 246. AND gate 246 provides an active signal to one input of OR gate 240 when the OPERATION line 41 from finite state machine 32 is activated and when the output of frame counter 220 is at a first value corresponding to an odd frame number, for example. The second input of OR gate receives the SEND SYNCHRO PATTERN signal from output line 39 of finite state machine 32.

When these conditions are met, the normal 01111110 flag in register 228 is provided on line 62 to be sent by AND gate 78 (figure 6) on medium link 96.

AND gate 236 provides an active shifting output signal during the flag sending period when the SEND SYNCHRO REQUEST
signal on line 40 from finite state machine 32 is activated.
Thus during this period the abort flag 01111111 is provided to AND gate 78 (Figure 6) to be sent on medium link 96.

AND gate 238 provides an active shifting output signal during the flag sending period when AND gate 248 is activated i.e. when the OPERATION signal on line 41 from finite state machine 32 is active and when frame counter 220 indicates an even frame number. Thus during this period, the q3~5 ~8 UCC flag is provided to ~ gat~ 78 to he sent on rnedium link 96.

Figure 9 represents part 128-1 which perf~rMs the fl,ag handling and generates the control signal ~Ihich allows the P- ENABLE line 120 to be activated when the r residual bits are received.

It comprises circuit 300 which detects the flag configuration during the initialization period i.e. ~hen the OPERATION signal 103 from finite state rnachine 101 is not activated. Circuit 300 comprises one-counter 302 ~Jhich counts the ones in the received bit stream. Received bit stream from link 96 is provided to AND gate 310 which also receives the medium link clock signal from 112. The output of AND gate 310 is provided to the one counter 302. Counter 302 content is compared with six in comparator 304 so that when six consecutive ones are found in the received bit stream output 306 of comparator is activated and counter 302 is reset.

The output 306 of comparator 304 is provided to AND gate 312 which also received the bit stream on link 96 inverted in inverter 314 and the OPERATION signal from line 103 inverted in inverter 316. Thus AND gate 312 provides on its output line 318 a eight-bit flag detect signal which is activated during the initialization period when si~ consecutive ones followed by a zero are received.

The value Nc or Nc+1 of the complex frame bits is found during the initialization period by means of medium bit counter 320, Nc/Nc+1 register 322, comparator 324 and AND
gates 326. Counter 320 counts the medium link clock pulses from 112 and is reset by Ns and n counter reset signal from line 138. The content of counter 320 is gated by AND gate 326 when signal on line 31~ is activated, in register 322.

~t,~ 5 Consequently register 322 contains the nurnbe~ of comple~
frame bits between -two flags.

The medium access manager loads the pararneters calculated from Nc/Nc+l and then becomes operational.

Then, register 322 content is compared with medium bit counter content in comparator 324, which provides an output signal on line 328 which is activated when medium bits counter 320 reaches the value recorded in register 322. This active signal set latch 330 which controls the detection of the 01 first bits of the received flag.

The output line 332 of latch 330 is provided to AND gate 334 to which is also provided the received medium bit from link 96 and the last received medium bit taken in register 127 (figure 7) and inverted in inverter 336. Consequently AND
gate 334 provides an output signal on line 338 indicating that the 01 delimiting configuration of the flag has been received. This signal is used to preset at 2, slot bit counter 340. Slot bit counter counts the slot bits and its content is compared to 8 in comparator 342. Output line 344 of comparator 342 is activated when an equality is detected which indicates a 8-bit medium link boundary. Counter 340 is reset by the output of OR gate 346 which receives the 8-bit flag detect signal on line 318 and the 8-bit medium link boundary signal on line 344.

Latch 348 is set by the 2 bi-t delimiting pattern of the flag received signal on line 338 and reset by the 8-bit medium link boundary signal on line 344, so that it remains set during six bit period after the detection of the 01 delimiting pattern of the flag.

The output line 350 of latch 348 is provided to AND gate 352 which also receives the output line 344 of comparator 342.
Thus the output signal of AND gate 352 is activated so as to ~2~ 3.3~

provide the n and Ns counter reset signal on line 13a during the flag detection period.

Latch 354 is set by the siynal on line 138 and is reset by the 8-bit medium link boundary signal 344 and provides to logic 118 in figure 7 the FLAG/UCC period signal on line 134 which is activated during eight bit period following the last bit of the flag. This signal is needed to compensate the delay of the received bit stream introduced by shift register 127 in figure 7.

During the six bit period following the 01 delimiting configuration of the flag, the received medium bits are shifted in register 356 through AND gate 358 the inputs of which are connected to link 96 and to output line 350 of latch 348. Output bus 132 of UCC register 356 is provided to medium access manager 100 and used to update slot table 106.

Output 350 of latch 348 provides the receive UCC signal on line 136 which is provided to logic 118 of figure 7 corresponding to -the event EMD4 of finite state machine diagram.

AND gate 360 receives the 8-bit medium link boundary signal on line 344, the flag detection period signal on line 350 inverted by inverter 362 and the r received signal on line 130 inverted in inverter 366 and provides on its output line 137 the NEXT SLOT signal used for scanning slot table 106 in figure 7.

The r received signal on line 364 is provided by latch 368 which is set when comparator 117 detects an equality and is reset by the reset signal on line 138. Consequently this latch is set so as to activate the P ENABLE line 120 for gating the r residual bits to the packet path PP.

~ t~t3 It will now be described how the bandwidth is allGcated as a function of the circuit user activity according to the present invention.

During the initialization phase, once the transrnittiny and receiving ends are set into the operational state, i.e. once the parameters are loaded into the transmittiny and receiving parameter registers, all bits which are transmitted between two flags are interpreted as packet switched bits until circuit user slots are established.
These bits are coded and decoded by the ends as a normal HDLC channel. They constitute an HDLC string having a conventional format. Each HDLC frame contains a packet and the two first bytes of the data field of the packet contain a logical channel number LCN as defined in the CCITT
recommendation X.25. This LCN value is set at O to indicate that the corresponding packet is a control packet used for managing a call in the networ~. This constitutes a logical control channel similar to the "D" channel of ISDN. The packets having their I,CN values different from O are used for other flow including the data flow.

The packet types are those defined by the X25 protocol, for example -Call request -Call connected -Clear request -Clear confirmation.

Figure 10 represents two adjacent nodes in a network, one medium link comprising transmit and receive legs is represented between the two nodes. However, other medium links connecting said nodes with other nodes in the network are in fact provided as shematically shown in figure 1.
Figure 10 shows more specifically the protocols and interfaces defined in the system according to the invention.

E'R 9 85 004 Medium interface ~00 defines the mediurrl cornple~ frarnes Medium access interface 402 defines the co~nands used by the medium access manager to control the mediurn access elernen~s such as shown in figures 6 and 7, to add or release circuit switch bandwidth by direct action on the cornple~ frarne.

~ledium configuration control MCC interface 404 defines the format of the messages i.e. packet bits circulating on logical channel 0 (LCN=0) that are the control packets as explained above.

Circuit switched function interface 406 defines the commands to the circuit switching function 408 in order to synchronize this function with the medium configuration. For this purpose, circuit switch function 408 comprises two switching tables 409. These tables are updated by service manager 412 through interface 406 so as to correlate the complex frame slot number on the receive leg of an input link of the node to the complex frame slot number on the transmit leg of the output link which is used for routing the call packets. In the end nodes i.e. originator and destination nodes, the switching tables correlate the circuit user number with one link and incoming and outgoing slots on this link~

Packet switched function interface 410 defines the necessary commands and signals between the service manager 412 and the packet switched function 414 in order to manage the packet flow including the data and control packet flows.

Network service interface 416 defines the messages exchanged between the system manager 418 and the network service function which includes the configuration service, the directory service, the measurement service and the maintenance service.

?~3 There are two kinds of protocols, namely the rnediurrl arcess protocol ~P that describes the e~chanyes over the medium at medium complex frame level ar1d ~hich has been desctribed in connectlon with figures 6 and 7 and the service rnanager protocol S~IP that describes the exchanyes bet~,1een two s~stem managers.

The residual clear channel is configured inside the complex frames built as described above, to carry bit packets using the virtual circuit/ logical channel number VC/LCN of the X25 protocol for example.

As already explained, the LC~1 = O is reserved and the packet circulating on this LCN are routed to the system service manager 418, as a network service communication channel used in cooperation with the metwork configuration services. This channel is schematically shown as the configuration service channel CSC in figure lO.

Figure ll shows the call set up flow through a system node in a specific case. It is assumed that circuit user X
connected to originator node A wants to establish a call with circuit user Z connected to destinator node C, through intermediate node B. Service manager 412 in node A causes the call initiation phase to be entered. During this phase using the asynchronous packet flow (LCN=O), a call request packet is sent by the origlnator node A to node B. This packet includes the called number and potentially the calling number, information indicating that a circuit switched call is to be established and the slot number assigned to user X on the incoming leg of link Ll connecting node A to node B. The opening flag of the subsequent complex frame generated by the transmitting means in node A is set to a value OlOl"xx", indicating that a circuit user is to be added and that slot number "xx" is assigned to it. For example if the complex frames contained 2 circuit slots, slot 3 is assigned to user ~ in the subsequent transmitted .
..

>,,~S
3~
complex frames. The slot table of the transmitting means in node A is upda-ted. The decoding b~ node B o this ne~" UCC
flag indicates to node B , the cornplex Erarne from ~Ihic~ the change is effective.

Node s service manager ~taits for the two correlated information: call request packet and UCC flay OlOl"xx" to determine whether it is the destination node or whether the call request packet has to be propagated to another node found as usual in a network. by consulting routing -tables.

If node B is, as assumed, an intermediate node the service manager in node B checks whether a circuit user slot ma~
still be allocated in the complex frame to be generated on the outgoing leg of the medium link L2 between node B and destination node C. If yes, the call packet is propagated to node C, said call packet including the called number, information indicating that a circuit switched call is to be established and the slot number "yy" assigned to user X in the complex frame generated from B toward C on link L2. The slot table in the transmitting means attached to the medium link L2 between B and C is updated and flag UCC in the subsequent frames transmitted on this link is set to OlOl"yy", where "yy" indicates the slot number assigned to user X on this link.

Receiving means in node C attached to this link receives the so generated complex frames. The node C service manager determines that destination user Z is attached to this node and sent to node B a call connected packet indicating that slot "zz" is assigned in the complex frame to be generated from node C toward node B, to user Z. The UCC flag is set to OlOl"zz".

Detection in node B of the call connected packet and correct correlation with the flag OlOl"zz"" causes the call connected packet to be propagated to node A, the slot table ~L ~ r3~

in the node B rec~iving m~ans con~rolling the me~dium lin~ I,2 between C and s is updated.

The call connected packet is propagated by nodfl ~ to node on the llnk Ll. Service manager in node s assigns slot "tt"
to user Z and the UCC flay in the subseqlient frarnes generated by node s transrnitting rneans controlling the link Ll between B and A is set to OlOl"tt".

Detection in node A of the call connected packet and of flag OlOl"tt" causes receiving slot table of the lin~. Ll between node B and A to be updated and completes the call initiation and call completion phases.

The switching tables in eaeh node are updated when the eall eontrol packets: call request packet and call connected packet are propagated through the node so as to contain the correlation between the slot nurnber on the incoming link with the identification of the outgoing link and slot number on this link. For example in node B, the switching slot tables keep track of the correlation between "xx" on link Ll and "yy" on link L2 and of "zz" on link L2 and "tt" on link Ll.

The eall eontrol paekets may have to be propagated through several intermediate nodes depending upon the routing eapabilities in the network. The sames operations as deseribed above are performed in eaeh node.

If it were found in one of the intermediate node that a eireuit user slot rnay not be alloeated, this occurs when there is no more bandwidth available for eireuit users, a elear request paeket i5 sent by this intermediate node to the originator node.

In ease node B were not an intermediate node, but the destination node, the eall eonneeted paeket or the elear i .~ ..

r ~ r 3 3~
packet as the case may be is directly sent by node B to node A with the flag OlOl"tt" correlated to the call connec~ed packet.

When the call initiation phase and the call corrlpletion phases as described above are comp]eted, a ne~ full duple~
circuit referenced by the slot numbers exists between nodes A and C. The bandwith used to carry these slots has been removed from the asynchronous flow.

Consequently, the complex frames must at any time include some bits dedicated to the asynchronous flow. It is the responsability of the node service manager to determine the minimum bandwidth that must remain available for the asynchronous flow. In fact the call control packets are sent using these bits in as many complex frames as required to transmit them. ~Ihenever this minimum number is reached, attempt to establish an additional circuit slot is rejected (clear phase) The same mechanisms as those described above in connection with the call initiatiorl and call completion phases are used for the clear initiation and clear completion phases for deleting the circuit user slots, except that the C flag bit is set to O instead of being set to 1 and the call request packet is replaced by a clear request packet and the call connected packet is replaced by a clear confirmation packet.

The establishment of a circuit connection between two nodes may involve up to four diferent links in the most general case instead of unique link L1 as shown in figure 11, namely:

- first incoming lin~ transporting the call request packet, in this case the call control information comprises in addition to the slot number, the called number, the calling number and the identification of a 3~ t~

second link on which the circuit slot is to be established, - third outgoing link transportiny the call connected packet, ln this case the call control information comprises in addition to the slot number, the called number, the calling number and the identification of a fourth link on which the circuit slot is to be established.

Although the mechanism of the invention has been described in the specific environment wherein the complex frames have the structure shown in figure 2, the man skill in the art may implement it so as to add or delete circuit user slots in frames having different configurations.

i .

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. System to be used for dynamically allocating circuit slots in the frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, said frames being delimited by flags and divided into bit slots which may be devoted to synchronous circuit flow and to asynchronous packet flow, characterized in that it comprises in each node:

means for changing the flags preceding at least one frame in which at least one slot is to be added or deleted to a value including a first number of delimiting bits and a second number of bits which are coded to indicate that one or more slots are to be added or deleted and the corresponding slot numbers, means for sending call control packets which are propagated through the network nodes, comprising call control information, routing information and indicating the circuit user slot numbers to be added or deleted on specified link interfaces, means for receiving the call control packets and the changed flags for adding or deleting circuit user slots in the subsequent frames depending upon the flag value.

2. System according to claim 1 characterized in that the frames contain at least a predetermined integer number of bits and the first number of delimiting bits is equal to 2 bits which are set to opposite binary values, and the second number of bits include at least two bits, the first one selectively indicating that the remainder of the second number of bits are coded to indicate that a circuit slot is to be added or deleted.

3. System according to claim 1 characterized in that the frames contain at least a predetermined integer number of bits and the first number of delimiting bits is equal to 2 bits which are set to opposite binary values, and the second number of bits include at least three bits, the first one indicating that the following two bits are coded to indicate that a circuit slot is to be added or deleted and the remainder indicating the slot number which is to be added or deleted.

4. System according to claim 1 or 3 characterized in that for adding one or more circuit slots in the frames in order to establish a full duplex connection between a calling user connected to an originator node and a called user connected to a destination node, the call control packet comprises:

a call request packet, which is sent on the transmit interface of one of the originator node outgoing links and which indicates the calling user number, the called number and the slot number to be added on a specified node outgoing link interface, said call request packet being propagated through the network until it reaches the destination node, in such a way that the slot number is updated in each node crossed to indicate the slot number to be added on a specified node outgoing link, a call connected packet, which is sent on the transmit interface of one of the destination node outgoing links and which indicates the calling number, the called number and the slot number to be added on a specified node outgoing link interface, said call request packet being propagated through the same network nodes as the call request packet until it reaches the originator node, in such a way that the slot number is updated in each crossed node to indicate the slot number to be added on a specified node outgoing link.

5. System according to claim 4 characterized in that it comprises means in each node for determining whether one or more slots may be added depending upon the frame configuration, whereby if said means find that the maximum number of slots which may be allocated to circuit users is reached it causes a clear request packet to be propagated to the originator node, said clear request packet comprising the calling number, the called number and the slot number to be deleted on the interface which was previously selected for sending the call request packet and this packet is propagated in the network until the originator node, the slot number being updated in each crossed node so as to indicate the slot number to be deleted on the outgoing interfaces which were previously selected for propagating the call request packet and the opening flags of the subsequent frames sent on these interfaces are set to coded values indicating which slot is to be deleted.

6. System according to claim 5 characterized in that the receiving by the originator node of the clear request packet causes a clear configuration packet to be sent by the originator node.

7. System according to claim 4 characterized in that:
for deleting circuit slots in the frames in order to release the full duplex connection which were previously established between the calling user and the called user, the call control packets comprise:
a clear request packet, which is sent on the transmit interface of one of the outgoing link of the node connected to one of the users and which indicates the calling user number, the called number and the slot number to be deleted on the specified node outgoing link interface, said clear request packet being propagated through the network by crossing the same nodes as the call request packet or the call connected packet depending upon which user initiates the release procedure, until it reaches the node connected to the other user, in such a way that the slot number is updated in each crossed node to indicate the slot number to be deleted on the specified node outgoing link, a clear confirmation packet, which is sent on the transmit interface of one of the outgoing link of the node connected to the other user and which indicates the calling number, the called number and the slot number to be deleted on the specified node outgoing link interface, said clear confirmation packet being propagated by crossing the same nodes as the call request packet or the call connected packet depending upon which user initiates the release procedure until it reaches the node connected to the first user, in such a way that the slot number is updated in each crossed node to indicate the slot number to be deleted on the specified node outgoing link.