CA1245781A - Timing signal correction system for use in direct sequence spread spectrum signal receiver - Google Patents

Abstract

TIMING SIGNAL CORRECTION SYSTEM FOR USE IN
DIRECT SEQUENCE SPREAD SPECTRUM SIGNAL RECEIVER

Abstract A direct sequence spread spectrum transmitter and receiver can be synchronized when the timing reference frequency is less than or equal to the data sampling rate and the ratio of the data sampling rate to the timing reference is an integer by combining two, four or eight consecutive data samples to yield one data sample point. By combining these data samples, an optimum data sample point may be determined while receiving an alternating sign preamble by comparing the magnitudes of all possible summations and selecting the sample which gives a maximum output. If each sample is assigned to its own synchronization point, then synchronization may be accomplished by locking to the time that gives the maximum output.

Description

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44.389 Canada TIMING SIGNAL CORRECTION SYSTEM FOR usæ IN
DIRI~CT SEQ~ENOE SPR~D SPE~ M SIÇ~L RECEIVER

Technical Field The invention relates generally to code division multiplexing using direct sequence spread spectrum signal processing, and more particularly, toward signal processing to increase the number of transmitters multiplexed or a given code length.

Back~round Art In a spread spectr~n system, a transmitted signal is spread over a frequency band that is rnuch wider than the minimum bandwidth required to transmit particular info~nation. ~hereas in other fvrms of modulation, such as amplitude modulation or frequency modulation, the transmission bandwidth is comparable to the bandwidth of the information itself, a spread ~pectrum syst~n ~4~7 .57~

spreads an information bandwidth of r for example, only a few kilohertz over a band that is many megahert:z wide, by modulating the information with a wideband encoding signal. Thus, an important characteristic distinguishing spread spectrum systems from other types of broadband transmission systems is that in spread spectrum signal processing, a signal other than the information being sent spreads the transmitted signal.
Spreading of the transmitted signal in typical spread spectrum systems is provided by (1) direct sequence modulation,

(2) frequency hopping or (3) pulsed-FM or ~chirp" modulation. In direct sequence modulation, a carrier is modulated by a digital code sequence whose bit rate is much higher than the information signal bandwidth. Frequency hopping involves shifting the carrier frequency in discrete increments in a pattern dictated by a code sequence, and in chirp modulation, the carrier is swept over a wide band during a given pulse interval. Other, less requently used, carrier spreading techniques include t~me hopping, wherein transmission time, usually of a low duty cycle and short duration, is governed by a code sequence and time-frequency hopping wherein a code sequence determines both the transmitted frequency and the time of transmission.
Applications of spread spectrum systens are various, depending upon characteristics of the codes being employed for band spreading and ~other ~actors. In direct sequence spread spectrum systems, for example, wherein the code is a pseudo-random sequence, the composite signal acquires the characteristics of noise, making the transmission undiscernable to an eavesdropper who is not capable of decoding the transmission. Additional applications include navigation and ranging with a resolution depending upon the particular code rates and sequence lengths used. Reference is made to the textbook of R.C. Dixon, Spread Spectrum S~stems~ John Wiley and Sons, New York, 1976. especially Chapter 9 for application details.

Direct sequence modulation involves modulation of a carrier by a code sequence of any one of several different formats, such as AM or FM, although biphase phase-shift keying is the most common. In biphase phase-shift keying (PSK), a balanced mixer w~hose inputs are a code sequence and an RF carrier, controls ~he carrier to be transmitted with a first phase shift of X when the code sequence is a "l" and with a second phase shift of (180 ~ X) when the code sequence is a 1l0'-, Biphase phase-shift keyed modulation is advantageous over other forms because the carrier is suppressed in the transmission making the transmission more difficult to receive by conventional equipment and preserving more pcwer to be applied to information, as opposed to the carrier, in the transmission. Characteristics of biphase phase-shift keying are given in Chapter 4 oE the Dixon text, supra.
~he type of code used Eor spreading the bandwidth of the transmission is preferab].y a linear code, particularly if message security is not required, and is a maximal code for best cross correlation characteristics. Maximal codes are, by deEinition, the longest codes that could be generated by a given shift register or other delay element of a given length. In binary shift register sequence generators, the maximum length (ML) sequence that is capable of being generated by a shift register having n stages is 2n _ 1 bits. A shift register sequence generator is formed fram a shift reg ster with certain of the shift register stages fed back to other stages. The output bit stream has a length depending upon the number of stages of the register and feedback employed, before the sequence repeats. A
shift register having five stages, for example, is capable of generating a 31 bit binary sequence (i.e. 25 - l), as its maxlmal length (ML) sequence. Shift register ML sequence generators having a large number of stages generate ML sequences that repeat so infrequently that the sequences appear to be random, acquiring the attributes of noise, and are difficult detect. Direct sequenoe sys~e~s are thus sometimes caLled "pseudo-noise' systems.
Properties of maximal sequences are sumnarized in Section 301 of Dixon and feedback connections for maximaL code generators from S 3 to 100 stages are listed in Table 3.6 of the Dixon text. For a 1023 bit code, corresponding to a shift register having 10 stages with maximal length feedback, there are 512 "l"s and 511 "O"s; the difference is 1. Whereas the relative positions of ~lns and "onS
vary among ML code sequences, the number of "l~s and the number of "O"s in each maximal length sequence are constant for identical ML
length sequences.
Because the difference between the number of "l"s and the number of "0"9 in any maximal length sequence is unlty, autocorrelation of a maximal linear code, which is a bit by bit lS comparison of the sequence with a phase shifted replica of itself, has a value of -1, except at the 0 + 1 bit phase shiEt area, in which correlation varies linearly from -1 to (2n - 1). A 1023 bit maximal code (2n - 1) therefore has a oeak-to average autocorrelation value of 1024, a range of 30.1 db.
It is this characteristic which makes direct sequence spread spectrwm transmission useful in code division multiplexing.
Receivers set to different shifts of a common ~L code are synchronized only to transmitters having that shift of the common code. Thus, more than one signal can be unambiguously transmitted at the same Erequency and at the same time. In an autocorrelation type multiplexed system, there is a common clock or timing source to which several transmitters and at least one receiver are synchronized. The transmitters generate a common maximal length sequence with the code of each transmitter phase shifted by at least one bit relative to the other codes. The receivec generates a local replica of the common transmitted m2ximal length sequence having a code sequence shift that corresponds to the shift of the particular transmitter to which the receiver is tuned. The ~457~.~

locally generated sequence is autocorrelated with the incoming signal by a correla~ion detector adjusted e;o as to recognize the level associated with only ~ l-bit synchronization to despread and extract information from only the signal generated by the predetermined transmitter.
Because the autocorrelation characteristic of a maxirnal length code sequence has an orfset corresponding to the inverse of the code length, or V/(2n 1) where V is the magnitude of voltage corresponding to ~1" and n is the number of shift register stages, overlap occurs in neighboring channels. Thus, there is imperfect rejection of unwanted inc~ming signals. Unambiguous signal discrimination thus requires a guard band between channels reducing the number o~ potential lS transmitters ~o~ a given code length. A long maxirnal length sequence ccmpensates eor the guard band to increase the nurnber of potential transmitters, but this slows synchronization and creates power imbalance of the multiplexing transmitters.
In one ~ype of code division multiplexer a pLurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the cl~ck, discriminates the signal transmitted by a predetermined transmitter frcm signals transmitted by the others by cross-correlating the incoming signal with a trinary sequence that is developed at the receiver. The receiver develops the trinary sequence by generating a first pseudo-random code tha~ is a replica of the common bipolar pseudo-randcn code tr~nsmitted by the transmitters and having a code sequence shift corresponding to that of the predetermined transmitter to which the receiver is tuned, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift.

Correlation consists of multiplication of an incoming signal with the local reference signal that corresEonds to the difference between the first and second bipolar pseudo-random code sequences. Integration of the product averages out random noise to enhance the signal-to-noise ratio. When the information transmitted is binary, two different waveforms are generatecl: one for a "zero" and another for a "one" at the receiver. When the transmitted signal is biphase, the transmitted waveforms for a "one" and a "zero'~ differ from each other by a 180 phase shift. When the predetermined transmitter and the receiver are synchronized with each other, the multiplier output is at a maximum at a positive polarity for a "one" and a negative polarity for a "zero". The multiplier output is integrated for the duration oE l-bit period. If the initial integrator output is "zero" then the polarity of the integrator output at the end of a bit period corresponds to the transmitted binary information.
The degree of correlation between the predetermined transmitter and the receiver is determined by comparing the outputs of several correlation detectors having reference signals that are displaced in time with each other. Each detector develops ~o output signals, an in-phase signal that is at a maximum and a quadrature-phase signal that is at a minimum when the receiver and predetermined transmitter are aligned. The receiver is fine tuned to the predetermined transmitter by adjusting the receiver timing until the quadrature-phase signal is minimized.
During fine tuning of the receiver, a decision is made on each incoming sequence bit whether to advance or retard receiver timing by an equal fraction of a ccde chip. The receiver timing is advanced by the code chip fraction if the in-phase and quadrature-phase correlation signals are of opposite polarity. If the in-phase and quadrature-phase correlation signals are of the same polarity, the receiver timing is retarded.

During perfect correlation between the receiver and predetermined transmitter, however, the fine tuning mechanism of the receiver tends to drive the receiver timing from the optimum reception point, causing the receiver to continually search for correct synchronization, since there is no deadband. Further, because there is a delay inherent in the feedback loop of the receiver, the correction decision is made using information more than one data bit old, causing the receiver to tend to overshoot as it attempts to lock in the optimu~ synchronization point.
As another problem, a direct sequence spread spectrum receiver does not readily distinguish between a signal and noise, particularly slnce the int_oming signal is a data modulated carrier that is spread by a pseudo-noise sequenoe.
The receiver will thus tend to attempt to lock onto noise in the absence of a signal.
Disclosure of Invention It is accordingly one ob;ect o~ the invention to improve synchronization in a direct setquence spread spectrum receiver.
A further object is to improve receiver synchronlz-ation in a direct sequence spread spectrum receiver in which the data sampling rate can be higher than the timing signal frequencyO
These and other objects are satisfied by the method ctf the present invention which improves the synchronization between a transmittar and a receiver used in a direct sequence spread spectrum code division multiplex system, and in particular where a plurality of transmitters and at least one receiver are synchronized ~o a common timing signal source. Each transmitter transmits a data signal spread by a pseudo-random code which is a different assigned shift of a common code sequence. The receiver is synchronized to one of the transmitters transmitting a data signal spread by the pseudo-random code having a predetermined assigned code sequence and to the timing signal source by the steps of sampling the data signal at a rate equal to the fret~lellcy ~.2~

of the timing signal source or an integral multiple thereof, combining one or more consecutive data samples together to generate a data sample point corresponding to a particular timing point of the timing signal source, detecting which one of the data sample points has a maximum value, and locking the receiver to the timing point of the timing signal source corresponding to which one of the data sample points is detected as having a maximum value.
An advantage of the a~ove method is that it eliminates the need for redundant data channels sampling each point of possible synchronization ambiguity. Further, the above method allows data sampling to take place at a rate fa~ter than the ~requency of the timing signal source. By combining together consecutive data samples to generate a data point, data sampllng may takQ place at a rate greater than the net data rate, which is in eEfect the number of data sample points or bits (generated from the combination of one or more consecutive data samples) per second.
This arrangement allows the data samples to be combined digitally ~for example in a microprocessor) and allows the data rate to be independent of the actual hardware timing.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from tne following detailed description, wherein there is shown and described only the preferred embodiment of the invention, simply by way of illustration of the best mKdes contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and that several details are capable of modification in various, obvious respects, all without departing from ~he invention. Accordingly, the drawings and description are to be regarded as illustr~tive in nature, and not as restrictive.

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Brief Description of the Drawings Figure 1 is a simplified block diagram showing a DSSS code division multiplex receiver;
Figure 2 is a representation of a bipolar pseudo-random pulse sequence;
Figure 3 is a diagram showing an autocorxelation pattern for a bipolar pseudo-random pulse sequence of the type shown in Figure 2;
Figure 4 is a superposition of several autocorrela-tion patterns corresponding to neighboring transmitters in a code division multiplex system;
Figure 5 is a diagram corresponding to Figure 4, with signals of neighboring transrnitters separated by guard bands;
F:igures 6(a)-6(d) are wave forms showing trinary code generation;
Figure 7 is a simplified block diagram showing a receiver operated in accordance with the principles of the invention;
Figure 8, on the second sheet of drawings, is a diagram showing an ideali.zed cross-correlation pattern between a locally developed trinary code sequence and an incoming binary code sequence in accordance with the invention;
Figures 9(a)-9(c) are diagrams showing correlation patterns developed by multiple channel correlation detectors in accordance with various embodiments of the invention;
Figure 10, on the fourth sheet of drawings, illus-trates an actual correlation pattern obtained in the receiver of the present invention when operated in the presence of various degrading fac-tors;

Figure 11 illustrates an analog embodiment of mul-tiple correlation detectors for determining the degree of cor-relation in accordance with the invention;
Figure 12 is a circuit simplification of the analog embodiment of Figure 11 using binary reference signals;
Figure 13 is a further circuit simplification of the analog circuit of Figure 11, using digital logic to reduce the number of analog multiplexers;
Figures 14(a) and 14(b) illustrate two methods of implementing the circuit of Figure 13;
Figure 15 is a digital implementation of one channel of the circuit shown in Figure 11;
Figure 16 is an N-channel generalization of the cir-cuit implementation in Figure 15;
Figure 17, on the tenth sheet of drawings, shows another digital implementation of a single channel correlator of a type shown in Figure 11;
Figure 18 is an N-channel generalization of the circuit shown in Figure 17;
Figure 19 illustrates an in-phase and quadrature-phase correlation pattern, together with -the locations of sub-receiver channels for correlation detection;
Figures 20(a) and 20(b) are flow charts showing two alternative methods for performing fine tuning of the receiver;
Figure 21~ on the seventh sheet of drawings, illus-trates a microprocessor based circuit for performing fine tuning of the receiver and signal presence detection;
Figures 22(a) and 22~b) are flow charts respectively showing methods for correcting receiver timing and for performing signal presence detection and appear on the fifteenth and four-teenth sheets of drawings, respectively;

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-lOa- 60398-11540 Figure 23 is a flow chart showing one technique for performing coarse tuning of the receiver;
Figures 24(a) - 24(e) are timing diagrams showing the relationship of timing pulses between a transmi-tter and a receiver;
Figure 25, on the ninth sheet of drawings, illus-trates a circuit for locking a transmitter and receiver to the same timing pulse; and Figure 26 illustrates a microprocessor based circuit for performing data recovery in the receiver.
Best Mode for Practicing the Inven-tion .
General In spread spectrurn communica-tions, sp.read.Lng of signal bandwidth beyond -the bandw:Ld-th normally rcqui.red Eor clata belng transmitted is accGmplished by first phase shift keyed (PSK) mcdulating a carrier waveform by data to be transmitted, and then modulating the resulta~t signal by a reference pseudo-random code of length L running at a reFetition rate which is normally at least twice the data rate. Forms of modulation other than PSK can be applied to modulate the carrier as ~ell as to spread the composite signal, although PSg is preferred for reasons set forth earlier.
To d~modulate the signal transmission, the received signal is heterodyned or m~Ltiplied by the same reference code as the one used to spread the co~posite transmission, and assuming that the transmitted and locally generated receiver codes are synchronous, the carrier in~ersions caused by the code PSR modulation at the transmitter are removed and the originaL base-band modulated carrier is restored in the receivar.
Figure l illustrates the Eundamental elements o~ a basic spread spectrum receiver incorporating one aspect o the invention. Receiver lO0 receives a direct sequence spread spectrum ~DSSS) signal transmitted by a particular transmitter among a plurality of such transmitters, and processes the received signal to discriminate the signal transmitted by the particular transmitter fr~m among the signals transmitted by all the trans~itters. Bearing in mind that the received signal is essentially modulated twice, that is, the carrier is modulated 2~ with data and then the composite is modulatQd oy a pseudo-random code sequence to spread the cG~posite over a bandwidth that is comparable to the bandwidth of the pseudo-random sequence, receiver 100 provides two stages of demodulation of the received signal to extract the transmission data. The received DSSS signal is first heterodyned or multiplied by the code of the particular transmitter whose signal is being discriminated from amcng tne others. Thus, assuming that the codes generated at the transmitter and receiver are synchronous, the carrier inversions caus~d b~ the code PSK modulation at the transmitter are removed ~iæ~ 7~ .

at multiplier 102, and the original base-band modulated carrier is restored. The narrcw-band restored carrier is applied to a band pass filter (not shown) designed to pass only the base~band modulated carrier. Base-band data are then extracted by heterodyning or multiplying the restored carrier by a locally generated carrier at multiplier 104. The ou~put of multiplier 104 is applied to a conventional correlation filter 106, such as an integrate and dump circuit, followed by a sample and hold circuit which develops signals corresponding to the transmitted data.
qhe receiver 100 is controlled by a standard microprocessor 108, synchronized to a system clock 110, to which the transmitters are also synchronized. Because noise and undesired transmissions are treated in the same process of multiplication in multiplier 102 by the locally generated reference code that compresses the received direct sequence signal into the original carrier bandwidth, any incoming signal not synchronous with the locally generated reference code is spread into a bandwidth equal to the sum of the bandwidth of the incoming signal and the bandwidth of the reference code~ Since this unsynchronized input signal is mapped into a bandwidth that is at least as wide as the reference code, a band pass filter can reject a significan~ amount of the pcwer of an undesired signal. This is the significance of a DSSS
system: synchronous input signals at the reference code modulated bandwidth are transfo~med to the base-band modulated bandwidth, ~hereas non-synchronous input signals remain spread over ~he code-modulated bandwidth.
Synchronization processing makes use of a property inherent in the particular code that is employed at the transmitter. ~he autocorrelation of a maxi~al length (ML) sequence, that is, multiplication of the sequence by a time shifted replica of itself, is at a peak when synchronization is achieved and has an absolute value tha~ drops to -P2/L, where P is the magnitude of the code sequence and L is the code leng~h, as synchronization becomes lost (i.e., the time difference between the code and its replica approaches a code chip or greater). The sign of the aut~correlation pattern is dependent uFon the data bit being used to modulate the transmitter. It i~ thu possible to recover the transmitted data a~ the receiver by monitoring the sign of the autocorrelation output when the receiver and transmitter are properly synchronized.
Referring to Figure 2, a ~seudo random code sequence of a type to which receiver 100 is tuned is bipolar, tha~ isl it is assumed to switch polarities of a constant voltage pcwer supply.
In the invention, bipolar, rather than unipolar, sequences are used to improve power transmission efficiency, since the carrier is suppressed in bipolar transmission. Bipolar transmission also avoids high concentrations o ener~y in any fre~uency band to help avoid interference between transmissions by diferent transmitters in the system. Eac~ bipola~ sequence has a magnitude P and a chip duration Tc. The length of the M1 sequence depends upon ~le number of different transmitters whose signals are to be code-division multiplexed within the system. Each transmitter is assigned the same transmission code having a different specified chip of the ccmmon ML sequence. The m~ximum numcer of transmitters that are capable of being multiplexed within this system thus corresponds to the length of the ML sequence~
The n~m~er of transmitters that may ~e multiplexed without interference within a code-division multiplex system of this ty,~e is equaL, theoretically, to the bit length of the sequence. For an ML code having a length of 63 bits, for exampLe, the transmission channel is theoreticaLly capab]Q of multiplexing 63 different transmitters. This assumes that svnchronization is deemed to be achieved between the receiver and a preselected transmitter when the autocorrelation between the code received fram the transmitter and the locally generated code, both synchronized to a ccmmon timing source, is at a peak. In practice, however, the number of tran-smitters that can be code division multiple~ed in the system is much lower than the theoretical maximum, because there is overla~ between neighboring correlation curves due to the -P /L term in the autocorrelation of the ML sequence. This can be better appreciated with reference to Figure 3 which shows a correlation cur~e for a single S transmission and Figure 4 which shc~s a number of csrrelation curves for neighboring transmissions, that is, for transmissions that are time offset from each other by a single code chip.
In Figure 3, the correlation curve has a magnitude -~2/L
when the transmitted and locally generated code sequen oe s a~e time offset fr~m each other by greater than a code-chip Tc, where P
is the absolute magnitude of the sequence and L is the se~uence length in bits. When the transmitted and locally generated codes are near synchronization, that is, are within a time offset of one code chip of each other, the correlation increases in magnitude to a peak of ~2 at perect synchronization. Thus, synchronization between the receiver and a single transmitter can be detected by monitoring the correlation output and deeming synchronization to exist when the correlation signal is above a predetermined positive value.
Referring now, however, to Figure 4, assume that there are three transmitted code sequences ~, k-l and k+l, time shifted from each other by a single code chip. ~ach correlation has a positive peak value of p2 and a negative peak value of _p2/~l as in Figure 3. The correlation curves of neighboring code sequences overlap, within the reglons shown by cross-hatching in Figure 4.
In those regions, neighboring code sequences have common correlations, making it impossible to distinguish between transmissions. .~s a practical matter, to avoid interference between transmissions, it is necessary to insert a guard band between sequences, as shown in ~igure 5. This is provided by assigning transmissions to sequence shifts corresponding only to alternate code chip delays, rather than to every code chLp delay as in Figure 4. The result is that, at best, only one-half the number of transmissions, conpared to the theoretical maximum nunber, can be mul~iplexed. In practice, even fe~er than one-half the theoretical maximum transmitters are capable of being multiplexed in a code division multiplex system using bipolar sequences because a guard band that is greater than that provided using only alternate code shift delays is required to avoid synchronization ambiguities.
In accordance with one aspect of the invention, the number of transnitters that are capable of being multiplexed is increased to one less than the theoretical limit by cross-correlating the in~ut signal with a trinary code developed by obtaining the difference between the code sequence assigned to the particular transmitter to which the receiver is tuned and a code sequence that is Imassigned. In other words, two bipolar code sequences are developed at the receiver. One of the codes is the repLica of the common code sequence transmitted by all the transmitters and has a s~quence shift that corresponds to the sequence s~ift of a predetermined one of the transmitters. The second code is a replica of the common bipolar sequence and has a code sequence shift that is not assigned to any of the transmitters. One of the locally generated codes is subtracted from the other, and the resultant, which is a trinary code sequence, is correlated with the incoming signals. ~he sequence shift of the trinary code sequence is brought to within one code chip of the sequence generated by the preselected transmitte~, using a static synchronization technique to be described keLow. Perfect synchronization bet~een the receiver and preselected transmitter is obtained using dynamic synchronization, also to be described in detail ~elow, obtained generally by successively shifting the timing of the receiver by a fraction of a code chip and monitoring the ou~put of the correlator. When the correlation output is at a peak, the receiver and preselected transmitter are considered to be synchronized to each other. Assuming ncw that the receiver and transnitter are also synchronized to corresFonding clock pulses (i.e., the transmitter i5 not synchronized to one clock pulse and the receiver synchronized to another~, the polarity of the correlation output is monitored to extract the transmitted data.

.S7 ~evelopment of the trinary pulse sequen oe to be cros~-correlated with the transmitted sequences is better understood with reference to Figures 6(a)-6(d). In Figure 6(a), a transmitted bipolar sequence s(t) having an absolute magnitude P
S and chip period Tc is shown. This sequence is a simplification of an actual se~uence which, in practice, wo~d be substantially langer, e.g., 63 bits. Within the receiver i9 developed a first reference pulse sequence r(t) shown in Figure 6(b). The se~uence r(t~ is identical to the sequence s(t) transmitted by the predetermlned transmitter shown in Figure 6(a), because the transmitter and receiver sequences have the same delay and are presumed synchronized to each other.
The receiver generates a second reference pulse sequence e(t)l shown in Figure 6(c), which is the same sequence as the one transmitted by the preselected transmi~ter as well as by all the other transmitters but has a sequence delay that is not assigned to any of the transmitters.
The difference [r(t) - e(t)] between the two locally generated reference pulse sequences is obtained, to provide the trinary pulse sequence shcwn in Figure 6(d). The trinary sequence has a value [+2, 0, -2], depending upon the relative binary values of the t~o reference pulse sequences r(t) and e(t).
It is to be understood that the sequence length in the example shown in Figure 6 is 7 bits, although in practice, much longer sequences would be applied to accommodate a relatively large nunber of transmitters to be code division multiplexed.
Referring to Figure 7, development of the trinary reference sequence to be cross-correlated with incoming bipolar pulse sequences for signal demultiplexing is provided in a receiver 200. The receiver 200 receives the transmit~ed pulse sequences s(t) and applies the incaming sequences to the inputs of a first correlation multiplier 202 and a second correlation multiplier 204. The first correlation multiplier 202 multiplies the incominy sequences s(t) by the locally generated reference pulse sequence ~ 3 r(t) having a sequence shift corresponding to the 5 quence shift of the preselected transmltter. The multiplier 204 multiplies the inccmin~ sequ~nces s(t) by tne pulse sequence e(t) having an unassigned pulse sequence shift. The resultant multiplication products are applied to a difference circuit 206, and the difference is integrated and sampled in a standard correlation filter 208 to develop an output signal YOut.
It is pointed out that in Figure 7, the input s~quences s(t) are first multiplied respectively by the two reference pulse lG sequences r~t) and e(t), and then the product difference is obtained in difference circuit 206. This is e~uivalent to obtaining the differenc2 between the two reference pulse sequences r(t) and e(t) and then multiplying the difference by the incoming sequences s(t).
The resultant cross-correlation is shown in Figure a. Note that each correlation curve has a value 0 when the preselected transmission and locally generated reference sequence r(t)-e(t) are displaced from each other by more than one code chip. This contrasts with the cross-correlation curve of Figure 3, wherein there is a negative residual correlation having a magnitude P2/L. Ihe magnitude of the correlation curve increases linearly to a peak value of P(L~l)/L when the preselected transmitted and locally generated reference pulse sequences are synchronized.
The advantage of-this correlation strategy is appreciated by camparing Figure 9a shGwing the correlations of a number of neighboring transmissions in accordance with the invention and Figure 4. In particular, Fig. 9a shows codes with a separatlon of 2 code chips. However, it will be appreciated that the Figure 9a transmissions can be displaced from each other by a single code shift and that there is no overlap between the correlations of adjacent transmissions, whereas in Figure 4, overlap occurs in ~he cross~hatched portions. The invention thus enables the number of tr~nsmissions capable of being multiplexed ~o be equal to one less than the length of the pulse sequence in bits, a result that is i7~ .

not possible usiny prior art systems. Even if a guard band is placed bet~een transmissions in the str~tegy sho~n Ln Figure 9a, the number of transmissions tnat can be reliably multiplexed is substantially greater than the number that can ~e reliably multiplexed using the correlation strategy shown in Figure 4.
Assume that the code-division multiplexed PSK signal Y(t) incoming at the receiver is expressed as follows:
Y(t) = ~ PjdjXj(t)cos(W~t + 0) + ~(t) (1) - where or J incoming transmissions:
O ' t C T, where T is a code chip period;
P is the pcwer within each incoming bipolar pulse sequence;
d~ ls the polarity or sign of each corresponding incoming sequence;
Xj(t) is the transmitted data;
Wc is the frequency of the carrier in radians;
0 is the carrier phase; and N(t) is noise.
The output ~A(T) of the conventional receiver, using a single reference code sequence, is defined by the following:
1 ~
V~(T) = Prdr + L ~ Pjdj + ~A (2) ~=1 j~r where:
2S P is the pcwer of the desired incoming seqyence;
dr is the data sign of the desired sequence;
L is the pulse sequence length in bits;
P. is the pcwer o each of the undesired sequences;
dj is the corresponding data sign of the undesired sequence; and NA is noise.
The output V3(T) of the receiver operating in accordance with the principles of the invention is defined as follows:
VB(T) a Prdr (1 ~ lJL) + NB (3) Because the correlation method o the invention involves a subtraction of a code sequence having an unassigned code sequence shift, all undesired transmission ccmponents (identified by the subscript "rn) in the output VB~T) are perfectly rejected, whereas in the prior art receiver, the output VA(T) in~olves contributions of the undesired transmissions ~having the subscrip~
"j') as well as the desired transmissions (subscript ''r").
Multiplexer trin ry signal correlation induces an additionaL
three decibels of degradation in data signal-to-noise dem~dulation with resp~ct to white noise appearing at the receiver input, compared to conventional correlation using only the particular transmission binary pulse sequence. Thus, NA

__ (4) N2 ~ 2(1~1/L) N2.

The multiplexing strategy discussed above results in perfect unwanted access rejection capability using ~L codes of any length in a code-division multiplex system. In the past, only ML codes of sufficiently long length were potentially usable with the number of allowable multiplexers being much less than the code length. Even there, power imbalances of the multiplexing transmitters occurred.
hdditionally, the ideal cross correlation pattern in Fig. 9a lends its~lf to multiplexing schemes using more than the theoretical limit of code, each time-of~set by less than a code chip, and assuming a more complex receiver configuration. For example, it has been discovered that the number of transmitters which could be multiplexed can be increased to 2 x (~-2) channels by adding a code between each of the code sequences shcwn in Fig.
4, with only a slight trade off in overall receiver signal-to-noise performance. As shown in Eig. 9b an additional code can be inserted between each of the codes shown in Fig. 4.
~he codes are detected at a pLurality of taps provided at the receiver. The ou~puts of the various receiver taps shown in Fig.
9b are as follows:

T~B~Z I
1. extra code 2. l/2 extra code

3. null s 4. 1/2 code 1 5. oode l ~ 1/2 code 1' 6. l/2 code 1 + code l' ~ 1/2 code 2 7. 1/2 code 1' + code 2 -~ l/2 code 2' The sequence of equations m2y then be solved for each channel:
channel 1 = 2 x tap 4 channel 1' = 2 x (tap 5 - channel 1) channel 2 = 2 x (tap 7 - channel 1' - tap 4) channel 2' = 2 x (tap 7 - channel 2 - tap 5) ,. .. ..
channel L' = 2 x tap(2L ~ 3) In practice, the above arrangement would be somewhat difficult to implement due to both noise and synchronization problems. An alternative implementation would re~uire that a null of the carriers occurred at the point where the correlation envelope is equal to 1/2 the maxlmum. In such an arrangement, the equations for the outputs of the ta~s beco~e:

~5 l. extra code 2. null 3. null

4. null

5. code 1

6. code 1'

7. code 2 This arrang~ent allows for full data recovery without Lnterference. However, it may still be somewhat susceptible to noise.

In order to overcome the above problems, there is shown in Fig. 9c an arrangement in which two or more code sequences are grouped together and se~arated by guard-bands. ~he exact separation of the groups or the patterns comprising the groups is independent of this arrangement. This approach also allows th~
grouping of transmitters with similar characteristics and sim~lifi~s synchronization problems.
Any additional modulation by data bearing sisnals and that necessary for improved ccmmunication between transmitters and receivers can be incorpocated in the above descr~bed strategies.
The only condition required is that any additional modulation must not destroy the necessary timing of the shifted pulse sequences thereby maintalning receiver multiplexing sensitivity.

Synchronization - General The receiver and preselected transmitter must be time synchroni2ed to each other before data can be extracted. Assuming that ~he receiver and transmitter are synchronized to a common timing source (if the ccmmercial power line is the transmission medium, common timing can be obtained from the 60 Hert~ pcwer source~, synchronization is a matter of adapting receiver timing to different propaga~ion delays of the transmitted signal as well as to the timing signal and to delays inherent in the transmitter and receiver. SGme of these delays are fixed, and can be compensated using a "static" delayl to synchronize the receiver and predetermin d transmitter to within one code chip of each other, wherein a chip is defined as the bit period of the pseudo-random code generator.
In general, static delay can be compensated during initial calibration of the re~eiver, since most static delays are fixed.
difficulty occurs, however, wnen the transmission medi~m is a transmission line with the transmitter and receiver synchronized to a co~mon tLming source, and wherein communication between the two units is bidirectional. Static delay must thus be examined from two reference points, one where the transmltter is at the timing sou~ce and the other where the receiver is at the timing source.
With the transmitter located at the timing source and the receiver located elsewhere, the timing signal and transmitted signaL will propagate at approximately the same speed from the transmitter to the receiver. Other timing variations bet~een the transmitter and receiver are due to delays i~duced within the transmitter and receiver circuitry, and can be preset to synchronize the tra~smitter and receiver to within one code chip of each other. ALL receivers remote from the timing source can thus have identical static delays.
IE the receiver is located at the timing source and the transmitter is located elsewhere, however, each receiver may re~uire a static delay that is unique or each remote transmitter to account for different signal propagation distances. Thus, to enable a receiver to receive sign~l~ from a multiplicity of transmitters, the sta~ic delay of the receiver must be variable.
In practice, the static delay between each transmitter and the receiver is measured upon instalLation of the transmitter; that static delay vaLue for all future comm mications with a particular transmitter is preset within the receiver. Whenever a transmission is received from that transmitter, to obtain united synchronization of the transmitter, receiver timing is aut atically adjusted to accom~odate the delay associated with the particular transmitter.
In one embodiment of the invention, there are a plurality of transmitter/receiver units disposed in a so-called "master/slave"
arrangement. In this arrangement, one transmi~ter/rec~iver unit, called the master station, acts as the source of t~ming signals for the other stations (slave units). The amount of deLay associated with the timing signals between the master station and each of the slave stations includes such things as the filter delay for the timing signal source at the master station, the ~ '7 received filter delay at the master station, the signal propagation delay between the mzster and a particular slave, the coupling delay at the master station and the transmit filter dela~
at the master station. Knowledge of these various delays will give an estimate of the a~ount of static delay associated between the master station and a particular slave station. ~owe~er, some variation in each delay will occur with changes in the transmission line associated with ~emperature changes, transmission frequency, etc.
While dynamic delay adjustments can take care of most of these changes in the st~tic delay characteristics between tne m2ster and slave units, the multiplexing capabilities of the system may be somewhat reduced because the receiver at a particular master or slave unit must be capable of tracking delay variations lS over a range of severaL code chips~ This requires a guard band that 13 wide ~nough ~o allow the signals of two adjacent receivers to vary in time over their associated bands without interference.
~owever, it has been discovered that the amount of required guard band may be reduced by seriodically measuring, at the master station, the static delays associated with signal transmission bet~een the master station and each of the slave stations and then periodically adjusting the transmitter signal timing at the slave in order to bring the static delay back into a desired range.
This allows more slave stations to transmit at one time since the guard band re~uired for delay variations can be greatly reduced ~hus allcwing more usable code delays for multiplexing.
Variations fram synchronization established by the static delay are cc~pensated by a dynamic delay mechanism within each receiver. The dynamic delay consists of two s~ages: fine tuning and coarse tuning. Whereas static delay timing causes the receiver and predetermined transmitter to be synchronized to each other to within one code chip, fine tuning uses correlation detec~ion to make fine adjustments in receiver timing as a function of received transmission, rather than as a function of an expected transmission (static delay).
After fine tuning has established that receiver tLming is at a local correlation peak, it becomes necessary to determine if the local peak to which the receiver is timed is the "correct" local peak for best correlation. This is necessa,ry because, depending upon the correlation properties of the code selected, as well as other factors, there are likely to be multiple correlation peaks, with the primary local peaks having the greatest peak magnitude.
These multiple peaks arise from carrier correlation within the ~lTc code correlation peak. Finally, it must be determined which of the system timing pulses present in each data bit is the proper one for synchronization. Without such a determination, a condition can exist wherein the transmitter is locked to one timing pulse while the receiver is locked to another ~Lming pulse. This is because these are two timing pulses in a data period and incorrect timing causes a quadrature condition between transmitter and receiver data periods. Thus, the net energy for such quadrature data periods is zero. Even with the receiver and transmitter properly synchronized to each other, data cannot be extracted from the received sequence because i~ is not possible to detect and decode the data transmission unless the receiver and transmitter are locked to the same timing pulses. Fine tuning and coarse tuning as well as synchroni~ation to the proper timing ~5 pulse within each data bit shall now be described in more detail.
Figure 10 illustrates the correlation pattern obtained by cross-correlating an inco~ing, bi-polar pulse sequence together with its carrier and the locally generated trinary reference se~uence. The correlation pattern has a major peak at receiver tLming Vl and has minor correlation peaks at recelver timings V2~
V3, V6 and V7, referred to hereinafter as "channels". The correlation peak at primary channel Vl depends upsn the correlation properties of the code selected as a function of code chip tLme delay difference between the incoming code sequence and ~ ;~4.~-i7~ .

the reference code sequence. m e correlation is at a peak when synchronization between ~he receiver and tran~nitter is achie~ed, with the absolute value of the correlation dro!~æing to zero as the synchronization differen oe aFproaches a code chip or greater. It ~hould be noted that, due to imperfect correlation ~roperties of the code and due to ~he influence on correlation by the sinusoidal carrier, the correlation shown in Figure lO is ap~roximately sinusoidal as ccmpared to the piece-wise linear, ideal correlation profile shown in Figure 9a which does not include a carrierO This is the reason that coarse tuning is required; fine tuning adjusts receiver timing until a correlation peak is determined; coarse tuning then determines whether the correlation peak is the ma~or correlation peak associated with channel Vl or is a minor correlation peak associated with channels V2, ~3, V6 or vr/~ or others.
In accordance with one aspect of the invention, synchronization of the receiver is achieved by providing a plur lity of se~arate sub-receivers or correlation detectors that are tuned to each receiver channel. Assuming that each of the zo channeLs Vl, V2, V3, V6 and V7 are spaced apart from each other in time by one third of a code chip, fine tuning adjusts the receiver tlming such that the channeLs are all located at local peaks.
Furthermore, assuming that channel Vl is within a code chip of b~ing synchroni~ed, the channel Vl is within one 3ixth of a ccde chip of a local peakn The outputs of the correlation detectors are applied ~o a microprocessor 314, described below, to develop a receiver timing signal for synchronization to the transmitter and to extract transmission data~ Various embcdiments of the multiple correlation detectors are illustrated in Figures 11-18.
Correlation Detection One embodiment of the multiple channel correlation detector slhown in Figure ll is generalized for N correlation channels. The multiple channel correlation circuit identified generally by 300 ca~prises for each channel a correlator 302 each camprising a first multiplier 304, a second multiplier 306 and a difference circuit 308. ~he first muLtiplier 304 has one input that receives the incGning sequences s~t) and a second input that receives the first locally generated reference sequence r(t) having a sequence shift that corresponds ~o the sequence shift of a predetermined transmitter. ~he multiplier 306 has one mput that receives incaming sequences s(t) and a second input that receives the second reference sequen oe e(t) having an unassigned sequence shift. The outputs of the two multipliers 304 and 306 representing, respectively, the products of the incoming sequences and the two locally generated reference sequences are applied to the inputs of difference circuit 308. The difference output is applied to an integrate and dump type filter 310, matched to the period of a bit at the chip rate, to develop a signal VN or each channel as follows:

VN = S S(t)[r(tN) - e(tN)]dt wherein VN and s(t) are analog signals while r(tN) and e(t~) are binary signals. The out2ut of the integrate and dump circuit 310 is applied to a sample and hold circuit 312 which monitors and stores the magnitude and polarity of the integrator output V~.
This value if applied to a conventional microprocessor 314 that in response to outputs from all N of the detectors 302 extracts the binary data from the predetermined transmission and develops a tLming error signal to retain t~he receiver locked in synchronism with the predetermined transmitter, as discussed in more detail below.
The analog multiple channel correlation detector shown in Figure 11 requires a substantial number of calibration adjustments associa~ed with the multipliers 304, 306, the difference circuits 3089 the integrate and dw~p circuits 310 and the sample and hold circuits 312. In practice, an 8-channel detector of this type requires approximately 80 calibration adjustments.

If only the polarity of ',he reference sequences r(t) and e(t) is used, considerable si~plification of the system results, with only a slight de~radation in perorm~nce. Because the two reference sequences are binary (bi-polar) signaLs, multiplication can ~e achieved in an N channel correlator using ZN two;input analog multiplexers and one inverter, shown in Figure 12~ In this implen~ntation, the binary reference signal determines whether the input signal s(t) or an inverted input signal s(t) is selected to be applied to subtrac~ion circuit 308. Bearing in mind that the desired output of each of the N difference circuits 308 is s(~)[r(t~) - e(tN)], each channel in the correlation detector 400 sho~n in Figure 12 comprises a first two-input multiplexer 402 and a second two-input multiplexer 404 controlled, respectively, by the instantaneous polarities of the first and second bi-polar reference sequences r(tN) and e(tN). Cne input of each o~ the two multiplexers 402, 404 is connected to a first line 406 that receives the incoming sequences s(t) and a second input connected to a line 408. The line 4~8 receives the incoming sequences s(t) inverted in polarity by an inverter 410.
The multiplexers 402 and 404 are driven by tne reference sequences r(~) and e(tN) through drivers 412 and 414.
Assuming that the polarities of r(t~) and e(t~) are identical, both of ~he multiplexers 402 and 404 are connected to the line 406. The input sequence s(t) is thus applied to ~oth the 2S positive and negative input terminals of the difference circuit 308 whereby a zero signal is aFplied to integrate and dump circuit 310 (Fig. ll). If r(~) is positive and e( ~) is negative, multiplexer 402 is connected to line 406 and multiplexer 404 is connected to line 408. The sequence s(t) is thus applied to the positive input of difference circuit 308 and the inverted sequence s(t) is applied to the negative input terminal of circuit 30~; the sequence 2s(t) is ~hus applied ~o integrate and dump circuit 310.
If, on the other hand, the relative polarities of the two reference sequences are reversed, the sequence s(t) is applied to the nPgative input of difference circuit 308 and the inverted input sequen oe s(t) is applied to the positive input of difference circuit 308. The sign~l -2s(t) is thus applied to integra~e and dump circuit 310, thereby satisfying the equation VN(t) - s(tN)[r(tN) - e(~
The circuit of Figure 12 is advantag~ous over the circuit of Figure 11 because analog multiplier calibration adjustments are not required in Figure 12, altnough the inverter 410 requires t~o (balance and offset) calibration adjustments. The number of adjustments required for an eight-channel detector is thus reduced from a~proxLmately 80 to 34.
Referring to ~igure 13, a further simplification of the clrcuit shown in Figure 11 can be achieved by recognizing that the Lnput to each Lntegrate and dump circuit 310 is the dif~erence between two signals, each o~ which is the mput ~equence s(t) multiplied by a +l or a -1, with the output being zero when the two refer~nce sequences are equal to each other. In accordance with Figure 13, the 2N multipliers and the N subtractors are replaced, in circuit 500, by N three-input analog multiplexers 502. One input of each of the multiplexers 502 is connected to a line 504 which receives the input sequ~nce s(t). A second input of multiplexer 502 is connected to a line 506 which receives an inversion s(t) of the input sequence, inverted by 508. The third input of multiplexer 502 is connected to a line 510 that in turn is connected to ground.
The first reference sequence r(tn) is connected directly to the control input of multiplexer 502 through an inverter/driver 5120 Also connected to the control input of multiplexer sn2 is an exclu~ ve-CR circuit 514 having inputs connected respectively to the two reference sequences r(tn) and e(tn).
When the two reference sequences are equal to each other, the output of the exclusive-OR circuit 514 drives the multipLexer to line S10, causing the output of mul~iplexer 502 to generate a zero signal to integrate/dump circuit 310 (Fig. 11)~ If the first 5~

reference r(tn) equals 1, the output v(t) of multlplexer 502 equals s(t). If r(t) equals 0, on the other hand, the multiplexer output v(t) equals -s(t). The output of the difference circuit thus generates the signal s(tn)[r(tn) - e(tn)] and the S Lntegr~te and du~p output for each channel is S s(t)[r(tn) - e(tn)]dt, as required. (6) Two circuits for implementing the three-input analog multiplexer 502 of Figure 13 re shown respectively in Figures 14a and 14b. In Figure 14a, each of the two two-input multiplexers 600, 602 have the following characteristics:
X 3 Xo~ when A - 0;
x - xl~ when A = 1.
lS The first reference sequence r(t) is connected to control terminaL
A of multiplexer 600 and to one input of an exclusive-OR cixcuit 604. The second reference sequence e(t) is connected to a second input of exclusive-CR circuit 604. The output of the exclusive-OR
604 is connected to the control terminal A of multiplexer 602.
m e incoming sequences s(t) are connected to one input terminal xl of multiplexer 600, and, through an inverter 606, to the second input x0 of the same multiplexer. The output x of multiplexer 600 is applied to one input xl of multipLexer 602;
the second input x0 of multiplexer 602 is connected to ground.
The output v(t) of the multiplexec shown in Figuce 14a is defined by the following truth table, which corresponds to the required equation v(t) = s(t)[r(tn) - e(tn)].
T~BLE III
r(t) e(t) r ~3 e v(t) o 0 0 0 0 1 1 -s(t) 1 0 1 s(t) ~ ~?t 8 In the ~mbodiment of the three-input multiplexer 606 shown in Figure 14b, the output x is connected selectively to any one of the four inputs xO, xl, x2, x3, depending upon t~e binary values of control inputs A, B. m e input sequences s(t) are s connected directly to input x2 and through an inverter 60a to input xl. Inpu~s xO and X3 are connected to ground. The two reference sequences e(t) and r(t) are connected respectively to control inputs A and B of multiplexer 606.
The operation of mNltiplexer 606 is described by the truth table set forth a~ove with respect to Figure 14a and also provides the desired output v(t).
The correlation d~tector embodiments of Figures Ll-14 are based upon the analog technique of integrating a continuo~s signal. The number of calibration adjustments required can be reduced further by replacing analog integration in the correlation detector by discrete signal summation. Referring to Figure 15, correlation detector 700, provided in each channel of the receiver, digitizes the incoming sequences s(t) and algebraically sums the digitized signal in an accumulator over a period of time equal to a bit period. ~he difference between the initial and final values in the accumulator represents the value of s(t) integrated over a bit period. Accumulation is controlled by the values of the reference sequ~nces r(t) and e(t). When the two reference sequences are equal, the accumulated value is unchanged. When r(t) and e(t) are unequal, the accumulation is increment~d or decremented by the value of s(t) depending upon tne value of r(t).
Correlation detector 700 comprises an analog-to-digital converter 702 that receives the analog sequence s(t) and in response generates a corresponding digital signal at output terminal D. The output of analog-to-digital converter 702 is applied to one input A of an adder/subtracter circuit 704 having an ou~put applied to the input of an accumulator registsr 706.
The output of the accu~ulator 706 is applied to out~ut register 708 and also to the second input 8 of adder/subtracter 704.

~ 31 -Operation of the units 702-708 as well as of a seqyencer 710 are synchronized to a bit period T. SequenceI: 710 in turn controls the conversion tLmes of AJ3 convertes 702 and the accumulation times o accumulator register 706 at outputs 712 and 71~, respectively. The accumulator register 706 is also controlled by the values of the two refrence sequences r(t) and e(t) through exclusive-CR gate 716 and AND gate 718.
The adder/subtracter 704 develops an output signal which is the sum of the digitized input sequenca s(t) and the contents of accumulator register 706 when reference sequence r(t) is 1 and generates the difference between the accumulator register contents and the digitized value of input sequence s(t) when reference sequence r(t) is zero. Selective addition and subtraction of the t~o signals applied at adder/subtracter inputs A, B are controlled by the signal applied at input F, developed by re~erence sequence r(t) through an inverter 720.
If r(t) equals e(t), the exclusive-OR gate 716 develops a logic 0 signal that is applied to one input of ~ND gate 718. To the output input of ~ND gate 718 is a write-accumulation signal developed by se~uencer 710. Sequencer 710 alternately develops a "convert input" signal applied to ~D converter 702 to provide an analog-to-digital conversion of input sequence s(t) and a "write accumulator~ signal which adds or subtracts the instantaneous value of s(t) to the current accumulated value, to be applied to output register 708 and then to microprocessor 314 (Figure 11) which develops binary output and timing error signals.
Thus, the content of the accumulator register 706 remains unchanged when r(t) equals e(t) under control of 2n exclusive-OR
gate 716. When r(t) equals a logic 1, the content of accumulator register 706 is incremented by the value of the inconing sequence s(t); ~hen r(t) equals a logic 0, on the other hand, the content of the accumulator register is decr~mented by the value of the input sequence s(t). This has the effect of multiplying s(t) by +l or -1 and integrating.

- 3~ -m e correlation detector 700 of Figure li is generalized into an N-channel correlation detector 800 in Figure 16~ The reference sequences r(tn~ and e(tn) are applied to an input latch 802 having r(tn) and e(tn) outputs that are applied respectively to a pair of N to 1 multiplexers 804~ 806. The outputs of the two multiplexers aO4, 806 in turn are applied to the inputs of e~clusive-CR gate 808 that controls accumulator memory 810 through ~ND gate 812.
Accumulator mQmory 810 in Figure 16 correspcnds to accumulator register 706 in Figure 15. Memory 810, however, contains a plurality of memory regions corresponding to each channel and addressed by a channel sequencer 814 controlled by the output of sequencer 816. Similarly, the output of accumulator memory 810 i9 applied to an output memory 818 that corresponds to output register 708 in Figure 15. Memory 818, however, contains a plurality of memory regions corresponding to the correlation channels and addressed by the output of sequencer 816.
The incoming sequence s(t) is sampled by a sa~ple and hold circuit 820 and applied to analog-to-digital converter a22 wherein the incoming analog sequence s(t) is digitized and applied to adder/subtracter 824 in a manner described witn respect to Figure 15.
In operation, sample and hol~ circuit 820 samples the incoming analcg sequence s(t) and converts the samples to corresponding digital value~ in synchronism wi~h the bit period T
developed by microprocessor 314 (Figure 11) and applied to sequencer 816. The content of the accumulator memory 810, within each memory region addressed by sequencer 816 is incremented or decremented by the current value of s(t~, depending upon the value of the reference sequence r(t) at the corresponding channel. The circuit 800 thus successively samples the input sequence, multiplies the sequence by +l or -1 and integrates for each channel N, under control of channel sequencer 3la and sequencer 81~, as well as of the microprocessor 314. The accumulator memory al0 and output memory 818 thus monitor N accumulation channels, with time synchronism of signals during channel sequencing being preserved by the sample and hold circuit 820 and the input latch 802.
Referring now to Figure 17~ another digital implementation of a single channel correlation detector 900 comprises a conventional voltage-to-frequency converter 902 that receives the absolute value of input sequence s(t) through an absolute value circuit 904. Absolute value circuit 904 is required because the voltage-to-frequency converter 902 responds, as is conven~ional, to a unipolar input signal. Voltage-to-frequency converter 902 converts the instantaneous magnitude of the inconing sequence s(t) to a single corresponding frequency signal to be applied to an up/down counter 906 through one input of an AND gate 908.
The input sequence s(t) i9 also applied to an analog ccmparator 908 which keeps track of the polarity of the input sequence s(t). In other words, the output of the analog comparator 908 is representative of the sign of the input sequence s(t). The reference sequences r(t) and e(t) are applied ~o the remaining input of gate 908 through exclusive-CR gate 910.
The up/down counter 906 is controlled by a second exclusive-OR gate 912 that receives the output of the analog comparator 90~ and the first reference sequence r(t). Thus, the up/down counter is controlled to increment when the signs of the input sequence s(t) and reference sequence r(t) are the same;
otherwise the counter is caused to decrement. The output of counter 906 is applied to a latch 914 synchronized to bit period T.
The cloc~ CLK of up/down counter 906 is disabled by exclusive OR gate 910 wh~n the two reference sequences r(t) and e(t) are equal to each other. Otherwisef the counter clock is enabled and the counter 906 tracks the incoming sequence s(t)O In other words, when r(t) is 1, the counter counts ~ for a positive polarity sequence bit s(t) and counts down for a negative polarity sequence bit s(t). ~hen the refer~n oe sequence r(t) is a logic L~ 7~.

zero, on the other hand, accumulation is subtracted and tne count direction is reversed.
The circuit 900 of Figure 17 is generalizc~d to ~ channels of correlation detection by circuit 1000 in Figure 18. In circuit 1000/ voltage-to-frequency converter 1002, absolute value circuit 1004 and analog camparator 1006 correspond to corres~onding compcnents in Fi~ure 17 and are ccmmon to all channels. Up/down counter 1008 as well as ~ND gate 1010 and exclusive-OR gates 1012 and 1014, hcwever, are duplicated for each channel. The output of each binary up/down counter 1008 i5 applied to a latch 1016, commonly synchronized to a bit period T. The outputs o~ tne N
latches are applied to microprocessor 314 (such as shown in Fig.
11) which processes the individual channel correlation signals and in response develops binary data recovered frcm the predetermined transmitter and timing s~gnals to shi~ receiver timing into synchronism with the predetermined transmitter.

Dynamic Synchronization As discussed above, static synchroni2ation involves establishing predetermined delays in ~he receiver that correspond to different propagation times associated witn different transmitters. Static delays, preset in the receiver during initial set-up, synchronize the transmitter and receiver to within one code chip of each other. Perfect correlation is then es~ablished by microprocessor 314 in response to the correlation signals developed by the correlation detectors described above.
~icro~rocessor 314 more specifically processes the channel correlation signals to control receiver t~ming to synchronize to the predetermined transmitter in two stages; namely, fine and coarse tuning, followed oy synchronization correction, if necessary, to the proper pulses of the system clock.
Referri~g again to Figure 10, it is recalled that code correlation is a function of code chip time delay differences between a received code and a reference code and, depending upon 7~

the particular correlation properties of the ccae employed, has a peak when synchronization is achieved and has an absolute ~alue that drops to zero as the synchronization differenoe approaches a code chip or greater. Data are r~c~vered from the correlation pattern, based upon the rec~gnition that the sign of the pattern depends upon the data bit used to modulate the transmitter. Thus, wnen the receiver and a predetermined t~ansmitter are properly synchronized to each other, transmitted data are recovered by nitoring the sign of the voltage Vl at ~he prim2ry correlation channel.

Fine Tuning Referring to Figure 19, a correlation pattern corresponding to the correlation pattern shown in Figure 10 is identiEied by 1100. This is an "in-phase" correlation pattern, with coarse correction channels Vl, V2, V3, V6 and V7 that are used to determine which of the correlation peaks corresponds to the primary channel, with maximum correlation at synchronizatlon. An additional pair of channels V4, V5 are fine, or vernier, correction channels, which maintain receiver synchronization by maximizing the correlation output of the primary channel Vl. In the oregoing discussion, it should be recognized that all references to fraction of a code chip are related to the ratio between the carrier requency and code generation frequencies. As one example, the carrier fr~quency is 5O70 Hz, and the code generation frequency is at 3870 bits/second, so that references to fractions of a code chip are related by a ratio of 3/2, allowing three peaks per code chip. The additional correlation curve 1200 in Figure lg i5 a quadrature-phase correlation curve that is displac~d from the in-phase correlation curve by 90 degrees. The significance of the quadrature-phase correlation curve is that the value of the quadrature-phase curve is at zero when the value of the in-phase quadrature curve is at a maximum. As shall be discussed below, signal processing, and particularly correlation peak detection, is simplified using quadrature-phase correlation.

~ 7 ~.

Because there are three correlation peaks per code chip, assuming that the primary correlation channel Vl is within a code chip of being properly synchronized, the prin~ry channel Vl is within one-six~h of a code chip of a "local" I~ak. ~ine tuning causes the receiver to adjust its timing, under control of mlcroprocessor 314, such that the correlation channels Vl, V2, V3, V6 and V7, spaced apart frGm each other by one-third of a code chip, are all located at local peaks. one method of adjus~ing receiver timing to locate the five correlation channels to 1 al peaks i5 b~ serial hunting shcwn in the flow chart given in Figure 20(a) 7 This involves use of a preamble of a length 2(p- s)~ where s is the number of smoothings on each blt and p is equal to one-sixth (in this example) of a code chip period divided by th~
receiver correlation resolution, or the number o~ correlationq o minimum resolution required to adjust the receiver from a synchronization null to a peak.
For each data bit in the preamble, the receiver primary correlation channel Vl timing is adjusted by a minLmum fraction 1/6(p) of a code chip (step 1320) and the ma~nitude of the correlation voltage Vl is stored (1330). This process is repeated until the receiver has changed its timing over a maximum o a full one-third of a code chip (1340). ~hereafter, the point at wnich the magnltude of the primary correlation Vl is at a m3ximum is select~d as being the local peak (1350), and the timing of the receiver is adju~ted to position channel Vl at that point (1360).
An alternative fine tuning method controlled by microprocessor 314 is the use of fine tuning channels V4 and V5 shown in Figure 19. m e fine tuning channels V4 and V5, provided by an additional pair of correlation detectors (not shown3, are offset in time fram the primary correlation channel Vl by an equal fraction of a cade chip that is less than one-sixth of a code chipo Optionally, a preamble may ~e included in the method, having a worst case length of p s with a minimum receiver correction (resolution) being l/6(p) of a code chip. Referring to i7~

Figure 20(b), the correlation voltages V4 and V~ are applied to microprocessor 314 (step 1950) along with the correlation voltage of the prima~y channel Vl. By cc~paring the relative magnitudes of V4 and ~5 (steps 1960, 1970), the microprocessor determines the direction toward which receiver tIming is to ~e shifted (ste~s 1980~ 1990) to position ~he primary channel Vl at the major local correlation peak. A system of this type is shown schematically in Figure 21. Progr~,~ing o~ microprocessor 314 is omitted for brevit~, but is considered routine to implement bas~d upon the simplified flcw chart of Figure 20(b) and the discussion here m.
Another alternative fine tuning method involves the use of a channel whose timing i9 generated with a quadrature-phase carrier. Recognizing ~rom Figure 19 that the nulls of the q~ladrature-phase correlation patte~n 1200 occur at the peaks o~
in-phase correlation pattern 1100, an error voltage may be developed by microprocessor 314 based upon the sign of the product of the in-phase and quadrature-phase patterns. The sign of the error voltage thus indicates a direction to which receiver tLming must be shift~d to cause the receiver correlation channels to synchronize to local correlation peaks. It i also possible to apply the magnitudes of the in-phase and quadrature-phase correlation voltages 1100 and 1200 to determine not only the direction of shift of receiver timing to ~chieve synchronization but also the amount o~ shift required to obtain a local peak.
Thus, in accordance with another aspect of the invention and as summarized in the flow chart of Figure 22(a), the in-phase Vl and quadrature-phase Vlq cor~elation voltages are measured (step 2050). The ratio of the in-phase Vl and quadrature-phase Vlq correlation voltages is calculated (2060), and if the ratio is positive (2080), the two correlations are presumed to have the sa~e polarity and receiver timing delay is increased (2095);
otherwise, the two correlations are presumed to have opposite polarities and receiver timing delay is decreased (2090). To prevent ceceiver tLming from being changed if the receiver is '7~

~ 38 -perfectly synchronized to the predete~nined transmitter, and to avoid complications caused by delay in the receiver whereby a correction decision is made using information that is more than one data bit old, the absolute value of the ratio Vl/Vlq, which is S essentially a cotangent function, is ~onitored. A table stored in a memory associated with microprocessor 312 relates ~he ratio Vl~Vlq to the numker of fine tuni~g corrections, e.y., 1/48th of a ccde chip for each correction, to reach optimal synchronization.
The table is set forth below.
~.
~umber of Corrections (Equal fractions of a Vl~Vlq Code Chip) 1 S.02 2 2.~1 3 1.49 4 1.00 0.668 6 0~414g 7 0.1999

8 0 Thus, the number of corrections applied to receiver timing is determined directly fron Vl~Vlq, and there is a correction dead band when the ratio is greater than 5.02, eLiminating recelver hunting about optLmum synchronization. Furthermore, the n~m~er of data bits needed to move the receiver from a correction null to a correlation peak is reduced from 8 (in this example) to as low as 1, minimizing the length of any required preamble and providing accelerated serial hunting. Finally, it is possi~le to inhibit tracking corrections on consecutive data bits without decreasing the tracking ra~e of the receiver, thereby eliminating overshoot.

Signal Presence Detection The provision of quadrature-phase Vlq as well as in-phase Vl correlation voltages furthermore makes it possible to determine a signal present with m a background of noise. As summarized in the progra~ flow chart of Figure 22(b), when only noise is present at the receiver input, ~oth the in-phase Yl and quadrature-phase Vlq voltages will have approximately the same value K, such that the ratio Vl/Vl~ will ~e close to unity. With both signal and noise present, however, fine tuning maxinizes Vl and minLmizes Vl~ to cbtain a ratio much greater than unity. The ratio Vl/Vlq is ~hus used as an indication of signal present. In practice, the ratio may be monitored over a number of data bits, with smoothing techniques or majority voting being a~plied to ensure accuracy.
Circuitry fo~ detecting presence of a signal in a background of noise is qhown in Figure 21, wlth microprocesso~ 314 developing signals Vl and Vlq in response to th~ outputs of the cor~elation detectors discussed above. The signals Vl, Vlq are processed with the microprccessor 314 to develop the ratio Vl~Vlq and the absolute 0 value Vl~Vlq of the resultant is magnitude compared witn a predetermined threshold magnitude to det~rmine ~hether an inccming signal represents a data transmission or whether it is merely noise.
Following determunation that the receiver is tuned to a local peak using fine tuning as described above, it becomes necessary to determune through coarse tuning, ~hether the current local peak is the ~correctU local peak such that the receiver has best correlation.

Coarse Tuning In accordance with one embodiment, coarse tuning of the receiver to a predetermined transmitter to ensure that the receiver is tuned to the maximum, and other than a secondary, correlation peak involves serial hunting wherein, having once fixe~ a point as a local peak, the receiver is adjusted in - 4~

multiples of one third of a code chip to measure the magnitude of the receive signal at each adjacent local peak. Once the magnitudes of the peaks are determ m ed, a decision as to the proper peak is made. Because the magnitudes of adjacent peaks near the center of the correlation pattern are difficult to distinguish from one another due to channel filter distortion, a conventional "center-of-mass" approach may ~e used to identify the maximum local peak by basing the decision on the relative values of all channels rather than on only a selection of the channeL
having the greatest correlation magnitude.
m e microprocessor 314 is programmed in a coarse tuning, serial hunt mode to cause the receiver, following identification of a local peak, to shift in timing by multiples of one-third of a code chip, measure and store correlation magnitudes and make ccmparisons using the ce~ter of mass approach or other approach to identify the correct correlation peak. Serial hunting reyuires a transmission preamble of length W- s where W is the width of the peak search range (in thirds of a code chip) and s is the number of bits of smoothing in the voltage readings.
In Figure 23, a simplified flow chart of programming of microprocessor 314 to provide coarse tuning by serial hunting includes a test at step 1200 to determine, using fine tuning as discussed above, whether the receiver is at a local peak. If the receiver is not at a local peak, the receiver is fine tuned until the receiver is determlned to be at a local peak. The receiver, once at a local peak, is incremented (step 1202) until its timing is at ~ + M, wherein K is the timing of the local peak obtained during fine tuning and N is a predetermined num~er of thirds of a code chip. me correlation value of K + N is measured and stored (step 1204), and the receiver timing is decremented by one-t~ird of a code chip (step 1206). The correlation of the receiver and predetermined transmitter is now measured and stored (step 1208), and receiver tim mg is tested to determine whether it is a~
(K - N), that is, at the opposite side of the initially detected ~ 7 ~3 - 41 ~

local peak ~ (step 1210). If not, the receiver timing is again decremented and ~he correlation is measured ~ld stored.
Othe~wise, all the stored correlations are tested (step 1212) to identify a peak correlation.
In accordance with another emkodiment, to reduce the preamble leng~h, multiple secondary receiver channel~, offset frcm each other by multlples of one-third of a code chi~ on both sides o the primary channel Vl develop primary and secondary correlation signals to ~e applied to microprocessor 314. The microprocessor 314 is programmed, using center of mass analysis or other analysis, to identify the primary channel Vl which has the greatest maximum correlation and the secondary channels. 8y using a multiple num~er of receiver channels or correlation detectors, rather than serial hunting circuitry or programming, the length o the preambLe r~quired Eor coarse corrections may be reduced to the n~mber o bits of smoothing, s. This assumes of course that or the desired width of search, a channel exists with common offsets of multiples of one-third of a code chip on bo~h sides of the primary correlation channel Vl.
With multiple receivers it is not necessary to program the microprocessor to serially hunt. The microprocessor 314 is instead programmed to simply compare the outputs of the correlation detectors, all tuned to a local ~eak, to identify the peak having the greatest magnitude.
Timing Signal Correction If the data bit rate of the transmission is less than one-half the pulse repetition rate of the timing source, the transmi~ter and receiver may become locked to different timing pulses even though they appear to be perf~ctly synchroni7ed to each other~ For examFle, for a data bit rate of 30 bits per second, a timing pulse source of 60 Hz and a carrier frequency located ~etween 60 Hz harmonics, the transmitter may become locked to a first 60 ~z timing pulse with the receiver locked to the next 7~3~

successive 60 HZ timing pulse. An alternating data trans~ission will not be detected due to improFer receiver data timing recovery with otherwise perfect synchronization betweeQ the receiver and transmitter.
To illustrate this condition more clearly, Figure 24(a) is a diagr~m representing the timing pulses to which ~he receiver and a predetermined transmitter are synchronized. The transmitter carrier is shown in Figure 24(b) and transmitted data representing al~ernate ones and zeros are shown in Figure 24(b). Assuming that the receiver and transmitter are synchronized to the same tLming pulses, the integrate and dump circuits 310 of the receiver will be synchroni~ed to the transmitted data inversions so as to dump at the trailing edge of each datum, as shown in Figure 24(d), where "dots" designate integration dump points. The sampled integrator output is thu~ a replica of the data embedded within the transmission.
If the transmitter and receiver are not synchronized to the same timing pulses, however, the integrate and dump circuits 310 will not ~e properly synchronized to the data being transmitted.
This condition is shown is Figure 24(c), where the integration dump points cccur ~etween transmission data in~ersions, and the samæled out2ut of the integrator 310 is at zero.
In other words, with the receiver and transmitter respectively synchrontæed to successive, rather than the same, timing pulses, it is impossible to recover any of the transmission data. It is thereore necessary to test the receiver and transmitter to ensure that the two units are svnchronized to the same, rather than successive, timing pulses.
In accordance with one aspect of the invention, associated with the primary receiver channel Vl is a secondary receiver channel Vl' having a bullt-in additional delay of one~half a data bit. One of the two channels Vl and Vl' will always therefore detect the transmitted signal. A determination is made by applying an alternating data prea~ble associated with the transmission to the primary and secondary receiver channeLs. 9y ccmparing ~he magnitudes o the correlation OUtpUtâ of the two receiver channels, the correct channel (having the larger correlation magnitude) is the one synchronized to the same timing pulse as the transmitter is. Data are monitsr~d at the "correct"
channel only.
~ simplified circuit for synchronizing receiver timing to cause the receiver and transmitter to be locked to the same tLming pulses as shown in Figure 25. Microprocessor 314 develops a secondary channel Vl' offset from channel Vl by one-half of a data bit. In response to an incoming sequence having an alternating preamble, the microprocessor conpares the magnitudes of the data outputs frcm the channel Vl and its half bit delayed channel Vl', and identifies the one channel having the larger magnitud~. ~liS
channel is thus presumed to be ~he one which is locked to the same timing pulses as the transmitter is, and is reapplied to the microprocessor for data recovery.
In an alternative embodiment of the invention, the need for the secondary receiver channel Vl' may be elimin~ted. The transmitter and receiver can be synchronized ~hen the tlming reference frequency is less than or e~ual to the data sampling rate and the ratio of the data sampling rate to the timing reference frequency is an integer by combining more than one of the consecutive data sa~ples together to yield one data point or bit. By conbining these data samples, an optimum data sample po m~ may be determined while receiving an alternating sign preamble by comparing the magnitudes of all possible summations and selecting the sample which give a maximum output. If each sample is assigned to its o~n synchronization point, then synchronization may be accomplished by locking to the time that gives the maximum output.
For example, if the timing signal has a frequency of 60 ~ertz ~nd a data sampling rate of 30 samples per second, for a data rate of 30 bits ~er second each data sample is used to yield one data point or bit. For data rates of 15, 7.5 or 3175 bits Fer second two, four and eight consecutive data samples are used to yield one data bito In addition to eliminating the nee~ for a redundant data channel, the a~ove technique elimina~es the need for the data sampling rate to ~e the same as the data rate. In fact, sampling may occur at a rate higher than the data rate. This allows the data samples to ~e combined digitally, for example in a microprocessor, and allows the data rate to be independent of the actual hardware timing.
~ata Recovery Data recovery in spread spectrum systems is well known. As background, reference is made to section 5.3 of the Dixon text mentioned eaclier, and particularly to the discussion of Costas loop demoduLators beginning on page 155.
~ecause the spread spectrum system as provided herein mcludes multiple correlation channels, data recovery is improved in accordance with one aspect of the invention by extracting data at each channel rather than at only a single correlation channel.
It i5 thereby possible to lower system message erroc rate and possibly to also reduce the length of or eliminate any required preambles for receiver syr.chronization.
With reference again to Figure 19, it is noted that the correlation pattern 1000 is centered about the pr~ary correlation channel Vl. The sign of the primary correlation channel Vl is deFendent upon the sign of the data being transmitted~ A positive value of Vl thus corresponds to a logic 1 be mg transmitted whereas a negative value of the correlation Vl corresponds to a logic 0 being transmitted.
The correlations at V2, V3, V6 and V7 also have vaiues that correspond to the sign of the data being transmitted.
Specifically, the relationship of the voltage outputs at channels Vl~ V2, V3, V6 and V7, in the absence of noise and dlstortion, are descri~ed as follows:

7~9~

V2 = V3 = R1 Vl V6 = V7 = R2 Vl where (7) Rl = 2/3 R2 = l/3 In accordan~e with the invention, the data sign at the output of each correlation deteçtor, following proper receiver synchronization, is monitored. Depending upon the characteristics of noise a~d distortion, data may be extracted usiny only the outputs at channels V1, V2 and V3, with an effective sisnAt-to~noise ratio gain of (l~l/L) ( ~ uj Kj)2 (8) .

(l+l/L) ~ uj 2 ~ 2-(Rl+l/L) ul~(u2+u3) + 2 (R2~l~L) u2 u3 j-l where ~ = relative noise free amplitude or Vj with respect to V1~ j = 2, 3 (R; - Rl in the distortion free case), L - the length o the pseudo-random code and Uj = weighting factor for Vj, j = l, 2, 3. The weighting factors are selected according to the particular distortion present.
Figure 26 is a si~plified circuit diagram showing microprocessor 314 responsive to channels Vl, V2 and V3 and prQgrammed to combine all three correlation channel outputs to extract transmission data, with weightin~ factors selected according to particular distortion known to be present on the transmission medium. Table ~ illustrates the signal-to-noise enhancements under a ew possible distortion and weighting fac~or scenarios~

i7~:3~

~BIE V

S/N
WEIG~TqNG FACICRS FCR Vj DISTCRTIoN FACTORS FCR Vj ~PRDVE~ENT
ul u~ u3 kl k2 k3 F~CTOR
_ _ _ . ~ _ _ . __ 1 -l -1 1 -1 -l 1.44 __ _ . . . . _. _. . . _ 1 -1 -l l -0.9 -0.9 1.254 ,, _ , ,. _ _ . . _. __ 1 ~1 -l 1 -0.8 -0.8 1.082 . _ _ _ ~ - ~ . ~
1 -1 -1 l -0.7 -0.7 0~922 ~ _ 3 _ 1 -0.34 ~0.34 l -0.67 -0.67 0.971 . _ _ _ _ _, ~ __ l -0.67 -0.67 l-0.67 -0.67 0.918 _ _ _ _ _ , ._ _ 1 -0.9 -0.6 l ~0.9 -0.6 1.055 __ __ _. __ .
l -0.8 -0.~ l -0.8 -~.8 l.09 ___ _ _ _ _ _ _ _ 1 -0.9 -0.9 l -0.9 -0.9 1.252 _ _ An additional advantage of providing a recovery on all channels of the receiver is that random and burst errors, which tend to aff~ct all channels, can be identified and ignored. This is similar to signal presence detection using in-phase and quadrature-phase correlation outputs, as discussed above, but employs all channels rather than orthogonal outputs associa~ed with a single channel.
Furthermore, as an additional advantage of obtaining data recovery at all correlation channels or at least several correlation channels, it is possible to monitor synchronization during message receptlon. Although synchroni~ation adjustments are not feasible during message reception, the message content ~ay be recovered, without repeats, using the additional re~eiver channels.
In this disclosure, there is shown and described only the preferred e~b~diments of the invention; hcw~ver, it is to be i7~

understood that the inve~tion is capable of use in various other combinations and environments and i~ capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims (2)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. In a data receiver adapted to receive a data signal from one of a plurality of transmitters, each transmitting a data signal spread by a common pseudo-random code which is a different assigned shift of a common pseudo random code sequence and timing signals from a timing source, the receiver including means for establishing initial synchronization between the receiver and a predetermined one of the transmitters transmitting a data signal spread by the pseudo-random code having said predetermined assigned code sequence and means for sampling said data signal at an integral multiple of the frequency of the timing signal source to obtain data samples, and wherein there is a tendency of the receiver and predetermined transmitter to become locked to different signals of said timing signal source and thereby have a reduced data recovery characteristic, a method of locking a receiver and the predetermined transmitter to common timing signals following initial synchronization of said receiver and predetermined transmitter by said synchronization means, comprising the steps of:
a) combining one or more at least two consecutive data samples to generate data sample points corresponding to particular timing points of said timing signal source;
b) detecting which one of said data sample points has a maximum value: and c) locking the receiver to the timing point of the timing signal source corresponding to said detected maximum value data sample point.

2. In a direct sequence spread spectrum code division multiplex system comprising a timing signal source, a plurality of transmitters synchronized to the timing signal source and each transmitting a data signal spread by common pseudo-random code which is a different assigned shift of a common pseudo-random code sequence, and a receiver normally synchronized to the timing signal source for receiver said transmitted pseudo-random code from a predetermined one of said transmitters having a predetermined assigned code sequence shift, said re-ceiver including means for establishing initial synchronization between the receiver and a predetermined one of the transmitters transmitting a data signal spread by the pseudo-random code having said predetermined assigned code sequence and means for sampling said data signal at an integral multiple of the frequency of the timing signal source to obtain data samples, and wherein there is a tendency of the receiver and predetermined transmitter to become locked to different signals of said timing signal source and thereby have a reduced data recovery characteristic, a method of locking said receiver and predetermined transmitter to common signals of said timing source, following initial synchronization of said receiver and predetermined transmitter by said synchronization means, comprising the steps of:
a) combining at least two consecutive data samples together to generate data sample points correspond-ing to particular timing points of said timing signal source;

b) detecting which one of said data sample points has a maximum value; and c) locking the receiver to the timing point of the timing signal source corresponding to said detected maximum value data sample point.