CA1244161A - Write-protect apparatus for bit mapped memory - Google Patents
Write-protect apparatus for bit mapped memoryInfo
- Publication number
- CA1244161A CA1244161A CA000486297A CA486297A CA1244161A CA 1244161 A CA1244161 A CA 1244161A CA 000486297 A CA000486297 A CA 000486297A CA 486297 A CA486297 A CA 486297A CA 1244161 A CA1244161 A CA 1244161A
- Authority
- CA
- Canada
- Prior art keywords
- coordinate
- signals
- representative
- value
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 title claims abstract description 20
- 238000013479 data entry Methods 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/02—Storage circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
Abstract
ABSTRACT OF THE DISCLOSURE
A pattern write protect system approximates a memory area for data entry with a multiplicity of rectangles and determines when a point for entry is within the window by establishing a relative position of the address point coordinates to the coordinates of the sides of the rectangles. A less than/greater than signal for each address coordinate relative to the sides of each rectangle is derived. These signals are summed and the resulting sum signals are then multiplied to provide an enable gate signal.
A pattern write protect system approximates a memory area for data entry with a multiplicity of rectangles and determines when a point for entry is within the window by establishing a relative position of the address point coordinates to the coordinates of the sides of the rectangles. A less than/greater than signal for each address coordinate relative to the sides of each rectangle is derived. These signals are summed and the resulting sum signals are then multiplied to provide an enable gate signal.
Description
61.
BACKGROUND OF THE INVENTION
1 1. Field of the Invention -The invention pertains generally to the field of electronic graphic systems and more particularly to write-protecting areas or patterns of a bit mapped memory used in these graphic systems.
BACKGROUND OF THE INVENTION
1 1. Field of the Invention -The invention pertains generally to the field of electronic graphic systems and more particularly to write-protecting areas or patterns of a bit mapped memory used in these graphic systems.
2. Description of the Prior Art Graphic systems typically use full field or bit mapped memories configured in an X, Y plane format to hold information for utilization in the generation of a graphic display. These memories are X and Y addressed for entering one bit of data at each addressed point. Data stored in this manner is subsequently displayed on a CRT as an X, Y plane graphic.
A vector generator, directed by a central positioning unit (CPU) software, creates a display for entry into the bit map memory. In a real time graphic system speed or execution time is an important factor. mis speed may be achieved by using a set of routines each configured to draw different parts of the display.
These routines are repeated for each frame of the display system with only the input data altered to reflect dynamic changes. This procedure, however, may cause segments of one routine to be drawn over an area controlled by another routine when the input coordinates are changed. In the prior art this overlapping is eliminated with software having limits set therein which, when exceeded, cause unwanted segments of a routines display to be erased. These prior art remedies, however, require additional execution time, thus adversely affecting the speed of the display system. Some prior write-protect circuits use a PROM mask. These masXs require large PROM sizes, extra chips to latch addresses and to multiplex output signals, and exhibit slow access times.
A need exists for a write-protect system capable of detecting when a write operation is inside or outside of a specified area or pattern with sufficient speed to respond within a single write operation.
SUMMARY OF THE INVENTION
1 In accordance with the present invention, pattern write protection for bit map memories is acccmplished by providing interior/exterior detection for a multiplicity of defined rectangles. The detection circuits are combined to provide an output that indicates whether a write attempt is being made inside or outside of a desired pattern. This output signal is coupled to the bit map memory enable terminal, thus penmitting data entry only when the write attempt is within the specified pattern.
Conbinational logic is used for detector circuits, requiring only three gate delays between the address input tenminals and the enable terminal of the bit memory.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a partial block diagram of a graphic display system.
Figure 2 is an illustration of a vertical situation display window.
Figure 3 is an approximation to the window of Figure 2 fonned by superposing three rectangles.
Figure 4 illustrates the window formation of Figure 3.
Figure 5 is a logic diagr~m of an interior/exterior detector for a pattern formed with N rectangles.
Figure 6 is a logic diagram for an interior/exterior detector for the pattern of Figure 4 with specified rectangular ~oundaries.
DESCRIPTIO~ OF THE PREEERRED EMBODIMENT
Refer to Figure 1 wherein a block diagram of apparatus for entering data into a bit mapped memory to establish therein a graphic display in X-Y format is presented. Data from a central processing u1lt 11 is coupled via a data bus 12 to a vector generator 13, wherefrom vector data and address codes are coupled via line 15 and buses 16,17 to bit mapped memory 14.
A vector generator, directed by a central positioning unit (CPU) software, creates a display for entry into the bit map memory. In a real time graphic system speed or execution time is an important factor. mis speed may be achieved by using a set of routines each configured to draw different parts of the display.
These routines are repeated for each frame of the display system with only the input data altered to reflect dynamic changes. This procedure, however, may cause segments of one routine to be drawn over an area controlled by another routine when the input coordinates are changed. In the prior art this overlapping is eliminated with software having limits set therein which, when exceeded, cause unwanted segments of a routines display to be erased. These prior art remedies, however, require additional execution time, thus adversely affecting the speed of the display system. Some prior write-protect circuits use a PROM mask. These masXs require large PROM sizes, extra chips to latch addresses and to multiplex output signals, and exhibit slow access times.
A need exists for a write-protect system capable of detecting when a write operation is inside or outside of a specified area or pattern with sufficient speed to respond within a single write operation.
SUMMARY OF THE INVENTION
1 In accordance with the present invention, pattern write protection for bit map memories is acccmplished by providing interior/exterior detection for a multiplicity of defined rectangles. The detection circuits are combined to provide an output that indicates whether a write attempt is being made inside or outside of a desired pattern. This output signal is coupled to the bit map memory enable terminal, thus penmitting data entry only when the write attempt is within the specified pattern.
Conbinational logic is used for detector circuits, requiring only three gate delays between the address input tenminals and the enable terminal of the bit memory.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a partial block diagram of a graphic display system.
Figure 2 is an illustration of a vertical situation display window.
Figure 3 is an approximation to the window of Figure 2 fonned by superposing three rectangles.
Figure 4 illustrates the window formation of Figure 3.
Figure 5 is a logic diagr~m of an interior/exterior detector for a pattern formed with N rectangles.
Figure 6 is a logic diagram for an interior/exterior detector for the pattern of Figure 4 with specified rectangular ~oundaries.
DESCRIPTIO~ OF THE PREEERRED EMBODIMENT
Refer to Figure 1 wherein a block diagram of apparatus for entering data into a bit mapped memory to establish therein a graphic display in X-Y format is presented. Data from a central processing u1lt 11 is coupled via a data bus 12 to a vector generator 13, wherefrom vector data and address codes are coupled via line 15 and buses 16,17 to bit mapped memory 14.
-3~ 6~
1 Vector data on line 15 is stored in the bit mapped memory 14 at points dete~mined by the X address code bus 16 and the Y
address code on bus 17, each X, Y address having one bit of vector data stored therein. Vector generator 13 additionally provides an enable signal coupled to an OR gate 21 via line 22 and a position signal to a pattern write protect circuit 23 via line 24. me pattern write protect circuitry 23 couples a low level signal to OR
gate 21 via line 25 when the vector data on line 15 is for entry within a penmissible region of the X-Y display and a high level signal to the OR gate 21 otherwise. When a low level signal is coupled from OR gate 21 to the enable terminal of bit mapped memory 14, the vector data on line 15 may be written therein at the addressed position.
In Figure 2 a representation of a vertical situation display is shown. This display contains a window h~ing periphery 31 within which a Roll-Pitch Indicator 32 is displayed. To prevent the deletion of data that is displayed outside the window, the Roll-Pitch Indicator 32 must be contained within the periphery 31. The periphery 31 may be approximated by superposing a multiplicity of rectangles as shown in Figures 3 and 4. In these ~igures, X
coordinates increase to the right and Y coordinates increase down as shown in Figure 3. By superposing three rectangles I, II and III, having the corner coordinates shown, the window periphery may be approximated as shown in Figure 4. The pattern write protect circuit 23 o~ Figure 1 performs to ensure that the Roll-Pitch Indicator 32 is displayed solely within the periphery of the window 31. Though Figures 3 and 4 show an approximation to the window by superposing three rectangles, it should be evident that a finer approximation to the window periphery may be obtained by using additional rectangles. The coordinates of each point on the Roll-Pitch Indicator 32, originating in the vector generator 13, are coupled to the pattern write protect circuit 23 wherein a 1 comparison with the coordinates of the rectangles approximating the window periphery 31 is made.
In Figure 5 a circuit is shown wherein each point on the Roll-Pitch Indicator 32 is compared with the boundary coordinates oE
the rectangles that are used to approximate the window periphery 31. Comparator 35 provides a low level signal when the X coordinate of the point is ~qual to or greater than the X coordinate of the line X10 while the comparator 36 provides a low level signal when the X coordinate of the point is equal to or less than the IQ coordinate of the line Xll. Similarly, the comparator 37 provides a low level signal when the Y coordinate of the point is equal to or greater than the Y coordinate of the Y10 and a low level signal when the Y coordinate of the point is equal to or less than the Y
coordinate of the line Yll. Thus, four low level signals are coupled to OR gate 39 to provide a low level output signal therefrom. If a pOillt on the Roll-Pitch Indicator 32 is not within the rectangle I at least one output signal of the comparators 35-38 will be at a high level, thereby establishing a high level signal at the output terminal of OR gate 39. Similar comparisons are made for all the rectangles approximating the window periphery to provide low level signals at OR gates having input terminals coupled to the comparators for each rectangle when a point on the Roll-Pitch Indicator 32 is within that rectangle. The output terminals of each OR gate, such as 39, 40, and 41 are coupled to the input terminals of an AND gate 42. If the point on the Roll-Pitch Indicator 32 is in anyone o~ the rectangles approximating the periphery 31, that point is within the window boundary and is eligible for display.
Since AND gate 42 provides a low level signal at the output terminal thereof when at least one input terminal has a low level signal coupled thereto, it is evident that a low level signal coupled l thereto, it is evident that a low level signal at the output terminal of AND gate 42 indicates that the point is within the window boundary. The output terminal of AND gate 42 is coupled to one input terminal of OR second input terminal of which, as previously stated, is coupled to receive enabling signals from vector generator 13. OR gate 21, therefore, provides a low level signal to enable the bit mapped memory 14 during the generation of the Roll-Pitch Indicator 32 for each point generated that is within the periphery 31 of the window, otherwise a high level signal is provided to the enable terminal of the bit mapped memory 14 and the point is not entered for subsequent display.
Refer now to Figure 6 wherein a preferred embodiment of a comparator for the three rectangles approximation to the window is shown. miS comparator forms a sum of products (SOP) of selected bits from the address of each point. Each boundary may require more than one selected bit of the boundary for proper comparison and thus may require more than one product for each coordinate. Consider the boundaries for the three rectangles of Figure 4 as shown in Table 1.
BOUNDARY DECIM~L BINARY
Y~8Y~Y~
_ Xl0 128 0 1 0 0 0 0 0 0 0 Xll 384 1 1 0 0 0 0 0 0 0 I Yl0 160 0 1 0 1 0 0 0 0 0 Yll 320 l 0 1 0 0 0 0 0 0 Y21 352 1 0 l l 0 0 0 0 0 ~31 320 l 0 1 0 0 0 0 0 0 IIIY30 96 0 0 1 l 0 0 0 0 0 1 Each boundary is represented by a nine bit binary number as shown in the Table. It should be evident that all X coordinate values, within the coordinate range of interest, that are less than the X
value of the boundary X10 show zeros for the binary digits X8 and X7. By inverting these binary digits and multiplying in AND gate 51 a high level signal will be provided whenever an X coordinate is less than the X value of the boundary X10 and a low level signal will appear at the output terminals of AND gate 51 when the X-coordinate exceeds the value of the boundary X10. It is further evident from Table I that points having X coordinates that are less than the coordinate of the X boundary Xll will have at least one zero for the Xg and X7 digits. Coupling these digit levels to an AND gate 52 therefor provides a low level signal at the output terminal of an AND gate 52 which persists until the X coordinate of the point exceeds the Xll position. At this time a high level signal exists for both the X8 and X7 digits, causing a high level signal to appear at hte output terminal of AND gate 52.
AND gates 53, 54, 55, nd 56 provide the logic for the determination that the Y coordinate of the point is greater than the value Y10 and less than the value Yll. Coupling inverted digits Y8 and Y7 to AND gate 53 provides a low level signal for all binary values greater than 001111111 and the product of the inverted digits Yg, Y6 and Y5 given by AND gate 54 provides a high level signal for all digital values between 001111111 and 010100000 and thereafter a low level signal. musl AND gates 53, 54 both provide low level signals for all values greater than Y10, while at least one provides a high level signal for values less than Y10. Logic for the upper boundary of the Y coordinates is provided by AND gates 55, 56.
Binary digits Y8 and Y7 are coupled to the input terminals of AND
gate 56. AND gate 55 provides low level signals for all digital values equal to or less than 101111111 after which a high level 1 signal will appear Eor coordinate values up to and including 111111111. AND gate 56 will provide high level signals between the binary numbers 111111111 and 101000000 inclusive and a low level signal for all binary values of interest above and below this range. Though both AND gates 55 and 56 provide low level signals for the Y coordinate of the point greater than the 111111111, high level signals are provided by ~ND gates 53 and 54 for the remainder of the binary values of interest. Ihe output terminals of AND gates 51-56 are coupled to an OR gate 57, the output terminal of which is coupled to an input terminal of an AND gate 58. When the X and Y
coordinates of a point are within the boundaries of rectangle I OR
gate 57 couples a low level signal to AND gate 58 otherwise OR gate 57 couples a high level signal to AND gate 58. Similarly, low and high level signals are respectively coupled from OR gate 61 and 62 to AND gate 58 to indicate the location of a point relative to rectangles II and III. Should at least one low level signal be coupled to AND gate 58, thereby indicating a point that is within at least one of the rectangles, AND gate 58 couples a low level signal to one terminal of OR gate 21, the other terminal of which is coupled to receive the write enable signal from the vector generator 13. Thus, OR gate 21 couples a low level signal to the bit mapped memory 14 when a write enable signal is received from the vector generator 13 and a point for entry into in the memory is within one of the rectangles representative of the display window.
1 Vector data on line 15 is stored in the bit mapped memory 14 at points dete~mined by the X address code bus 16 and the Y
address code on bus 17, each X, Y address having one bit of vector data stored therein. Vector generator 13 additionally provides an enable signal coupled to an OR gate 21 via line 22 and a position signal to a pattern write protect circuit 23 via line 24. me pattern write protect circuitry 23 couples a low level signal to OR
gate 21 via line 25 when the vector data on line 15 is for entry within a penmissible region of the X-Y display and a high level signal to the OR gate 21 otherwise. When a low level signal is coupled from OR gate 21 to the enable terminal of bit mapped memory 14, the vector data on line 15 may be written therein at the addressed position.
In Figure 2 a representation of a vertical situation display is shown. This display contains a window h~ing periphery 31 within which a Roll-Pitch Indicator 32 is displayed. To prevent the deletion of data that is displayed outside the window, the Roll-Pitch Indicator 32 must be contained within the periphery 31. The periphery 31 may be approximated by superposing a multiplicity of rectangles as shown in Figures 3 and 4. In these ~igures, X
coordinates increase to the right and Y coordinates increase down as shown in Figure 3. By superposing three rectangles I, II and III, having the corner coordinates shown, the window periphery may be approximated as shown in Figure 4. The pattern write protect circuit 23 o~ Figure 1 performs to ensure that the Roll-Pitch Indicator 32 is displayed solely within the periphery of the window 31. Though Figures 3 and 4 show an approximation to the window by superposing three rectangles, it should be evident that a finer approximation to the window periphery may be obtained by using additional rectangles. The coordinates of each point on the Roll-Pitch Indicator 32, originating in the vector generator 13, are coupled to the pattern write protect circuit 23 wherein a 1 comparison with the coordinates of the rectangles approximating the window periphery 31 is made.
In Figure 5 a circuit is shown wherein each point on the Roll-Pitch Indicator 32 is compared with the boundary coordinates oE
the rectangles that are used to approximate the window periphery 31. Comparator 35 provides a low level signal when the X coordinate of the point is ~qual to or greater than the X coordinate of the line X10 while the comparator 36 provides a low level signal when the X coordinate of the point is equal to or less than the IQ coordinate of the line Xll. Similarly, the comparator 37 provides a low level signal when the Y coordinate of the point is equal to or greater than the Y coordinate of the Y10 and a low level signal when the Y coordinate of the point is equal to or less than the Y
coordinate of the line Yll. Thus, four low level signals are coupled to OR gate 39 to provide a low level output signal therefrom. If a pOillt on the Roll-Pitch Indicator 32 is not within the rectangle I at least one output signal of the comparators 35-38 will be at a high level, thereby establishing a high level signal at the output terminal of OR gate 39. Similar comparisons are made for all the rectangles approximating the window periphery to provide low level signals at OR gates having input terminals coupled to the comparators for each rectangle when a point on the Roll-Pitch Indicator 32 is within that rectangle. The output terminals of each OR gate, such as 39, 40, and 41 are coupled to the input terminals of an AND gate 42. If the point on the Roll-Pitch Indicator 32 is in anyone o~ the rectangles approximating the periphery 31, that point is within the window boundary and is eligible for display.
Since AND gate 42 provides a low level signal at the output terminal thereof when at least one input terminal has a low level signal coupled thereto, it is evident that a low level signal coupled l thereto, it is evident that a low level signal at the output terminal of AND gate 42 indicates that the point is within the window boundary. The output terminal of AND gate 42 is coupled to one input terminal of OR second input terminal of which, as previously stated, is coupled to receive enabling signals from vector generator 13. OR gate 21, therefore, provides a low level signal to enable the bit mapped memory 14 during the generation of the Roll-Pitch Indicator 32 for each point generated that is within the periphery 31 of the window, otherwise a high level signal is provided to the enable terminal of the bit mapped memory 14 and the point is not entered for subsequent display.
Refer now to Figure 6 wherein a preferred embodiment of a comparator for the three rectangles approximation to the window is shown. miS comparator forms a sum of products (SOP) of selected bits from the address of each point. Each boundary may require more than one selected bit of the boundary for proper comparison and thus may require more than one product for each coordinate. Consider the boundaries for the three rectangles of Figure 4 as shown in Table 1.
BOUNDARY DECIM~L BINARY
Y~8Y~Y~
_ Xl0 128 0 1 0 0 0 0 0 0 0 Xll 384 1 1 0 0 0 0 0 0 0 I Yl0 160 0 1 0 1 0 0 0 0 0 Yll 320 l 0 1 0 0 0 0 0 0 Y21 352 1 0 l l 0 0 0 0 0 ~31 320 l 0 1 0 0 0 0 0 0 IIIY30 96 0 0 1 l 0 0 0 0 0 1 Each boundary is represented by a nine bit binary number as shown in the Table. It should be evident that all X coordinate values, within the coordinate range of interest, that are less than the X
value of the boundary X10 show zeros for the binary digits X8 and X7. By inverting these binary digits and multiplying in AND gate 51 a high level signal will be provided whenever an X coordinate is less than the X value of the boundary X10 and a low level signal will appear at the output terminals of AND gate 51 when the X-coordinate exceeds the value of the boundary X10. It is further evident from Table I that points having X coordinates that are less than the coordinate of the X boundary Xll will have at least one zero for the Xg and X7 digits. Coupling these digit levels to an AND gate 52 therefor provides a low level signal at the output terminal of an AND gate 52 which persists until the X coordinate of the point exceeds the Xll position. At this time a high level signal exists for both the X8 and X7 digits, causing a high level signal to appear at hte output terminal of AND gate 52.
AND gates 53, 54, 55, nd 56 provide the logic for the determination that the Y coordinate of the point is greater than the value Y10 and less than the value Yll. Coupling inverted digits Y8 and Y7 to AND gate 53 provides a low level signal for all binary values greater than 001111111 and the product of the inverted digits Yg, Y6 and Y5 given by AND gate 54 provides a high level signal for all digital values between 001111111 and 010100000 and thereafter a low level signal. musl AND gates 53, 54 both provide low level signals for all values greater than Y10, while at least one provides a high level signal for values less than Y10. Logic for the upper boundary of the Y coordinates is provided by AND gates 55, 56.
Binary digits Y8 and Y7 are coupled to the input terminals of AND
gate 56. AND gate 55 provides low level signals for all digital values equal to or less than 101111111 after which a high level 1 signal will appear Eor coordinate values up to and including 111111111. AND gate 56 will provide high level signals between the binary numbers 111111111 and 101000000 inclusive and a low level signal for all binary values of interest above and below this range. Though both AND gates 55 and 56 provide low level signals for the Y coordinate of the point greater than the 111111111, high level signals are provided by ~ND gates 53 and 54 for the remainder of the binary values of interest. Ihe output terminals of AND gates 51-56 are coupled to an OR gate 57, the output terminal of which is coupled to an input terminal of an AND gate 58. When the X and Y
coordinates of a point are within the boundaries of rectangle I OR
gate 57 couples a low level signal to AND gate 58 otherwise OR gate 57 couples a high level signal to AND gate 58. Similarly, low and high level signals are respectively coupled from OR gate 61 and 62 to AND gate 58 to indicate the location of a point relative to rectangles II and III. Should at least one low level signal be coupled to AND gate 58, thereby indicating a point that is within at least one of the rectangles, AND gate 58 couples a low level signal to one terminal of OR gate 21, the other terminal of which is coupled to receive the write enable signal from the vector generator 13. Thus, OR gate 21 couples a low level signal to the bit mapped memory 14 when a write enable signal is received from the vector generator 13 and a point for entry into in the memory is within one of the rectangles representative of the display window.
Claims (7)
1. An apparatus for enabling data entry to a memory unit, arranged in accordance with a defined coordinate system, at selected coordinate locations obtained by a boundary specified to define a data entry window within the memory unit comprising: comparator means coupled to receive address coordinate signals for providing signals representative of locations of said coordinates relative to said specified boundary; means coupled to receive said coordinate location representative signals for providing signals representative of point locations relative to said window; and means coupled to receive said point location representative signals and enabling signals for providing data entry enabling control signals to said memory unit.
2. An apparatus in accordance with claim 1 wherein said window is approximated by a multiplicity of geometrical figures each having a predetermined boundary and wherein said comparator means comprises means for providing signals representative of positions of said address coordinates relative to each of said geometrical figures, thereby providing a multiplicity of signals comprising said coordinate location representative signals.
3. An apparatus in accordance with claim 2 wherein each geometrical figure is a rectangle having a side at a first value of a first coordinate, a side at a second value of said first coordinate, a side at a first value of said second coordinate, and side at a second value of said second coordinate, said second values being greater than said first values and wherein said position representative signal means includes: means for comparing a first coordinate value of said address signal to said side first value of said first coordinate for providing signals representative of address first coordinate values less than or greater than said side first value of said first coordinate; means for comparing said first coordinate value of said address signal to said side second value of said first coordinate for providing signals representative of address first coordinate values less than or greater than said side second value of said first coordinate; means for comparing a second coordinate value of said address signal to said side first value of said second coordinate for providing signals representative of address second coordinate values less than or greater than said side first value of said second coordinate; means for comparing said second coordinate value of said address signal to said side second value of said second coordinate for providing signals representative of address second coordinate values less than or greater than said second values of said second coordinates; and means coupled to receive said signals representative of values less than or greater than said first and second coordinate values of said rectangles for providing said location representative signals to said point relative location means.
4. An apparatus in accordance with claim 3 wherein said coordinate comparison means includes means for multiplying selected binary digits of a binary signal representative of said address coordinate for providing said first and second coordinate less than or greater than signals.
5. An apparatus in accordance with claim 4 wherein said location representative signal means includes means for summing said less than or greater than signals.
6. An apparatus in accordance with claim 5 wherein said point location representative signal means includes means coupled to said position representative signal means for multiplying said position representative signals to provide said point location representative signals.
7. An apparatus in accordance with claim 6 wherein said multiplying means of said coordinate comparator means and said multiplying means of said position location representative signal means are AND gates, and said summing means are OR gates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US675,112 | 1984-11-27 | ||
| US06/675,112 US4764764A (en) | 1984-11-27 | 1984-11-27 | Write-protect apparatus for bit mapped memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1244161A true CA1244161A (en) | 1988-11-01 |
Family
ID=24709112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000486297A Expired CA1244161A (en) | 1984-11-27 | 1985-07-04 | Write-protect apparatus for bit mapped memory |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4764764A (en) |
| EP (1) | EP0183498B1 (en) |
| JP (1) | JP2591603B2 (en) |
| CA (1) | CA1244161A (en) |
| DE (1) | DE3585911D1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2215956A (en) * | 1988-03-23 | 1989-09-27 | Benchmark Technologies | Arbitrary shape clipper |
| NZ239370A (en) * | 1990-08-22 | 1994-04-27 | Merck & Co Inc | Bioerodible implantable controlled release dosage form comprising a poly(ortho ester) or a polyacetal with an active agent incorporated into the chain backbone |
| US6571155B2 (en) | 2001-07-02 | 2003-05-27 | The Boeing Company | Assembly, computer program product and method for displaying navigation performance based flight path deviation information |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3497760A (en) * | 1968-06-10 | 1970-02-24 | Sperry Rand Corp | Logical expansion circuitry for display systems |
| US3639736A (en) * | 1969-11-19 | 1972-02-01 | Ivan E Sutherland | Display windowing by clipping |
| US3889107A (en) * | 1972-10-16 | 1975-06-10 | Evans & Sutherland Computer Co | System of polygon sorting by dissection |
| US3996673A (en) * | 1975-05-29 | 1976-12-14 | Mcdonnell Douglas Corporation | Image generating means |
| US4492956A (en) * | 1980-02-29 | 1985-01-08 | Calma Company | Graphics display system and method including preclipping circuit |
| ZA836241B (en) * | 1982-09-02 | 1985-03-27 | Ici Australia Ltd | Herbicidal cyclohexane-1,3-dione derivatives |
| JPS5995669A (en) * | 1982-11-25 | 1984-06-01 | Toshiba Corp | Graphic processor |
| US4663618A (en) * | 1983-12-22 | 1987-05-05 | Rockwell International Corporation | Arbitrary raster blanking circuit |
-
1984
- 1984-11-27 US US06/675,112 patent/US4764764A/en not_active Expired - Fee Related
-
1985
- 1985-07-04 CA CA000486297A patent/CA1244161A/en not_active Expired
- 1985-09-02 JP JP60193690A patent/JP2591603B2/en not_active Expired - Lifetime
- 1985-11-25 DE DE8585308524T patent/DE3585911D1/en not_active Expired - Fee Related
- 1985-11-25 EP EP85308524A patent/EP0183498B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4764764A (en) | 1988-08-16 |
| JP2591603B2 (en) | 1997-03-19 |
| EP0183498B1 (en) | 1992-04-22 |
| EP0183498A2 (en) | 1986-06-04 |
| DE3585911D1 (en) | 1992-05-27 |
| EP0183498A3 (en) | 1989-12-13 |
| JPS61133985A (en) | 1986-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4330834A (en) | Graphics display apparatus | |
| US4736200A (en) | Graphic processing apparatus with clipping circuit | |
| KR0164265B1 (en) | An image processing circuit for processing image data fro graphics, a semiconductor integrated circuit device including such an image processing circuit, an image processing system including such a semiconductor integrated circuit device, and a method of testing such a semiconductor integrated circuit device | |
| EP0393722A3 (en) | Memory access control circuit for graphic controller | |
| GB1036024A (en) | Data processing | |
| EP0416421B1 (en) | A clipping processor | |
| CA1244161A (en) | Write-protect apparatus for bit mapped memory | |
| US5459822A (en) | Sorting processor | |
| JP2892176B2 (en) | Font memory access method | |
| EP1109133B1 (en) | CAD Data compressing method and apparatus thereof | |
| CA1152661A (en) | Symbol generator for a graphic console | |
| US3974497A (en) | Display device | |
| EP0102750B1 (en) | Character font display systems | |
| JPH0119589B2 (en) | ||
| US6598185B1 (en) | Pattern data inspection method and storage medium | |
| EP0339588B1 (en) | Coordinate input method employing touch panel | |
| KR910004262B1 (en) | Memory device having address control function | |
| US4931958A (en) | Display system with fewer display memory chips | |
| KR890001794B1 (en) | Cord double using display circuit | |
| JPH0697393B2 (en) | Bitmap processor | |
| JPS5834471Y2 (en) | Cathode ray tube color display device | |
| JPS6156555B2 (en) | ||
| JPH0133851B2 (en) | ||
| JP2879572B2 (en) | Display device | |
| JPS6258509B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |