CA1243432A - Apparatus for displaying scrolling image - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
An apparatus for scrolling the display of images obtained from a plurality of data units, each having pattern signals representing a plurality of horizontal lines and a corresponding color signal includes a video display having a plurality of horizontal display lines, a first memory for storing the pattern signals formed with first addresses corresponding to the plurality of horizontal display lines and a first buffer area for temporarily storing received pattern signals, a second memory for storing the color signal formed with second addresses ccrresponding to the numbers of the data units and a second buffer area for temporarily storing a received color signal, the pattern signals and a corresponding color signal being stored in the first and second buffer areas, respectively. A read out system operates so that the first memory, including the first buffer area, is read out by accessing the first addresses in a pre-determined order and so that the second memory, including the second buffer area, is read out by accessing the second addresses in a pre-determined order.
Also provided is a circuit for transferring the pattern signal of a horizontal line stored in the first buffer area to a corresponding address of the first memory and for transferring a corresponding color signal stored in the second buffer area to a corresponding address of the second memory, and a circuit for supplying the pattern signals and the corresponding color signal to the display tube.

Description

~Z43432 BACKGROUND OF THE INVEMTION
Field of the Invention This invent~on relates generally to image display apparatus and, in particular, to apparatus for scrolllng displayed images obtained through a sc-called character and pattern telephone access information network system I CApTAIN ) .

Deâc,i~tion of .he Background Systems have been proposed utilizlng ~tandard elephone network lines to transmit various kinds of imase information and to display such image information on the picture screen of a television receiver. One such proposed system is the so-called C~PIAIN system.
In such CAPTAIN system the format of the displaying picture screen is formed of 204 dots in the column direction and 248 dots in the row direction. In describing such screen display the following definitions are generally employed.
(1) dot: the minimum unit for forming the picture screen;

(2) line: a series of 248 dots in the lateral or horizontal direction of the display picture screen that i6 used as the minimum unit indicating the display position in the longitudinal or vertical direction;

(8) cub-row: a number of display areas each of ~lZ~343Z

which is Cormed by dividing the display picture screen at its upper end by an area includiny 248 dots in the row direction and 12 dots in the column direction and which is used as a unit indicative of the display position in the column direction;
(4) sub-column: a number of displ2y areas each of which is formed by dividing the display pisture screen a~ its upper-l-ft end by ar area including 8 dors in th~ ow dlrection and 204 dots in the col~n direction and which is used a.s a unit indicating the display position in the row direction;
(5) sub-block: a display area where the sub-column and the sub-row overlap that is used to specify the color; and (6) picture screen header: the uppermost sub-row on which is displayed a title or the like concerning the information now being displayed , that is, the monitor display.

A typical display picture screen is formed of ~7 sub-rows x 204 lines and cne sub-row is formed of 12 lines, however, in the followins description, when the lines are counted from top to bottom, they are numbered from the 1st line to the 204th line, respectively, and when the lines are counted at every sub-row, they are numbered from the 1st to 12th line of each sub-row, respectively. Further, the sub-rows are numbered as the 0th sub-row to the 16th sub-row, respectively.

~g3~32 Generally, the format of the data signals, which are transmitted from the data base center of the CAPTAIN
system to the terminal apparatus is chosen such that one section or the format is called a "packetn. Each OI these packets includes at its beginning a packet coda indica~ing the kind of the packet it belonqs .o. Generally, there is a picture screen control packet, a color information packet, and a cmall cha acter sequentlal display pac~et. Further, the plclure screen control packet includes, followirs ~he p c~e, code, a code inaicative of the display mode a.~ a csde for designating the color of the pictu~e screGn header and the like. The color lnformation packet includes a code indicating to which sub-row this packet belon~s, or the display position per sub-row unit in the column direction and a color code for specifying the color of each sub-block in the sub-row designated by this code and so on.
Additionally~ the small character sequential display pattern packet includes a code indicating to which line this packet belongs, or indicating the display position of the line unit in the longitudinal direction and a pattern data indicative of dots on the line designated by this code. These pac~ets are divided by flags each of which has a particular bit arrangement and then transmitted from the data base center of the CAPTAIN system tG the terminal app~ratus of the user.
The above-described picture screen control packet, can designate a fixed display mode and a scroll display mode, and in the scroll display mode, a difference between the display position of the displayed picture information and the display position of the newly received picture information is obtained and the picture information being ~Z~ 32 displayed is shifted upward~s ~y th.;s di~fer~.nce amount, thus, the picture in~ormation is~dI~played under the condition that the new~picture in~ormat;on is inserted into the lowermos~t portion of tne d.isplay picture screen. The picture screen h.eader i~s not d.i~splayed in the scroll display mode.
One kind of terminal apparatus for the CAPTAIN
system is controlled ~y a microcomputer, having a central processing unit for parallel processing, a read only memory in wh~ch is stored its processing program, a random access memory for work area and ~uffer area, a. video RAM having a capacity of one picture screen amount or above, a color picture tube, a read address control c~rcuit, and a deflecting circu~t. Th.e output from the deflecting circuit is supplied to the color picture tu~e in which the deflection is carried out. The syncHron;zing signal from the deflecting c~rcuit is suppl;ed to the read address control cixcuit whicn tHen produces a read address signal corresponding to tne deflection position of the picture tube, and this signal is also supplied to the video RAM.
Accordingly~ f~om tHe ~deo ~AM, t~ere ts read out address data corre~pond~ng to th.e de~lection position of the color picture tube, and this data is supplied to the color picture tube which d~.splays the data whic~ ;~s written in the video RAM, Additionally, circuitry is required for connection to the telephone lines used to transmit the data.
Consequently, the data signal from the data base center of the CAPTAIN system fed through the telephone network lines is demodulated by a modulator/demodulator, :IZL~3~132 converted from ~ ser.~l signal to a parallel sign~l ~y a serial-to-parallei converting circuit and then ~ed to the CPU. Conversely, a data ~equest signal Xrom the CPU ~.s converted from parallel to serial Dy the parallel-to-serial converting circuit, modulated ~y the modulator~demodulator and then fed through.the telephone networX. line to th~e data base center of th.e CAPTAIN system.
When the above-mentioned scrolling display is carried out, the data access for the video RAM is generally carried out such that the video RAM is formed into one section in which the pattern data is accessed and one section in which the color code is accessed.
The read-outs for the video RAM sections are carried out at every field in synchronism with the scanning of the color picture tu~e. Wherein, the read address of the first section of the video RAM is varied at every horizontal per;~od, while since the color is determined on a su~-~lock unit basis and one sub-~lock ~s formed of 12 lines, the read address of the second section of the video RAM is varied at every 12 horizontal l~nes~
~ ince the dat~ trans~ssion fro~ the data ~a~e cente,X ~f. ~e C~PTAI~ s~ys~m and-the s~cann~ng Qf tne CQ~O~
picture tube are not synchronized with each other, the writing and the reading of data into and out of the video RAM sections are not always carried out alternately, and since the data transmission rate is lower than the display speed, the data is read out several times for one writing.

~ 43~32 In short, upon scrolling display, the fir~st to 12th addresses of the first video RAM section and the 0th address of the second video RAM section are used for the picture screen header and the data are written therein once.
~owever, the last addresses or 216th and 17th addresses of the video R~M sections are connected to the 13th and first addresses thereof in an operation standpoint. Thus, the 13th to 216~h addresses or the video R~V1 ~_rst sectior. and ~he ~irs, to 17-n addresses of the video ~M secGnd sectlor.
are formed as so-callec- ring shapes, respec_ively. Ther, the data newly recei-~Ted are written in the next address-s (the address followed b~ the 216th and 17th addresses are 13th and 1st addresses) of the ring shapes. The scrolling display ~s generally carried out as mentioned above.
In this method, however, when the data of the color information packet cr the small character sequential display pattern packet is not cbtained due to noise and so on, mis-matching will occur hetween the pattern and the color which will hereinafter be scroll-displayed.
More particularly, since the color code and the pattern dat~ of the 0th sub-row of the 1st page are the picture screen header and they are not scrolled, except the color code and the pattern data as described above, the beginning of each page becomes the 1st sub-row. For example, when the addresses of the video R~M sections in which the color code of the 1st sub-row and the pattern data of the 1st line are written are considered, they are written in the 17th and 205th addresses with respect to the 1st page, while they are written in the 16th and 193rd addresses with respect to the 2nd page, and they are written in the lZ4343Z

15th and l~lst addre~ses with respect to the 3rd page. In other words, if the page ~s changed, even with. the same suB-row and the same line, the addresses ~n which the color code and the pattern data thereof are written are decremented at every page ~y 12 addresses and l address, respectively-.
Accordingly, even if the color information packet and th.e small ch.aracter sequential d~splay pattern packet contain the codes indicative of their display posit;ons, the addresses in wh~ch. the data are wri.tten are ch.anged with the pages so that i.t l,s Very d~ffi:cult to write the color code or th.e pattern data in the two sections of the video RAM ~y using the display po~t;`,on code.s.
To cope ~it~ thi~s defect, when the color code or the pattern data I$ obtai,ned, th~.s color code or the pattern data is written in the address following the address in which the previous color code or pattern data is written.
Accordingly, if the color code of the color information packet at its n-th address is not o~tained due to, ~or example, no~se, the color code of the color i.n~ormat~on pac~et at ~ts ~n ~ l~t~ address ~s written in the addre~s~ in ~ch,the color code of the color i.nformat~on p~c~et at the _-th,address should ~e written. Thus, th.ereafter, all color code$ are ~ri,tten in th.e video RAM
wi,th addres$es decremented ~y every one address (the color code of one sub~row amount is displaced up~ard ~.n th.e picture screenl.
As a result, if the color code and the pattern data are read out to thereby carry out the scroll display, all the pictures under the sub-row of which the ~24343Z

color code can not be obtained are scroll-displayed with the color beiny displaced by one sub-row amount relative to the pattern data, and this is continued until the scrolling display is ended.
On the other hand, when the pattern data of the small character ssquential display pattern packet is not obtained, due to the s~milar reascn, the succeedin~ pattern daia is incremented bv one addrcss and ihen writ.en in th video R~ hereinafier. Consequ~n~ly, all picture images below th line of which the patterr aata is r.ot oblained are scroll~displayed such that the patterns and .he colors thfr_of are mis-matched by orle line each. This is continued until the scrolling display is ended.
As described above, if the color code of the color information packet and/or the pattern data of the small character sequential display pattern packet are not obtained, in the following scrolling display the pattern and its color are all displaced with each other.

OBJECTS AND SU~MARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved image display apparatus.
It is another object of this invention to provide an image display apparatus that can prevent a displayed pattern and its assoclated color from being displaced relative to each other.

It is a further object of this invention to provide an image display apparatus for use in scrolling display.

_g_ According to an aspect of this invention, there is provided an apparatus for displaying scrolling images obtained from a plurality of data units each having pattern signals of a plurality of horizontal lines and a corresponding color signal, including a video display OI ihe kind having a plurality of horizontal display lines; a firsL memory for storing pattern signals and having first addr_cses corresponcing to the plurality~ of hori~ontal display lines, ard a buI~er area for tempGr2rily storina ~he pat'err signals being received; a second m-mory for storlns .he color sign~l and having secGnd addre~ses corresponcing to the number of data units, and a buffer area also for temporarily storing the color signal being received; a pattern signal store for storing pattern signals and a corresponding color signal in said first and second buffer areas, respectively; a controller for reading out the first memory including reading out the first buffer area by accessing first addresses in a pre-determined order and for reading out the second memory including reading out the second buffer area by accessing the second addresses in a pre-determined order; a transfer device for transferring a pattern signal of a horizontal line stored in the first buffer area to a corresponding address of the first memory , and a corresponding color signal stored in said the second buffer area to a corresponding address of the second memory and for supplying the pattern signals and corresponding color signal to the video display.
These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments ~2~3432 theleof taken in conjunction ~ith the accompanying drawings, throughout which like reference numerals designate li~.e elements and parts.

BRIEF D~SCRTPTION OF THE DRAWINGS
.~
Figs. lA and lE are diagrammatic representations oS data fGrmats ror a pic_ure screen o~ a character and pattern telephcne access informatiGn network system (C,~TA-M);
F~gs. ?~ to 2C are d~agrar~ati c represent~tions OL
~crmats for data signals used in the CAPTATN system:
Fig. 3 is a diagrammatic representation ~howing a combination of the data signals present upon scrolling display;
Fig. 4 is a block diagram of a special terminal apparatus used in the CAPTAIN system;
Fiqs. 5A to 5L are pictorial representations of data arrangements useful in explaining the accessing operation of the viaeo RAM used in the terminal apparatus of Fig. 4;
Figs. 6A t~ 6D are pictorial representations of data arrangements useful in explaining the accessing operation of the video RAM of Fig. 4;
Figs. 7A to 7Q are pictorial representations of data arrangements useful in explaining the present invention;

Figs. 8A to 8Q are pictorial representations of data arrangements relative to the video RAM of Fig. 4 useful in explaining the present invention; and ~LZ43432 Fig. 9 is a block diagram of an embodiment of a scrolling image display apparatus according to the preserlt invention.

DESCP~IPTION OF THE PR~FERRED EMBO~IMENT
Fis6. 1 to 3 illustrate data formats for the CAPTAIM svstem and, more specifically, Figs. lA and lB, respecti-~7ely, are diagrams shcwing the format o- .he displaying piclure screen. his pictur_ screen is ormed of 204 dots in Ihe colu~n direction by 24& dots in the ro-w directions, and the terrms used in describing such picture screen are as defined hereinabove.
One display picture screen is formed of 17 sub-rows x 204 lines and one sub-row is formed of 12 lines.
In the following description, when the lines are counted from top to bottom, they are numbered as the 1st line to the 2C4th line, respectively, and when the lines are counted at every sub-row, they are denoted the 1st to 12th line of each sub-row, respectively. Further, the su~-rows are numbered as the 0th sub-row to the 16th sub-row, respectiv~ly.
Figs. 2A to 2C are diagrams showing the formats of the data signals that are transmitted from the data base center of the CAPTAIN s~7stem to the terminal apparatus of each user, shown in more detail in Fig. 4. One section of the format is called a "packet", and Fig. 2A illustrates a picture screen control packet (hereinafter simply referred to as a "G packet"); Fig. 2~ illustrates a color information packet (hereinafter simply referred to as "C
packet"); and Fig. 2C illustrates a small character sequential display pattern (hereinafter simply referred to 9,;i~3432 as "S packet"). Each of these packets includes at its beginning a packet code indicating what kind of packet it is .
Following the packet code, the G packet includPs a code indicative of the display mode and a code for designating the color of the picture screen header or the like. The C packet includes a code indicating to which sub-row this packet ~elongs1 or indicating the display position per sub-row unit in the column direction, ar.d a colo code or speclfyinG .he color o each sub-hlock in the sub-ro~- designated by this code. Further, the S pacl~et includes - code indicating to which line this packet belongs, or indicatins the display position of the l~ne unit in the longitudinal direction and a pattern data indicative of dots on the line designated by this code. These packets are divided by flags each of which has a particular bit arrangement and are then transmitted from the data base center of the CAPTAI~ system to the terminal apparatus of the user.
In regard to the display modes designed by the above-described G packet, there can be a fixed display mode and a scroll display mode. In the scroll display mode, a difference between the display position of the displayed picture information and the display position of the newly recei~ed picture information is obtained, and the picture information being displayed is shifted upwards ~y this diference amount. Thus, the picture information is displayed under the condition that the new picture information is inserted into the lowermost portion of the :!~Z43432 display picture screen, however, the picture screen header is not displayed in this scroll display mode.
Accord1nyly, in this scroll display mode, the packets are transmitted in the combinations as shown in Fig.

3, that is, the G packet is transmltred rirst and then the C
packet ~0] for designating the color o- the 0th sub-row and so on -_ transmitted. Thereafter, 12 S packets [O -l] to [O
- 12] including ~a.tern da.a o- 12 lines a. the 0th sub-ro~
-re transmitted sequentlall ~r~ . The plcture screen header is aisplay_c in the 0th sub-row by the C and S packets [Oj, [O
- 13 to ~0 - 12], respectively.
Subsequently, the C packet Gr designating the color of the first sub-rcw is transmitted and then 12 S
pacXets ~1 - 1] to [1 - 12] including the pattern data of the lines of the first sub-row are transmitted sequentially.
Similarly, the C packet and the S packet are transmitted se~uentially thereafter. Thus, the picture information is continuously being shifted one-by-one upwardly on the picture screen.
When the S packet 116 - 12] of the last line of the 16th sub-row (204 lines in total) is transmitted and then displayed on the display picture screen, the display of the first page is completed and the ne~t succeeding page is scroll-displayed by the respective C and S packets following the first page.
Fig. 4 illustrates an example of a special terminal apparatus for use in the CAPTAIN system in which a telephone subscriber's te]ephone network line 1 and a standard telephone 2 are connected to the special terminal apparatus 10. The terminal apparatus 10 is controlled by a ~Z43432 S0207~

microcomputer, including a.n 8-bit central processing unit (CPU) 11 for parallel processing, a read only memory (ROM) 12, in which stored is the processing program, a random access memory (RAM) 13for wcrk area and buffer area, and a video R~ 1 A having a data capacity of at le2st one picture screen amount. A color picture tube or cathode ray tube ~CRT) lS is providcd along ~ith a read address control circuit 16 and G dFflectlon circuit 17.
The output signal fro~ dcflectlon c-rcuit 17 is fcd to color p c~ure tube 15, wherein the de~~lecticn is car_ied out ard - synchroni~lng signal rom derlection circuit 17 is fed to read address con, ol circuit 16, whicr.
-then produces a read address signal corresponding to the deflection position on the picture tube 15, and this read address signal is fed to video RAM 14. Accordingly, from video RAM 14, there is read out address data corresponding to the deflection position on color picture tube 15, and this data is supplied to color picture tube 15, which therefore displays thereon the data, which is written in video RAM 14.
Also provided is a hybrid circuit or line coupling unit (LCU) 21, a modulator and demodulator (MODEM) 22, a serial-to-parallel converting circuit 23, a parallel-to-serial converting circuit 24, I/O ports or interface circuits 25 and 26, and a key pad 27 used by a user to carry out various operations. LCU 21 is controlled by the output of CPU 11 through interface circuit 25 and, upon use of the CAPTAI~ system, the telephone network line 1 is coupled through LCU 21 to MODEM 22.

Consequently, the data signal from the data base center of the CAPTAIN system throu~h the telephone network lines l is demodulated by MODEM 22, converted from a serial signal to z parallel sigr.al by serial-to-parallel converting circuit and then fe~ LO CPU 11. Conversely, the data signal, which is a request signâl, from CPU 11 is converted from a parallel signal to a serial signel by parallel-to-serial convertor q, modulated by MODEM 2q and then ~ed through the tPlephone network line to the dala bzsc center o~ the CAPTA~-~I system.
Only that portion OI the CAPTAIN s~stem that r-lates to tnis inventiGn is su~mârized above and it ls to be understood that other elements and data are involved, for example, there is a packet which includes other data.
Nevertheless, such packet is not directly related to this invention and can be represented by the above-described packets, so that its detailed description can be omitted for brevity and clarity.
When the scrolliny display is carried out, the data access for video RA~7 14 is generally carried out in a manner represented in Figs. 5A to 5L and 6A to 6D. Figs. 5 schematically illustrates the internal addresses of video r~! 14, in which reference numeral 14P designates a video RAM in which the pattern data is accessed and reference numeral 14C designates a video RAM in which the color code is accessed. In video RP~-l 14P, numerals [1 to 216]
represent line addresses, in which the pattern data of one line can be accessed from each address and further in the video RAM 14C, numerals [O - 17] represent sub-row addresses (sub-row addresses) of the RP~I 14C, in which the color code ~Z43432 of one sub-row can be accessed from each address. The addresses 1 to 12 of video RAM 14P and the 0th address of video RAM 14C correspond to the picture screen header. Fig.
6 shows exclusively the addresses 1 to 12 and the 0th address o videG R~Ms 14P and 14C which correspond to the picture screen header. In Figs. 5A to 5L and 6A to 6D, the cross-hatchcd addresses indicated those whereat the newest data o~ each page is ~ritten.
Re ding ou, o- vid^o Ra~ss 14P and 14C is carried out a~ every ,ield in s-~nchronism with th_ scanning cf Lhe color pic.ure tUDe 1 ~ . In lhis case~ in Figs. 5A to 5L and ~A to 6D arrows ~ and ~ indic2te a range of addresses being accessed and the order thereof in the reading at ev~ry field, respectivel~. The read address of the RAM 14P is varied at every horizontal period, while because the color is determined on a sub-block unit basis and one sub-bloc~ is formed of 12 lines, the read address of video RAM 14C is varied at every 12 horizontal lines. For exampl~, when the 2st to 12th addresses of viJdeo ~AM 14P are sequentially read out, the 0th address of video RA~ 14C is read out 12 times simultaneously.
Because the data transmission from the data base center of the CAPTAIN system and the scanning of color picture tube are not synchronized with each other, the writing in and the reading out of data relative to video RAMs 14P and 14C are not always carried out strictly alternately, and because the data transmission rate is lower than the display rate, the data is read out several times for one writing in period.

~;~43432 Accordingly, when the scrolling display is carried out and if the data is transmitted as shown in Fig. 3, the following operations will be carried out.
(i) When the C packet Eo] of the 0th sub-row is transmitted, the color code is wri.ten in the G.h address of viaeo P~M 14C, as shown by the cross-hatched portion in Fig.
6A but as shown in Fig. 5A, the reading of video R~M 14P ls starte~ form the lrst address and carrled out continucusly up .o the 204th address, while ât the same tlm~e, the reading o video R~ 14C st~~ting from the 0th address ~p to the 16th address ls continuo~sly carried out 12 times.
(ii) When the S packet [O - 1] of the first line of the 0th sub-row is transmitted, the pattern data thereof is written in the first address of video PU~I 14P, as shown by the cross-hatched portion of Fig. 6B, and the reading of video RA~s 14P and 14C is the same as that of operation (i) above.
(iii) When the S packet [O - 2] of the second line of the 0th sub-row is transmitted, the pattern data thereof is written in the second address of video RAM 14P, as shown by the cross-hatched portion of Fig. 6C, and the reading of video RAMs 14P and 14C is again the same as that of operation (i) above.
(iv) The similar operation is repeated and when the packet [O - 12] of the 12th line of the 0th sub-row is transmitted, the pattern data thereo' is written in the 12th address of the video RAM 14P, as shown by the cross-hatched portion in Fig. 6D, and the reading of video RAMs 14P and 14C is also the same as that of operation (i) above.

~Z~3~32 Consequently, by the reading in according to the above (i) to (iv) operations, the picture screen header is displayed in color at the position of the 0th sub-row on the picture screen of cclor picture tube 15.
(v) When the C packet [1~ of the first sub-row is trarlsmitted, the color code thereof is written in the 17th address of video R~l lgC, as shGwn by the cross-hatched portion OL Fig. 5B, and the readlng is th~ same as that of operation (i) above.
(v j When the S packet [1 -1] of the ~irst line OL- the lr-~ sub~row is transmitted, the pattern data ihereof is written in the 205th address of video RAM 14P, as shown by the cross-hatched portion of Fiy. 5B, and when the writing is ended, as shown in Fig. 5B, the reading of video RA~I 14P is sequential starting from the 1st address to the 12th address and then skipping to the 14th address.
Thereafter, the reading of video RAM l~P is sequentially carried out from the 14th address to the 205th address. At the same time, although the reading of the RAM 14C is started from the 0th address, the succeeding first address is read out 11 times (normally 12 times) and the 2nd to 12th addresses are read out 12 times each. Finally, the 17th address is read out once.
Accordingly, by this reading, the picture screen header is displayed in color at the position of the 0th sub-row on the screen of color picture tube 15 and the first line of the first sub-row id displayed in color at the position of the lowermost line thereon, that i5, the scrolling display is started.

~Z4343~, (vii) When the S packet [1 - 2] of the second line of the first sub-row is transmitted, the pattern data thereof is wrltten in the 206th address of video P~M 14P as shown by the cross-hatched portion of Fig. 5C, and after this ~rlting, as shGwn in Fig. 5C, the reading of videG p~r~
14P is carried out with respect to the area ~ , then skipp d to tne 15th address and sequentially carried out _rom the 15th address to the 206th address. At the same time, the reading of video R~ 14C is moved from the ar~
to the ~irst address, the -irst address s read out lO
t-~es, and the aaaresses _rom the second address to the 16th address are read out 12 times each. Thereafter, the 17th address is read out twice.
Accordingly, by this reading, the picture screen header is displayed in color at the position of the 0th sub-row, and the first and second lines of the first sub-row are displayed in color at the positions of the next following two lines. That is, the scrolling display of one line is carried out for operation (vi).
(viii) Subsequently a similar operation is carried out and when the S packet [1 - 12~ of the 12th line of the first sub-row is transmitted, the pattern data thereof is written in the 216th address of video ~A~I 14P, as shown by the crcss hatched portion of Fig. 5D. After this writing (Fig. 5D) the reading of video RAM 14P is carried out on the area ~ , then skips to the 25th address and the addresses ~rom the 25th address to the 216th address are read out sequentially. At the same time, although the flrst address of video RAM 14C should be read out after the area ~ , that reading is not carried out, or the reading of the ~st ~L243q~3~

address i5 skipped, and the readiny is then moved to the 2nd address. Then, the 2nd address to the 17th addresses are sequentially read out 12 times each.
Thence, under ~his condition, the picture screen header is displayed in color at ,he position of the 0th sub-row and the 1st sub-row is displayed in color at the position of the lowermos. sub-row ~the 16th sub-row), that is, ine scrolling display of one sub-row amoun, is carried ou, .
lix~ When the C packet [2~ of the second sub-row is transmit_êd, .he color code thereol is wrltten in the 1st address of video R~ 14C, as shown by the cross-hatched portion of Fig. 5E, and the reading is the same as that of operation (viii) above.
(x) ~hen the S packet [2 - 1] of the first line of the second sub-row is transmitted, the pattern data thereof is written in the 13th address of video RAM 14P, as shown by the cross-hatched portion of Fig. 5E, and after this writing (Fig. 5E) the area ~ of video RAM 14P is read out and the reading then skips to the 26th address.
Thereafter, the 26th to the 216th addresses are sequentially read out. The 13th address is read out next and at the same time, the 2nd address of video RAM 14C is read out 11 times after the area ~ , the 3rd address to the 17th address are sequentially read out 12 times each and, finally, the 1st address is read out once.
Accordingly, at this time, the picture screen header is displayed in color on the picture screen at the position of the 0th sub-row, and the full lines of the 1st sub-row and the first line of the 2nd sub-row are displayed ~2~3~3Z

respectively in color ak the positions of the 12th line of the 15th and 16th sub-rows, that is, the scrolling display of one line is carried out further.
~ xi) Similar operations will be repeated, as shown in Figs. 5F to SH, and ~ig. 5F showns a state in which the pattern daia cr the l~th line of the 2nd sub-row is wrltten, Fig. 5G shcws a state in which the pattern data OL
the 1st line OL the 16th sub-row is written, and Fig. 5~:
shcws a state ln whicr the pattern d2~a of the 12th line c the 16th sub-ro~, or ~ne last pattern da a o~ he irst page ls ~ritten, respectively. Ir. the state shown in Fig. 5H, the data of the 1st line of the 1st sub-row is scrolled tG
the position o~ the 1st line of the 1st sub-ro~, and this means that all data of just one page is scroll-displayed.
(xii) When the C packet [1] of the 1st sub-row of the second page is transmitted, the color code thereof i5 written in the 16th acdress of video RAM 14C, as shown by the cross-hatched portion of Fig. SI, and the reading is the same as that of operation (xi) above.
(xiii) When the S packet El - 1] of the 1st line of the 1st sub-row of the second page is transmitted, the pattern data thereof is written in the 193rd address o~
video RAM 14P, as shown by the cross-hatched portion of Fig.
5I, and after this writir.g has ended (~ig. 5I) the area ~
of video RAM 14P is read out, and then the reading skips to the 206th address. The 206th address to the 216th address are then read out sequentially and then this reading is then further skipped to th~ 13th address. Thereafter, the 13th address to the 193rd address are read out sequentially. At the same time, after the area 1 of video RAM 14C is read ~L2~343;2 out, the 17th address of video RP~I 14C is read out 11 times and the first address to the 15th address are sequentially read out 12 times each. Finally, the 16th address is read out once.
Therefo e, upon this reading, the first pase is scrolled further by the amount of one line so that the 1st line or the 1st sub-row thereof disapp-ars and the 1st line of the 1st SUD-rC-vi 0- the second page is nawly dlsplayed _t the lowermost position, thzi is, at the bottom line. ~n o.her words, the second page ls scrolIed after the first pcge.
txiv) Wnen the C pack~t and the S packet of the second page 2 are transmitted subsequently, the scrolling display is carried out similar to the first pase, or to the operations shown ir Figs. 5B to 5H. When the S packet [16 -22] of the 12th line of the 16th sub-line is transmitted, the state as shown in F~g. 5J is presented.
(xv) When the C packet of the first sub-row of the third page and the S packet [1 - 1] of the 1st line are secuentially transmitted, the state as shown in Fig. 5K is established and similar operations will be subsequently carried out.
In short, as shown in Fig. 5L, upon performing a scrolling display, the 1st to 12th addresses of video R~l 14P arld the 0th address of video RAM 14C are usPd for the picture screen header and the data are written therein once, however, the last addresses, or the 216th and 17th addresses, of video RAMs 14P and 14C are connected to the 13th and 1st addresses thereof from an operation standpoint, as represented by broken line arrows of Fig. 5L, ~lZ43432 respectively. Thus, the 13th to 216th addresses of video RAM 14P and the 1st to 17th addresses of video RA~ 14C are respecti~ely formed in so-c_lled ring shapes. Then, the newly recei~ed data are written in the next addresses (the aadress -ollowed by the 216.h and 17th addresses are 13th and 1st addresses) of the ring shzpes. Therefore, in order for the addresses ir which th_ new data are written to become the last add-esses upcn reading, the area ~ is r-ad out ov_r 152 lines (the l-umber of lir;es less .he area ~ ).
As pointed out above, in this method, however, when the data o~ the color information packet or the small character sequential display pattern packet is no~ obtained due to noise or other signal disturbances, a mis-matching will occur between the pattern and the color which is to be scroll-displayed.
Because the color code and the pattern data of the 0th sub-row of the 1st page are the picture screen header and are not scrolled, except the color code and the pattern data as described above, the beginning of each page becGmes the 1st sub-row. For e~ample, when the addresses of video RP~I 14C and 14P in which the color code of the 1st sub-row and the pattern data of the 1st line are written are considered, they are writt~n in the 17th and 205th addresses with respect to the 1st page, as shown in Fig. 5B, while they are written in the 16th and 193rd addre~ses with respect to the 2nd page, as shown in Fig. 5I, and they are written in the 15th and 181st addresses with respect to the 3rd page, as shown in Fig. 5K. In other words, if the page is changed, even with the same sub-row and the same line, the addresses in which the color code and the pattern data lZ4~43;2 thereof are written are decremented at every page by 12 addresses and 1 address, respectively.
Thus, even if the C packet and the S packet contzin the codes indicative of their display positions, the addresses at which the data are written are changed witr the pages so that it is very difficult to write the color code or ,he patterr. data in vldeo RAMs 14C and l~P by using ths display position coa~s.
Tnat ls ~hy, when the color code or the pattern data is cbtained, this color code or the pat'era data is wr~tten in the address Lollo-wing the address in which the previous color code or patterr. data is written.
Accordingly, if the color code of the color information packet at its n-th address is not obtained due to noise, for example, the color code of the C packet at its (n l)th address is written in the address in which the color code of the color information packet at the n-th address should be written. Thereafter, all color codes are written in the video R~ wlth addresses decremented by one every address, so that the color code is displaced upward by one sub-row amount on the picture screen.
As a result, if such the color code and the pattern data are read out to carry out the scroll display, all the pictures under the sub-row of which the color code can not be obtained are scroll-displayed with the co3or being displaced by one sub-row amount relative to the pattern data, and this continues until the scrollin~ di~play is ended.

On the other hand, when the pattern data of the small charac~er sequent~al display pattern packet is not ~Z43432 obtained, for similar reasons, the succeeding pattern data is incremented by one address and then writt:en in the video RAM. Consequently, all picture images below the line of which the patLern data is not obtained are scroll-displayed such tha. the patterns and the colors tnereor are each is-matched by one line, and this continues until the scrolling display is ended. If the color code of the color in~erm2tion peck2. andior the patte1--. data of th2 small character se~uential display pattern packe- a~e n~t cbtained, i.n the 'ollowirg scrolling dispiay t~e pa'tern and its colcr are all displaced with each othe~.
The present invention provides a me.hod and apparatus whereby data is accessed as shown, for example, in Fig. 7, wherein llke elements corresponding to those of Fig.
5 are marked with the same reference numerals and will not be described in detail.
Referring to Fig. 7, the princlples of the present invention are described as follows:
(I~ When the C packet [O] and th S packets [O -1] to [O - 12~ of the 0th sub-row are transmitted, similar to operation (i) above, the writing and the reading of the color code and pattern data are carried out as shown in Figs. 6A to 6D and in Fig. 7A. Note that Fig. 7A is the same as Fig. 5A. Accordingly, the picture screen header is displayed in color at the position of the 0th sub-row on the screen of color picture tube 15.
(II) When the C packet ~i] of the 1st sub-row is transmitted, the color code thereof is written in the 17th address of video RAM 14C, as shown by the cross-hatched ~243g~32 portion of Fig. 7B, and the reading is th~ same as operation (I) above.
(III) When the S packet [1 - 1] of the 1st line of the 1st sub-row is transmitted, the pattern data thereof is written in the 205th address of video RA~l 14P, as ~hown by the cross-hatched portion of Fig. 7B, and after this writing (Fig. 7s) the area ~ of videG P~M 14P is read cut and the reading is then skips to the 14th address. Then, the 14th tc 2C5th addresses are re2d out sequentially. At the same time after the area ~ , the 1st address of video P~! 14C
is read out 112 tlmes. Then, the 2nd to 16th addresses are read out 12 times each, and the 17th address is then rinally read out once.
Accordingly, by this reading, on the screen of color picture tube 15 the picture screen header is displayed in color at the position of the 0th sub-row and the 1st line of the 1st sub-row is displayed at the bottom line position.
In other words, the scrolling display is started. When ~he reading assumes the state described above, the pattern data at the 205th address of video RAM 14P is transferred to the 13th address, as shown by the cross-hatched portions in Fig.
7B.
(IV) When the S packet [1 - 2] of the 2nd line of the 1st sub-row is transmitted, the pattern data thereof is written at the 206th address of video R~M 14P, as shown by the cross-hatched portion in Fig. 7C, and after this writing (Fig. 7C) the area ~ of video RA~i 14P is read out and then the reading is skipped to the 15th address, in which the 15th to 206th addresses are sequentially read out. At the same time, after the area ~ , the 1st address of video RAM

2~-i2439132 14C is read out 10 times and the ~nd to 16th addres~es are read out 12 times each. Thereafter, the 17th address is read out twice.
Accordingly, by this reading operation the picture screen header is displayed on the screen of in color at the positio~ of the 0th sub-ro~, and the 1st line and 2nd line of the 1st sub-row are displayed in color at a position two lines frGm the bottom. That is, the scrolllng clsplay of one line amount is carrled out for operation '~I) above.
.hen the reading ass~es th~ state described above, the pattern data of the 206-h address of video R~l 14P is transferred to the 14th address, as shGwn by the cross-hatched portions in Fig. 7C.
(V) ~hen similar operations are repeated and then the S packet [1 - 12] of the 12th line of the 1st sub-line is transmitted, the pattern data thereof is written at the 206th address of video P~M 14P, as shown by the cross-hatched portion in Fig. 7D, ~nd after this writing (Fig. 7D) the area ~ of video RAM 14P is read out and then the reading skips to the 25th-address. Thereafter, the 25th to 216th addresses are read out sequentially. Although as to video RAM 14C the 1st address thereof should be read out after its area ~ , the 1st address is read out zero times and, hence, the 1st address following area ~ is skipped and the 2nd address thereo. is then read out. Thereafter, the 2nd to 17th addresses thereof are read out sequentially 12 times each.
Accordingly, under this state, the picture screen header is displayed in color at the position of the 0th sub-line and the first sub-row is displayed in color at the ~Z~3~;~2 position of the last sub-row. That is, the scrolling display of the one sub-row is carried out. When the reading assumes the state described above, the pattern data at the 216th address OI vldeo R~M 14P is transferred to the 24th address thereof, aS shown by the cross-hatched portions in Fi~. 7D.
Further, as sho~r by the cross-hatched portions in Fig. 7E, the color code of the 17th address o vldeo RA~! 14C
is t_ansferred LO lts 1st address. In this case~ although the nata cf the 205th to 216_n addreases of -~ideo R~M 14P
and the data of the 17th addre~ses o- video R~ 14C are transferredf these data still rema-n ~t ,he orisinal addreâses, but they are not shown by the cross-hatched portions in Fig. 7E.
After the transfer of the color code at the 17th address of video RAM l~C is ended, as shown in Fig. 7E, the area ~ of the R~l 14P is read out and the reading is then skipped to the 25th address and the 25th address thereof is read out. Subsequently, the 25th to 204th addresses are read out in turn. Thereafter, the 13th to 24th addresses are read out sequentially and at the same time, after area of the RAM 14C has been read out, the readin~ skips to the 2nd address and the 2nd to 16th addresses are read out 12 times each. Subsequently, the 1st address is read out 12 times.
In this case, because the data of the 13th - 24th addresses of video RAM 14P and the data of the 1st address of video RAM 14C are those which are respectively transferred from the 205th to 216th addresses and from the 17th address, even if the read address is varied as shown in ~Z~343;;~

Fig. 7E, the displayed state is the same as shown in Fig.
7D.
(VI) When the C packet [2] of the 2nd sub-row is .ransmitted, the color code thereof is writter at the 17th zcdr~ss of video RAM 14C, as shown by the cross~hatched portion in Fig. 7F, and the reading is the same as that of operation (V~ above (Fig. 7E).
!-~IIl When _he S pac~et ~2 - 1] of the 1SL line o_ the 2nd sub-row is transmitted, the paLt_rn data ihereof is wri.ten at-the 205~h address of video ~ P, as shown by the crcss-hatck_d portion in Fis. 7~, and a,te this writing (Fig. 7F) the area ~ of the P~1 l P is read out and the reading is s~ipped to the 26th address. Then, the 26th to 204th addressPs are sequentialiy read out. Further, after the 13th to 24th addresses are read out sequentiallyr the 205th address is then read out. At the same time, the area ~ of video RAM 14C is first read out and the reading is skipped to the 2nd address, which is then read out 11 ti~es. In turn, the 3rd to 16th addresses are sequentially read out 12 times each. Thereafter, the 1st address is read out 12 ti~.es and, finally, the 17th address is read out once.
Accordingly, by this reading the picture screen header is displayed in color at the position of the 0th sub-row on the picture screen of color picture tube 15, and the full lines of the 1st sub-row and the 1st line of the 2nd sub-r~w are displayed in color at the positions of the 12th line of the 15th sub-rGw and the 16th sub-row. That is, the scrolling display of one line is carried out further.

~Z43432 When the reading assumes the ctate described above, the pattern data at the 205th address of video RAM
14P is transf~rred to its 25th address, as shown by the crcss-hatched portions in Fig. 7F.
(VIII) When the S packet [2 - 2] of the 2nd line of the 2nd sub-row ls transmitted, the pattern data thereof is ~rit.en in the 06th address of video RA~ 14P, as shcwn by the cross-hatched port~Gn in Fig. 7G, and ar.er .his writing (~lg. 7G~ tne area ~ o video ~ 14P is read out and hen the read ng j~!ps to ,he 27th adc-ess. Therear.er, the 27th io 204th addresses are ead out seauentially.
Further, after the 13th to 24th addresses are sequentiallv read out, the 205th and 206th addresses are read out, respectively. At the same time, after the area ~ of video P~M 14C is read out, the 2nd address is read out 10 times and the 3rd to 16th addresses are read out sequentially 12 times each. Thereaft~r, the 1st address is read out 12 times and the 17th address is read out twice. Accordingly, the display is scrolled by extra one line. When such reading state appears, the pattern data at the 206th address of video R~ 14P is transferred to its 26th address, as shown by the cross-hatched portions in Fig. 7G.
(IX~ 5imilar operations will be succeedingl~
carried out and when the pattern data of the S packet [2 -12] at the 12th line of the 2nd sub-row is transmitted, the reading of the data from video Pl*1s 14P and 14C is as shown in Fig. 7H. Under this state, th~ scrolling display is carried out to the positions of the 15th and 16th sub-rows on the picture screen of the color picture tube 15. When such state is brought about, as shown in Fig. 7I, the color ~3432 code at the 17th address of video R~M 14C is transferred to its 2nd addre~s. After the transfer of the color code, video RAMs 14P and 14C are read out, as shown in Fig. 7I.
~ X) When the C packet ~3] and the S packets [3 -1] to ~3 - 12] of the 3rd sub-ro~ are transmitted, the data o video R~Ma 1 4P and 14C and the reading or the data therefrom simllarly assu~.e the states shown in Figs. 7J to 71. That ls, the cclor code and the pattern data OL the 3rd sub-row are accessed based on the 17th a~dr-ss o~ v~deo ~M
14C and the 205th to ?1 6th addresses of -~ideo ~ P, ana the pattern data is transferred to the 37th to 48th addresses of video RAM 14P corresponding to the 3rd sub-line. Then, when the pattern data of the S pack~t E 3 -12] at the 12th line of the 3rd sub-row is written in the 216th address of video RAM 14P, the state shown in Fig. 7L
appears. As shown in Fig. 7M, the color code of video RAM
14C is transferred to the 3rd address and thereafter the reading is carried out as shown in Fig. 7M.
(XI) The similar operations will be carried out thereafter and when the C packet [16] and the S packets [16 - 1] to [16 - 12] of the 16th sub-row are transmitted, the data and the reading of the data therefrom become shown ln Figs. 7N to 7P, respectively. Under the state as shown in Fig. 7P, the 1st line of the 1st sub-row is scrolled to the position of the 1st line of the 1st sub-row on the picture screen of color picture tube 15 or, in other words, the images of exactly one page amount are scroll-displayed.
When the state as shown in Fig. 7P is brought about, the color code at the 17th address of video RAM 14C

--3~

~L243432 is transferred to its 16th address, as shown in Fig. 7Q, and th~reafter the reading is carried out as shown in Fig. 7Q.
Since the state of Fig. 7Q is exactly the same as that of Fig. 7A, when the C packet [1] of the 1st sub-row of the 2nd page is transmitted, the data and the state thereof become as shown in Fig. 7A, while when the color code and the pattern data of the 2nd pase are transmitted, the op~rations shGwn in Figs. 7A to 7~ are onc_ again carried out. Color codes ar.d pa _ern data o_ the 3rd page and ihe follow-~ng pages are processed similârly, in which eacr page begins with the state shGwn in Fig. 1~ and enss with the stats shown in Fig. 7Q, and the same operations as shown in Fig. 7 are carried out for each page.
According to this invention, the sub-row to which the transferred color c~de belongs, and the line to which the transferred pattern data belongs, are each made correspcnding to the addresses of video RAMs 14C and 14P
one-by-one and only when the pattern data of one sub-row are not complete, the color code and the pattern data belonging to the sub-row are written in and read out from the buffer areas (its 205th to 216th addresses and 17th address), while when the pattern data belonging to the sub-row are all cGmplete, the color code and the pattern data are read out from the addresses corresponding to the sub-row and the lines.
Thus, even if the color code of a certain sub-row can not be obtained due to noise, for example, the color code is not written at the corresponding address but the succeeding color code can correctly be written at the corresponding address on the basis of the position ~Z439L32 indicating code (Fig. 2) which is indicative of the position of that color code. Thus, although the color of the sub-row of which the color code is not obtained due to the noise is disturbed, no mis-matching will occur between the dlsplayed pat~ern znd color in the succeeding sub-row.
Furthermore, even if the pattern data of a certain line is not obtained, the succeeding pattern data can be ri.,en in the corresponing address so that nc mis-matchinc will cccur between the displa~ed pattern and color.
Fig. 8 is a dlagrGm subst2ntiGlly the s~me as Fis.
7, e~cept that i_ is parti_ll. revlsed. In Fig. 8, of the addresses in video R~ls 14P and l~C, the addresses from which no reading is carrled out are not shown, and, the areas ~ and ~ are read out successively so that they are shown in continuous form. Figs. 8A to 8Q correspond to Figs. 7A to 7Q, respectively. According to Figs. 8A to 8, the reading of video RA~I 14P begins with the 1st addresss at every vertical scanning line and continues to the 12th address. The address which will be read out next is the address marked by a O , and such the address increments by one address each time the pattarn data is obtained. The reading from the address marked by O is continued and when the reading arrives at the 204th address, the 13th address is read out (except in Figs. 8B to 8E~. Then, the reading is continued from the 13th address to the 24th address and, next, the reading begins with the 205th address.
At the same time, the RAM 14C is also read out similarly. In this case, after the 0th address is read out, an address mar~ed by X will be read out and such address is incremented by Gne address each time the color code is --3d--~2~343~

obtained, and the number of the readin~s of the address marked by X is decremented by one address each time the pattern data is obtained.
An embodiment of the image aispla~ apparatus accordins to ,his invention will hereinafter be des~ri~d with reference to Fig. 9, in which circuits 61 to 65 are principally for .he read address of video RAM 14P, while circuits 71 t~ 77 are principally fo the read ad~ress of the -~i 14C r C-rcuit 61 is an 8-~it presett2ble up-counter that is suppllcc wi.h a hori~ontal syr.chronizing pulse Ph 2a the couni input a~d which then forms a line address signal 1A
(which signal becomes the above-descri~ed 1st to 216th addresses~ upon the reading of video RAM 14P. Counter 61 is formed such that when the level at input terminal L changes from "0" to "l", the data input at a terminal DI can be loaded (preset) as its count initial value. Circuit 62 is an 8-bit 3-state latch circuit and is supplied with the address (which is the start address of area 2 ) of video R~ 14P through the CPU 11 and is latched therein. Latch circuit 62 assumes a high output impedance (open) when the level of the terminal OC is "1", while when it is "0", latch circuit 62 supplies its latched content to counter 61 as the preset input thereof.
Circuits 63 and 64 are 3-state output buffers each of which assumes a hi~h output impedance (open), when the level at terminal ~C is at "1". When the level at terminal OC is "0", output buffer 63 supplies the value "13" to counter 61 as its preset input, and output buffer 64 supplies the value "205" to counter 61 as it~ preset input.
Accordingly, after any one of the thres output values, namely, "the value of mark 0 ", "13", and "2Q5" of latch circuit 62 and output burfers 63 and 64 is loaded into counter 61, the address signal LA is incremented by "1" from iis loaded value at every horizon~al synchronizins signal Ph.
Circuit 65 is a d^ccder thaL is supplied wi.h the add-=ss signal L~ from up-courter 61 so that when _A =
'l20~", th_ ou.put Q55 thereof becomes 10ll. Clrcui_ 76 is a 1-blt preset~able l^~-scale down-counter, and circuit 77 is a

4-bi. latch circuit. Counter ,6 counts the r.umber reading out of each address of videG RP~q 14C and latch circuit 77 is supplied with the number reading out of the addresses marked by X of video RAM 14C from CPU 11 and then latched therein.
The latched output from latch circuit 77 is supplied to counter 76 as its preset input and the horizontal synchronizing pulse Ph is supplied to counter 76 as its count input.
Accordingly, counter 76 pxoduces a borrow output Q76 and the borrow output Q76 is obtained as shown in the right-hand side of Pigs. 8A to 8Q. In other words, in the address marked by X, after the number of the readings designated by latch circuit 77 (the number of the horizontal synchronizing pulses Ph), the borrow output Ç76 = "1" is established, and thereafter, at every 12 horizontal synchronizing pulses Ph, Q76 = "1" is established.
Circuits 71 to 75 correspond respectively to circuits 61-65 and, more particularly, circuit 71 is a 5-bit presettable up-counter and is used tc produce a sub-row ~24343Z

address signal CA (~hich becomes the O-th to 17th addresses set forth above) upon reading of video RA~ 14C. To this end, the horizontal synchronizing pulse Ph is supplied to counter 71 2s its count input and the borrow output Q76 is supplied as the count enaDle signal thereof. Consequently, the address specified by the address signal CA is varied at every -~ign21 Q75, as shown in Fig. 8.
Circuit 72 is a 5-bit 3-staie latch circuit and thl~ latch circu~t ls supplied with the sta-t aad-ess (adaress marked by ~) o- the a-ea 1~! 0 ~ .C f CPU 11 to ~e latched therein, and thi~ l.,ch circuit 72 supplies the latched csntent to counter 71 as its preset input when the level at terminal OC is "1".
Circuits 73 and 74 are 3-state output buffers each of which assumes a high output impedance when the signal level at terminal OC is "1". On the other hand, when it is "O", output buffer 73 supplie5 the value "1" to counter 71 as its preset input, while buffer 74 supplies the value "17"
to ccunter 71 as its preset input. Accordingly, any one of the output values, namely, "the value of the mark X", "1", and "17" of latch circuit 72 and output buffers 73 and 74 is loaded to the counter 71. After the value is loaded thereto, the address signal CA is incremented by "l"from the loaded value at each borrow signal ~76~
Circuit 75 is a decoder that is supplied with the address signal CA from up-counter 71 so that when the address signal CA = "16", the level o its output Q75 becomes "O".
A flip-flop circuit 81 is used to produce a flag.

Flip-flop circuit 81 is controlled by CPU 11, and its output ~2~3~32 Q81 becomes "1" when the 205th to 216th buffer areas and the 17th addresses of video RAMs 14P and 14C are used in writing and reading. It becomes "0" when they are not used, that is, under the states shown in Figs. 8E,8I,8M and 8~, Q81 =
"G" is established, while under the other s~ates, Q81 = "1"
is establlshed.
A signal DSP 1 is provided by counting, for example, ,he pulse P'. and which becomes "1" durins a period from the time point p-icr to ,he 1st line by one horizontal period ,o .he end c _he ~04th line, as shown in Fig. 8R.
Thls s~grâl DSP 1 is supplied to ,he clear terminal CLP~ of counter 61, so that counter 61 is cleared durina the period of DSP 1 ="0", so as to hold the CL = "0", while its clear mode is released during the period of DSP l ="1".
A signal DSP 2 becomes "1" during the period from the beginning of the 1st line to the end of the 204th line, as shown by Fig. 8S, and this signal DSP 2 is fed to the clear terminals CLR of counters 71 and 76, respectively.
Further, a signal LD becomes "0" during the period of the scanning period of the 12th line in total, ar.d a signal SCGT
is â gate signal which becomes "l" during during scanning period at the positio}ls of the 193rd to 204th lines (sub-row 16), as shown in Fig. 8T.
By employing the circuit arrangement of Fig. 9, the following operations can carried out:
(A) As shown in Fig. 8R, because during the period prior to the 1st line (this line number is the number on the picture screen of the color picture tube 15 which is used in the ~ollowing) by olle horizontal period, DSP 1 = "0"

is established, counter 61 ls cleared, and hence LA = "0" is ~L~43432 established. Moreover, as shown in Fig, 8C, since DSP 2 =
"O" is established during this period, counters 71 and 76 are also cleared so that CA = "O" and Q76 = "" are satisfied.
(B) At a time point one hori~ontal period before the 1st line, the DSP 1 = nl" is established, so that counter 61 is set in the count mode.
IC! A~ ,h~ start pOillt or tne 1st line, becau..e the s~-nch-onlzing pulse Ph is counted in counter 61, LA =
"1" is established, or the 1st address o~ video ~M , dp 15 accessed b~ the address signal LA. As a result, the pattern data at ihe 1st line is read out from the 1st address OL
video RP~ P.
At this time, since the DSP 2 = "1" is satisfied, counters 71 and 76 are placed in the count mode. At this time, however, CA = "O" is satisfied, or the 0th address of video RA~5 14C is accessed by the address signal CA so that the color code of the 0th sub-row is similarly read out from the 0th address of video RAM 14C si~llar to the pattern data, thus, the 1st line is displayed.
(D) At the start of the 2nd line, the synchronizing pulse Ph is counted b~ counter 61 to establish LA = "2", so that the 2nd address of video RAM 14P is accessed by the address signal LA, thereby to read out the pattern data at the 2nd line.
At this time, although the synchronizing signal Ph is counted by counter 76, since Q76 = "" remains as it is CA = "O" is established, thus, the color code of the 0th sub-row is read out from video RAM 14C. As a result, the 2nd line is displayed.

_~9_ ~L2439~3z (E) Similar operations will be hereinafter carried out to the 12th line, and the color code and the pattern data of the 0th sub-row are read out and then displayed on the picture screen of color picture tube 15.
(F3 Durlng the period in which the above operations (A~ to (3) are belng carried out, CPU ll loads , :ne address marked by O tc latch circuit 62, the address marked by X tc latch circult 72, and further the re~cing nu~er o_ the address marked by X to atcn c rcuit 77.
~ C-~ although during thê r.orizon.al scanning pGricG c~ the 12 h line, L3 = IIQ'I i s êstablished~ the signal LD rises up from "O" to "1" by the synchronizing pulse Ph at the beginning of the 13th line. Then~ this signal ~D is supplied to latch circuit 62 as its load p~llse.
Accordingly, the address marked by O which is latched in latch circuit 62 is loaded to counter 61 when starting the horizontal scanning of the 13th line.
The signal LD is supplied to latch circuit 72 and also through an OR circuit 83 to the load terminal L of counter 71 as its load pulse. Consequently, the address marked by X and latched ln latch circuit 72 is loaded to counter 71. Further, the signal LD is supplied to the load terminal L of counter 76 as its load pulse and, hence, the reading number of the address marked by X (and latched in latch circuit 77) is loaded in counter 76.
In other words, when starting the horizontal scanning of the 13th line, the address marked by O is loaded to counter 61, the address marked by X is loaded to counter 71, and the reading number of the address marked by X is loaded to counter 76.

-- O--~Z43432 (H) During the horizontal scanning of the 13th line, because of operation (G) above, the pattern data and the color code are read out from the addresses marked by and X and they are displayed as the 13th llne.
(I) Thereafter, the counted value LA of counter 61 lncremented at every synchroni~ing pulse Ph and the read address LA of video R~ 14P is incremented address-by-address ~rom the address m~-~rked b~ O at every lino r ~S shown in Fis. 8.
On the other hand, in the counter 76, when the synchronizins pulse Ph is ccunted by thc reading n~er o~
the address marked by X, Q76 = ~ is sztisried and thereafter, Q76 = "1" is established at every 12 horizontal synchronizing pulses Ph. Since the horizontal synchronizing pulse Ph is counted by counter 71 only when Q76 = "1" is satisfied, its counted value CA, or the read address CA of RA~ 14C is incremented one address by one address from the address marked by X at every 12 lines, as shown in Fig. 8, if the horizontal scanning is carried out in the reading number of the address marked by X. As described above, the pattern data and the color code are read out up to the LA =
"204" and are displayed.
(J) When the LA = "20~" i5 satisfied, Q65 = "" `~`
is satisfied. In the following description, however, it is assumed that the color code and the pattern data of the sub-row following the 2nd sub-row be transferred, as shown in Fiys. 8F to 8Q, for simplicity. Then, when the condition f Q65 = "" is established, since SCGT = "O" is established, an output Q84 of an A~lD circuit 84 is "O".

Accordingly, the signal Q65 is supplied through an AND

~243~3;i~

circuit 85 to the terminal OC of output buffer 63 and through OR circuit 82 to the load terminal L of counter 61.
When the scanning period of the LA = "204" is ended and ~he succeeding synchronizing signal Ph is obtained, the sigr,al ~65 rises from 1l0~ to "1". As a result, at that time, the data "13" OL GUtpUt buffer 53 is loaded to counter 61. At the Sâm6 time, the simllar cperations are carr ed out in output buf_er 73 and ceunter 71. ~!ore specifically, ~her CA = "15~, Q73 = 1!0~ is es-ablish~d, ho~-_ver, at the neYt Q7~ = "1", when the syr.ch_onizing pulse Ph is supplied ther-to, the output of 2n A~D circuit 86 is changed from "O" to "1". Since this AND
output is supplied to the terminal OC of output buf fer 73 and a so through OP~ circuit 83 to the load terminal L of counter 71, at this time, the data "1" of output buffer 73 is loaded to counter 71. In other words, after LA = "204"
and C~ = "16", LA = "13" and CA = "1" are established, respectively.
(~) From the succeeding horizontal scanning period, the reading begins with the state of LA = "13" and CA = "1". Thereafter, this address signal LA is incremented one address by one address at every line and the address signal CA is incremented cne address by one address at every 12 lines. Further, in response to the address, the horizontal scanning position is shifted downward one line by one line.
(L) Under the states shown in Figs. 8F to 8H, Figs. 8J to 8L, and Figs. 8N to 8P, because the buffer area (205th to 216th and 17th address~s) of video RAMs 14P and 14C are used, Q81 = "1" is satisfled, when the horizontal -~2-:~Z43432 scanning position arrives at the position of the 16th sub-row (since at this time, SCGT = "1" i5 established) 5;8'1 = "1" is satisfied. Then, because the signal Q84 and the signal Q76 are both supplied to a NAND circu~t 87, when Q76 is established during the period in which the hcrizontal scar,ning position is at the 16th sub-row, the output ;;!~37 of N~ND circult 87 becomes "0". This signal Q87 is sl~pplied to he termircl OC of OUlpUt buffer 64 and also through OP~ clrcult ~2 to the load term,~nal L o~ counter 61, sc that the d2t ~2051l of output bu er 6~ is 1O2ded to countr 61. Thus, under ih.e states shown in Figs. 8F to 8H, Figs. ~J to 8L, a~d Figs. 8N to 8P, when the horizontal scanning positlon or the address signal LA proceeds to the position of the 16th sub-row, on the following line with the pulse Q76 = "l", the address LA becomes "205".
Further, since the signal Q87 is supplied to the terminal OC of output buffer 74 and also through O~ circuit 83 to the load terminal L of counter 71, the data "205" is loaded to counter 61 and, at the s~me time, ~hé data ~17~ of output buffer 7A iS loaded to counter 71 In consequence, the address signal LA becomes "205" and the address signal CA becomes ~17 ~ at the same time.
(M) Thereafter, the address signal LA is incremented from "205" by each address at every line, while the address siyna' CA remains "17".
(N) After the vertical display period is ended, DSP 1 = "0", DSP = "0" and SCGT = "0" are established, respectively, thus forming a picture image of one field amount.

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(L') Under the states as shown in Figs~ 8I, 8M, and 8Q, and because the buffer areas (205th to 216th and 17th addresses) of video RAMs 14P and 14C are not used, Q&l = 'G" is established. Accordingly, ev2n when the hcrizontal scanning position is reached to the positior of the 16th sub-row and SCGT = "1" ls astablished, Q~4 = llOII is left as it is, thus also leaving Q~7 = 'll' as it is.
Consequen,ly urder the statas as shGwn in Figs.
8I, 8~, and 8Q, even when .;-e horizontal scanning position re_ches 'G the posi.ion OI the 15-rl sub-ro~, the add_essGs L~ and CA ar- not changed over to the 2G5-h and 17th addresses but become continuous.
As described above, in the case of Figs. 8F to 8Q, the color code and the pattern data of video RAMs 14P and 14C are read out and then displayed respectively.
(j~ Under the states as shown in Figs. 8A to 8E, or the state that the color code and the pattern data of the 1st sub-row are transmitted, if LA = "204" is established, Q65 = "" is satisfied, however, at this time, sirlce Q81 =
"1" and SCGT = "1" are established, 84 = "1" is satisfied~
so that when the succeeding signal Q76 is changed from "0"
to "1" and then to "0", the signal Q~7 is changed fror.~ "0"
to l'1". Thus, by the change of the signal Q87' the data "205" of output buffer 64 is loaded to counter 61, and the data "17" of the output buffer 74 is loaded to the counter 71. In other words, the addresses LA and CA respectively become "204" and "16" after "205" and "17"~
(k) Thereafter, the state becomes sir.lilar to that of operatio~ (M) above,and the address LA is 4343;2 incremeIlted by one address each from the "205" at every line, while the address CA remains as "17".
(l) After the vertical display period is ended, DSP 1 = "0", DSP 2 = "0" and SCGT = nO1l are established (same as operation (N) above). Accordingly, the picture image of one field amount is ormed.
As describea above, according to the address control circuit 16, as showm in Fia. 9, the read addresses LA ar.d CA of video R~Is 14P and 1 A~C are controlled and the patterri cata and 'he color code are respectivelv read out.
As set forth 2bove, 5ccording to .his in~ention, the sub-row to whicr. ihe transmitted color code belongs and the lins to which the pattern data belongs are made to correspond to the addresses of video RAMs 14C and 14P one by one and only when the pattern data of one sub-row are not complete, the color code and the pattern data belonging to the sub-row are written in the buf~er areas (205th to 216th and 17th addresses) and then read out therefrom, while when the pattern data belonging to the sub-row are all complete, the color code and the pattern are read out from the addresses corresponded to the sub-row and the line.
As a result, even if the color code of a certain sub-row is not obtained due to noise, for example, such color code is not merely written in the coxresponding address but the succeeding color code can correctly be written in the corresponding address on the basis of the display position code (Fig. 2) indicative of the position of the color code. Therefore, although the color of the sub-row of which the color code can not be obtained due to the noise is disturbed, it is possikle to prevent -4~

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mis-matching from being produced between the displayed pattern and color in the succeeding sub-row. Even if the pattern data of a certain line can not be obtained, the succeeding pattern data can be correctly written in the corresponding address so that no mis-matching will occur between the dlsplayed pattern and color.
Since the buffer areas (205th to 215th and 17th adaressGs) o, videc ~rs l~P and 14C can be changed to cesir_d acdress_s only by cnanglng th_ data "2Q5" and "17"
of outpu. bu~ r5 ~4 and 7d, it iS pogsible ~0 simpli_y output buf;ers 6 A and 7~ in con-~ruction.
Furth~r, the apparatus Ot- this inven,ion can be applied to a television receiver O r a television character multiplexing broadcast.
Furthermore, the pattern data written in the buffer areas 205th to 216th addresses of video RAM 14P may not always be transferred to the inherent address at every one address but can be transferred to the inherent address with all its addresses together.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without deparing from the spirit or scope of the novel concepts of the invention, so that the scope of the invention should be determined solely by the appended claims.

-'6-

Claims (10)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS
FOLLOWS:

1. Apparatus for scrolling display images derived from a data signal formed as a plurality of packets that include pattern signals formed of a plurality of horizontal lines and a corresponding color signal, said apparatus comprising:
display means for producing a visual display of an input signal as a plurality of horizontal lines;
first memory means connected for receiving and storing said pattern signals and having a plurality of first addresses corresponding respectively to said plurality of horizontal display lines and having a first buffer area for temporarily storing received pattern signals;
second memory means connected for storing said color signal and having a plurality of second addresses corresponding respectively to said plurality of packets and having a second buffer area for temporarily storing received color signals;
means for storing said pattern signals and a corresponding color signal in said first and second buffer areas, respectively;
means for reading out said first memory means and said first buffer area by accessing said first addresses in a first predetermined order and for reading out said second memory means including said second buffer area by accessing said second addresses in a second predetermined order;
means for incrementing the number of an initial accessing address of said first memory means every horizontal period and means for incrementing the number of an initialaccessing address of said second memory means every plurality of horizontal periods, whereby said first and second buffer memory areas are read out respectively, after said first and second memory means; and means for transferring a pattern signal of a horizontal line stored in said first buffer area to a corresponding address of said first memory means and for transferring a corresponding color signal stored in said second buffer area to a corresponding address of said second memory means, whereby said pattern signals and said corresponding color signal are fed to said display means.

2. Apparatus according to claim 1, further comprising means for incrementing the number of an initial accessing address of said first memory means every horizontal period and means for incrementing the number of an initial accessing address of said second memory means every plurality of horizontal periods, whereby said first and second buffer memory areas are read out respectively, after said first and second memory means.

3. Apparatus according to claim 1, in which said first and second memory means further include header portions respectively corresponding to upper horizontal display lines of said display means and means for reading out said header portions prior to said initial accessing address.

4. Apparatus according to claim 3, further comprising counter means for producing address accessing signals that determine said accessing addresses of said first and second memory means according to a predetermined pattern.

5. Apparatus according to claim 4, further comprising preset means for presetting said counter means according to said predetermined pattern.

6. Apparatus for displaying scrolling images obtained from a data signal formed as a plurality of packets having pattern signals formed of a plurality of horizontal lines and a corresponding color signal, said apparatus comprising:
display means for producing a visual display as a plurality of horizontal lines;
first memory means connected for storing said pattern signals and having first addresses corresponding to said plurality of horizontal display lines and having a first buffer area for temporarily storing pattern signals received by said first memory means;
second memory means connected for storing said color signal and having second addresses corresponding to said plurality of packets and having a second buffer area for temporarily storing color signals received by said second memory means;
means connected to said first and second memory means for causing said pattern signals and a corresponding color signal to be stored in said first and second buffer areas, respectively;
means for reading out said first memory means and said first buffer area by accessing said first addresses in a predetermined order;
means for reading out said second memory means including said second buffer area by accessing said second addresses in said predetermined order;
means for incrementing the number of an initial accessing address of said first memory means every horizontal period and means for incrementing the number of initial accessing address of said second memory means every plurality of horizontal periods, whereby said first and second memory areas are read out respectively, after said first and second memory means; and means for transferring a pattern signal of a horizontal line stored in said first buffer area to a corresponding address of said first memory means and for transferring a corresponding color signal stored in said second buffer area to a corresponding address of said second memory means, whereby said pattern signals and said corresponding color signal are fed to said display means for visual display.

7. Apparatus according to claim 6, further comprising means for incrementing the number of an initial accessing address of said first memory means every horizontal period and means for incrementing the number of initial accessing address of said second memory means every plurality of horizontal periods, whereby said first and second buffer memory areas are read out respectively, after said first and second memory means.

8. Apparatus according to claim 6, in which said first and second memory means further include header portions respectively corresponding to upper horizontal display lines of said display means and means for reading out said header portions prior to said initial accessing address.

9. Apparatus according to claim 8, further comprising counter means for producing address accessing signals that determine said accessing addresses of said first and second memory means according to a predetermined pattern.

10. Apparatus according to claim 9, further comprising preset means for presetting said counter means according to said predetermined pattern.