CA1243110A - Method and arrangement for refreshing a frame memory in an interframe encoding system - Google Patents
Method and arrangement for refreshing a frame memory in an interframe encoding systemInfo
- Publication number
- CA1243110A CA1243110A CA000494765A CA494765A CA1243110A CA 1243110 A CA1243110 A CA 1243110A CA 000494765 A CA000494765 A CA 000494765A CA 494765 A CA494765 A CA 494765A CA 1243110 A CA1243110 A CA 1243110A
- Authority
- CA
- Canada
- Prior art keywords
- refreshing
- signal
- sub
- block
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
- H04N19/152—Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/103—Selection of coding mode or of prediction mode
- H04N19/107—Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
Abstract
ABSTRACT A method of refreshing a frame memory in an interframe encoding system which prevents refreshing data from being produced all at once is des-cribed. According to the invention, a video signal stored in the frame memory is divided into n number of blocks, which in turn comprise m number of lines each. Each of the blocks is further segmented into ? number of sub-blocks. Each of the sub-blocks is refreshed once for every one frame, repeating for ? number of times to complete refreshing one block. By repeating such a block refreshing for m number of times, the frame memory can be refreshed.
Description
124311~) METHOD AND ARRANGEMENT FOR REFRESHING A FRAME MEMORY
IN AN INTERFRAME ENCODING SYSTEM
BACKGROUND OF THE INVENTION
The present invention relates to a method and an arrangement for refreshing a frame memory in an interframe encoding system.
Since in a television system, 30 frames of video signals are transmitted in one sec~nd at 33 msec. time interval between two successive frames, it is known that there is little variation from one frame to the other.
In case of video signals of televising a conference ~hereunder referred to as TV conference signals) in particular, video signals of two successive frames : differ very little since participants very rarely exhibit motions. With such video signals, considerable compression of frequency bandwidth is effected by taking a difference between two frames and transmitting the difference from the areas of motions alone. This is known as an interframe encoding system.
In the prior art interframe encoding system, a frame of video signals is segmented into blocks, each of which has a size of m lines x n picture cells (pixels). When all the pixels in one block are, for example, static, the block is then considered as ineffective and an ineffective ~;~431~0 block signal is transmitted. On the other hand, when a block contains areas of motion, the block is considered as effective and an effective block signal is transmittedO
At the same time the difference between the pixels contained in the effective block is quantized and encoded to be transmitted to the receiving side. Details of such a block encoding system are available in the conference record of International Conference on Digital Satellite Communications, 1975, ppO 309-314, under the title of "H-l NETEC System: Interframe Encoder for NTSC Television Signal" (reference 1) by T. Ishiguro et al.
In the prior art interframe encoding system as described above, the interframe difference alone is transmitted, while at the receiving side the interframe difference is added to the content from a frame memory to reproduce the original video signal. If a code error occurs in a transmission line, the original video signal can not be reproduced precisely at the receiving side because the interframe difference transmitted differs from the interframe difference received at the receiving side. Effect of such a code error in the transmission line continues until the contents of the frame memories at the transmitting and receiving sides become identical.
It is therefore necessary to refresh the contents of the frame memories with updated data. Such a technique is generally termed as the refreshing of a frame memory.
3L243~1~
The conventional refreshing methods can roughly be classified into two:
(i) A demand refreshing method in which the contents of the frame memories of both transmitting and receiving sides are refreshed by transmitting via an additional transmission line a refreshing demand signal and by synchronizing the refreshing of the two frame memories when a code error in the transmission line is detected at the receiving side.
(ii) A periodic refreshing method in which a command instructing a refreshing of the frame memory at the receiving side is supplied periodically from the transmitting side at a given interval irrespective of code error occurrence in the transmission line.
However, since the demand refreshing method requires an additional transmission line for the refreshing demand signal from the receiving side to the transmitting side, the method can not be employed in the one-way communication system which is not provided with such an additional line.
A periodic refreshing method is described in USP 4,051,530 (reference 2), in which the difference between the pixels is taken for each pixel, requiring an enormous amount of refreshing data to finish the refreshing of all the frame memory contents. It has therefore been a common practice to limit the number of pixels per frame to be refreshed to, ~24311~) for example, those of 5 lines. However, it is still defective in that since a large amount of the refreshing data for pixels in 5 lines will be produced at one time, a necessary video signal indicative of the movements of an object can not be adequately transmitted. For example, assuming that the refreshing data consists of an 8 bit PCM data per pixel, the number of pixels per line is 455, and the number of lines to be refreshed per frame is 5 lines. Then, the refreshing data amounting as much as to 5 x 455 x 8 = 18,200 bits will occur all at once burstingly. The amount corresponds to 36~ of about 50 Kbits which is the approximate transmission capacity per frame period when a video signal is transmitted at 1.5 Mb (30 frames)/s, making it difficult to transmit sufficient motion of the object as mentioned above.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for refreshing a frame memory which prevents refreshing data from being produced all at once.
According to one aspect of the present invention, there is provided a method for refreshing a frame memory which is used in a system for efficiently encoding video signals. The video signal stored in the frame memory is divided into n number of blocks, which in turn comprise _ number of lines each. Each of the blocks is ~Z431~
further segmented into æ number of sub-blocks. Each of the sub-blocks is refreshed once fox evexy one frame, repeating for ~ number of times to complete refreshing one block. By repeating such a block refreshing for _ number of times, the frame memory can be refreshed.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description when taken with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs.lA and lB are block diagrams showing one embodiment of the present invention;
Fig. 2 is an illustration showing the construction of a video frame;
Fig. 3 is an illustration explaining assignment of lines for periodic refreshing; and Figs. 4 and 5 are circuit diagrams of the refreshing controller at the transmitting and receiving sides, respectively.
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring now to Fig. lA, a video signal supplied to an input terminal 1 is bandlimited with a low-pass filter
IN AN INTERFRAME ENCODING SYSTEM
BACKGROUND OF THE INVENTION
The present invention relates to a method and an arrangement for refreshing a frame memory in an interframe encoding system.
Since in a television system, 30 frames of video signals are transmitted in one sec~nd at 33 msec. time interval between two successive frames, it is known that there is little variation from one frame to the other.
In case of video signals of televising a conference ~hereunder referred to as TV conference signals) in particular, video signals of two successive frames : differ very little since participants very rarely exhibit motions. With such video signals, considerable compression of frequency bandwidth is effected by taking a difference between two frames and transmitting the difference from the areas of motions alone. This is known as an interframe encoding system.
In the prior art interframe encoding system, a frame of video signals is segmented into blocks, each of which has a size of m lines x n picture cells (pixels). When all the pixels in one block are, for example, static, the block is then considered as ineffective and an ineffective ~;~431~0 block signal is transmitted. On the other hand, when a block contains areas of motion, the block is considered as effective and an effective block signal is transmittedO
At the same time the difference between the pixels contained in the effective block is quantized and encoded to be transmitted to the receiving side. Details of such a block encoding system are available in the conference record of International Conference on Digital Satellite Communications, 1975, ppO 309-314, under the title of "H-l NETEC System: Interframe Encoder for NTSC Television Signal" (reference 1) by T. Ishiguro et al.
In the prior art interframe encoding system as described above, the interframe difference alone is transmitted, while at the receiving side the interframe difference is added to the content from a frame memory to reproduce the original video signal. If a code error occurs in a transmission line, the original video signal can not be reproduced precisely at the receiving side because the interframe difference transmitted differs from the interframe difference received at the receiving side. Effect of such a code error in the transmission line continues until the contents of the frame memories at the transmitting and receiving sides become identical.
It is therefore necessary to refresh the contents of the frame memories with updated data. Such a technique is generally termed as the refreshing of a frame memory.
3L243~1~
The conventional refreshing methods can roughly be classified into two:
(i) A demand refreshing method in which the contents of the frame memories of both transmitting and receiving sides are refreshed by transmitting via an additional transmission line a refreshing demand signal and by synchronizing the refreshing of the two frame memories when a code error in the transmission line is detected at the receiving side.
(ii) A periodic refreshing method in which a command instructing a refreshing of the frame memory at the receiving side is supplied periodically from the transmitting side at a given interval irrespective of code error occurrence in the transmission line.
However, since the demand refreshing method requires an additional transmission line for the refreshing demand signal from the receiving side to the transmitting side, the method can not be employed in the one-way communication system which is not provided with such an additional line.
A periodic refreshing method is described in USP 4,051,530 (reference 2), in which the difference between the pixels is taken for each pixel, requiring an enormous amount of refreshing data to finish the refreshing of all the frame memory contents. It has therefore been a common practice to limit the number of pixels per frame to be refreshed to, ~24311~) for example, those of 5 lines. However, it is still defective in that since a large amount of the refreshing data for pixels in 5 lines will be produced at one time, a necessary video signal indicative of the movements of an object can not be adequately transmitted. For example, assuming that the refreshing data consists of an 8 bit PCM data per pixel, the number of pixels per line is 455, and the number of lines to be refreshed per frame is 5 lines. Then, the refreshing data amounting as much as to 5 x 455 x 8 = 18,200 bits will occur all at once burstingly. The amount corresponds to 36~ of about 50 Kbits which is the approximate transmission capacity per frame period when a video signal is transmitted at 1.5 Mb (30 frames)/s, making it difficult to transmit sufficient motion of the object as mentioned above.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for refreshing a frame memory which prevents refreshing data from being produced all at once.
According to one aspect of the present invention, there is provided a method for refreshing a frame memory which is used in a system for efficiently encoding video signals. The video signal stored in the frame memory is divided into n number of blocks, which in turn comprise _ number of lines each. Each of the blocks is ~Z431~
further segmented into æ number of sub-blocks. Each of the sub-blocks is refreshed once fox evexy one frame, repeating for ~ number of times to complete refreshing one block. By repeating such a block refreshing for _ number of times, the frame memory can be refreshed.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description when taken with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figs.lA and lB are block diagrams showing one embodiment of the present invention;
Fig. 2 is an illustration showing the construction of a video frame;
Fig. 3 is an illustration explaining assignment of lines for periodic refreshing; and Figs. 4 and 5 are circuit diagrams of the refreshing controller at the transmitting and receiving sides, respectively.
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring now to Fig. lA, a video signal supplied to an input terminal 1 is bandlimited with a low-pass filter
2, and then is supplied to an A/D converter 3 and a ~L243~0 synchronization (sync) signal separator 4. The sync separator 4 separates from the video signal a horizontal sync signal (H sync) and a frame sync signal (F sync)O
A clock generator 5 generates various clock pulses (C) S necessary for encoding responsive to the H sync signal - and F sync signal and supplies the same to circuits which require clock pulses. The clock generator 5 also generates a multiplexer control signal (Cl) necessary for controlling a multiplexer 14. A refreshing controller 6 responsive to the H sync and F sync signals generates a refreshing control signal R, a line indication signal CRM
for designating lines to be refreshed and a switch control signal SWCONT. soth the signals R and SWCONT are described later. The A/D converter 3 samples an analog - lS video signal and converts the same into an 8 bit PCM signal per pixel. A prediction signal from a switch 12 is subtracted from the PCM signal in a subtractor 7 to produce the difference which is then quantized in a quantizer 8 in accordance with a predetermined quantization characteristic. The quantized output is added to the prediction signal from the switch 12 in an adder 9 to obtain a locally decoded signal. The locally decoded signal is stored in a frame memory 10 and a one-sample memory 11 for generating the prediction signal for the subsequent encoding. The frame memory 10 delays the `` 1243110 locally decoded signal by one frame period while the one sample memory 11 delays the same by one sample period.
The switch 12 receives the prediction signals from the frame memory 10 and the one sample memory 11 and, depending on the switch control signal SWCONT from the refreshing controller 6, it selects either the output from the one sample memory 11 when refreshing is required or the output from the frame memory 10 when refreshing is not necessary.
The prediction signal from the switch 12 is supplied to the subtractor 7 and the adder 9.
The quantizer ~ supplies a signal indicative of the quantization level to a code converter 13. When there is no difference between each pixel in one block comprising _ lines x _ pixels and each corresponding pixel of the previous period, the code converter 13 deems the block as ineffective and outputs an ineffective block signal alone and deems all the other blocks effective. For the effective block, the code converter 13 converts, in succession to an effective block signal, quantization levels of all the pixels contained in the effective block into codes V in accordance with the predetermined code assignment. A shorter code word is assigned to a quantization level which occurs at higher probability while a longer code word is assigned to a less probable quantization level. A mode controller 16 detects the ~243~10 amount of data stored in a buffer memory 15 and controls the amount of code generation in accordance with an encoding mode signal, which relates to the detected memory amount, ~ prevent overflow of the buffer memory 5.
More specifically, when the buffer occupancy increases, the mode controller 16 controls the quantizer 8 to roughly quantize signals. Alternatively, the controller 16 selects the coding mode such as a subsampling coding mode in which every other pixel instead of all the pixels is coded; and a field repeating mode in which instead of coding all the fields, every other field is coded. The multiplexer 14 multiplexes in time division the F sync signal, the encoded codes V from the code converter 13, the refreshing signal R as well as the line indication signal CRM from the refreshing controller 6, and the encoding mode signal Q from the mode controller 16, and feed them to a buffer memory 15. The buffer memory 15 stores the output from the multiplexer 14 temporarily, reads out the stored data at a given transmission rate, constructs a transmission frame and then transmits the same to a digital transmission line.
Referring to Fig. ls, at the receiving side, the transmitted video signal is supplied to a terminal 101 and is stored in a buffer memory 102. A clock generator 113 extracts a clock data from the transmitted signal and lL243~
generates on the basis of the clock data various clock pulses (C, Cl) which are required for decoding and supplies them to the necessary circuits. A demultiplexer 103 responsive to the clock pulse Cl reads out data from the buffer memory 102 and supplies the encoding mode signal Q
to a mode controller 114, the refreshing control signal R
and the line indication signal CRM to a refreshing controller 104, and the ineffective or effective block signal and the encoded codes V to a decoder 105, respectively. The mode controller 114 controls the decoding mode according to the encoding mode signal Q
so that the decoding mode corresponds with the encoding mode at the transmitting side such as the subsampling mode or field repeating mode. In response to the refreshing signal R and the line indication signal CRM, a refreshing controller 104 produces the switch control signal SWCONT to a switch 109 synchronously with the switching operation of the switch 12 at the transmitting side. The decoder 105 decodes the ineffective or effective block signal and the code V to a decoded signal. Anadder 106 obtains the original digital video signal by adding the decoded signal from the decoder 105 and the prediction signal from the switch 109 and supplies the same to a D/A converter 110, a frame memory 107 and a one sample memory 108, respectively. The frame memory 107 has one
A clock generator 5 generates various clock pulses (C) S necessary for encoding responsive to the H sync signal - and F sync signal and supplies the same to circuits which require clock pulses. The clock generator 5 also generates a multiplexer control signal (Cl) necessary for controlling a multiplexer 14. A refreshing controller 6 responsive to the H sync and F sync signals generates a refreshing control signal R, a line indication signal CRM
for designating lines to be refreshed and a switch control signal SWCONT. soth the signals R and SWCONT are described later. The A/D converter 3 samples an analog - lS video signal and converts the same into an 8 bit PCM signal per pixel. A prediction signal from a switch 12 is subtracted from the PCM signal in a subtractor 7 to produce the difference which is then quantized in a quantizer 8 in accordance with a predetermined quantization characteristic. The quantized output is added to the prediction signal from the switch 12 in an adder 9 to obtain a locally decoded signal. The locally decoded signal is stored in a frame memory 10 and a one-sample memory 11 for generating the prediction signal for the subsequent encoding. The frame memory 10 delays the `` 1243110 locally decoded signal by one frame period while the one sample memory 11 delays the same by one sample period.
The switch 12 receives the prediction signals from the frame memory 10 and the one sample memory 11 and, depending on the switch control signal SWCONT from the refreshing controller 6, it selects either the output from the one sample memory 11 when refreshing is required or the output from the frame memory 10 when refreshing is not necessary.
The prediction signal from the switch 12 is supplied to the subtractor 7 and the adder 9.
The quantizer ~ supplies a signal indicative of the quantization level to a code converter 13. When there is no difference between each pixel in one block comprising _ lines x _ pixels and each corresponding pixel of the previous period, the code converter 13 deems the block as ineffective and outputs an ineffective block signal alone and deems all the other blocks effective. For the effective block, the code converter 13 converts, in succession to an effective block signal, quantization levels of all the pixels contained in the effective block into codes V in accordance with the predetermined code assignment. A shorter code word is assigned to a quantization level which occurs at higher probability while a longer code word is assigned to a less probable quantization level. A mode controller 16 detects the ~243~10 amount of data stored in a buffer memory 15 and controls the amount of code generation in accordance with an encoding mode signal, which relates to the detected memory amount, ~ prevent overflow of the buffer memory 5.
More specifically, when the buffer occupancy increases, the mode controller 16 controls the quantizer 8 to roughly quantize signals. Alternatively, the controller 16 selects the coding mode such as a subsampling coding mode in which every other pixel instead of all the pixels is coded; and a field repeating mode in which instead of coding all the fields, every other field is coded. The multiplexer 14 multiplexes in time division the F sync signal, the encoded codes V from the code converter 13, the refreshing signal R as well as the line indication signal CRM from the refreshing controller 6, and the encoding mode signal Q from the mode controller 16, and feed them to a buffer memory 15. The buffer memory 15 stores the output from the multiplexer 14 temporarily, reads out the stored data at a given transmission rate, constructs a transmission frame and then transmits the same to a digital transmission line.
Referring to Fig. ls, at the receiving side, the transmitted video signal is supplied to a terminal 101 and is stored in a buffer memory 102. A clock generator 113 extracts a clock data from the transmitted signal and lL243~
generates on the basis of the clock data various clock pulses (C, Cl) which are required for decoding and supplies them to the necessary circuits. A demultiplexer 103 responsive to the clock pulse Cl reads out data from the buffer memory 102 and supplies the encoding mode signal Q
to a mode controller 114, the refreshing control signal R
and the line indication signal CRM to a refreshing controller 104, and the ineffective or effective block signal and the encoded codes V to a decoder 105, respectively. The mode controller 114 controls the decoding mode according to the encoding mode signal Q
so that the decoding mode corresponds with the encoding mode at the transmitting side such as the subsampling mode or field repeating mode. In response to the refreshing signal R and the line indication signal CRM, a refreshing controller 104 produces the switch control signal SWCONT to a switch 109 synchronously with the switching operation of the switch 12 at the transmitting side. The decoder 105 decodes the ineffective or effective block signal and the code V to a decoded signal. Anadder 106 obtains the original digital video signal by adding the decoded signal from the decoder 105 and the prediction signal from the switch 109 and supplies the same to a D/A converter 110, a frame memory 107 and a one sample memory 108, respectively. The frame memory 107 has one
3~
-- 10 ~
frame delay while the one sample memory lC8 has one sample delay. The switch 1.09, in response to the switch control signal SWC~NT from the refreshing controller 104, selects the prediction signal from the one sample memory 108 when the refreshing is required wh,ile selectir,g the prediction signal from the frame memory 10 when the refreshing is not required. The selected prediction signal is supplied to the adder 106. As a result, d~lring the period of the refreshing, the input of the adder 106 and that of the one sample memory 108 are added to produce the refreshing data, which is used to refresh the contentsof the frame memory 107. In this manner, influence of the code error in the transmission line can be eliminated. The D/~
converter 110 receives the original diyital video signal supplied from the adder 106 and converts the same into the original analog video signal. This analog video signal is bandlimited by a lo~-pass filter 111 and transmitted to a video signal output terminal 112.
The method for designating lines to be refreshed will now be explained in relation to the method for constructing a video frame in the multiplexer 14.
Referring no~ to Fig. 2, a video frame comprises 64 blocks, each of which consists of 8 lines. Of 64 blocks, the first block comprises a frame sync signal, a frame mode, a line mode and video data. The second through `- ~Z43~0 64th blocks comprise a line mode and video data each.
The frame sync signal is assigned with a pattern which never appears with other signals. Thus, it is possible to synchronize the video frames by detecting the pattern from the data sequence. The frame mode contains a signal showing what coding mode is applied to the whole frame, e.g. subsampling mode as mentioned above. The frame mode also contains the line indication signal CRM which designates the lines to be refreshed as mentioned above.
The line indication signal CRM is a signal indicative of the serial number of lines refreshed in the block (m lines) in question. If one block consists of 8 lines and refreshing is continuously conducted for two lines at one time, then the line indication signal CRM comprises 2 bits. The line mode has a coding mode which is applied to each block (8 lines). The line mode also includes the signal Q showing quantization characteristics supplied from the mode controller 16 and the refreshing control signal R. "O" of the signal R indicates that lines requiring refreshing exist, whereas "1" of the signal R
means that none of the _ lines (block) requires refreshing.
Fig. 3 is a chart to explain how lines are designated for refreshing. For example, when the bits CRM 1 and CRM 2 of the line indication signal CRM are "1" and "0", respectively, then the 5th and 6th lines of the 8 lines ~Z4311Q
are refreshed while the rest of the 8 lines are encoded in the coding mode designated by the line mode. As mentioned above, if two lines per each block are refreshed once for one frame, 256 frames will be required to refresh one frame. It should be noted that the structural components of the systems shown in Figs. lA and lB are disclosed in the reference 1 and 2 except for the refreshing controllers 6 and 104. The refreshing controllers 6 and 104 will therefore be described in more detail hereinafter.
Fig. 4 shows the refreshing controller 6 at the transmitting side.
Referring to Fig. 4, a counter 20 counts the number of lines in one frame by counting the number of H sync signals supplied from the sync separator 4. A counter 21, on the other hand, counts the number of F sync signals.
A first comparator 22 compares the output of the 4th through 9th bits (B4 - B9) of the counter 20 with the output of the 3rd through 8th bits (b3 - b8) of the counter 21 and produces the refreshing signal R.
For example, when the first block is refreshed, the counter output b3 - b8 keeps "000000" during the first through 4th frames, while the counter output B4 - B9 in each frame from the first through 4th frames holds "000000" during the first through 8th lines. The 12~31iO
comparator 22, therefore, produces the refreshing signal R
for 4 times for one block. It is noted that since the first and the second bits (bl - b2) of the counter 21 change from frame to ffame, the output bl - b2 is used as the line indication signal having the refreshing bits CRM 1 and CRM 2. A second comparator 23 and an AND gate 24 form the switch control signal SWCONT for controlling the switch 12 to transmit the output from the one sample memoxy 11 as refreshing data during the refreshing period.
A comparator 23 compares the counter output B2 - B3 which do not vary in the first and the 2nd lines of each block with the counter output bl - b2 indicative of the first through 4th frames and produces a signal corresponding to the lines to be refreshed in the first through 4th frames.
For example, when "00" indicating the first frame appears at the output bl - b2, "00" showing the first and 2nd lines appears at the output B2 - B3. The comparator 23 compares the output B2 - B3 and bl - b2, and produces a signal for refreshing the first and 2nd lines. The AND gate 23 responds to the output of the comparator 23 and the refreshing signal R from the comparator 22 and produces the switch control signal SWCONT. Since the signal R is outputted in correspondence with the block position which is to be refreshed once per frame, the switch control signal is so outputted as to refresh two lines once per ~Z4311~3 frame. As described above, the refreshing control signal R
and the line indication bits CRM 1 and CRM 2 are multiplexed by the multiplexer 14.
Referring now to Fig. 5 which shows the refresh controller 104 at the receiving side in detail, a counter 30 generates an H-sync signal by counting the clock pulses from the clock generator 113 and supplies the H-sync signal to a counter 31 which outputs the number of lines by counting the H-sync signal. since the output (b2 - b3) of the counter 31 changes in every two lines, a line indication signal is obtained at the receiving side by comparing the output b2 - b3 in a comparator 32 with the line indication bits CRM 1 and CRM 2 separated. An AND
gate 33 performs an AND operation in response to the refresh line indication signal and the refreshing signal R
to form the switch.control signai SWCONT at the receiving side.
Although the method for refreshing a frame memory of a simple interframe encoding system has been described in the foregoing, the method can be applied for other encoding systems which incorporate motion compensation predictive processing and the like. In the foregoing description, each block which contains plural sub-blocks to be refreshed exists only once in one frame; however, it is again possible that plural blocks containing sub-blocks exist in one frame.
243~0 As has been described above, according to the method of the present invention for an interframe encoding system, since the block of encoding is further segmented into smaller sub-blocks for periodic refreshing, refreshing data can be transmitted without being burstingly produced at one time. As a result, amount of data assigned for transmitting the movements of an object can be increased, enabling high quality encoding.
-- 10 ~
frame delay while the one sample memory lC8 has one sample delay. The switch 1.09, in response to the switch control signal SWC~NT from the refreshing controller 104, selects the prediction signal from the one sample memory 108 when the refreshing is required wh,ile selectir,g the prediction signal from the frame memory 10 when the refreshing is not required. The selected prediction signal is supplied to the adder 106. As a result, d~lring the period of the refreshing, the input of the adder 106 and that of the one sample memory 108 are added to produce the refreshing data, which is used to refresh the contentsof the frame memory 107. In this manner, influence of the code error in the transmission line can be eliminated. The D/~
converter 110 receives the original diyital video signal supplied from the adder 106 and converts the same into the original analog video signal. This analog video signal is bandlimited by a lo~-pass filter 111 and transmitted to a video signal output terminal 112.
The method for designating lines to be refreshed will now be explained in relation to the method for constructing a video frame in the multiplexer 14.
Referring no~ to Fig. 2, a video frame comprises 64 blocks, each of which consists of 8 lines. Of 64 blocks, the first block comprises a frame sync signal, a frame mode, a line mode and video data. The second through `- ~Z43~0 64th blocks comprise a line mode and video data each.
The frame sync signal is assigned with a pattern which never appears with other signals. Thus, it is possible to synchronize the video frames by detecting the pattern from the data sequence. The frame mode contains a signal showing what coding mode is applied to the whole frame, e.g. subsampling mode as mentioned above. The frame mode also contains the line indication signal CRM which designates the lines to be refreshed as mentioned above.
The line indication signal CRM is a signal indicative of the serial number of lines refreshed in the block (m lines) in question. If one block consists of 8 lines and refreshing is continuously conducted for two lines at one time, then the line indication signal CRM comprises 2 bits. The line mode has a coding mode which is applied to each block (8 lines). The line mode also includes the signal Q showing quantization characteristics supplied from the mode controller 16 and the refreshing control signal R. "O" of the signal R indicates that lines requiring refreshing exist, whereas "1" of the signal R
means that none of the _ lines (block) requires refreshing.
Fig. 3 is a chart to explain how lines are designated for refreshing. For example, when the bits CRM 1 and CRM 2 of the line indication signal CRM are "1" and "0", respectively, then the 5th and 6th lines of the 8 lines ~Z4311Q
are refreshed while the rest of the 8 lines are encoded in the coding mode designated by the line mode. As mentioned above, if two lines per each block are refreshed once for one frame, 256 frames will be required to refresh one frame. It should be noted that the structural components of the systems shown in Figs. lA and lB are disclosed in the reference 1 and 2 except for the refreshing controllers 6 and 104. The refreshing controllers 6 and 104 will therefore be described in more detail hereinafter.
Fig. 4 shows the refreshing controller 6 at the transmitting side.
Referring to Fig. 4, a counter 20 counts the number of lines in one frame by counting the number of H sync signals supplied from the sync separator 4. A counter 21, on the other hand, counts the number of F sync signals.
A first comparator 22 compares the output of the 4th through 9th bits (B4 - B9) of the counter 20 with the output of the 3rd through 8th bits (b3 - b8) of the counter 21 and produces the refreshing signal R.
For example, when the first block is refreshed, the counter output b3 - b8 keeps "000000" during the first through 4th frames, while the counter output B4 - B9 in each frame from the first through 4th frames holds "000000" during the first through 8th lines. The 12~31iO
comparator 22, therefore, produces the refreshing signal R
for 4 times for one block. It is noted that since the first and the second bits (bl - b2) of the counter 21 change from frame to ffame, the output bl - b2 is used as the line indication signal having the refreshing bits CRM 1 and CRM 2. A second comparator 23 and an AND gate 24 form the switch control signal SWCONT for controlling the switch 12 to transmit the output from the one sample memoxy 11 as refreshing data during the refreshing period.
A comparator 23 compares the counter output B2 - B3 which do not vary in the first and the 2nd lines of each block with the counter output bl - b2 indicative of the first through 4th frames and produces a signal corresponding to the lines to be refreshed in the first through 4th frames.
For example, when "00" indicating the first frame appears at the output bl - b2, "00" showing the first and 2nd lines appears at the output B2 - B3. The comparator 23 compares the output B2 - B3 and bl - b2, and produces a signal for refreshing the first and 2nd lines. The AND gate 23 responds to the output of the comparator 23 and the refreshing signal R from the comparator 22 and produces the switch control signal SWCONT. Since the signal R is outputted in correspondence with the block position which is to be refreshed once per frame, the switch control signal is so outputted as to refresh two lines once per ~Z4311~3 frame. As described above, the refreshing control signal R
and the line indication bits CRM 1 and CRM 2 are multiplexed by the multiplexer 14.
Referring now to Fig. 5 which shows the refresh controller 104 at the receiving side in detail, a counter 30 generates an H-sync signal by counting the clock pulses from the clock generator 113 and supplies the H-sync signal to a counter 31 which outputs the number of lines by counting the H-sync signal. since the output (b2 - b3) of the counter 31 changes in every two lines, a line indication signal is obtained at the receiving side by comparing the output b2 - b3 in a comparator 32 with the line indication bits CRM 1 and CRM 2 separated. An AND
gate 33 performs an AND operation in response to the refresh line indication signal and the refreshing signal R
to form the switch.control signai SWCONT at the receiving side.
Although the method for refreshing a frame memory of a simple interframe encoding system has been described in the foregoing, the method can be applied for other encoding systems which incorporate motion compensation predictive processing and the like. In the foregoing description, each block which contains plural sub-blocks to be refreshed exists only once in one frame; however, it is again possible that plural blocks containing sub-blocks exist in one frame.
243~0 As has been described above, according to the method of the present invention for an interframe encoding system, since the block of encoding is further segmented into smaller sub-blocks for periodic refreshing, refreshing data can be transmitted without being burstingly produced at one time. As a result, amount of data assigned for transmitting the movements of an object can be increased, enabling high quality encoding.
Claims (3)
1. A method for refreshing a frame memory used in an encoding system for efficiently encoding video signals comprising the steps of:
(a) dividing a video signal stored in said frame memory into n number of blocks consisting of m number of lines;
(b) dividing each of said block into ? number of sub-blocks;
(c) refreshing one of said sub-blocks once for every one frame;
(d) repeating the step of (c) for ? number of times to complete refreshing one of said blocks; and (e) repeating the step of (d) for m number of times to refresh said frame memory.
(a) dividing a video signal stored in said frame memory into n number of blocks consisting of m number of lines;
(b) dividing each of said block into ? number of sub-blocks;
(c) refreshing one of said sub-blocks once for every one frame;
(d) repeating the step of (c) for ? number of times to complete refreshing one of said blocks; and (e) repeating the step of (d) for m number of times to refresh said frame memory.
2. An arrangement for refreshing a transmission and a receiving frame memories used in a system for efficiently encoding video signals, each of said frame memories being divided into n blocks consisting of m lines, each of said block being divided into ? sub-blocks, said arrangement comprising:
first control means for generating a refreshing control signal to indicate refreshing of said transmission frame memory, a sub-block indication signal to designate a sub-block to be refreshed, and a first control signal to control refreshing of said transmission frame memory;
first refreshing means responsive to said first control signal for refreshing said sub-block designated by said sub-block indication signal with refreshing data;
transmitting means for transmitting said refreshing data, said sub-block indication signal and said refreshing control signal to a transmission line, means for separating said refreshing data, said sub-block indication signal and said refreshing control signal from the transmitted signal from said transmission line, second control means responsive to said sub-block indication signal and said refreshing signal for generating a second control signal; and second refreshing means responsive to said second control signal for refreshing said receiving frame memory with said transmitted refreshing data.
first control means for generating a refreshing control signal to indicate refreshing of said transmission frame memory, a sub-block indication signal to designate a sub-block to be refreshed, and a first control signal to control refreshing of said transmission frame memory;
first refreshing means responsive to said first control signal for refreshing said sub-block designated by said sub-block indication signal with refreshing data;
transmitting means for transmitting said refreshing data, said sub-block indication signal and said refreshing control signal to a transmission line, means for separating said refreshing data, said sub-block indication signal and said refreshing control signal from the transmitted signal from said transmission line, second control means responsive to said sub-block indication signal and said refreshing signal for generating a second control signal; and second refreshing means responsive to said second control signal for refreshing said receiving frame memory with said transmitted refreshing data.
3. An arrangement as claimed in Claim 2, wherein said first control means comprises first counter means responsive to a horizontal sync signal for counting the number of lines of said input video signal to produce a first counter output once every m lines, second counter means responsive to a frame sync signal for counting the number of said frames to produce a second counter output once every n frames, first comparator means for comparing the first and second counter outputs to produce said refreshing control signal, third counter means responsive to said horizontal sync signal for counting the number of said lines to produce a third counter output once every ?(n = ?) lines, fourth counter means responsive to said frame sync signal for producing said sub-block indication signal, second comparator means for comparing the outputs from the third and fourth counter means, and means responsive to the output from the second comparator means and said refreshing control signal for producing said first control signal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP235906/1984 | 1984-11-08 | ||
JP59235906A JPH0620303B2 (en) | 1984-11-08 | 1984-11-08 | Refresh processing method in interframe coding method |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1243110A true CA1243110A (en) | 1988-10-11 |
Family
ID=16992984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000494765A Expired CA1243110A (en) | 1984-11-08 | 1985-11-07 | Method and arrangement for refreshing a frame memory in an interframe encoding system |
Country Status (5)
Country | Link |
---|---|
US (1) | US4731664A (en) |
JP (1) | JPH0620303B2 (en) |
AU (1) | AU598184B2 (en) |
CA (1) | CA1243110A (en) |
GB (1) | GB2167267B (en) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0746862B2 (en) * | 1985-11-30 | 1995-05-17 | ソニー株式会社 | Frame dropping compression encoding and decoding method |
DE3855114D1 (en) * | 1987-05-06 | 1996-04-25 | Philips Patentverwaltung | System for the transmission of video images |
US4875095A (en) * | 1987-06-30 | 1989-10-17 | Kokusai Denshin Denwa Kabushiki Kaisha | Noise-shaping predictive coding system |
US4972261A (en) * | 1987-08-28 | 1990-11-20 | The General Electric Company, P.L.C. | Motion compensation image signal encoding system |
US4868653A (en) * | 1987-10-05 | 1989-09-19 | Intel Corporation | Adaptive digital video compression system |
AU624089B2 (en) * | 1987-10-05 | 1992-06-04 | Intel Corporation | Digital video compression system |
FR2625638B1 (en) * | 1987-12-30 | 1994-06-17 | Thomson Grand Public | SYNCHRONIZATION METHOD FOR THE TRANSMISSION, ON AN ASYNCHRONOUS CHANNEL, OF A SEQUENCE OF IMAGES ENCODED BY MEANS OF A VARIABLE LENGTH CODE, AND DEVICE FOR CARRYING OUT SAID METHOD |
US6563875B2 (en) * | 1987-12-30 | 2003-05-13 | Thomson Licensing S.A. | Adaptive method of encoding and decoding a series of pictures by transformation, and devices for implementing this method |
FR2628276B1 (en) * | 1988-03-02 | 1991-06-28 | France Etat | METHOD FOR REDUCING THROUGHPUT OF A SEQUENCE OF DATA FOR ASSISTING THE RECONSTRUCTION OF AN ELECTRONIC IMAGE FROM A SUB-SAMPLE SIGNAL |
DE3809443A1 (en) * | 1988-03-21 | 1989-10-12 | Siemens Ag | Method for correcting picture faults in the digital transmission of reduced-data video signals |
CA1330599C (en) * | 1988-06-28 | 1994-07-05 | Nec Corporation | Video signal decoding system having a frame synchronizer function |
US5327173A (en) * | 1989-06-19 | 1994-07-05 | Fujitsu Limited | Moving image coding apparatus and moving image decoding apparatus |
DE3926154A1 (en) * | 1989-06-30 | 1991-01-10 | Thomson Brandt Gmbh | SIGNAL PROCESSING SYSTEM |
JP2689632B2 (en) * | 1989-08-15 | 1997-12-10 | ソニー株式会社 | Image signal transmission device and transmission method |
US4969040A (en) * | 1989-10-26 | 1990-11-06 | Bell Communications Research, Inc. | Apparatus and method for differential sub-band coding of video signals |
JPH0714209B2 (en) * | 1989-12-20 | 1995-02-15 | 松下電器産業株式会社 | Video coding device |
US5164828A (en) * | 1990-02-26 | 1992-11-17 | Sony Corporation | Video signal transmission and method and apparatus for coding video signal used in this |
US5542008A (en) * | 1990-02-28 | 1996-07-30 | Victor Company Of Japan, Ltd. | Method of and apparatus for compressing image representing signals |
FR2664455B1 (en) * | 1990-07-06 | 1997-01-31 | Thomson Csf | METHOD AND DEVICE FOR REGULATING ADJUSTABLE THROUGHPUT IMAGE DECODER ENCODERS ADAPTED TO MAGNETOSCOPES. |
US5138447A (en) * | 1991-02-11 | 1992-08-11 | General Instrument Corporation | Method and apparatus for communicating compressed digital video signals using multiple processors |
JP3070110B2 (en) * | 1991-02-27 | 2000-07-24 | 日本電気株式会社 | Video signal transmission system |
JPH05122683A (en) * | 1991-10-30 | 1993-05-18 | Mitsubishi Electric Corp | Picture storage transfer device |
KR100213018B1 (en) * | 1994-07-30 | 1999-08-02 | 윤종용 | Apparatus for encoding moving picture |
US6025888A (en) * | 1997-11-03 | 2000-02-15 | Lucent Technologies Inc. | Method and apparatus for improved error recovery in video transmission over wireless channels |
US6873368B1 (en) * | 1997-12-23 | 2005-03-29 | Thomson Licensing Sa. | Low noise encoding and decoding method |
US6590441B2 (en) * | 2001-06-01 | 2003-07-08 | Qualcomm Incorporated | System and method for tuning a VLSI circuit |
GB2492163B (en) | 2011-06-24 | 2018-05-02 | Skype | Video coding |
GB2492330B (en) | 2011-06-24 | 2017-10-18 | Skype | Rate-Distortion Optimization with Encoding Mode Selection |
GB2492329B (en) | 2011-06-24 | 2018-02-28 | Skype | Video coding |
GB2493777A (en) | 2011-08-19 | 2013-02-20 | Skype | Image encoding mode selection based on error propagation distortion map |
GB2495468B (en) | 2011-09-02 | 2017-12-13 | Skype | Video coding |
GB2495467B (en) | 2011-09-02 | 2017-12-13 | Skype | Video coding |
GB2495469B (en) | 2011-09-02 | 2017-12-13 | Skype | Video coding |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1042097A (en) * | 1974-10-21 | 1978-11-07 | Nippon Telegraph And Telephone Public Corporation | Interframe coding system with automatic control of magnitude of interframe difference signal |
GB1568379A (en) * | 1976-02-19 | 1980-05-29 | Micro Consultants Ltd | Video store |
US4125873A (en) * | 1977-06-29 | 1978-11-14 | International Business Machines Corporation | Display compressed image refresh system |
US4183096A (en) * | 1978-05-25 | 1980-01-08 | Bell Telephone Laboratories, Incorporated | Self checking dynamic memory system |
JPS55117387A (en) * | 1979-03-02 | 1980-09-09 | Fujitsu Ltd | Connection switch control system for inter-frame coding device |
US4357686A (en) * | 1980-09-24 | 1982-11-02 | Sperry Corporation | Hidden memory refresh |
DE3376613D1 (en) * | 1982-11-30 | 1988-06-16 | British Telecomm | Television signal transmission |
US4654484A (en) * | 1983-07-21 | 1987-03-31 | Interand Corporation | Video compression/expansion system |
CA1223333A (en) * | 1983-07-29 | 1987-06-23 | Yoshiyuki Ota | Video signal processing apparatus |
-
1984
- 1984-11-08 JP JP59235906A patent/JPH0620303B2/en not_active Expired - Lifetime
-
1985
- 1985-11-04 US US06/794,667 patent/US4731664A/en not_active Expired - Lifetime
- 1985-11-05 GB GB08527250A patent/GB2167267B/en not_active Expired
- 1985-11-07 CA CA000494765A patent/CA1243110A/en not_active Expired
- 1985-11-07 AU AU49439/85A patent/AU598184B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
GB8527250D0 (en) | 1985-12-11 |
JPH0620303B2 (en) | 1994-03-16 |
GB2167267B (en) | 1988-05-25 |
AU4943985A (en) | 1986-05-15 |
US4731664A (en) | 1988-03-15 |
AU598184B2 (en) | 1990-06-21 |
JPS61114675A (en) | 1986-06-02 |
GB2167267A (en) | 1986-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1243110A (en) | Method and arrangement for refreshing a frame memory in an interframe encoding system | |
US4651206A (en) | Inter-frame coding apparatus for video signal | |
US4833535A (en) | Image transmission apparatus | |
US5684527A (en) | Adaptively controlled multipoint videoconferencing system | |
CA2077521C (en) | Method and arrangement of adaptively multiplexing data of a plurality ofvideo channels | |
EP0967807B1 (en) | Apparatus and method for motion vector encoding | |
KR100225542B1 (en) | Method and apparatus for image signal encoding | |
US4609941A (en) | Television signal standards conversion | |
US4133006A (en) | Predictive encoder or decoder with selection of one of two or more prediction signals according to prediction error signal amplitudes | |
US4733298A (en) | Method of coding a video signal whereby pictures can be reproduced with a high quality and a device therefor | |
CA1226664A (en) | Video data transmission | |
GB1525264A (en) | Frame-to-frame coding system | |
EP0180345A2 (en) | Method and apparatus for picture signal encoding and decoding | |
EP0105604B1 (en) | A dual mode encoding/decoding technique for use in a digital transmission system | |
GB2137045A (en) | Colour television transmission or storage system | |
Murakami et al. | 15/30 Mbit/s universal digital TV codec using a median adaptive predictive coding method | |
US5191446A (en) | Image data transmission system | |
JPS6359313B2 (en) | ||
KR100312083B1 (en) | A device for transmitting television images, a device for receiving the images and a storage medium | |
Mukawa et al. | An interframe coding system for video teleconferencing signal transmission at a 1.5 Mbit/s rate | |
US3749829A (en) | Slow scan procedure for high resolution graphics mode video scene compatible with conditional replenishment type of bandwidth reduction | |
US5710859A (en) | Image data recorder wherein compressed data recording is stopped/started at a different time than commanded | |
JP2547730B2 (en) | Data transmission system | |
JPH07274179A (en) | Dynamic image encoder | |
CA1243771A (en) | Method of coding a video signal whereby pictures can be reproduced with a high quality and a device therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry | ||
MKEX | Expiry |
Effective date: 20051107 |