CA1240079A - Graphic display scan line windowing capability - Google Patents

Graphic display scan line windowing capability

Info

Publication number
CA1240079A
CA1240079A CA000490800A CA490800A CA1240079A CA 1240079 A CA1240079 A CA 1240079A CA 000490800 A CA000490800 A CA 000490800A CA 490800 A CA490800 A CA 490800A CA 1240079 A CA1240079 A CA 1240079A
Authority
CA
Canada
Prior art keywords
scan line
bit
display
map memory
bit map
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000490800A
Other languages
French (fr)
Inventor
Kenneth E. Bruce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1240079A publication Critical patent/CA1240079A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14Display of multiple viewports
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/40Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory

Abstract

ABSTRACT

The invention pertains to a computer display system for displaying text and graphics on a scan line basis wherein a scan line windowing apparatus for selectively blanking the graphics display is provided.
A bit map memory, in addition to storing information to be displayed on a CRT, further stores a bit for each scan line which is utilized to control the enabling or disabling of a portion of the information in the bit map memory which is to be displayed on the CRT.

Description

Thi~ invention rela es ~nerally to a graphic~ dlsplay c~pabllity in a data proc~s~ing ~y~t~m, and more p~rticularly 5 to a hardware ap~ tuR and me hod ~r psrmittin~ the ~elective blankillq o~ the gra~bic3 portioil of the di~play on a scan line ba~ls witbout a~fectlng th~ graphic~ di~play mem~ry.

Th~ graphic~ option of a co~pute~ tem p~rmit~3 the 10 ay~tem to di splay po~n~-addr~s~ble gr~lc~. This option ~1;
aimed at the busines~ graphic~ ~ark~tplace wh~re ~he ability to ~a~ily generate ~nd modiy p~e chart~9 line cha~t~ and 80 orth are the prime objectiYe. Irl many oP the~e ~y~t~m~
graphic~ and alph~nwneric text ara di~play~d vi~ually. ~hl~
15 allow~ the relation~hip between many variable~ of tbe busln~s~
to b~ pr~sent~d in pie chart ox bar graph form. ~raphic~ can be further utili~ed to display and manipulate mechanical or other electronic type d~ign~.
In a ~y~tem where text and qraphic~ must sh~re ~:he sam~
20 viewing screen area~ it i~ difficult to read th~ t~xt when both are present. Wh~ needed i~ a ~y~te~n which allows blankin~ of a port~on of the graphics psrtion ~hat i~
di~played in ord~r to hlghligh~ the displ~y of the alphanumeric c~araG~er~ ThQ P~10r art 801V~d thi~ PrOb1em bY
25 co~cerl'crat~ng on the contr41 of tl~ di~play addre~s ~o provide ~uch window capabiligie~. Th~ re~auired axce~sl~re hardware ~o corlt~ol the count~rs ar~d multiplexing, and ~ubsequen~ly the addr~s~ing of each pl~el. ~ccordingly, addition~l co~t~ in th~ form o ha~dw~re wa~ added to :'ch~ comput~ - sy~tem, and 3Q ~or~ import~n ly~ it i~creased the proces~ing time the~eby ~ducing th~ oveEall ~y8~e~ throughputO

It i~ a prim~ry ob~ect o the lnv~ntion to h~e an improved combined gr~l?hic~ ~nd alphanu~eric di~play ~y~tem., . . .
'~.

~2~7~

~2--It i a f ur~her obj ect of the invention to have an improved graphic~ display sy~tem having window capabilitie~.
It is anot}ler obj ect o~ the invention to provide an improved graphics 3ystem incorpor~ting lmprov¢d apparatu~ for 5 s~lectlvely blanking of the graphies porl:ion o~ th~ di~play havlng comb:Lned graphle and alphanumeric in~ormation.
Yet anothe~ obj ec~ of the inventior~ i~ to providl~ a combined alphanum~ric graphic~ di~play sy~t~m which perluit~
the blank~ng of the ~raphlc~ port~orl of th~ di~play 10 ~lectiv~ly on a scan lin~ ba~ia w~thout affecting the graphics display memory.

The in~tant inYention provid~s for a di~play appar2,tu~
wherein alphanumeric data or graphic~ may b2 di~played on a 15 fluorescent screen, similar to a TV monitor,. ~ ~n a TV
~creen, an electron beam i8 caufied to 3carl the face 4~E the tube on a line-by-line ba~i6. Each scan linQ of th~ di~played da~a con~ain~ 720 pixels (bi~cs ) . These bits are read f roDc a bit map memory and stored in a regi8ter and 'chen ~3h~f ted 20 durlslg th~ di~play enabl~ ~ignal~, whic~ i~ 720 bit ti~ in dur~tioJI. The bi'i: map memory ~tores pixel~ in bit zlddres~blo locations. Arl image of the di~pl~y i~ stored in, th~ bi~ p memory ~ince each loeatio~ represent~ a poinl: o~ th~ di~ y.
The bit map ~emory i~ co~pri~ed o~ 300 ~can lin~ h ~c~n 25 line haYing 7~0 pixels compri~ing the usable portlon o~ th~
memoE:y and an additional 3û4 pix~18 compri~ing the non-di~playable portion of memoryD (The non-displa~lrabl por ion o~ memory i~ reserv~d for futur~ U~O) ~ch di~playable location in the bit map repre~ent~ ~ . pl~al to ~e 30 di~played on the moni~or, The addre~ng archi'c@c~u~
up to ~ddr~s each scan line on ~ modular 1024 p~xel count basi3, Oll~ pi~el per addres~7 i.e., ~c~n lin~ 0 includes addse~ pixel~ 0 through 1023 t scan line 1 includo~ ~ddre3s pixels 1024 through 1247, etc. The instant invention utilizes the 721st pixel to control the ne~t scan line. Accordingly, the 721st bit is loaded to control the display of the ne~t scan line of the bit map. If the 721st bit is loaded to a ONE, the followiny scan line data will be blanked and no data will be displayed. The 721st bit of scan line 300 will control the first scan line following the vertical retrace. This allows windows in the graphic~ display to allow text to be "ORed"
without overlaying the graphics data~
In accordance with the present invention, there is provided in a computer display system having a text and graphics display capability for displaying text and graphics on a scan line basis, a scan line windowing apparatus for select-ively blanking of the graphics display comprising:
(a) a bit map memory for storing electronic signals representative of information to be displayed on said display ~b) controller means responsive to said bit map mem-ory for controlling the display of the informa-tion in said bit map memory, on said display;
and (c) blanXing mean~ responsive to enable bits qtored in said bit map memory for either enabling the display of a portion of the inormation in said bit map memory, or blanking a portion of the information stored in bit map memory and prevent-ing information from appearing on the display.

BRIEF DESCRIPTI_N_OF_THE DRAWINGS
The novel features which are characteristic of the invention are ~et forth with particularity in the appended ; ~ .
2~
"- -3a- 72434-19 claims. The invention itself, however, both as to organization and operation! may best be understood by reference to the following description in conjunction with the drawinys in which:
Figure 1 is a logic block diagram of the invention.
Figure 2 is a schematic representation of the bit map memory utili~ed in the invention.
Figure 3 is a block diagram of a typical data proces-sing system which provides the environment for the invention.

Figure 4 is a bLock diagram of the graphic aubsystem including the invention .
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring to Figure 1 there is shown a logic block diagram of the invention. The invention provides for the blanking of the ne~t horizontal data scan line. The blanking operation logic is associated with the normal and inverse modes of operation~ Under the normal mode of operation the graphics is light and the background is dark; whereas in thP inverse mode of operation the graphics is dark and the background is light. When operating in a blanking mode, portions of the graphics are blanked out. Accordingly, the :~2~
--4~

video out signal must b~ modif ied to be suppr~sed wh~n the 721s~ bit of th~ bit map memory i~ loaded to 0~3E.
In the normal operation, the ~ignal vid~o out VIDOUT~00 i~ applied to one leg of laAND g~te 102 from ~hifter 28.
S Shifter 28 i8 a commerc~ ally available shi~t register.
A~uming al~o that we are in a graphic~ mode, th~ GRAFIC~00 ~ignal applied to another input of NAND galt~ lû2 i$ high.
Since al~o ~his is a normal operatio3l rather than a blanking operation~ ~ignal ~LANRL-00 i~ high al~o~ Acco~dislgly, the 10 output of the vldeo ena~le ~ign~? VID13NB-00 i~ ~n inverted f orm of the i~put ~ignal VIDO~Tt 00 ~ Si~nal irIDBNB-O
appli~d to olle i~put termis~al of n~gative A~D gate 103 ar~d i~
al~o applied to one input terminal of ~ANl) gate 104~ ce ~hi~ iB not an inver~e mode, ~ignal INr~ 00 i~ lo~ and i5 15 applied to another input terminal of NAND gate 104 and i~ also applied to a secorld input ter~ninal of n~gativ~ lD gate 1031.
Accordingly, when the signal~ of all the input t~r~inals of NAND gate 102 are high, the output ~ignal VID~NB~00 ~ lo~ and will f ollow in~ter~ely the VIDOUT~00 ~ignal as it goe~ high and 20 low. As we have seen~ the inver~ ignal I~ Q0 is low9 ~ince ~hi~ is not th~ inverse ~ode9 and accordingly as th~
VID~NB-00 signal varie~ up and d~wn9 the output sign~l on negati~re A~aD gate 103- ~IDREG-0û will al80 ~rary up and dowz~, follow~ng the ~TIDE~ 00 s~gnal. Accordinglys the VIDR~G-0û
25 output ~ignal of negativ~ AND gate 103 follows inversely the input ~ignal VIDOUT~00 or~ D gate 102. Similarl~; the ~ideo inver~e ~ignal VIDINV;~00 at the output ~cerminal of NAND gat~
10~, will inver~ly ~o:Llow th~ VIDOUT~û0 signal Oll on~ input termin~l of NAI~D. ga~ 102. Th~ signal~ applied to n~gativ~
30 O~ gate 105 cau~e ~h~ ~rIr~EoN~oo signal to fluc~ua'ce up an~
down. ~h~ V~D~ON~0û s~gnal ~ ~h~n applied to one inpu~
~erminal o~ ~ND gate 108. In order ~or the ~rIDEoN~o~ ~gnal to pa~ 'chrough ~N~ gat~ 108, the di~play enable ~i~nal DSPEN8~00 must also be high. Wh~n both input signals to AND
yate 108 are high, ~hen the output signal ENBVID~00 follows th~ video on signal VIDEON~00~ The ENBVID~00 signal is then appliea to the CD terminal o~ flip-~lop 110. A bit clo~k 5 signa} DOTCLR~lD is applied to th~ clock termin l CL~ of ~lip-~lop 110 and causes flip-flop 110 to set when the ENBVID~00 signal i8 high and reset~ wh~n the ENBVID~00 signal is low. Therefo~e the flo~ also follows the VIDEON~00 signal clocked to the bit clock signal DOTCL~lD. The outp~t signal YIDEOG-00 on ~lip-~lop 110 is ~ent through a driver lll to the display controller 106 and that signal i~ high when the bi ~
are to be aisplayed on the screen monitor and low when the bit~ are not to be di~playad on the screen ~onitor.
In the inverse modQ, on the other hand, there would be lS no dot on the monitor if in thQ nor~al mode there would be a dot. Therefore the signal which comes out from shif ter 28 VXDOUT~00 has to be inverted when th~ invention is operated in th~ inverse moae. This i5 done by adding the inverse signal INVERS+00 appli~d to NAND gat~ 104 high so that the output of 2G NAND gate 104 signal VIDINV-00 fol}ows the VIDOUT+00 sig~al, Accordingly, the video on sisnal VID~ON~OO 9 which is the output of n~gative OR ga~e 105 sees the negative or inverse of the VIDINV-OO signal and is ap~lied to AND g~te 108 causing ~lip-klo~ 110 to ~ollow ~hat signalO
~5 In ~he blank mode~the object is to aisable the VIDOUT~OO
sig~al from conveying any ~nformation on the scrQ~n during th@
next horizo~tal ~weep o~ the be~m acro~s the.~ace of the C~T
tube. ~his i~ done,by disabling the output of N~D gate 103 80 t~at it stay~ high and aoes ~ot ollo~ the VIDOUT signal.
30 This i~ done by utilizing ~he 721st bit which appears as the B~UPPO~QO signal. DS~E~8-00 is the display enable ~ignal DSPENA~OO received ~rom the display controller 106 delayed by 8 dot clock si~nals in r~gister 1200 Thi delay is neede~ to 51~02068 align graphics data with text data also displayed on the CRT.
A~ the ena of DSPEN8-00 time the ~ext bit from the bit map memory 10 is tran6ferred to Buffer B 24 v a ~uffer A 22~
Signal BBUFFO~00 which representR pixel 721 of this scan line s is ~hen also appliea to the CD terminal of ~lip-flop 101.
Flip-rlop 101 sets when the di~play enable signal DSPEN8-00 goe~ hig~. The DSPEN8-00 signal go~ high at the end of each horizontal ~can line.
Wh~n fli~-flop 101 set~ the blanking signal BLAN~L-00 will go low forcing the output o~ NAND gate 102 to go hiyh ana stay hish during th~ next horizontal scan line, thus provi~ing a blank line in the normal mode and a 601id l~n~ in the inver~e mode.
Referring now to Figur~ 2, there 18 ~hown in di~gr~Nnatic form a bit map memory. The memory is divided in~o two areas, the dis~layed portion of the memory a~d the unusable memory. The memor~ i9 f urther com~rised of 300 scan : lineR with each ~can line comprising 720 pixels which can be displayea ana 304 pixels that cannot be displayed. The 721st pixel of each scan line is utilized to aontrol the diæplay of the next scan line. If the 721st bit is loaded to a ONE, the following ~can lin~ data will be blanked and no ~ata will be ais~layed. The 721~t bit of scan line 300 will control the first scan lin~ following the vertical retrace.
Referring now to ~igure 3, there is shown a data proces~ing ~y~tem which includes a graphics capabllity in i~
di~play ~ubsystem~
An app~ications proce~or 3 controlled by firmware : ~tored i~ a read only memory (ROM) 1 executes applica~ions program~. The application~ proces~or 3 is coupl~d ~o a main memory 15 via bus conn¢ct 5 and a bus 39.

An input/output (I/O) microproces~or 9 controlled by fi~mware stored in a ROM 7 execute~ inpul:/ou'cput in~3truction~
required for the ~xecution of application~ prog~am~ by the appllcation~ proc~s~or 3O
Typically main memory 15 store~ the sperating sy~m, the applicatiorls program and th~ infsrmatiorl upon which the applications pro~ram operate~. ~en acce~ to a devic,e i~
re~uired, the applications proces~or 3 s~ore~ inputJoul:put instructions in an I/O r~ndom ac ess meD~ory (RA~ I/O
10 microprocessor 9 is re~ponsive to tha I/O ln~tructloA~ stored in I/O RAM 11 to control the tran~fer of inform~tivn b~t~een main memory 15 and a periph~ral device o~ misc~llaneous device~ and controller 13. Typical de~icQs tnot ~hown~ ar~
floppy àisk~, printer~, keyboards, hard di~ksv and 15 communication terminalsc A display subsy3tem 37 may be op~rative in conj unction with a keyboard to di~p:lay information tored in mai31 memory 15 and I/O RAM 1~ on a display 35, typically a cathode ray tube display. Di~play subsystem 37 includes a disp~ay 20 conl:roller 27 ~hich int~rfaces with I/O EaAM 11 and main ~e~ory lS unde~ the control o~ I/O ~icroproc~or 9 iEor thg tran~f er o~ information ~or di~play . The in~ormatlon for display is ~'cor~d- in a data RAM 31. A character generator 33 receive~
the informatio~ from data RAM 31 and conver~s it ~o a seri~s 25 of dots which i8 ti~ned to the raster ~can of th~ di~play 35 ~co shapa l:he alphab~t~c or nu~eric~ (text~ characters. An attribute R~M 29 typically provides for the underlining, blanking, and inv~rting of &elec~d charac~rs.
Th~ bu~ colmect 5, I/O microproc~sor 9, I/O RAM 1}~
3Q mi~cell~neou~ Vi~ 8 a~ld con'croller 13 and display controller 27 are all coupl@d in coDlmorl to a bus 41 which includes an 8 bi~ d~ta bus.

A microprocessor 17, typically an Intel 8086 microproce~sor, i4 coupled to main ~emory 15 and bus connect 5 by a ~u~ 3~ whlch include~ a 16 bit data bus. Microprocessor 17 run~ under ~SDOS ~operating system) which i~ ~tored in main memory 15. ~icroproces~or 17 i8 de~crib~d in the 80B6 Family U~er~ M~nu~l, October 197~ and publi~hed by Im~el Sorporation, 3065 ~ower~ Avenue~ Sant~ Clara, Califo~ni~ g5051.
~ graphics option 25 i~ coupled to microproces~or 17 by a bu~ 21 which include~ an 8 blt da~a bu~. ~u~s 21, 39 and 41 alco include the nece~ary address and control ~lg~als, The graphic option i8 aimed a the busin~s graphics marke~place wherein the ability to generat~ ~nd modify pie ch~rtsr line chart~ and th~ like in conjunctlon with ~he applica~ion~ progra~ being executed by application~ proc2~0r i8 a requirement. The graphics option 25 control~ ~he display of point addre3~able graphics on di~play 35. This is accomplished by applicstioQs processor 3 calling on the graphlcs option 25 by sending command information to main memory 153 Microproce or 17 is respo~ e ~o the com~and information to control graphics option 25 to send graphic~
inform~tion~to the characteE generator 33.
Figure 4 ~how~ a block diagram of the gra~hics option 2S. ~ bit map memory 10 store~ an image of ~he di~play screen of display 35. ~it m~p m~moey 10 ~tore 720 pixel~ ~bi~
25 portion~) ~o~ each of 300 ~carl lines for a total of 216,300 piYelsD Blt map memory 10 i~ addre~ed via an address multlplexer 4 which ~elects 16 add~ess signals, 8 a~ a tlme, f rom graphic~ int~r~ace 23 r or 8 ~ignals f rom a row add~ess s~lec~ S) count 6 and 8 3ignal~ f ro~ a colu~n addres~ count :~ 30 select ~CAS) count 8. . it map ~nemory 10 i~ ~ade up of 8 64~ X
1 dys~mic RA~ torir~g 216,000 pixel~ for di~play on di~play 35~ o ~tored ~re a number of control b~ts.

,, I ' .

The olatput si~nals of bit map memory lO i~ double bu~fered in a bu:Ef~r P. 22 and a buffer B 22, s~rializedl in a ~hift~ 28 and the stream of bit~ aI?plied to a riaeo control 30. A vid~o out regi~ter 32 output signal is applied to 5 character ~enerator 33, Figure l ~ for display on di~play 35 ~, ~ cycl~ control 20 control~ th~ timlng relation~3hip betwe~n the addre~iny of bit map m~mo~y lO, ~y app}ying t~ming signals 'co RAS count 6 i CAS count 8 and Mt~X 4 ~ ~nd the ~ubRequ~nt output ignal~ ~tored in buff~r A 22, and th@n 10 tran~ferred ~rom buffer A 22 to bu~er B 24.

Claims (4)

What is claimed is :
1. In a computer display system having a text and graphics display capability for displaying text and graphics on a scan line basis, a scan line windowing apparatus for selectively blanking of the graphics display comprising:
(a) a bit map memory for storing electronic signals representative of information to be displayed on said display;
(b) controller means responsive to said bit map memory for controlling the display of the information in said bit map memory, on said display; and (c) blanking means responsive to enable bits stored in said bit map memory for either enabling the display of a portion of the information in said bit map memory, or blanking a portion of the information stored in bit map memory and preventing information from appearing on the display.
2. The computer display system as recited in Claim 1 wherein a display bit is stored in said bit map memory for each scan line of display, said display bit being the next bit following the last displayable bit on the displayable portion of any scan line.
3. The computer display system as recited in Claim 1 wherein 720 bits are stored for each scan line on the displayable portion of said bit map memory, and 304 bits are stored for each scan line in the non-displayable portion of said bit map memory, and said enable bit is the 721st bit of each scan line.
4. The computer display system as recited in Claim 3 wherein the scan line data of a scan line following an enable bit at the end of any scan line, will be blanked when the enable bit is set to ONE.
CA000490800A 1984-09-17 1985-09-16 Graphic display scan line windowing capability Expired CA1240079A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US650,940 1984-09-17
US06/650,940 US4642626A (en) 1984-09-17 1984-09-17 Graphic display scan line blanking capability

Publications (1)

Publication Number Publication Date
CA1240079A true CA1240079A (en) 1988-08-02

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Country Status (6)

Country Link
US (1) US4642626A (en)
EP (1) EP0175341A3 (en)
KR (1) KR860002752A (en)
AU (1) AU584119B2 (en)
CA (1) CA1240079A (en)
MX (1) MX158238A (en)

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Publication number Priority date Publication date Assignee Title
US4724431A (en) * 1984-09-17 1988-02-09 Honeywell Information Systems Inc. Computer display system for producing color text and graphics
JPS6273385A (en) * 1985-09-27 1987-04-04 Toshiba Corp Boundary detecting object area indicating circuit
US4775859A (en) * 1985-10-18 1988-10-04 Hilliard-Lyons Patent Management, Inc. Programmable interlace with skip and contrast enhancement in long persistence display systems
US5043923A (en) * 1988-10-07 1991-08-27 Sun Microsystems, Inc. Apparatus for rapidly switching between frames to be presented on a computer output display
CA1316271C (en) * 1988-10-07 1993-04-13 William Joy Apparatus for rapidly clearing the output display of a computer system
US4965670A (en) * 1989-08-15 1990-10-23 Research, Incorporated Adjustable overlay display controller
US5150107A (en) * 1989-08-22 1992-09-22 Zilog, Inc. System for controlling the display of images in a region of a screen
US5229852A (en) * 1989-12-05 1993-07-20 Rasterops Corporation Real time video converter providing special effects
US5327243A (en) * 1989-12-05 1994-07-05 Rasterops Corporation Real time video converter
GB9027678D0 (en) * 1990-12-20 1991-02-13 Ncr Co Videographics display system

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Publication number Priority date Publication date Assignee Title
JPS5399826A (en) * 1977-02-14 1978-08-31 Hitachi Ltd Controller for data display
GB2030827B (en) * 1978-10-02 1982-06-16 Ibm Video display terminal with partitioned screen
US4520356A (en) * 1980-06-16 1985-05-28 Honeywell Information Systems Inc. Display video generation system for modifying the display of character information as a function of video attributes
GB2092346B (en) * 1980-07-25 1984-05-10 Mitsubishi Electric Corp Display apparatus
US4470042A (en) * 1981-03-06 1984-09-04 Allen-Bradley Company System for displaying graphic and alphanumeric data
US4542376A (en) * 1983-11-03 1985-09-17 Burroughs Corporation System for electronically displaying portions of several different images on a CRT screen through respective prioritized viewports

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KR860002752A (en) 1986-04-28
EP0175341A3 (en) 1987-05-27
AU4752285A (en) 1986-03-27
US4642626A (en) 1987-02-10
EP0175341A2 (en) 1986-03-26
AU584119B2 (en) 1989-05-18
MX158238A (en) 1989-01-16

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