CA1235227A - High speed program store with bootstrap - Google Patents
High speed program store with bootstrapInfo
- Publication number
- CA1235227A CA1235227A CA000481285A CA481285A CA1235227A CA 1235227 A CA1235227 A CA 1235227A CA 000481285 A CA000481285 A CA 000481285A CA 481285 A CA481285 A CA 481285A CA 1235227 A CA1235227 A CA 1235227A
- Authority
- CA
- Canada
- Prior art keywords
- program
- signals
- program instructions
- memory
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
Abstract
HIGH SPEED PROGRAM STORE WITH BOOTSTRAP
ABSTRACT OF THE DISCLOSURE
A microprocessor-based system is provided with a non-volatile store (such as a PROM) which stores a bootstrap program, a non-volatile store (such as an EPROM) which stores one or more program overlays, and a programmable volatile store (such as a RAM) which can be written into and read from.
When the system is powered up, the microprocessor executes the bootstrap program out of the PROM. The bootstrap program includes instructions which copy the program instructions stored in the EPROM into the RAM. The microprocessor then executes the program instructions out of the RAM. Program instructions may be stored in the EPROM in a plurality of overlays, and individual overlays selected by either the bootstrap program or instructions contained in another overlay may be selectively loaded into the RAM for execution. The EPROM is addressed by a programmable counter which appears to the microprocessor as an input/output device to be written into.
ABSTRACT OF THE DISCLOSURE
A microprocessor-based system is provided with a non-volatile store (such as a PROM) which stores a bootstrap program, a non-volatile store (such as an EPROM) which stores one or more program overlays, and a programmable volatile store (such as a RAM) which can be written into and read from.
When the system is powered up, the microprocessor executes the bootstrap program out of the PROM. The bootstrap program includes instructions which copy the program instructions stored in the EPROM into the RAM. The microprocessor then executes the program instructions out of the RAM. Program instructions may be stored in the EPROM in a plurality of overlays, and individual overlays selected by either the bootstrap program or instructions contained in another overlay may be selectively loaded into the RAM for execution. The EPROM is addressed by a programmable counter which appears to the microprocessor as an input/output device to be written into.
Description
1235~2 ~
HIGH SPEED PROGRAM STORE WITH BOOTSTRAP
FIELD OF THE INVENTION
The invention is related to apparatus and method for the performance of a plurality of stored predetermined program tasks. More particularly, the invention is related to the storage of program instructions and data for execution by a general purpose digital computing device (such as a microprocessor~ which requires initialization.
BACKGROUND OF THE INVENTION
Microprocessor-based systems presently are used in a wide variety of applications to provide computation and other signal processing functions under so-called "software" control. As is well known, memory structures are typically provided in such systems to store program instructions and data. It is usually necessary to provide both non-volatile memory ~i.e., memory that will retain its contents even when the power supply to the system is turned off) as well as read/write random access memory (RAM) which may be used for storing temporary data and user-developed program instructions. Due to speed and flexibility considerations, semiconductor memory devices are typically now used to provide both non-volatile and read/writ.e storage.
Of course, there are many different types of semiconductor memory devices presently commercially available. Perhaps the most commonly-used semiconductor memory device is the semiconductor read/write random access memory (RAM). RAMs are available in both bipolar and MOS
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technologies. In general, RAMs have the advantages of high density (i.e., high storage capability per unit volume~, high speed and low cost. For these reasons, RAMs are typically the memory device of choice for microprocessor-based systems. RAMs can be obtained which have a memory access time which is shorter than the switching speeds of available - microprocessors, so that the RAM does not limit the speed at which the microprocessor can execute program instructions.
RAMs, however, are volatile memory devices, and therefore lose their contents if their power supply is interrupted. Therefore, processing systems which may be turned on and off or which may have to be reset often are also typically provided with a non-volatile storage device for storing information which will be reused. Information which must be stored in a non-volatile storage device includes, for example, program instructions which must be executed each time the system is powered ~p. It is typically desirable to store all program instructions in non-volatile memory (unless those program instructions must be capable of being altered by the user during the course of operation of the system).
One type of non-volatile storage which is often used is a semiconductor read only memory (ROM). In general, semiconductor ROMs are available in three types: mask-programmed ROMs, electrically programmable read only memories ~PROM), and erasable programmable read only memories (EPROM). Informa-tion is stored in mask-programmed ROMs at the time of manufacture, and may not be changed by the user. Mask-programmed ROMs are relatively inexpensive if made in high volume, but are ~23~2~
ordinarily not used for small-volume applications because of the expense of preparing and specifying a mask. In addition, mask-programmed ROMs are ordinarily not used in a system unless the system 5 software has been thoroughly tested, since their contents may not be changed.
PROMs, on the other hand, may be electrically programmed by a user. PROMs store no information when purchased. The user "programs"
10 data into the PROM by applying electrical signals to it. Once the programming process is complete, the data which is stored in the PROM is permanent and cannot be altered. PROMs find wide use in low-volume applications (where mask-programmed ROMs 15 would be uneconomical), as well as in applications where the stored information might be subject to change (for instance, where the system is still under development). PROMs are non-volatile, but if their contents are to be changed, may must be replaced.
Erasable programmable read only memories (EPROMs) are similar to PROMs except that they may be erased and reused. Typically, EPROMs are provided with a quartz lid which passes ultraviolet radiation. When the EPROM is exposed to ultraviolet radiation, its contents are erased. The EPROM may then be electrically programmed in a manner similar to that used to program a PROM. EPROMs are very useful for storing information that might be subject to change. However, EPROMs are expensive compared to RAMs, mask-programmable ROMs and PROMs.
Moreover, EPROMs generally have greater access time than R~Ms' in the past, the speed of a microprocessor executing instructions stored in an EPROM has been limited by the relatively slow access , ~23~2Z~
speed of the EPROM. As technology has advanced, faster EPROMs have been developed. However, EPROMs are still slow relative to RAMs, and are far more expensive.
BRIEF DESCRIPTION OF_THE DRAWINGS
FIGURE 1 is a block schematic diagram of a prior art microprocessor signal processing system;
FIGURE 2 is a schematic block diagram of another prior art microprocessor-based signal processing system;
FIGURE 3 is a schematic block diagram of the presently preferred exemplary embodiment in accordance with the present invention;
FIGURE 4 is a detailed schematic diagram of the memory address map block shown in FIGURE 3;
and FIG~RE 5 is a flow chart of the program instructions stored in the bootstrap store block shown in FIGURE 3.
123~j22 4a One solution used in the past to provide non-volatile storage for program instructions is to use ~he architecture shown in FIGURE l. A PROM
memory device 20 stores micro-instructions to be executed by a processor l0. PROM memory 20 is non-volatile, and therefore retains the micro-instructions when the power to the system is shut off. A RAM 30 is used only to store temporary data developed by the processor 20 in the execution of the micro-instructions. It does not matter too much if the temporary data stored by RAM 30 is lost, so the fact that the RAM is volatile is not detrimental. ~his architecture is well known in the art, and is disclosed in, for instance, U.S. Patent No. 4,038,64~ to Kim (issued July 26, 1977), ~.S.
Patent No. 4,203,154 to Lampson et al (issued May 13, 1980) and U.S. Patent No. 4,085,442 to 1iaukus et al (issued April 18, 1978). The architecture shown in FIGURE l is quite suitable where PROM 20 need only store a small number of instructions (and therefore need only have a small number of locations). However, PROMs which have the capacity of storing a large number of instructions are relatively expensive. Moreover, if some portion of the stored program must be changed, PROM 20 must be discarded and a new P~OM programmed and installed.
Of course, a more flexible way to provide program instructions to the processor for execution is to simply load them into RAM 30 each time the system is powered up. Data residing on a non-volatile mâss storage device such as, for instance, ~23S227 a magnetic disk or tape might be loaded into RAM 30 each time the system power is turned on. The user need Gnly change the information stored on the mass storage device in order to change the function of the processor. The loading of information from mass storage into a RAM must itself typically be performed by the processor under program control.
The architecture shown in FIGURE 2 includes a PROM memory 20 for storing micro-instructions lQ which includes instructions which direct processor 10 to transfer information from magnetic disk 40 to RAM 30. PROM 20 may contain a variety of initialization information (such as values for pointers pointing to locations in RAM 30) which may be used to initialize processor 10 at the time that power is applied to the system. Processor 10 may execute instructions contained in PROM 20, instruc-tions loaded into RAM 30 from magnetic disk 40, or both. RAM 30 also may be used, of course, to store temporary data produced during execution of the instructions. This architecture is disclosed, for example, in U.S. Patent No. 4,025,904 to Adney et al (issued May 24, 1977), U.S. Patent No. 3,778,775 to Haring et al (issued December 11, 1973), U~S. Patent No. 4,165,534 to Dummermuth et al (issued August 21, 1979), U.S. Patent No. 4,204,206 to Bakula et al (issued May 20, 1980) and U.S. Patent No. 4,204,208 to McCarthy (issued May 20, 1980).
Not all of the instructions stored on 3a magnetic disk 40 need to be transferred into RAM 30 at once. U.S. Patent No. 4,080,651 (issued March 21, 1978, U.S. Patent No. 4,080,652 (issued March 21, 1978) and U.S. Patent No. 4,126,894 (issued November 21, 1978) all to Cronshaw et al disclose the transfer of information from mass storage 40 to 1~35i~;27 RAM 30 in overlays without intervention from processor 10 but rather through use of a separate processor (not shown) dedicated to that purpose.
RAM 30 may have a switching speed essentially the S same as processor 10, and therefore not limit the speed of execution of program instructions by the processor. However, since the cost of a RAM
increases with the amount of information which it must store, a small RAM is used and overlays of information from magnetic disk 40 are selectively loaded when needed into RAM 30 for execution by processor 10. Once the loaded instructions have been executed, they may be written over by new instructions yet to be executed which reside on magnetic disk 40. RAM 30 is typically called a "cache" or "accelerator" storage because it is both relatively small and has a low access time. The use of a cache store is also disclosed in U.S. Patent No. 4,313,158 to Porter et al (issued January 26, 1982) and U.S. Patent No. 4,051,461 to Hashimoto et al (issued September 27, 19773.
U.S. Patent No. 4,403,283 to Myntti et al (issued September ~, 1983) and U.S. Patent No.
4,295,192 to Porcella (issued October 13, 1981) both disclose memory mapping techniques for expanding the addressing space which a processor is capable of addressing. Although microprocessors typically are capable of addressing only a limited number of storage locations (the number of storage locations being limited by the number of bits in the address produced by the microprocessor), it is often necessary to address a larger address space than the microprocessor i5 designed for. Memory "mapping" or translating arrays (which may be either sequential machines or combinational logic arrays) supply ~L23~Z~
higher-order address bits, thus increasing the address space accessible by the processor.
SUMMARY OF THE INVENTION
The present invention provides low cost, flexible storage for storing program instructions, high access speed storage for storing instructions to be executed by a microprocessor, and a separate store for storing an initialization routine. In accordance with the presently preferred exemplary embodiment of this invention, a data bus conveys signals associated with program instructions. A
first non-volatile memory (which may comprise an EPROM) stores a first plurality of program instructions and applies the first plurality of instructions to the data bus in response to a first read signal produced by the microprocessor. The first plurality of program instructions defines at least vne function to be performed by the system. A
second non-volatile memory (which may be a semiconductor PROM) stores a second plurality of program instructions (a "bootstrapping" routine) which is used for initialization of the system. The second memory applies the bootstrap routine to the data bus in response to a first addressing signal produced by the microprocessor. The first addressing signal may be produced upon power-up as well as at any time that the system is to be reset. In response to the appearance on the data bus of signals associated with the second plurality of program instructions stored by the PROM, the microprocessor produces the first read signal to cause the first memory to apply signals to the data bus which are associated with the first plurality of ~23~ZX'~
program instructions. The microprocessor loads the first plurality of program instructions from the data bus into a programmable memory (which may be a semiconductor RAM) under the direction of the second plurality of program instructions. Once the first plurality of program instructions have been loaded into the programmable main memory, the microprocessor executes the first plurality of program instructions out of the main memory.
The first plurality of program instructions may be organi2ed into plural overlays, if desired.
The second plurality of program instructions stored in the PROM may direct that a particular one of the overlays stored in the EPROM be loaded into the RAM. The overlay loaded into the RAM may then direct that another particular overlay stored in the EPROM be loaded into the RAM (either concurrently or at the conclusion of execution of the first overlay). An address map may be used to prevent the microproc~ssor from addressing the PRO~ and the R~M
simultaneously.
The first memory in accordance with the present invention may comprise a large EPROM with relatively slow access time and a larger addressing space than is capable of being addressed directly by the microprocessor. The microprocessor may load ~
programmable counter with the starting location in the EPROM of an overlay to be transferred from the EPROM into the RAM. The counter may then sequentially address the EPROM to effect the transfer of information from the EPROM onto the data bus. A latch may be provided at the output of the EPROM to temporarily store the data produced by the EPROM until the RAM stores the information.
1;~35Z27 In accordance with the presently preferred embodiment of the invention, an EP~OM with relatively high access time may be used to store a library of routines of program instructions to be 5 executed by the microprocessor. The PROM may be extremely small since it is used only to provide the microprocessor with instructions necessary to transfer a first overlay from the EPROM to the RAM. The RAM can also be small, thus decreasing the cost of the system while permitting the processor to aCcesC instructions at high speeds.
10 1;2352z~
DETAILED DESCRIPTION O~ THE
PRESENTLY PREFERRED EM~ODIMENT
A schematic block diagram of the presently preferred exemplary embodiment of a system 45 in accordance with the present invention is shown in ~IGURE 3. The embodiment shown includes a microprocessor 50, a data bus 52, a memory address map 54, a main memory 56, a bootstrap store 58, a program store address pointer/counter 60, a program store 62 and a latch 64.
Microprocessor 50 may comprise any co~mercially available microprocessor ~such as the TI320 available from Texas Instruments, Inc., Dallas, Texas). Microprocessor 50 has a fixed number of address lines and is therefore capable of addres~ing a fixed address space. In the preferred embodiment, microprocessor 50 has twelve addres~
lines Ao~ All, enabling it to address 212 storage locations.
Microprocessor 50 is connected to data bus 52 (a tri-state bus in the preferred embodiment) by a data link 66 ~which may include a plurality of individual tri-state data lines). As is well known, microprocessor 50 includes a plurality of internal registers ~such as a memory address register, a status register, a program counter, an instruction register and general purpose registers), an arithmetic logic unit (for performing operations on data) and control logic (for producing a plurality o~ different control signals in response to the ~ ;~35X2~7 instructions being executed). Data appearing at the DATA input of microprocessor 50 may be stored in an internal register, and operations on the stored data may be performed by the arithmetic logic unit.
Microprocessor 50 produces addresses on its address lines (Ao~ll~, which are applied to the ADDRESS input of main memory 56 via address bus 67. Microprocessor 50 thereby addresses respective ones of a plurality of storage locations of main memory 56. In response to address signals and control signals (to be discussed shortly) applied to the main memory 56, the main memory produces signals corresponding to the contents of the addressed storage locations on its DATA output, which can be transferred (via data line 57 and data bus 52) into a register internal to microprocessor 50.
In the preferred embodiment, many of the storage locations of main memory 56 contain program instructions to be executed by microprocessor 50.
In the preferred embodiment, main memory 56 comprises a conventional read/write semiconductor random access memory (RAM) having 4K storage locations each storing one word of information. The access time of main memory 56 is faster than the cycle time of microprocessor 50 (i.e. the time which microprocessor requires to execute an nstruction, about 90 ns in the preferred embodiment) so that it does not ~low down the execution of instructions by microprocessor 50.
The contents of the internal register of microprocessor 50 which has been loaded with a program instruction from main memory 56 is decoded to enable the microprocessor to perform the tasks specified by the instruction. As is well known, the instruction may specify one or more of a large ~ 3522~
number of tasks (such as, for instance, outputting data onto data bus 52 via data link 66, manipulatin~
data stored in the registers internal to the microprocessor for application to a specified device 5 connected to the bus, changing the contents of the internal program counter to effect a conditional or unconditional branching, storing in an internal register the data present on data bus 52, changing the contents of one of the storage locations of main 10 memory 56, etc.).
As is well known, microprocessor 50 may produce a variety of control signals other than the address and data signals shown in FIGURE 3. For instance, in the preferred embodiment, microprocessor 50 produces signals to control the operation of data bus 52, signals to be applied to main memory 56 to permit reading or writing of the location in the main memory corresponding to the address output applied to address bus 67 (as will be explained shortly), I/O (input/output) control signals to control various I/O peripheral devices, etc. The various control signals are automatically produced at appropriate times in response to executed instructions (for instance, if an instruction bein~ executed calls for reading the contents of a location of main memory 56, microprocessor 50 automatically produces a control signal to place the main memory in the read mode, produces another control signal to control data bus 52 to permit transfer of information from the main memory DATA port to the microprocessor DATA input, and places an appropriate address onto address bus 67). These control signals and pathways are conventional and well known, and are therefore not shown in FIGURE 3.
~Z3~
As mentioned above, microprocessor 50 has twelve address lines (Ao_ll). In the preferred embodiment, Ao is the least significant bit (LSB) of the address produced by microprocessor 50, while A
5 is the most significant bit (MSB) of the address.
All of the address bits produced by microprocessor 50 are applied to the ADDRESS input of main memory 56 via address bus 67. The five least significant address bits (Ao~A4) produced by microprocessor 50 10 are applied to the ADDRESS input of bootstrap store 58. In addition, the seven most significant address bits (A5_11) produced by microprocessor 50 are applied to the input of memory address map 54. The function of memory address map 54 is to permit 15 microprocessor 50 to address ma`in memory 56 and bootstrap store 58 alternatively (i.e. never simultaneously) while ensuring that this alternative addressing scheme is completely transparent to the microprocessor. In other words, memory address map 54 permits microprocessor 50 to address main memory 56 and bootstrap store 58 as a single integrated memory address space rather than as two physically-distinct memory devices. Bootstrap store 58 is the preferred ernbodiment comprises an electrically programrnable read only memory (PROM) having 32 storage locations of one word each. Bootstrap store 58 has an access time approximately the same as that of main memory 56. The contents of the storage locations of bootstrap store 58 will be discussed in greater detail shortly.
FIGURE 4 shows a detailed schematic diagram of the memory address map 54. In the preferred embodiment, memory address map 54 comprises a simple combinational logic array which derives memory control signals for bootstrap store 58 and main 1235X2~7 memory 56 from the memory control signals produced by microprocessor 50 together with the seven most significant bits (A5_11) of the microprocessor address output. The conventional control signal WE
5 produced by microprocessor 50 is referred to as the "out write enable" signal, and when active (i.e., at logic level LOW), indicates that the microprocessor is attempting to output data on its DATA output to be written into the location of memory specified by the microprocessor address output. Conventional A
control signal MEN produced by microprocessor 50 is the "out memory enable" signal, and when active (i.e., at logic level LOW), indicates that the microprocessor address output contains a valid 15 memory address. The signal WE is routed directly to a corresponding control input of main memory 56 but not to bootstrap store SB ~since the bootstrap store is only read from and never written to). Memory address map 54 produces two mutually exclusive output signals, "bootstrap store enable" and "main memory enable", which cause either the bootstrap store 5~ or main memory 56 (respectively) to place data onto data bus 52.
Logic gates 68-76 decode the seven most significant bits A5_11 produced by microprocessor 50. The "bootstrap store enable" signal is produced only during the time when both microprocessor 50 issues control signals indicating that a valid address is on its address output and the issued address is one of the lowest 32 locations in the microprocessor address space. If microprocessor 50 produces a valid address which is higher than one of the lowest 32 locations in its addressing space, ~L235~
memory address map 54 produces the "main memory enable" signal. It will be understood that the memory address map 54, main memory 56 and bootstrap store 58 simulate a unitary 4K word memory in which the lowest 32 words are non-volatile (and read-only) while the remainder of the words are volatile and can be written into as well as read from.
The switching between main memory 56 and bootstrap store 58 is totally transparent to the program instructions executed by microprocessor 50, and thus need not worry a human programmer.
~ ooking back to FIGURE 3, when the "main memory enable" signal is produced by memory address map 5~, main memory 56 applies signals to data bus 52 representing the contents of the location of the main memory corresponding to the address present on address bus 67. When the "main memory write enable"
signal is produced by memory address map 54, main memory 56 stores the data present on data bus 52 into the location in the main memory corresponding to the address present on address line bus 67.
Similarly, when the "bootstrap store enable" signal is produced by memory address map 54 (and applied to the bootstrap store via control line 55), bootstrap store 58 applies to data bus 52 signals associated with the contents of the location in the bootstrap store associated with the signals applied to its ADDRESS input (the five least significant bits Ao-A4 of the address produced by microprocessor 50).
Program store address pointer/counter 60 is connected via data link 59 to data bus 52. Counter 60 in the preferred embodiment comprises a conventional programmable counter. In response to a "load" control signal produced by microprocessor 50 (in conjunction with external conventional logic not ~Z35~
shown), counter 60 loads the data present on data bus 52. Hence, counter 60 appears to microprocessor 50 as an I/O peripheral device capable of being written to. In response to a clock signal and a 5 COUNTER ENABLE control signal (not shown) produced by microprocessor 50, counter 60 increments the value which it has stored by one count in response to every clock pulse produced by a conventional system clock (not shown).
-10 The output of counter 60 is applied to the address input of program store 62 via an address bus 61. Program store 62 in the preferred embodi~ent comprises an erasable programmable read only memory (EPROM) having 32K locations each storing one word of information. The DATA output of program store 62 is applied to the input of a conventional latch 64 via a data line 63. The output of latch 64 is connected to data bus 52 by a data line 65. As will be readily surmised, the number of signals which must be latched by latch 64 and the counting capacity of counter 60 are directly related to the size of program store 62.
The function of counter 60 is to sequentially address program store 62 beginning at location loaded into the counter by microprocessor 50 via data bus 52. Although microprocessor 50 in the preferred embodiment produces only twelve bits of address, it produces a full sixteen bits of parallel data at its DATA output; therefore, the DATA output of the microprocessor can specify an arbitrary address of program store 62. Once this arbitrary address is loaded into counter 60, the counter increments automatically (at every other cycle of microprocessor 50 in the preferred embodiment) thereby addressing program store 62 ~Z3~227 sequentially beginning at the loaded address. The counter is only incremented at every other cycle of microprocessor 50 because the access time of program store 62 in the preferred embodiment is greater than one cycle time of the microprocessor but less than two cycle times. Latch 65 may be omitted if program store 62 is sufficiently fast with respect to the cycle time of microprocessor 50.
In response to an address applied by counter 60 to its ADDRESS input, program store 62 produces at its DATA output the data stored in the location corresponding to the address. ~n appropriate period of time after an address is applied to program store 62, latch 64 latches the data produced by program store 62, thereby making it available to be applied to data bus 52.
In the preferred embodiment, program store 62 contains a plurality of program instructions and data organized into "overlays" or blocks. Each overlay contains program instructions defining a particular task or function to be performed by microprocessor 50. The overlays stored in program store 62 may be arbitrarily organized according to user application. For instance, if system 45 is operated as a sequential file finite state sequential machine, one or more overlays might correspond to the task or tasks to be performed for each state which the machine may enter.
One constraint which is imposed upon the overlays in the preferred embodiment is that they must somehow be cross-linked, i.e., each overlay except the last overlay to be executed must include instructions which control the loading and transfer of control to another overlay to be executed.
Cross-linking Oe overlays will be explained in lZ35~7 greater detail shortly. Although each overlay typically performs a single task or function (which may include many subtasks to be performed by the microprocessor), oYerlays may be of arbitrary size (depending upon the complexity of the function which it performs). Some functions to be performed may contain so many instructions that more than one overlay is required to perform the function.
FIGURE S shows a flow chart of the instructions contained by bootstrap store 58 in accordance with the present invention. The flow chart is entered at block 86 when power is applied to system 45, which automatically causes microprocessor 50 to address the lowest location in its address space (i.e., by setting the micro-processor program counter to the value 16). ~his address resetting function is conventionally performed by hardware in the preferred embodiment.
The produced address is decoded by memory address map 54 to be the first location in bootstrap store 58, as previously discussed. Block 8~ sets a flag ~the purpose of which will become apparent shortly). Block 90 loads program store address pointer counter 60 with the starting location in program store 62 of the first overlay to be executed by microprocessor 50.
A loop (comprising blocks 92, 94, 96) copy the first overlay to be executed from bootstrap store 58 into main memory 56. Block 92 reads a single word from program store 62 and stores it into an internal register (the Instruction Register) in microprocessor 50. Block 94 then transfers the stored word just read from the internal register in microprocessor 50 into main memory 56 beginning at a specified location x. Block 95 increments x (which, ~.235Z2~
in the preferred embodiment, is stored in a general purpose register in the microprocessor) to the next seqeuential location in main memory 56. Block 96 tests to determine if the word just loaded into main memo`ry 56 was the last word to be transferred.
Block 96, of course, can be implemented in a number of wa~s (such as by testing the value of x, using a separate loop counter register which is simultaneously incremented when x is incremented, requiring that the last word to be transferred have some unique value which can be tested for by microprocessor 50, etc.). If the word just transferred into main memory 56 was not the last word to be transferred, control returns to block 92 to read another word.
If the last word in the overlay has been transferred, then the flag is tested by block 98.
If the flag is still set, block 100 begins executing the overlay just loaded into main memory 56 beginning at location x (block 100). The flag is also reset to 0 by block 100. In the preferred embodiment, the first overlay to be loaded into main memory 56 is a diagnostic testing program which is executed every time system 45 is powered up. In the preferred embodiment, at the conclusion of the execution of the diagnostic testing routine, the bootstrap routine stored in bootstrap store 58 is used again to load the next overlay to be executed from program store 62 to main memory 56. Blocks 90-96 perform the same function as before except thatblock 90 loads program store address pointer/counter ~ith the starting location in program store 62 of the next overlay to be executed.
After block 90 has been executed for the second time and the loop comprising blocks 92-96 has ~Z35~27 been traversed a second time, block 98 once again tests to determine if the flag is set. Because the flag was reset in block 100~ the flag will not be set at this time, and block 102 is entered. Block 102 simply loads the internal program counter of microprocessor 50 with x (the location in main memory 56 in which the last overylay loaded into main memory 56 begins) or with some other address of the main memory at which the first instruction to be executed exists. In the preferred embodiment, bootstrap store 58 is not addressed again until system 45 is either reset or powered off and then on again. It will be recognized that both blocks 100 and 102 in the flow chart of FIGURE 5 are performed by executing instructions stored in main memory 56, while blocks 88-98 are performed by executing instructions stored in bootstrap store 5~.
In the preferred embodiment, many overlays (including the diagnostic testing routine overlay) are stored in program store 62. As previously mentioned, since bootstrap store 58 only provides for the copying of a first and second overlay into main memory 56, the remainder of the overlays must themselves include cross-linking routines for copying of additional overlays into the main memory. For instance, the second overlay to be loaded into main memory 56 may include instructions to load a third overlay into main memory 56. This third overlay might be loaded at the conclusion of execution of the second overlay ~thus replacing the second overlay), at the beginning of the execution of the second overlay (so that the second and a third overlays would both reside in main memory 56 simultaneously), etc. Of course, branchins may be accomplished by loading one overlay if a condition ~235ZZ~
is satisfied and loading a different overlay if the condition is unsatisfied. Great flexibility in programming is provided through the use of overlays. Although each overlay must include some instructions to cause the next overlay to be executed to be loaded into main memory 56 and instructions to transfer control to that next overlay, such cross-linking routines have few instructions and do not occupy much memory space.
Although only one exemplary embodiment has been described in detail above, those skilled in the art will appreciate that many variations and modifications may be made in this embodiment without departing from the novel and advantageous features of this invention. For instance, instructions could be loaded directly from program store 62 to main memory 56 using direct memory access techni~ues.
Likewise, the cross-linking of overlays could be accomplished in a variety of different ways (such as a look-up table stored in program store 62 or elsewhere). Memory address map 54 could be implemented in a variety of different ways, and need not comprise combinational logic. Microprocessor 50 could be replaced by any processing device which is capable of performing tasks under program control.
Accordingly, all such variations and modifications are intended to be included within the scope of the following claims.
HIGH SPEED PROGRAM STORE WITH BOOTSTRAP
FIELD OF THE INVENTION
The invention is related to apparatus and method for the performance of a plurality of stored predetermined program tasks. More particularly, the invention is related to the storage of program instructions and data for execution by a general purpose digital computing device (such as a microprocessor~ which requires initialization.
BACKGROUND OF THE INVENTION
Microprocessor-based systems presently are used in a wide variety of applications to provide computation and other signal processing functions under so-called "software" control. As is well known, memory structures are typically provided in such systems to store program instructions and data. It is usually necessary to provide both non-volatile memory ~i.e., memory that will retain its contents even when the power supply to the system is turned off) as well as read/write random access memory (RAM) which may be used for storing temporary data and user-developed program instructions. Due to speed and flexibility considerations, semiconductor memory devices are typically now used to provide both non-volatile and read/writ.e storage.
Of course, there are many different types of semiconductor memory devices presently commercially available. Perhaps the most commonly-used semiconductor memory device is the semiconductor read/write random access memory (RAM). RAMs are available in both bipolar and MOS
Z3~
technologies. In general, RAMs have the advantages of high density (i.e., high storage capability per unit volume~, high speed and low cost. For these reasons, RAMs are typically the memory device of choice for microprocessor-based systems. RAMs can be obtained which have a memory access time which is shorter than the switching speeds of available - microprocessors, so that the RAM does not limit the speed at which the microprocessor can execute program instructions.
RAMs, however, are volatile memory devices, and therefore lose their contents if their power supply is interrupted. Therefore, processing systems which may be turned on and off or which may have to be reset often are also typically provided with a non-volatile storage device for storing information which will be reused. Information which must be stored in a non-volatile storage device includes, for example, program instructions which must be executed each time the system is powered ~p. It is typically desirable to store all program instructions in non-volatile memory (unless those program instructions must be capable of being altered by the user during the course of operation of the system).
One type of non-volatile storage which is often used is a semiconductor read only memory (ROM). In general, semiconductor ROMs are available in three types: mask-programmed ROMs, electrically programmable read only memories ~PROM), and erasable programmable read only memories (EPROM). Informa-tion is stored in mask-programmed ROMs at the time of manufacture, and may not be changed by the user. Mask-programmed ROMs are relatively inexpensive if made in high volume, but are ~23~2~
ordinarily not used for small-volume applications because of the expense of preparing and specifying a mask. In addition, mask-programmed ROMs are ordinarily not used in a system unless the system 5 software has been thoroughly tested, since their contents may not be changed.
PROMs, on the other hand, may be electrically programmed by a user. PROMs store no information when purchased. The user "programs"
10 data into the PROM by applying electrical signals to it. Once the programming process is complete, the data which is stored in the PROM is permanent and cannot be altered. PROMs find wide use in low-volume applications (where mask-programmed ROMs 15 would be uneconomical), as well as in applications where the stored information might be subject to change (for instance, where the system is still under development). PROMs are non-volatile, but if their contents are to be changed, may must be replaced.
Erasable programmable read only memories (EPROMs) are similar to PROMs except that they may be erased and reused. Typically, EPROMs are provided with a quartz lid which passes ultraviolet radiation. When the EPROM is exposed to ultraviolet radiation, its contents are erased. The EPROM may then be electrically programmed in a manner similar to that used to program a PROM. EPROMs are very useful for storing information that might be subject to change. However, EPROMs are expensive compared to RAMs, mask-programmable ROMs and PROMs.
Moreover, EPROMs generally have greater access time than R~Ms' in the past, the speed of a microprocessor executing instructions stored in an EPROM has been limited by the relatively slow access , ~23~2Z~
speed of the EPROM. As technology has advanced, faster EPROMs have been developed. However, EPROMs are still slow relative to RAMs, and are far more expensive.
BRIEF DESCRIPTION OF_THE DRAWINGS
FIGURE 1 is a block schematic diagram of a prior art microprocessor signal processing system;
FIGURE 2 is a schematic block diagram of another prior art microprocessor-based signal processing system;
FIGURE 3 is a schematic block diagram of the presently preferred exemplary embodiment in accordance with the present invention;
FIGURE 4 is a detailed schematic diagram of the memory address map block shown in FIGURE 3;
and FIG~RE 5 is a flow chart of the program instructions stored in the bootstrap store block shown in FIGURE 3.
123~j22 4a One solution used in the past to provide non-volatile storage for program instructions is to use ~he architecture shown in FIGURE l. A PROM
memory device 20 stores micro-instructions to be executed by a processor l0. PROM memory 20 is non-volatile, and therefore retains the micro-instructions when the power to the system is shut off. A RAM 30 is used only to store temporary data developed by the processor 20 in the execution of the micro-instructions. It does not matter too much if the temporary data stored by RAM 30 is lost, so the fact that the RAM is volatile is not detrimental. ~his architecture is well known in the art, and is disclosed in, for instance, U.S. Patent No. 4,038,64~ to Kim (issued July 26, 1977), ~.S.
Patent No. 4,203,154 to Lampson et al (issued May 13, 1980) and U.S. Patent No. 4,085,442 to 1iaukus et al (issued April 18, 1978). The architecture shown in FIGURE l is quite suitable where PROM 20 need only store a small number of instructions (and therefore need only have a small number of locations). However, PROMs which have the capacity of storing a large number of instructions are relatively expensive. Moreover, if some portion of the stored program must be changed, PROM 20 must be discarded and a new P~OM programmed and installed.
Of course, a more flexible way to provide program instructions to the processor for execution is to simply load them into RAM 30 each time the system is powered up. Data residing on a non-volatile mâss storage device such as, for instance, ~23S227 a magnetic disk or tape might be loaded into RAM 30 each time the system power is turned on. The user need Gnly change the information stored on the mass storage device in order to change the function of the processor. The loading of information from mass storage into a RAM must itself typically be performed by the processor under program control.
The architecture shown in FIGURE 2 includes a PROM memory 20 for storing micro-instructions lQ which includes instructions which direct processor 10 to transfer information from magnetic disk 40 to RAM 30. PROM 20 may contain a variety of initialization information (such as values for pointers pointing to locations in RAM 30) which may be used to initialize processor 10 at the time that power is applied to the system. Processor 10 may execute instructions contained in PROM 20, instruc-tions loaded into RAM 30 from magnetic disk 40, or both. RAM 30 also may be used, of course, to store temporary data produced during execution of the instructions. This architecture is disclosed, for example, in U.S. Patent No. 4,025,904 to Adney et al (issued May 24, 1977), U.S. Patent No. 3,778,775 to Haring et al (issued December 11, 1973), U~S. Patent No. 4,165,534 to Dummermuth et al (issued August 21, 1979), U.S. Patent No. 4,204,206 to Bakula et al (issued May 20, 1980) and U.S. Patent No. 4,204,208 to McCarthy (issued May 20, 1980).
Not all of the instructions stored on 3a magnetic disk 40 need to be transferred into RAM 30 at once. U.S. Patent No. 4,080,651 (issued March 21, 1978, U.S. Patent No. 4,080,652 (issued March 21, 1978) and U.S. Patent No. 4,126,894 (issued November 21, 1978) all to Cronshaw et al disclose the transfer of information from mass storage 40 to 1~35i~;27 RAM 30 in overlays without intervention from processor 10 but rather through use of a separate processor (not shown) dedicated to that purpose.
RAM 30 may have a switching speed essentially the S same as processor 10, and therefore not limit the speed of execution of program instructions by the processor. However, since the cost of a RAM
increases with the amount of information which it must store, a small RAM is used and overlays of information from magnetic disk 40 are selectively loaded when needed into RAM 30 for execution by processor 10. Once the loaded instructions have been executed, they may be written over by new instructions yet to be executed which reside on magnetic disk 40. RAM 30 is typically called a "cache" or "accelerator" storage because it is both relatively small and has a low access time. The use of a cache store is also disclosed in U.S. Patent No. 4,313,158 to Porter et al (issued January 26, 1982) and U.S. Patent No. 4,051,461 to Hashimoto et al (issued September 27, 19773.
U.S. Patent No. 4,403,283 to Myntti et al (issued September ~, 1983) and U.S. Patent No.
4,295,192 to Porcella (issued October 13, 1981) both disclose memory mapping techniques for expanding the addressing space which a processor is capable of addressing. Although microprocessors typically are capable of addressing only a limited number of storage locations (the number of storage locations being limited by the number of bits in the address produced by the microprocessor), it is often necessary to address a larger address space than the microprocessor i5 designed for. Memory "mapping" or translating arrays (which may be either sequential machines or combinational logic arrays) supply ~L23~Z~
higher-order address bits, thus increasing the address space accessible by the processor.
SUMMARY OF THE INVENTION
The present invention provides low cost, flexible storage for storing program instructions, high access speed storage for storing instructions to be executed by a microprocessor, and a separate store for storing an initialization routine. In accordance with the presently preferred exemplary embodiment of this invention, a data bus conveys signals associated with program instructions. A
first non-volatile memory (which may comprise an EPROM) stores a first plurality of program instructions and applies the first plurality of instructions to the data bus in response to a first read signal produced by the microprocessor. The first plurality of program instructions defines at least vne function to be performed by the system. A
second non-volatile memory (which may be a semiconductor PROM) stores a second plurality of program instructions (a "bootstrapping" routine) which is used for initialization of the system. The second memory applies the bootstrap routine to the data bus in response to a first addressing signal produced by the microprocessor. The first addressing signal may be produced upon power-up as well as at any time that the system is to be reset. In response to the appearance on the data bus of signals associated with the second plurality of program instructions stored by the PROM, the microprocessor produces the first read signal to cause the first memory to apply signals to the data bus which are associated with the first plurality of ~23~ZX'~
program instructions. The microprocessor loads the first plurality of program instructions from the data bus into a programmable memory (which may be a semiconductor RAM) under the direction of the second plurality of program instructions. Once the first plurality of program instructions have been loaded into the programmable main memory, the microprocessor executes the first plurality of program instructions out of the main memory.
The first plurality of program instructions may be organi2ed into plural overlays, if desired.
The second plurality of program instructions stored in the PROM may direct that a particular one of the overlays stored in the EPROM be loaded into the RAM. The overlay loaded into the RAM may then direct that another particular overlay stored in the EPROM be loaded into the RAM (either concurrently or at the conclusion of execution of the first overlay). An address map may be used to prevent the microproc~ssor from addressing the PRO~ and the R~M
simultaneously.
The first memory in accordance with the present invention may comprise a large EPROM with relatively slow access time and a larger addressing space than is capable of being addressed directly by the microprocessor. The microprocessor may load ~
programmable counter with the starting location in the EPROM of an overlay to be transferred from the EPROM into the RAM. The counter may then sequentially address the EPROM to effect the transfer of information from the EPROM onto the data bus. A latch may be provided at the output of the EPROM to temporarily store the data produced by the EPROM until the RAM stores the information.
1;~35Z27 In accordance with the presently preferred embodiment of the invention, an EP~OM with relatively high access time may be used to store a library of routines of program instructions to be 5 executed by the microprocessor. The PROM may be extremely small since it is used only to provide the microprocessor with instructions necessary to transfer a first overlay from the EPROM to the RAM. The RAM can also be small, thus decreasing the cost of the system while permitting the processor to aCcesC instructions at high speeds.
10 1;2352z~
DETAILED DESCRIPTION O~ THE
PRESENTLY PREFERRED EM~ODIMENT
A schematic block diagram of the presently preferred exemplary embodiment of a system 45 in accordance with the present invention is shown in ~IGURE 3. The embodiment shown includes a microprocessor 50, a data bus 52, a memory address map 54, a main memory 56, a bootstrap store 58, a program store address pointer/counter 60, a program store 62 and a latch 64.
Microprocessor 50 may comprise any co~mercially available microprocessor ~such as the TI320 available from Texas Instruments, Inc., Dallas, Texas). Microprocessor 50 has a fixed number of address lines and is therefore capable of addres~ing a fixed address space. In the preferred embodiment, microprocessor 50 has twelve addres~
lines Ao~ All, enabling it to address 212 storage locations.
Microprocessor 50 is connected to data bus 52 (a tri-state bus in the preferred embodiment) by a data link 66 ~which may include a plurality of individual tri-state data lines). As is well known, microprocessor 50 includes a plurality of internal registers ~such as a memory address register, a status register, a program counter, an instruction register and general purpose registers), an arithmetic logic unit (for performing operations on data) and control logic (for producing a plurality o~ different control signals in response to the ~ ;~35X2~7 instructions being executed). Data appearing at the DATA input of microprocessor 50 may be stored in an internal register, and operations on the stored data may be performed by the arithmetic logic unit.
Microprocessor 50 produces addresses on its address lines (Ao~ll~, which are applied to the ADDRESS input of main memory 56 via address bus 67. Microprocessor 50 thereby addresses respective ones of a plurality of storage locations of main memory 56. In response to address signals and control signals (to be discussed shortly) applied to the main memory 56, the main memory produces signals corresponding to the contents of the addressed storage locations on its DATA output, which can be transferred (via data line 57 and data bus 52) into a register internal to microprocessor 50.
In the preferred embodiment, many of the storage locations of main memory 56 contain program instructions to be executed by microprocessor 50.
In the preferred embodiment, main memory 56 comprises a conventional read/write semiconductor random access memory (RAM) having 4K storage locations each storing one word of information. The access time of main memory 56 is faster than the cycle time of microprocessor 50 (i.e. the time which microprocessor requires to execute an nstruction, about 90 ns in the preferred embodiment) so that it does not ~low down the execution of instructions by microprocessor 50.
The contents of the internal register of microprocessor 50 which has been loaded with a program instruction from main memory 56 is decoded to enable the microprocessor to perform the tasks specified by the instruction. As is well known, the instruction may specify one or more of a large ~ 3522~
number of tasks (such as, for instance, outputting data onto data bus 52 via data link 66, manipulatin~
data stored in the registers internal to the microprocessor for application to a specified device 5 connected to the bus, changing the contents of the internal program counter to effect a conditional or unconditional branching, storing in an internal register the data present on data bus 52, changing the contents of one of the storage locations of main 10 memory 56, etc.).
As is well known, microprocessor 50 may produce a variety of control signals other than the address and data signals shown in FIGURE 3. For instance, in the preferred embodiment, microprocessor 50 produces signals to control the operation of data bus 52, signals to be applied to main memory 56 to permit reading or writing of the location in the main memory corresponding to the address output applied to address bus 67 (as will be explained shortly), I/O (input/output) control signals to control various I/O peripheral devices, etc. The various control signals are automatically produced at appropriate times in response to executed instructions (for instance, if an instruction bein~ executed calls for reading the contents of a location of main memory 56, microprocessor 50 automatically produces a control signal to place the main memory in the read mode, produces another control signal to control data bus 52 to permit transfer of information from the main memory DATA port to the microprocessor DATA input, and places an appropriate address onto address bus 67). These control signals and pathways are conventional and well known, and are therefore not shown in FIGURE 3.
~Z3~
As mentioned above, microprocessor 50 has twelve address lines (Ao_ll). In the preferred embodiment, Ao is the least significant bit (LSB) of the address produced by microprocessor 50, while A
5 is the most significant bit (MSB) of the address.
All of the address bits produced by microprocessor 50 are applied to the ADDRESS input of main memory 56 via address bus 67. The five least significant address bits (Ao~A4) produced by microprocessor 50 10 are applied to the ADDRESS input of bootstrap store 58. In addition, the seven most significant address bits (A5_11) produced by microprocessor 50 are applied to the input of memory address map 54. The function of memory address map 54 is to permit 15 microprocessor 50 to address ma`in memory 56 and bootstrap store 58 alternatively (i.e. never simultaneously) while ensuring that this alternative addressing scheme is completely transparent to the microprocessor. In other words, memory address map 54 permits microprocessor 50 to address main memory 56 and bootstrap store 58 as a single integrated memory address space rather than as two physically-distinct memory devices. Bootstrap store 58 is the preferred ernbodiment comprises an electrically programrnable read only memory (PROM) having 32 storage locations of one word each. Bootstrap store 58 has an access time approximately the same as that of main memory 56. The contents of the storage locations of bootstrap store 58 will be discussed in greater detail shortly.
FIGURE 4 shows a detailed schematic diagram of the memory address map 54. In the preferred embodiment, memory address map 54 comprises a simple combinational logic array which derives memory control signals for bootstrap store 58 and main 1235X2~7 memory 56 from the memory control signals produced by microprocessor 50 together with the seven most significant bits (A5_11) of the microprocessor address output. The conventional control signal WE
5 produced by microprocessor 50 is referred to as the "out write enable" signal, and when active (i.e., at logic level LOW), indicates that the microprocessor is attempting to output data on its DATA output to be written into the location of memory specified by the microprocessor address output. Conventional A
control signal MEN produced by microprocessor 50 is the "out memory enable" signal, and when active (i.e., at logic level LOW), indicates that the microprocessor address output contains a valid 15 memory address. The signal WE is routed directly to a corresponding control input of main memory 56 but not to bootstrap store SB ~since the bootstrap store is only read from and never written to). Memory address map 54 produces two mutually exclusive output signals, "bootstrap store enable" and "main memory enable", which cause either the bootstrap store 5~ or main memory 56 (respectively) to place data onto data bus 52.
Logic gates 68-76 decode the seven most significant bits A5_11 produced by microprocessor 50. The "bootstrap store enable" signal is produced only during the time when both microprocessor 50 issues control signals indicating that a valid address is on its address output and the issued address is one of the lowest 32 locations in the microprocessor address space. If microprocessor 50 produces a valid address which is higher than one of the lowest 32 locations in its addressing space, ~L235~
memory address map 54 produces the "main memory enable" signal. It will be understood that the memory address map 54, main memory 56 and bootstrap store 58 simulate a unitary 4K word memory in which the lowest 32 words are non-volatile (and read-only) while the remainder of the words are volatile and can be written into as well as read from.
The switching between main memory 56 and bootstrap store 58 is totally transparent to the program instructions executed by microprocessor 50, and thus need not worry a human programmer.
~ ooking back to FIGURE 3, when the "main memory enable" signal is produced by memory address map 5~, main memory 56 applies signals to data bus 52 representing the contents of the location of the main memory corresponding to the address present on address bus 67. When the "main memory write enable"
signal is produced by memory address map 54, main memory 56 stores the data present on data bus 52 into the location in the main memory corresponding to the address present on address line bus 67.
Similarly, when the "bootstrap store enable" signal is produced by memory address map 54 (and applied to the bootstrap store via control line 55), bootstrap store 58 applies to data bus 52 signals associated with the contents of the location in the bootstrap store associated with the signals applied to its ADDRESS input (the five least significant bits Ao-A4 of the address produced by microprocessor 50).
Program store address pointer/counter 60 is connected via data link 59 to data bus 52. Counter 60 in the preferred embodiment comprises a conventional programmable counter. In response to a "load" control signal produced by microprocessor 50 (in conjunction with external conventional logic not ~Z35~
shown), counter 60 loads the data present on data bus 52. Hence, counter 60 appears to microprocessor 50 as an I/O peripheral device capable of being written to. In response to a clock signal and a 5 COUNTER ENABLE control signal (not shown) produced by microprocessor 50, counter 60 increments the value which it has stored by one count in response to every clock pulse produced by a conventional system clock (not shown).
-10 The output of counter 60 is applied to the address input of program store 62 via an address bus 61. Program store 62 in the preferred embodi~ent comprises an erasable programmable read only memory (EPROM) having 32K locations each storing one word of information. The DATA output of program store 62 is applied to the input of a conventional latch 64 via a data line 63. The output of latch 64 is connected to data bus 52 by a data line 65. As will be readily surmised, the number of signals which must be latched by latch 64 and the counting capacity of counter 60 are directly related to the size of program store 62.
The function of counter 60 is to sequentially address program store 62 beginning at location loaded into the counter by microprocessor 50 via data bus 52. Although microprocessor 50 in the preferred embodiment produces only twelve bits of address, it produces a full sixteen bits of parallel data at its DATA output; therefore, the DATA output of the microprocessor can specify an arbitrary address of program store 62. Once this arbitrary address is loaded into counter 60, the counter increments automatically (at every other cycle of microprocessor 50 in the preferred embodiment) thereby addressing program store 62 ~Z3~227 sequentially beginning at the loaded address. The counter is only incremented at every other cycle of microprocessor 50 because the access time of program store 62 in the preferred embodiment is greater than one cycle time of the microprocessor but less than two cycle times. Latch 65 may be omitted if program store 62 is sufficiently fast with respect to the cycle time of microprocessor 50.
In response to an address applied by counter 60 to its ADDRESS input, program store 62 produces at its DATA output the data stored in the location corresponding to the address. ~n appropriate period of time after an address is applied to program store 62, latch 64 latches the data produced by program store 62, thereby making it available to be applied to data bus 52.
In the preferred embodiment, program store 62 contains a plurality of program instructions and data organized into "overlays" or blocks. Each overlay contains program instructions defining a particular task or function to be performed by microprocessor 50. The overlays stored in program store 62 may be arbitrarily organized according to user application. For instance, if system 45 is operated as a sequential file finite state sequential machine, one or more overlays might correspond to the task or tasks to be performed for each state which the machine may enter.
One constraint which is imposed upon the overlays in the preferred embodiment is that they must somehow be cross-linked, i.e., each overlay except the last overlay to be executed must include instructions which control the loading and transfer of control to another overlay to be executed.
Cross-linking Oe overlays will be explained in lZ35~7 greater detail shortly. Although each overlay typically performs a single task or function (which may include many subtasks to be performed by the microprocessor), oYerlays may be of arbitrary size (depending upon the complexity of the function which it performs). Some functions to be performed may contain so many instructions that more than one overlay is required to perform the function.
FIGURE S shows a flow chart of the instructions contained by bootstrap store 58 in accordance with the present invention. The flow chart is entered at block 86 when power is applied to system 45, which automatically causes microprocessor 50 to address the lowest location in its address space (i.e., by setting the micro-processor program counter to the value 16). ~his address resetting function is conventionally performed by hardware in the preferred embodiment.
The produced address is decoded by memory address map 54 to be the first location in bootstrap store 58, as previously discussed. Block 8~ sets a flag ~the purpose of which will become apparent shortly). Block 90 loads program store address pointer counter 60 with the starting location in program store 62 of the first overlay to be executed by microprocessor 50.
A loop (comprising blocks 92, 94, 96) copy the first overlay to be executed from bootstrap store 58 into main memory 56. Block 92 reads a single word from program store 62 and stores it into an internal register (the Instruction Register) in microprocessor 50. Block 94 then transfers the stored word just read from the internal register in microprocessor 50 into main memory 56 beginning at a specified location x. Block 95 increments x (which, ~.235Z2~
in the preferred embodiment, is stored in a general purpose register in the microprocessor) to the next seqeuential location in main memory 56. Block 96 tests to determine if the word just loaded into main memo`ry 56 was the last word to be transferred.
Block 96, of course, can be implemented in a number of wa~s (such as by testing the value of x, using a separate loop counter register which is simultaneously incremented when x is incremented, requiring that the last word to be transferred have some unique value which can be tested for by microprocessor 50, etc.). If the word just transferred into main memory 56 was not the last word to be transferred, control returns to block 92 to read another word.
If the last word in the overlay has been transferred, then the flag is tested by block 98.
If the flag is still set, block 100 begins executing the overlay just loaded into main memory 56 beginning at location x (block 100). The flag is also reset to 0 by block 100. In the preferred embodiment, the first overlay to be loaded into main memory 56 is a diagnostic testing program which is executed every time system 45 is powered up. In the preferred embodiment, at the conclusion of the execution of the diagnostic testing routine, the bootstrap routine stored in bootstrap store 58 is used again to load the next overlay to be executed from program store 62 to main memory 56. Blocks 90-96 perform the same function as before except thatblock 90 loads program store address pointer/counter ~ith the starting location in program store 62 of the next overlay to be executed.
After block 90 has been executed for the second time and the loop comprising blocks 92-96 has ~Z35~27 been traversed a second time, block 98 once again tests to determine if the flag is set. Because the flag was reset in block 100~ the flag will not be set at this time, and block 102 is entered. Block 102 simply loads the internal program counter of microprocessor 50 with x (the location in main memory 56 in which the last overylay loaded into main memory 56 begins) or with some other address of the main memory at which the first instruction to be executed exists. In the preferred embodiment, bootstrap store 58 is not addressed again until system 45 is either reset or powered off and then on again. It will be recognized that both blocks 100 and 102 in the flow chart of FIGURE 5 are performed by executing instructions stored in main memory 56, while blocks 88-98 are performed by executing instructions stored in bootstrap store 5~.
In the preferred embodiment, many overlays (including the diagnostic testing routine overlay) are stored in program store 62. As previously mentioned, since bootstrap store 58 only provides for the copying of a first and second overlay into main memory 56, the remainder of the overlays must themselves include cross-linking routines for copying of additional overlays into the main memory. For instance, the second overlay to be loaded into main memory 56 may include instructions to load a third overlay into main memory 56. This third overlay might be loaded at the conclusion of execution of the second overlay ~thus replacing the second overlay), at the beginning of the execution of the second overlay (so that the second and a third overlays would both reside in main memory 56 simultaneously), etc. Of course, branchins may be accomplished by loading one overlay if a condition ~235ZZ~
is satisfied and loading a different overlay if the condition is unsatisfied. Great flexibility in programming is provided through the use of overlays. Although each overlay must include some instructions to cause the next overlay to be executed to be loaded into main memory 56 and instructions to transfer control to that next overlay, such cross-linking routines have few instructions and do not occupy much memory space.
Although only one exemplary embodiment has been described in detail above, those skilled in the art will appreciate that many variations and modifications may be made in this embodiment without departing from the novel and advantageous features of this invention. For instance, instructions could be loaded directly from program store 62 to main memory 56 using direct memory access techni~ues.
Likewise, the cross-linking of overlays could be accomplished in a variety of different ways (such as a look-up table stored in program store 62 or elsewhere). Memory address map 54 could be implemented in a variety of different ways, and need not comprise combinational logic. Microprocessor 50 could be replaced by any processing device which is capable of performing tasks under program control.
Accordingly, all such variations and modifications are intended to be included within the scope of the following claims.
Claims (30)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital signal processing system comprising:
main memory means for storing program control instructions;
first non-volatile program storing means for storing a first set of program control instructions;
second non-volatile program storing means for storing a second set of program control instructions, said second instruction set including instructions controlling the copying of predetermined instructions of said first instruc-tion set to said main memory means and processing means, directly coupled to and capable of directly addressing said second program storing means and to said main memory means and also operatively coupled to said first program storing means, said processing means being adapted to receive a reset signal, said process-ing means: (a) for reading said second instruction set from said second storing means and executing said second instruc-tion set in response to said reset signal, (b) for copying said predetermined instructions of said first instruction set from said first storing means to said main memory means under control of said second instruction set, and (c) for subse-quently reading said predetermined instructions of said first instruction set from said main memory means and executing said predetermined instructions.
main memory means for storing program control instructions;
first non-volatile program storing means for storing a first set of program control instructions;
second non-volatile program storing means for storing a second set of program control instructions, said second instruction set including instructions controlling the copying of predetermined instructions of said first instruc-tion set to said main memory means and processing means, directly coupled to and capable of directly addressing said second program storing means and to said main memory means and also operatively coupled to said first program storing means, said processing means being adapted to receive a reset signal, said process-ing means: (a) for reading said second instruction set from said second storing means and executing said second instruc-tion set in response to said reset signal, (b) for copying said predetermined instructions of said first instruction set from said first storing means to said main memory means under control of said second instruction set, and (c) for subse-quently reading said predetermined instructions of said first instruction set from said main memory means and executing said predetermined instructions.
2. A system as in claim 1 wherein said first non-volatile program storing means comprises a first semi-conductor read only memory, said second storing means comprises a second semiconductor read only memory, and said main memory means comprises a semiconductor random access read/write memory.
3. A system as in claim 2 wherein said first read only memory is capable of being erased and reprogrammed.
4. A system as in claim 1 wherein:
said first instruction set is stored in said first program storing means in at least first and second overlays; and said processor means first copies said first overlay to said main memory means under control of said second program control instruction set, and subsequent copies said second overlay to said main memory means under control of instructions included in said first overlay.
said first instruction set is stored in said first program storing means in at least first and second overlays; and said processor means first copies said first overlay to said main memory means under control of said second program control instruction set, and subsequent copies said second overlay to said main memory means under control of instructions included in said first overlay.
5. A system as in claim 1 wherein:
said first instruction set is organized into plural overlays, each of said plural overlays including at least one linking instruction, said linking instructions con-trolling said processor means to copy, from said first stor-ing means to said main memory means, an overlay other than the overlay said linking instruction is included within.
said first instruction set is organized into plural overlays, each of said plural overlays including at least one linking instruction, said linking instructions con-trolling said processor means to copy, from said first stor-ing means to said main memory means, an overlay other than the overlay said linking instruction is included within.
6. A system as in claim 1 further including data bus means for communicating said instructions between said first and second storing means, said main memory means and said processing means.
7. A system as in claim 1 wherein:
said processing means is adapted to receive a power supply voltage; and said apparatus further includes means for pro-ducing said predetermined signal whenever said power supply voltage is initially applied to said processing means.
said processing means is adapted to receive a power supply voltage; and said apparatus further includes means for pro-ducing said predetermined signal whenever said power supply voltage is initially applied to said processing means.
8. A system for processing digital signals compris-ing:
digital signal processing means of the type which executes program control instructions, said processing means being adapted to receive a power supply voltage;
high-speed semiconductor read only memory means, directly addressable by said processing means, for storing a first plurality of program instructions and for allowing said processor means to directly access said first plurality of program instructions stored therein;
further semiconductor read only memory means coupled to said processing means for storing a further plural-ity of said program instructions; and semiconductor random access read/write memory means, operatively connected to said processing means and to said further read only memory means, for storing program in-structions applied thereto;
said processing means for: (1) directly ad-dressing said first mentioned memory means in response to initial application of said power supply voltage to said processing means and for copying said further plurality of instructions from said further memory means to said read/write memory means under control of said first plurality of program instructions, and (2) for executing said further plurality of instructions copied into said read/write memory means.
digital signal processing means of the type which executes program control instructions, said processing means being adapted to receive a power supply voltage;
high-speed semiconductor read only memory means, directly addressable by said processing means, for storing a first plurality of program instructions and for allowing said processor means to directly access said first plurality of program instructions stored therein;
further semiconductor read only memory means coupled to said processing means for storing a further plural-ity of said program instructions; and semiconductor random access read/write memory means, operatively connected to said processing means and to said further read only memory means, for storing program in-structions applied thereto;
said processing means for: (1) directly ad-dressing said first mentioned memory means in response to initial application of said power supply voltage to said processing means and for copying said further plurality of instructions from said further memory means to said read/write memory means under control of said first plurality of program instructions, and (2) for executing said further plurality of instructions copied into said read/write memory means.
9. A system as in claim 8 wherein:
said further semiconductor read only memory means includes:
a semiconductor erasable programmable read only memory device, said device including a plurality of respec-tive addresssable locations storing said further plurality of program instructions, said further plurality of program in-structions being stored beginning at a predetermined starting location;
counting means, connected to said processing means and responsive to a load signal and to a starting ad-dress signal, for sequentially addressing said locations of said memory device beginning at a location specified by said starting address signal; and latch means, connected between said memory device and said random access memory means, for temporarily storing the program instructions contained in locations of said memory device addressed by said counting means until said random access memory means has stored said program instructions, wherein said processing means applies said load signal and a starting address signal specifying said predeter-mined starting location to said counting means in response to program instructions stored within said first-mentioned read only memory means.
said further semiconductor read only memory means includes:
a semiconductor erasable programmable read only memory device, said device including a plurality of respec-tive addresssable locations storing said further plurality of program instructions, said further plurality of program in-structions being stored beginning at a predetermined starting location;
counting means, connected to said processing means and responsive to a load signal and to a starting ad-dress signal, for sequentially addressing said locations of said memory device beginning at a location specified by said starting address signal; and latch means, connected between said memory device and said random access memory means, for temporarily storing the program instructions contained in locations of said memory device addressed by said counting means until said random access memory means has stored said program instructions, wherein said processing means applies said load signal and a starting address signal specifying said predeter-mined starting location to said counting means in response to program instructions stored within said first-mentioned read only memory means.
10. A system as in claim 8 wherein:
said processing means defines an addressing space encompassing a set of directly addressable locations from which said processing means obtains and executes program instructions; and said first-mentioned read only memory means in-cludes a first set of addressable locations and said random access memory means includes a second set of addressable locations, said first and second sets of addressable lo-cations both being included within said processing means addressing space.
said processing means defines an addressing space encompassing a set of directly addressable locations from which said processing means obtains and executes program instructions; and said first-mentioned read only memory means in-cludes a first set of addressable locations and said random access memory means includes a second set of addressable locations, said first and second sets of addressable lo-cations both being included within said processing means addressing space.
11. A system as in claim 8 wherein:
said further plurality of program instructions stored in said further memory means are organized into first and second overlays; and said processing means first copies all of the program instructions organized into said first overlay from said further memory means to said random access memory means under control of said first plurality of program instruc-tions, and subsequently copies all of the program instruc-tions organized into said second overlay from said further memory means to said random access memory means under control of said first overlay instructions.
said further plurality of program instructions stored in said further memory means are organized into first and second overlays; and said processing means first copies all of the program instructions organized into said first overlay from said further memory means to said random access memory means under control of said first plurality of program instruc-tions, and subsequently copies all of the program instruc-tions organized into said second overlay from said further memory means to said random access memory means under control of said first overlay instructions.
12. A digital signal processing system comprising:
data bus means for communicating signals asso-ciated with program instructions;
address bus means for communicating address signals;
first non-volatile memory means connected to said data bus means and to said address bus means for retain-ing a first plurality of program instructions and for apply-ing first signals associated with said first plurality of program instructions to said data bus means in response to the presence of first address signals on said address bus means;
second non-volatile memory means connected to said data bus means for retaining a second plurality of program instructions and for applying second signals asso-ciated with said second plurality of program instructions to said data bus means in response to a first control signal;
programmable main memory means, connected to said data bus means and to said address bus means and also connected to receive read and write control signals, for stor-ing program instructions associated with signals appearing on said data bus means in response to the presence of second ad-dress signals on said address bus means and in response to generation of a write control signal, and for applying the signals associated with said program instructions stored therein to said data bus means in response to presence of second address signals on said address bus means and in response to generation of a read control signal; and processing means, connected to said data bus means, said address bus means, said main memory means and said first memory means, said processing means capable of di-rectly addressing storage locations within said main memory means and said first memory means via said address bus means, for performing the following functions;
(1) applying first address signals to said ad dress bus means;
(2) generating said first control signal in response to the presence on said data bus means of said first signals applied thereto by said second memory means, thereby controlling said first memory means to apply said second sig-nals to said data bus means;
(3) applying second address signals to said ad-dress bus means and generating said write control signal so as to control said main memory means to store program instruc-tions associated with said second signals;
(4) applying second address signals to said ad-dress bus means and generating said read control signal so as to control said main memory means to apply to said data bus means the signals associated with said program instructions stored therein; and (5) performing tasks specified by said stored program instructions in response to said signals applied to said data bus means by said main memory means.
data bus means for communicating signals asso-ciated with program instructions;
address bus means for communicating address signals;
first non-volatile memory means connected to said data bus means and to said address bus means for retain-ing a first plurality of program instructions and for apply-ing first signals associated with said first plurality of program instructions to said data bus means in response to the presence of first address signals on said address bus means;
second non-volatile memory means connected to said data bus means for retaining a second plurality of program instructions and for applying second signals asso-ciated with said second plurality of program instructions to said data bus means in response to a first control signal;
programmable main memory means, connected to said data bus means and to said address bus means and also connected to receive read and write control signals, for stor-ing program instructions associated with signals appearing on said data bus means in response to the presence of second ad-dress signals on said address bus means and in response to generation of a write control signal, and for applying the signals associated with said program instructions stored therein to said data bus means in response to presence of second address signals on said address bus means and in response to generation of a read control signal; and processing means, connected to said data bus means, said address bus means, said main memory means and said first memory means, said processing means capable of di-rectly addressing storage locations within said main memory means and said first memory means via said address bus means, for performing the following functions;
(1) applying first address signals to said ad dress bus means;
(2) generating said first control signal in response to the presence on said data bus means of said first signals applied thereto by said second memory means, thereby controlling said first memory means to apply said second sig-nals to said data bus means;
(3) applying second address signals to said ad-dress bus means and generating said write control signal so as to control said main memory means to store program instruc-tions associated with said second signals;
(4) applying second address signals to said ad-dress bus means and generating said read control signal so as to control said main memory means to apply to said data bus means the signals associated with said program instructions stored therein; and (5) performing tasks specified by said stored program instructions in response to said signals applied to said data bus means by said main memory means.
13. An apparatus as in claim 12 wherein said first and second non-volatile memory means each comprise a semi-conductor programmable read only memory and said programmable main memory means comprises a semiconductor random access memory.
14. An apparatus as in claim 13 wherein said second memory means is capable of being erased and reprogrammed.
15. An apparatus as in claim 12 wherein:
said second memory means stores said signals associated with said second plurality of program instructions in respective storage locations; and said second memory means includes counting means, responsive to said first control signal, for generat-ing address signals and for indexing the second memory means respective locations with said last-mentioned address signals.
said second memory means stores said signals associated with said second plurality of program instructions in respective storage locations; and said second memory means includes counting means, responsive to said first control signal, for generat-ing address signals and for indexing the second memory means respective locations with said last-mentioned address signals.
16. An apparatus as in claim 15 wherein:
said counting means includes programmable counter means, connected to said data bus means and to said processing means, for addressing a plurality of respective storage locations of said second memory means beginning at a predetermined storage location, said programmable counter means also for indexing said predetermined storage location in response to load signal generated by said processing means and a signal appearing on said data bus means representing said predetermined storage location; and said processing means also performs the func-tions of (a) applying said signal representing said predeter-mined storage location to said data bus means, and (b) gener-ating said load signal.
said counting means includes programmable counter means, connected to said data bus means and to said processing means, for addressing a plurality of respective storage locations of said second memory means beginning at a predetermined storage location, said programmable counter means also for indexing said predetermined storage location in response to load signal generated by said processing means and a signal appearing on said data bus means representing said predetermined storage location; and said processing means also performs the func-tions of (a) applying said signal representing said predeter-mined storage location to said data bus means, and (b) gener-ating said load signal.
17. An apparatus as in claim 15 further including latch means, connected between said second memory means and said data bus means, for temporarily storing signals asso-ciated with said second plurality of program instructions until said signals have been copied to said main memory means.
18. An apparatus as in claim 12 wherein said pro-cessing means includes address decoding means for alternately producing said first and said second address signals.
19. A system as in claim 12 wherein:
said second plurality of program instructions are stored in said second memory means in at least first and second overlays, said first and second overlays each defining a predetermined function; and said processing means selects said first over-lay in response to said signals applied to said data bus means associated with said first plurality of program instruc-tions, and selects said second overlay in response to at least one of said program instructions included in said first overlay.
said second plurality of program instructions are stored in said second memory means in at least first and second overlays, said first and second overlays each defining a predetermined function; and said processing means selects said first over-lay in response to said signals applied to said data bus means associated with said first plurality of program instruc-tions, and selects said second overlay in response to at least one of said program instructions included in said first overlay.
20. A method of initializing a digital signal pro-cessing system, said method including the steps of:
(1) maintaining a first set of instructions in a first non-volatile program store;
(2) maintaining a second set of instructions in a second non-volatile program store, said second instruc-tion set including instructions controlling the copying of said first instruction set into a main memory;
(3) directly addressing said second store with a processor and executing said second instruction set out of said second store with said processor in response to a reset signal received by said processor;
(4) copying, with said processor, said first set of instructions from said first store to said main memory under control of said second instruction set; and (5) executing with said processor the instruc-tions stored in said main memory.
(1) maintaining a first set of instructions in a first non-volatile program store;
(2) maintaining a second set of instructions in a second non-volatile program store, said second instruc-tion set including instructions controlling the copying of said first instruction set into a main memory;
(3) directly addressing said second store with a processor and executing said second instruction set out of said second store with said processor in response to a reset signal received by said processor;
(4) copying, with said processor, said first set of instructions from said first store to said main memory under control of said second instruction set; and (5) executing with said processor the instruc-tions stored in said main memory.
21. A method as in claim 20 wherein:
said maintaining step (1) includes the step of maintaining at least first and second instruction set over-lays each including a set of instructions;
said copying step (4) includes copying said first overlay from said first store to said main memory;
said first overlay includes instructions con-trolling copying of said second overlay from said first store to said main memory; and said method further includes the step of copy-ing said second overlay from said first store to said main memory with said processor with the control of said first overlay instructions.
said maintaining step (1) includes the step of maintaining at least first and second instruction set over-lays each including a set of instructions;
said copying step (4) includes copying said first overlay from said first store to said main memory;
said first overlay includes instructions con-trolling copying of said second overlay from said first store to said main memory; and said method further includes the step of copy-ing said second overlay from said first store to said main memory with said processor with the control of said first overlay instructions.
22. A method as in claim 20 wherein:
said first set of instructions are organized in a plurality of overlays specifying different predetermined tasks;
said copying step (4) includes copying a first of said plurality of overlays from said first store to said main memory; and said predetermined tasks specified by said first overlay includes a linking task controlling copying of a further overlay to said main memory.
said first set of instructions are organized in a plurality of overlays specifying different predetermined tasks;
said copying step (4) includes copying a first of said plurality of overlays from said first store to said main memory; and said predetermined tasks specified by said first overlay includes a linking task controlling copying of a further overlay to said main memory.
23. A method as in claim 20 wherein said addressing step (3) and said executing step (5) each include the step of conveying signals along a data bus, said data bus communicat-ing with said first and second program stores, said pro-cessor, and said main memory.
24. A method of initializing a digital signal pro-cessing system comprising the steps of:
(1) providing read only memory means having program instructions stored therein;
(2) accessing said read only memory means with a microprocessor and executing said program instructions with said microprocessor in response to the initial application of a power supply voltage, said executing step including the step of loading ones of a further plurality of program in-structions stored in a further semiconductor read only memory means and selected by said first-mentioned program instruc-tions into a semiconductor random access memory means with said microprocessor under control of said first-mentioned program instructions; and (3) executing with said microprocessor the program instructions stored in said semiconductor random access memory means.
(1) providing read only memory means having program instructions stored therein;
(2) accessing said read only memory means with a microprocessor and executing said program instructions with said microprocessor in response to the initial application of a power supply voltage, said executing step including the step of loading ones of a further plurality of program in-structions stored in a further semiconductor read only memory means and selected by said first-mentioned program instruc-tions into a semiconductor random access memory means with said microprocessor under control of said first-mentioned program instructions; and (3) executing with said microprocessor the program instructions stored in said semiconductor random access memory means.
25. A method as in claim 24 wherein said step of loading said selected ones of said further plurality of program instructions includes the steps of:
loading, in response to program instructions stored by one of said first-mentioned read only memory means, a starting address into a programmable counter;
sequentially addressing locations of said further semiconductor read only memory means with the output of said counter by incrementing said starting address loaded n said counter; and temporarily buffering the program instructions contained in the location of said further semiconductor read only memory means addressed by said counter until said random access memory means has stored said program instructions.
loading, in response to program instructions stored by one of said first-mentioned read only memory means, a starting address into a programmable counter;
sequentially addressing locations of said further semiconductor read only memory means with the output of said counter by incrementing said starting address loaded n said counter; and temporarily buffering the program instructions contained in the location of said further semiconductor read only memory means addressed by said counter until said random access memory means has stored said program instructions.
26. A method as in claim 24 wherein:
said further program instructions stored in said further read only memory means are organized in plural overlays; and said executing step (3) includes the step of selecting all of the program instructions stored in a first of said overlays and storing said selected program instruc-tions in said random access memory means.
said further program instructions stored in said further read only memory means are organized in plural overlays; and said executing step (3) includes the step of selecting all of the program instructions stored in a first of said overlays and storing said selected program instruc-tions in said random access memory means.
27. A method initializing a digital signal process-ing system comprising the steps of:
(1) reading signals associated with a first plurality of program instructions directly from a first non-volatile memory with a digital signal processor in re-sponse to the application of an externally applied signal;
(2) executing said first plurality of instruc-tions with said digital signal processor in response to said signals read by said reading step, said executing step includ-ing controlling a second non-volatile memory to apply signals associated with a second plurality of program instructions stored in said second non-volatile memory to a data bus;
(3) storing said applied signals associated with said second plurality of program instructions into a main memory;
(4) addressing said main memory with said digital signal processor to cause signals associated with said second plurality of program instructions stored in said main memory to appear on said data bus; and (5) executing said second plurality of program instructions with said digital signal processor in response to the appearance on said data bus of the signals associated with said second plurality of program instructions.
(1) reading signals associated with a first plurality of program instructions directly from a first non-volatile memory with a digital signal processor in re-sponse to the application of an externally applied signal;
(2) executing said first plurality of instruc-tions with said digital signal processor in response to said signals read by said reading step, said executing step includ-ing controlling a second non-volatile memory to apply signals associated with a second plurality of program instructions stored in said second non-volatile memory to a data bus;
(3) storing said applied signals associated with said second plurality of program instructions into a main memory;
(4) addressing said main memory with said digital signal processor to cause signals associated with said second plurality of program instructions stored in said main memory to appear on said data bus; and (5) executing said second plurality of program instructions with said digital signal processor in response to the appearance on said data bus of the signals associated with said second plurality of program instructions.
28. A method as in claim 27 wherein said externally applied signal is produced whenever a power supply voltage is initially applied to said processor.
29. A method as in claim 27 wherein:
said applying step supplies signals associated with selected subsets of second plurality of program instruc-tions to said data bus, said subsets being selected by said first plurality of program instructions and/or a previously selected subset; and said storing step (3), said addressing step (4) and said performing step (5) are repeated for a plurality of said subsets.
said applying step supplies signals associated with selected subsets of second plurality of program instruc-tions to said data bus, said subsets being selected by said first plurality of program instructions and/or a previously selected subset; and said storing step (3), said addressing step (4) and said performing step (5) are repeated for a plurality of said subsets.
30. In a digital signal processing system of the type including a microprocessor connected to a volatile random access memory read/write store via an address bus and a data bus, said address bus communicating address signals produced by said microprocessor, said address signals select-ing storage locations within said read/write store, said data bus communicating signals stored in selected storage locations to said microprocessor, said communicated data signals representing program instructions which said microprocessor executes to perform tasks, an improved method of initializing said system comprising the steps of:
(1) in response to an externally generated reset signal, generating first address signals with said microprocessor and applying said first address signals to said at address bus;
(2) inhibiting said read/write store from re-sponding to said first address signals;
(3) selecting storage locations within a non-volatile bootstrap store high-speed read only memory also connected to said address bus and to said data bus with said generated first address signals, said bootstrap store read only memory retaining signals representing initialization pro-gram instructions;
(4) applying the initialization program in-struction signals stored in said selected bootstrap read only memory storage locations to said data bus;
(5) executing said initialization program in-structions with said microprocessor in response to said signals applied to said data bus by said applying step (4), including the step of controlling a further non-volatile pro-gram store to apply further signals representing program instructions to said data bus;
(6) applying second address signals to said ad-dress bus and controlling said read/write store to store said further signals therein in storage locations selected by said second address signals;
(7) applying third address signals to said ad-dress bus and controlling said read/write store to apply said stored said further signals to said data bus; and (8) performing tasks represented by said further signals applied to said data bus by said applying step (7) with said microprocessor.
(1) in response to an externally generated reset signal, generating first address signals with said microprocessor and applying said first address signals to said at address bus;
(2) inhibiting said read/write store from re-sponding to said first address signals;
(3) selecting storage locations within a non-volatile bootstrap store high-speed read only memory also connected to said address bus and to said data bus with said generated first address signals, said bootstrap store read only memory retaining signals representing initialization pro-gram instructions;
(4) applying the initialization program in-struction signals stored in said selected bootstrap read only memory storage locations to said data bus;
(5) executing said initialization program in-structions with said microprocessor in response to said signals applied to said data bus by said applying step (4), including the step of controlling a further non-volatile pro-gram store to apply further signals representing program instructions to said data bus;
(6) applying second address signals to said ad-dress bus and controlling said read/write store to store said further signals therein in storage locations selected by said second address signals;
(7) applying third address signals to said ad-dress bus and controlling said read/write store to apply said stored said further signals to said data bus; and (8) performing tasks represented by said further signals applied to said data bus by said applying step (7) with said microprocessor.
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Families Citing this family (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06103460B2 (en) * | 1985-11-19 | 1994-12-14 | ソニー株式会社 | Program transfer method |
| DE3639571A1 (en) * | 1986-11-20 | 1988-06-01 | Standard Elektrik Lorenz Ag | METHOD AND CIRCUIT ARRANGEMENT FOR CHARGING A SECONDARY COMPUTER |
| GB2201816A (en) * | 1987-02-27 | 1988-09-07 | Mitac Inc | High speed digital processor |
| US5155833A (en) * | 1987-05-11 | 1992-10-13 | At&T Bell Laboratories | Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory |
| US5093915A (en) * | 1988-11-02 | 1992-03-03 | Xerox Corporation | Method for selectively loading bootable fiber to control apparatus based upon the corresponding bootable attributes |
| FR2645989A1 (en) * | 1989-04-17 | 1990-10-19 | Bull Sa | MULTIFUNCTION COUPLER BETWEEN A CENTRAL COMPUTER UNIT AND THE DIFFERENT PERIPHERAL ORGANS OF THE SAME |
| US5440749A (en) * | 1989-08-03 | 1995-08-08 | Nanotronics Corporation | High performance, low cost microprocessor architecture |
| US5307464A (en) * | 1989-12-07 | 1994-04-26 | Hitachi, Ltd. | Microprocessor and method for setting up its peripheral functions |
| US5557799A (en) * | 1990-03-22 | 1996-09-17 | International Business Machines | Computer determination of operating system or data |
| JP2772103B2 (en) * | 1990-03-28 | 1998-07-02 | 株式会社東芝 | Computer system startup method |
| JPH0476681A (en) * | 1990-07-13 | 1992-03-11 | Mitsubishi Electric Corp | Microcomputer |
| JPH0792744B2 (en) * | 1990-08-20 | 1995-10-09 | インターナショナル・ビジネス・マシーンズ・コーポレイション | A method of installing multi-level application software on a data processing device. |
| DE69130667T2 (en) * | 1990-12-06 | 1999-05-06 | Tandberg Data | Data storage system with removable media for loading a control program from the removable media |
| US5799186A (en) * | 1990-12-20 | 1998-08-25 | Eastman Kodak Company | Method and apparatus for programming a peripheral processor with a serial output memory device |
| US5594903A (en) * | 1991-02-26 | 1997-01-14 | Lynx Real-Time Systems, Inc. | Operating System architecture with reserved memory space resident program code identified in file system name space |
| JPH06214670A (en) * | 1991-04-29 | 1994-08-05 | Intel Corp | Computer system and method for initializing it |
| US5471674A (en) * | 1992-02-07 | 1995-11-28 | Dell Usa, L.P. | Computer system with plug-in override of system ROM |
| US5261055A (en) * | 1992-02-19 | 1993-11-09 | Milsys, Ltd. | Externally updatable ROM (EUROM) |
| US6131159A (en) * | 1992-05-08 | 2000-10-10 | Paradyne Corporation | System for downloading programs |
| US5511183A (en) * | 1992-05-12 | 1996-04-23 | Fujitsu Limited | Non-volatile memory controlling apparatus and applications of the same to electronic computer peripheral equipments |
| EP0592079A2 (en) * | 1992-09-20 | 1994-04-13 | Sun Microsystems, Inc. | Automated software installation and operating environment configuration on a computer system |
| US6101421A (en) * | 1993-09-10 | 2000-08-08 | Motorola, Inc. | Reset recovery in a microprocessor controlled device |
| US5586327A (en) * | 1994-09-27 | 1996-12-17 | International Business Machines Corporation | Extended initialization for personal data processing systems |
| US5606710A (en) * | 1994-12-20 | 1997-02-25 | National Semiconductor Corporation | Multiple chip package processor having feed through paths on one die |
| DE19506957C2 (en) * | 1995-02-28 | 1999-01-07 | Siemens Ag | Method for updating and loading user programs in a program memory of a microprocessor system |
| FR2733612B1 (en) | 1995-04-28 | 1997-06-13 | Sgs Thomson Microelectronics | DEVICE FOR COMMISSIONING AN INTEGRATED CIRCUIT |
| KR100198382B1 (en) * | 1996-05-07 | 1999-06-15 | 윤종용 | Computer with multi-booting function |
| US6636963B1 (en) * | 1999-12-30 | 2003-10-21 | Cardiac Pacemakers, Inc. | Quick starting for microprocessor-based system by retrieving a target state memory image and a target state data structure from an image storage medium |
| US20020150185A1 (en) * | 2001-03-29 | 2002-10-17 | Joseph Meehan | Diversity combiner for reception of digital television signals |
| US7373491B2 (en) * | 2002-02-27 | 2008-05-13 | Rockwell Automation Technologies, Inc. | Processor with versatile external memory interface |
| US6970985B2 (en) * | 2002-07-09 | 2005-11-29 | Bluerisc Inc. | Statically speculative memory accessing |
| US20050114850A1 (en) * | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
| US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
| US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
| US7529921B2 (en) * | 2004-12-17 | 2009-05-05 | Cardiac Pacemakers, Inc. | Fast initialization of medical device system having multiple operating systems |
| KR100776112B1 (en) * | 2006-02-15 | 2007-11-15 | 삼성전자주식회사 | Method for reducing booting time in wireless terminal |
| US20070294181A1 (en) * | 2006-05-22 | 2007-12-20 | Saurabh Chheda | Flexible digital rights management with secure snippets |
| US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
| US20080154379A1 (en) * | 2006-12-22 | 2008-06-26 | Musculoskeletal Transplant Foundation | Interbody fusion hybrid graft |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3778775A (en) * | 1971-05-10 | 1973-12-11 | Computek Inc | Microprogrammed terminal |
| US4025904A (en) * | 1973-10-19 | 1977-05-24 | Texas Instruments Incorporated | Programmed allocation of computer memory workspace |
| US4085442A (en) * | 1975-03-31 | 1978-04-18 | Bunker Ramo Corporation | Data display system designed as a microcontroller |
| JPS51127626A (en) * | 1975-04-30 | 1976-11-06 | Hitachi Ltd | Information processor |
| US4038643A (en) * | 1975-11-04 | 1977-07-26 | Burroughs Corporation | Microprogramming control system |
| IT1052738B (en) * | 1975-12-24 | 1981-07-20 | Cselt Centro Studi Lab Telecom | DEVICE FOR AUTOMATIC LOADING OF THE CENTRAL MEMORY OF ELECTRONIC CALCULATORS |
| US4080652A (en) * | 1977-02-17 | 1978-03-21 | Xerox Corporation | Data processing system |
| US4080651A (en) * | 1977-02-17 | 1978-03-21 | Xerox Corporation | Memory control processor |
| US4126894A (en) * | 1977-02-17 | 1978-11-21 | Xerox Corporation | Memory overlay linking system |
| US4165534A (en) * | 1977-04-25 | 1979-08-21 | Allen-Bradley Company | Digital control system with Boolean processor |
| US4204206A (en) * | 1977-08-30 | 1980-05-20 | Harris Corporation | Video display system |
| US4172281A (en) * | 1977-08-30 | 1979-10-23 | Hewlett-Packard Company | Microprogrammable control processor for a minicomputer or the like |
| US4204208A (en) * | 1977-08-30 | 1980-05-20 | Harris Corporation | Display of video images |
| US4203154A (en) * | 1978-04-24 | 1980-05-13 | Xerox Corporation | Electronic image processing system |
| US4313158A (en) * | 1978-12-11 | 1982-01-26 | Honeywell Information Systems Inc. | Cache apparatus for enabling overlap of instruction fetch operations |
| US4295192A (en) * | 1979-04-13 | 1981-10-13 | Sperry Rand Corporation | Row address memory map overlap |
| US4430704A (en) * | 1980-01-21 | 1984-02-07 | The United States Of America As Represented By The Secretary Of The Navy | Programmable bootstrap loading system |
| US4403283A (en) * | 1980-07-28 | 1983-09-06 | Ncr Corporation | Extended memory system and method |
| JPS57176456A (en) * | 1981-04-22 | 1982-10-29 | Fanuc Ltd | Data processing system |
| US4654783A (en) * | 1982-07-26 | 1987-03-31 | Data General Corporation | Unique process for loading a microcode control store in a data processing system |
| JPS5960464A (en) * | 1982-09-30 | 1984-04-06 | 株式会社東芝 | Program ciphering system |
-
1984
- 1984-05-30 US US06/615,362 patent/US4720812A/en not_active Expired - Fee Related
-
1985
- 1985-05-10 CA CA000481285A patent/CA1235227A/en not_active Expired
- 1985-05-15 GB GB08512329A patent/GB2162346B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2162346B (en) | 1988-11-16 |
| US4720812A (en) | 1988-01-19 |
| GB8512329D0 (en) | 1985-06-19 |
| GB2162346A (en) | 1986-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |