CA1234224A - Computer memory management system - Google Patents
Computer memory management systemInfo
- Publication number
- CA1234224A CA1234224A CA000482566A CA482566A CA1234224A CA 1234224 A CA1234224 A CA 1234224A CA 000482566 A CA000482566 A CA 000482566A CA 482566 A CA482566 A CA 482566A CA 1234224 A CA1234224 A CA 1234224A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- signals
- aye
- predetermined
- ones
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0653—Configuration or reconfiguration with centralised address assignment
Abstract
ABSTRACT
A computer memory management system for detecting the presence of memory chips connected to predetermined memory banks of a plurality of memory modules in a computer system, receiving and remapping address signals, and contiguously enabling the predetermined memory banks in response thereto. A
programmable logic array generates enable signals for enabling the predetermined memory banks of the memory modules in response to receiving address and control signals from a main controller. The remapping process is performed during power Up such that no wait states are introduced during subsequent memory accesses. The system is self-adaptive and inexpensive.
A computer memory management system for detecting the presence of memory chips connected to predetermined memory banks of a plurality of memory modules in a computer system, receiving and remapping address signals, and contiguously enabling the predetermined memory banks in response thereto. A
programmable logic array generates enable signals for enabling the predetermined memory banks of the memory modules in response to receiving address and control signals from a main controller. The remapping process is performed during power Up such that no wait states are introduced during subsequent memory accesses. The system is self-adaptive and inexpensive.
Description
I
01 This invention relates in general to 02 computer systems, and in particular to a memory 03 management system for detecting the presence of memory 04 circuits in a computer system and remapping memory 05 addresses in response thereto.
06 Computer systems are typically comprised 07 ox one or more memory modules comprised of a plurality 08 of memory banks to which memory circuits, such as 09 dynamic random access memory chips (Drams), are lo connected. A main controller (erg. a CPU) typically if generates address signals for accessing predetermined 12 memory locations of the memory circuits. For example, 13 an address signal is usually received by the memory 14 modules and decoded therein, such that a predetermined one of the memory banks is enabled and a predetermined I DRAM memory location defined by the address signal, is 17 accessed.
18 In a straightforward computer system 19 having a fixed (non-expandable) amount of memory, there is typically a one-to-one correspondence 21 (mapping) between the generated address signals and 22 the DRAM memory locations.
23 It is desirable that the number of memory 24 banks be expandable, thereby accommodating a greater number ox memory circuits, in order to implement I software revisions, or store large amounts of data, 27 etc. In order to effect memory expansion in the past, 28 costly redesign and rewiring of memory module address 29 decoding circuitry was typically required.
One prior art memory management system 31 sought to overcome the disadvantages of costly 32 redesign and rewiring by utilizing a plurality of 33 hardware address multiplexes and an operating system 34 program which included a subroutine for remapping address signals during execution of an application 36 program. The remapping process was said to be 37 "on-line". The remapped address signals were then 38 - l -~23~
01 used for accessing the actual DRAM memory locations.
02 The aforementioned remapping subroutine and additional 03 hardware was complex, and execution of the subroutine 04 was found to be time consuming. Typically, one or 05 more main controller wait states were required to 06 implement the address remapping since a multiplicity 07 of bank switching access instructions were inserted in 08 the program code, thereby substantially reducing speed 09 of execution of the application program as well as increasing the likelihood of memory access errors.
11 The remapping subroutine was dedicated, or 12 non self-adaptive, since further memory expansion or 13 reduction) required modification ox various parameters 14 of the program which in turn, usually required replacement of a floppy disk or ROM on which the 16 operating system program was stored.
17 According to the present invention, an 18 inexpensive, self-adaptive memory management system 19 is provided for detecting the presence of memory circuits connected to predetermined memory banks of a 21 plurality of memory modules in a computer system, and 22 during an initialization procedure remapping address 23 signals generated by a main controller and 24 subsequently generating enable signals for contiguously enabling the predetermined memory banks.
26 According to a preferred embodiment, the 27 enable signal circuits are comprised of programmable 28 logic circuits generating the aforementioned enable 29 signals for enabling the predetermined ones of the memory banks during each memory access without 31 requiring any extra time penalty in the form of wait 32 states.
33 A typical computer system may haze two 34 memory modules, denoted as main and expander memory modules, wherein each module accommodates up to 2.5M
36 bytes of memory using five 512k byte memory banks.
37 Emory addresses of the main and expander modules are '"
~234~2~
01 required to be contiguous. Thus, the first memory 02 location of the expander memory module would have an 03 address of 280000 (hex). However, in the event the 04 main memory module is not filled to capacity (2.5 M
05 bytes), but actually has only lo byte of DRAM chips 06 connected thereto (i.e. two of the five memory 07 banks are filled, the last valid memory address on 08 the main memory module is OFF (hex), and the next 09 contiguous address would be 100000 (hex).
According to the present invention only lo 11 byte of memory would be detected on the main memory 12 module, and in response predetermined control signals 13 are transmitted to the enable signal circuits such 14 that, in the event the main controller generates an address signal of 100000 (hex), the enable signal 16 circuits on the expander module remap the memory 17 locations starting at 2~30000 (hex) to an address of 18 100000 (hex) and the enable signal circuits on the 19 main memory module disable the memory address space from 100000 (hex) such that the access is made to the 21 first location on the expander memory module and not 22 the location 100000 on the main memory module. Thus, 23 the second memory bank of the main memory module is 24 made contiguous with the first bank of the expander module.
26 The system is inexpensive, and the memory 27 detection process is preferably performed prior to the 28 first memory access (i.e. during power-up), such that 29 no wait states are required to be executed during subsequent memory accesses, as in the prior art 31 "on-line" technique.
32 In the event further banks of the main 33 memory module are filled it the third, fourth or 34 fifth banks, etc.`, the memory management system detects the presence of the expanded memory during 36 initialization or power-up, and remaps the first 37 memory location of the memory module so as to be I
01 contiguous with the last valid memory address of the 02 expander main memory module. Hence, the system is 03 self-adaptlve and the prior art disadvantage of 04 requiring revision of the operating system program by 05 replacement of a floppy disk or ROM, or by extensive 06 redesign and rewiring, is overcome.
07 In general, the invention is a computer 08 memory management system for connection to a plurality 09 of memory modules each having a plurality of memory banks thereof, predetermined ones of which have one or 11 more memory circuits connected thereto. The invention 12 is comprised of a circuit for generating address 13 signals, circuitry for receiving first ones of the 14 address signals and detecting the presence of memory circuits connected to the predetermined memory banks 16 in response thereto, and circuitry for receiving and 17 remapping further ones of the address signals and 18 contiguously enabling the predetermined memory banks 19 in response thereto, whereby variations in the number of memory circuits connected to the aforementioned 21 plurality of memory modules is automatically 22 compensated for while addressing said modules.
23 More particularly the invention is a 24 computer memory management system for connection to a plurality memory each having a plurality of memory 26 banks thereof, predetermined ones of which have one or 27 memory circuits connected thereto. The invention is 28 comprised of a circuit generating address signals, a 29 circuit for receiving predetermined first ones of the address signals and generating enable signals for 31 enabling successive ones of the plurality of memory 32 banks in response thereto, a circuit for detecting the 33 presence of memory circuits connected to predetermined 34 ones of the aforementioned successfully enabled memory banks and generating one or more control signals in 36 response thereto, and a circuit for receiving the 37 control signals and further ones of the address ~L23~
01 signals, remapping received further address signals 02 and contiguously enabling the predetermined memory 03 banks in response thereto.
04 The invention is also a method of computer 05 memory management for use in conjunction with one or 06 more memory modules each having a plurality of memory 07 banks, predetermined ones of which have one or more 08 memory circuits connected thereto, comprising the 09 steps of generating address and control signals, receiving first ones of the address and control 11 signals and detecting the presence of memory circuits 12 connected to the predetermined memory banks in 13 response thereto, and receiving second ones of the 14 address and control signals and contiguously enabling corresponding ones of the predetermined memory banks 16 in response to receiving the second address and 17 control signals and the detection of the presence of 18 the memory circuits.
19 A better understanding of the invention will be obtained with reverence to the detailed 21 description below, in conjunction with the following 22 drawings, in which:
23 Figure l is a block diagram of a memory 24 management system according to the present invention, and 26 Figure 2 is a schematic diagram of an 27 enable signal generation circuit according to a 28 preferred embodiment of the present invention.
29 With reference to Figure 1, a main memory module 1 and an expander memory module 2 are each 31 comprised of a plurality of memory banks 32 By, By, B2BN. Each memory bank is typically 33 comprised of one or more DRAM chips (such as 64k or 34 256k DRAM chips). Data terminals of respective ones of the memory banks are connected to a data bus 3, and 36 address inputs to the memory banks are connected to 37 address lines Allah of an address bus 4 connected to . . , :~LZ3~iL2~
01 main controller 5, such as a microprocessor.
02 First and second enable signal generation 03 circuits PA and 6B have enable outputs thereof 04 connected to inputs of respective ones of the memory 05 banks By, By, B2BN in the main and expander memory 06 modules 1 and 2. A first plurality of address inputs 07 to the enable signal circuits are connected to Ai-Aj 08 address lines ox the address bus 4, and a second 09 plurality of inputs are connected to a control bus 7 connected to the main controller 5. In addition, a 12 RSTVEC signal output from the main controller 5 is 13 connected to a further input of enable signal circuit 14 PA and via a latch 8 to a further input of enable signal circuit 6B, under control of signals on the 16 address and control buses 4 and 7 respectively.
17 In operation, the main controller 5 18 generates predetermined address and control signals on the address and control busses 4 and 7, and on the 21 RSTYEC output thereof, for application to enable 22 signal circuit PA. In response, circuit PA under 23 software control successively enables memory banks By, 24 By, B2BN of the main memory module 1, and the main controller 5 detects the presence of memory chips 26 connected thereto.
27 For example, memory bank By is enabled by 28 the enable signal circuit PA and the main controller 5 29 venerates a data signal on data bus 3 for storage in a predetermined location ox memory bank By. Next, the 31 main controller 5 reads the data signal stored in the 32 predetermined location. In the event memory bank By 33 has DRAM chips connected thereto, the main controller 34 5 reads the data signal previously stored therein.
However, in the event memory bank By has no DRAM chips 36 connected thereto, a default signal of or example 37 OF hex), is read by the main controller 5 in response ~2342Z~
01 to accessing the non-existent DRAM chips. In the 02 event of detection of DRAM chips, memory bank By is 03 maintained enabled and bank By is enabled and the DRAM
04 chip detection process is repeated.
05 In the event of detection of an empty 06 memory bank (i.e. a bank having no DRAM chips 07 connected thereto), the main controller 5 disables the 08 empty memory bank and stores predetermined control 09 signals in enable signal circuits indicative of the number of memory banks By, By, B2.~.BN of main memory 11 module 1 having DRAM chips connected thereto, such 12 that the first valid memory location of expander 13 memory module 2 is remapped so as to be contiguous 14 with the last valid location of the main memory module 1, as described in greater detail below with respect 16 to Figure 2.
17 Hence, during execution of a program by 18 the main controller 5, memory addresses are remapped 19 by the circuits PA and 6B so as to enable contiguous memory locations of the main and expander memory I modules 1 and 2, respectively.
23 The RSTVEC signal is a reset signal which 24 disables all memory modules during a system reset to allow a vector fetch from ROM. It alternately enables 26 the main expander memory modules via latch 8 in order 27 to resolve data bus contention during the remapping 28 process.
29 With reference to Figure 2, a schematic ; 30 diagram of the enable signal circuit PA or 6B is 31 illustrated. According to the preferred embodiment of 32 the invention, each of the modules 1 and 2 is 33 comprised of five memory banks denoted B0-B4. A
34 programmable array logic (PAL) 9 is shown having ADDRESS inputs thereof connected to address lines 36 AYE of the address bus 4. The address lines 37 AYE correspond to address lines Ai-Aj in Figure 38 1. Data lines D0-D4 of the data bus 3 (Figure 1) are :
~3~2~
01 connected to data inputs lD-5D respectively, of a data 82~ register 10. A reset input of register 10 is 04 connected to a RESET control line of control bus 7.
05 Outputs lo, 2Q, 3Q, 4Q and 5Q of register 10 are 06 connected to control inputs CURL of PAL 9, and 07 generate control signals A, B, C, D and X
I respectively, described in further detail below.
A further control input of PAL 9, denoted as RSTVEC, 12 is connected to the RSTVEC output of the main 13 controller 5 as discussed above with reference to I Figure 1, or in the case of enable signal circuit 6B, ho the RSTVEC input of PAL 9 is connected to the output 18 of latch 8 connected to the RSTVEC output of main I controller 5.
I Outputs RCAS0, RCASl, RING, RCAS3 and 23 RCAS4 of PAL 9 are connected to first inputs of RAND
24 gates 11, 12, 13, 14 and 15 respectively, and to NOT
gates 16, 17, 18, 19 and 20 respectively. Second 26 inputs of RAND gates 11-15 are connected to an output 27 of RAND gate 21.
28 A first input of RAND gate 21 is connected 3209 to an output of a NOT gate 22, an input of which is 31 connected to a REFRESH control line of control bus 7 32 connected to controller 5. A second input of RAND
33 gate 21 is connected to the output of series connected 34 NOT gates 23 and 24. An input of gate 24 is connected to an address line Aye of the main controller 5, and 36 an output thereof is connected to an input of NOT gate 37 23.
38 Outputs of RAND gates 11-15 are connected 39 to first inputs of RAND gates 25-29 respectively, and the outputs of NOT gates 16-20 are connected to first 41 inputs of a plurality of RAND gates 30-34 I
01 respectively. Outputs of RAND gazes 25-34 are 02 connected to output resistors 35-44, respectively.
I Output resistors 35-39 are connected to 05 row address select output terminals ROUSERS
8q respectively, and output resistors 40-4~ are 08 connected to column address select terminals CAS0-CAS4 respectively. The row and column address output 11 terminals RUSES and CASO-CAS4 are connected to row 12 and column enable inputs of respective ones of memory banks B0-B4, of the main memory module 1.
An address select output AS from the main 16 controller 5 is connected to a NOT gate 45, an output 17 of which is connected to second inputs of RAND gates 18 25-29, and to an input (IN) of a delay line 46, an 19 output (OUT) thereof being connected to second inputs of RAND gates 30-34.
21 In operation, the amount of memory 22 connected to adjacent ones of the memory banks B0-B4 23 of the main memory module 1 (Figure 1) is first detected. PAL 9 generates active low signals on 26 predetermine ones of the outputs RCAS0-RCAS4 in 27 response to receiving predetermined signals on the 28 address and control inputs (ADDRESS and CURL) thereof, 29 as a result of being programmed in a well known manner according to equations set out below with reference to 31 TABLES 1 and 2.
32 According to the preferred embodiment, 33 memory modules 1 and 2 (Figure 1) are each comprised 34 of five memory banks B0-B4 containing 64k or 256k byte DRAM chips, as discussed above. In the event main 36 memory module 1 is comprised of 64k chips, it will 37 accommodate up to 640k bytes of data. In the event 38 the main memory module is comprised of 256k chips, it 39 will accommodate up to 2.5M bytes of data. Similarly, the expander memory module 2 will also accommodate 41 either 64k or 256k chips, but not both.
I _ 9 _ 4~2~
I PAL equations for generating the active 03 low enable signals on the RCAS0-RCAS4 outputs, for 04 enabling predetermined ones ox the memory kinks, are 05 illustra~d in TABLES 1 and 2 respectively.
08 PAL EQUATIONS FOR 64k CHIPS
O 9 _ I ho J AYE tall ZOO AYE R5TVEC /X
o AYE ZOO try ZOO Alp RSTVEC X XC ED ' A
1 2 Jo 2 PA l ~20 D AYE SAID AYE RSTVEC ^ X o C ED
13 AYE AYE A 0 Alp AYE ~t~17~ ATTICA X C I- ED
Jo 2 l PA 0 awoke ZOO AYE ' nSTVEC X C 0 PA
4 it o Awl AYE Alp Alp AYE 6 R5TVEC X C
/,~22 AYE ZOO Aye ALLAH AYE R3TvEC X I D
1 7 AYE AYE ' AYE Alec Auto Alp RSTVEC OX A
18 tail o jail AYE ' Aye Aye Tao RSTVEC X XC I Jo +
AYE X~21 Aye o AYE o AYE o Alp R6TYEC X C I PA D t ~22 ~21 I Aye aye Aye R9TVEC X C I
01 This invention relates in general to 02 computer systems, and in particular to a memory 03 management system for detecting the presence of memory 04 circuits in a computer system and remapping memory 05 addresses in response thereto.
06 Computer systems are typically comprised 07 ox one or more memory modules comprised of a plurality 08 of memory banks to which memory circuits, such as 09 dynamic random access memory chips (Drams), are lo connected. A main controller (erg. a CPU) typically if generates address signals for accessing predetermined 12 memory locations of the memory circuits. For example, 13 an address signal is usually received by the memory 14 modules and decoded therein, such that a predetermined one of the memory banks is enabled and a predetermined I DRAM memory location defined by the address signal, is 17 accessed.
18 In a straightforward computer system 19 having a fixed (non-expandable) amount of memory, there is typically a one-to-one correspondence 21 (mapping) between the generated address signals and 22 the DRAM memory locations.
23 It is desirable that the number of memory 24 banks be expandable, thereby accommodating a greater number ox memory circuits, in order to implement I software revisions, or store large amounts of data, 27 etc. In order to effect memory expansion in the past, 28 costly redesign and rewiring of memory module address 29 decoding circuitry was typically required.
One prior art memory management system 31 sought to overcome the disadvantages of costly 32 redesign and rewiring by utilizing a plurality of 33 hardware address multiplexes and an operating system 34 program which included a subroutine for remapping address signals during execution of an application 36 program. The remapping process was said to be 37 "on-line". The remapped address signals were then 38 - l -~23~
01 used for accessing the actual DRAM memory locations.
02 The aforementioned remapping subroutine and additional 03 hardware was complex, and execution of the subroutine 04 was found to be time consuming. Typically, one or 05 more main controller wait states were required to 06 implement the address remapping since a multiplicity 07 of bank switching access instructions were inserted in 08 the program code, thereby substantially reducing speed 09 of execution of the application program as well as increasing the likelihood of memory access errors.
11 The remapping subroutine was dedicated, or 12 non self-adaptive, since further memory expansion or 13 reduction) required modification ox various parameters 14 of the program which in turn, usually required replacement of a floppy disk or ROM on which the 16 operating system program was stored.
17 According to the present invention, an 18 inexpensive, self-adaptive memory management system 19 is provided for detecting the presence of memory circuits connected to predetermined memory banks of a 21 plurality of memory modules in a computer system, and 22 during an initialization procedure remapping address 23 signals generated by a main controller and 24 subsequently generating enable signals for contiguously enabling the predetermined memory banks.
26 According to a preferred embodiment, the 27 enable signal circuits are comprised of programmable 28 logic circuits generating the aforementioned enable 29 signals for enabling the predetermined ones of the memory banks during each memory access without 31 requiring any extra time penalty in the form of wait 32 states.
33 A typical computer system may haze two 34 memory modules, denoted as main and expander memory modules, wherein each module accommodates up to 2.5M
36 bytes of memory using five 512k byte memory banks.
37 Emory addresses of the main and expander modules are '"
~234~2~
01 required to be contiguous. Thus, the first memory 02 location of the expander memory module would have an 03 address of 280000 (hex). However, in the event the 04 main memory module is not filled to capacity (2.5 M
05 bytes), but actually has only lo byte of DRAM chips 06 connected thereto (i.e. two of the five memory 07 banks are filled, the last valid memory address on 08 the main memory module is OFF (hex), and the next 09 contiguous address would be 100000 (hex).
According to the present invention only lo 11 byte of memory would be detected on the main memory 12 module, and in response predetermined control signals 13 are transmitted to the enable signal circuits such 14 that, in the event the main controller generates an address signal of 100000 (hex), the enable signal 16 circuits on the expander module remap the memory 17 locations starting at 2~30000 (hex) to an address of 18 100000 (hex) and the enable signal circuits on the 19 main memory module disable the memory address space from 100000 (hex) such that the access is made to the 21 first location on the expander memory module and not 22 the location 100000 on the main memory module. Thus, 23 the second memory bank of the main memory module is 24 made contiguous with the first bank of the expander module.
26 The system is inexpensive, and the memory 27 detection process is preferably performed prior to the 28 first memory access (i.e. during power-up), such that 29 no wait states are required to be executed during subsequent memory accesses, as in the prior art 31 "on-line" technique.
32 In the event further banks of the main 33 memory module are filled it the third, fourth or 34 fifth banks, etc.`, the memory management system detects the presence of the expanded memory during 36 initialization or power-up, and remaps the first 37 memory location of the memory module so as to be I
01 contiguous with the last valid memory address of the 02 expander main memory module. Hence, the system is 03 self-adaptlve and the prior art disadvantage of 04 requiring revision of the operating system program by 05 replacement of a floppy disk or ROM, or by extensive 06 redesign and rewiring, is overcome.
07 In general, the invention is a computer 08 memory management system for connection to a plurality 09 of memory modules each having a plurality of memory banks thereof, predetermined ones of which have one or 11 more memory circuits connected thereto. The invention 12 is comprised of a circuit for generating address 13 signals, circuitry for receiving first ones of the 14 address signals and detecting the presence of memory circuits connected to the predetermined memory banks 16 in response thereto, and circuitry for receiving and 17 remapping further ones of the address signals and 18 contiguously enabling the predetermined memory banks 19 in response thereto, whereby variations in the number of memory circuits connected to the aforementioned 21 plurality of memory modules is automatically 22 compensated for while addressing said modules.
23 More particularly the invention is a 24 computer memory management system for connection to a plurality memory each having a plurality of memory 26 banks thereof, predetermined ones of which have one or 27 memory circuits connected thereto. The invention is 28 comprised of a circuit generating address signals, a 29 circuit for receiving predetermined first ones of the address signals and generating enable signals for 31 enabling successive ones of the plurality of memory 32 banks in response thereto, a circuit for detecting the 33 presence of memory circuits connected to predetermined 34 ones of the aforementioned successfully enabled memory banks and generating one or more control signals in 36 response thereto, and a circuit for receiving the 37 control signals and further ones of the address ~L23~
01 signals, remapping received further address signals 02 and contiguously enabling the predetermined memory 03 banks in response thereto.
04 The invention is also a method of computer 05 memory management for use in conjunction with one or 06 more memory modules each having a plurality of memory 07 banks, predetermined ones of which have one or more 08 memory circuits connected thereto, comprising the 09 steps of generating address and control signals, receiving first ones of the address and control 11 signals and detecting the presence of memory circuits 12 connected to the predetermined memory banks in 13 response thereto, and receiving second ones of the 14 address and control signals and contiguously enabling corresponding ones of the predetermined memory banks 16 in response to receiving the second address and 17 control signals and the detection of the presence of 18 the memory circuits.
19 A better understanding of the invention will be obtained with reverence to the detailed 21 description below, in conjunction with the following 22 drawings, in which:
23 Figure l is a block diagram of a memory 24 management system according to the present invention, and 26 Figure 2 is a schematic diagram of an 27 enable signal generation circuit according to a 28 preferred embodiment of the present invention.
29 With reference to Figure 1, a main memory module 1 and an expander memory module 2 are each 31 comprised of a plurality of memory banks 32 By, By, B2BN. Each memory bank is typically 33 comprised of one or more DRAM chips (such as 64k or 34 256k DRAM chips). Data terminals of respective ones of the memory banks are connected to a data bus 3, and 36 address inputs to the memory banks are connected to 37 address lines Allah of an address bus 4 connected to . . , :~LZ3~iL2~
01 main controller 5, such as a microprocessor.
02 First and second enable signal generation 03 circuits PA and 6B have enable outputs thereof 04 connected to inputs of respective ones of the memory 05 banks By, By, B2BN in the main and expander memory 06 modules 1 and 2. A first plurality of address inputs 07 to the enable signal circuits are connected to Ai-Aj 08 address lines ox the address bus 4, and a second 09 plurality of inputs are connected to a control bus 7 connected to the main controller 5. In addition, a 12 RSTVEC signal output from the main controller 5 is 13 connected to a further input of enable signal circuit 14 PA and via a latch 8 to a further input of enable signal circuit 6B, under control of signals on the 16 address and control buses 4 and 7 respectively.
17 In operation, the main controller 5 18 generates predetermined address and control signals on the address and control busses 4 and 7, and on the 21 RSTYEC output thereof, for application to enable 22 signal circuit PA. In response, circuit PA under 23 software control successively enables memory banks By, 24 By, B2BN of the main memory module 1, and the main controller 5 detects the presence of memory chips 26 connected thereto.
27 For example, memory bank By is enabled by 28 the enable signal circuit PA and the main controller 5 29 venerates a data signal on data bus 3 for storage in a predetermined location ox memory bank By. Next, the 31 main controller 5 reads the data signal stored in the 32 predetermined location. In the event memory bank By 33 has DRAM chips connected thereto, the main controller 34 5 reads the data signal previously stored therein.
However, in the event memory bank By has no DRAM chips 36 connected thereto, a default signal of or example 37 OF hex), is read by the main controller 5 in response ~2342Z~
01 to accessing the non-existent DRAM chips. In the 02 event of detection of DRAM chips, memory bank By is 03 maintained enabled and bank By is enabled and the DRAM
04 chip detection process is repeated.
05 In the event of detection of an empty 06 memory bank (i.e. a bank having no DRAM chips 07 connected thereto), the main controller 5 disables the 08 empty memory bank and stores predetermined control 09 signals in enable signal circuits indicative of the number of memory banks By, By, B2.~.BN of main memory 11 module 1 having DRAM chips connected thereto, such 12 that the first valid memory location of expander 13 memory module 2 is remapped so as to be contiguous 14 with the last valid location of the main memory module 1, as described in greater detail below with respect 16 to Figure 2.
17 Hence, during execution of a program by 18 the main controller 5, memory addresses are remapped 19 by the circuits PA and 6B so as to enable contiguous memory locations of the main and expander memory I modules 1 and 2, respectively.
23 The RSTVEC signal is a reset signal which 24 disables all memory modules during a system reset to allow a vector fetch from ROM. It alternately enables 26 the main expander memory modules via latch 8 in order 27 to resolve data bus contention during the remapping 28 process.
29 With reference to Figure 2, a schematic ; 30 diagram of the enable signal circuit PA or 6B is 31 illustrated. According to the preferred embodiment of 32 the invention, each of the modules 1 and 2 is 33 comprised of five memory banks denoted B0-B4. A
34 programmable array logic (PAL) 9 is shown having ADDRESS inputs thereof connected to address lines 36 AYE of the address bus 4. The address lines 37 AYE correspond to address lines Ai-Aj in Figure 38 1. Data lines D0-D4 of the data bus 3 (Figure 1) are :
~3~2~
01 connected to data inputs lD-5D respectively, of a data 82~ register 10. A reset input of register 10 is 04 connected to a RESET control line of control bus 7.
05 Outputs lo, 2Q, 3Q, 4Q and 5Q of register 10 are 06 connected to control inputs CURL of PAL 9, and 07 generate control signals A, B, C, D and X
I respectively, described in further detail below.
A further control input of PAL 9, denoted as RSTVEC, 12 is connected to the RSTVEC output of the main 13 controller 5 as discussed above with reference to I Figure 1, or in the case of enable signal circuit 6B, ho the RSTVEC input of PAL 9 is connected to the output 18 of latch 8 connected to the RSTVEC output of main I controller 5.
I Outputs RCAS0, RCASl, RING, RCAS3 and 23 RCAS4 of PAL 9 are connected to first inputs of RAND
24 gates 11, 12, 13, 14 and 15 respectively, and to NOT
gates 16, 17, 18, 19 and 20 respectively. Second 26 inputs of RAND gates 11-15 are connected to an output 27 of RAND gate 21.
28 A first input of RAND gate 21 is connected 3209 to an output of a NOT gate 22, an input of which is 31 connected to a REFRESH control line of control bus 7 32 connected to controller 5. A second input of RAND
33 gate 21 is connected to the output of series connected 34 NOT gates 23 and 24. An input of gate 24 is connected to an address line Aye of the main controller 5, and 36 an output thereof is connected to an input of NOT gate 37 23.
38 Outputs of RAND gates 11-15 are connected 39 to first inputs of RAND gates 25-29 respectively, and the outputs of NOT gates 16-20 are connected to first 41 inputs of a plurality of RAND gates 30-34 I
01 respectively. Outputs of RAND gazes 25-34 are 02 connected to output resistors 35-44, respectively.
I Output resistors 35-39 are connected to 05 row address select output terminals ROUSERS
8q respectively, and output resistors 40-4~ are 08 connected to column address select terminals CAS0-CAS4 respectively. The row and column address output 11 terminals RUSES and CASO-CAS4 are connected to row 12 and column enable inputs of respective ones of memory banks B0-B4, of the main memory module 1.
An address select output AS from the main 16 controller 5 is connected to a NOT gate 45, an output 17 of which is connected to second inputs of RAND gates 18 25-29, and to an input (IN) of a delay line 46, an 19 output (OUT) thereof being connected to second inputs of RAND gates 30-34.
21 In operation, the amount of memory 22 connected to adjacent ones of the memory banks B0-B4 23 of the main memory module 1 (Figure 1) is first detected. PAL 9 generates active low signals on 26 predetermine ones of the outputs RCAS0-RCAS4 in 27 response to receiving predetermined signals on the 28 address and control inputs (ADDRESS and CURL) thereof, 29 as a result of being programmed in a well known manner according to equations set out below with reference to 31 TABLES 1 and 2.
32 According to the preferred embodiment, 33 memory modules 1 and 2 (Figure 1) are each comprised 34 of five memory banks B0-B4 containing 64k or 256k byte DRAM chips, as discussed above. In the event main 36 memory module 1 is comprised of 64k chips, it will 37 accommodate up to 640k bytes of data. In the event 38 the main memory module is comprised of 256k chips, it 39 will accommodate up to 2.5M bytes of data. Similarly, the expander memory module 2 will also accommodate 41 either 64k or 256k chips, but not both.
I _ 9 _ 4~2~
I PAL equations for generating the active 03 low enable signals on the RCAS0-RCAS4 outputs, for 04 enabling predetermined ones ox the memory kinks, are 05 illustra~d in TABLES 1 and 2 respectively.
08 PAL EQUATIONS FOR 64k CHIPS
O 9 _ I ho J AYE tall ZOO AYE R5TVEC /X
o AYE ZOO try ZOO Alp RSTVEC X XC ED ' A
1 2 Jo 2 PA l ~20 D AYE SAID AYE RSTVEC ^ X o C ED
13 AYE AYE A 0 Alp AYE ~t~17~ ATTICA X C I- ED
Jo 2 l PA 0 awoke ZOO AYE ' nSTVEC X C 0 PA
4 it o Awl AYE Alp Alp AYE 6 R5TVEC X C
/,~22 AYE ZOO Aye ALLAH AYE R3TvEC X I D
1 7 AYE AYE ' AYE Alec Auto Alp RSTVEC OX A
18 tail o jail AYE ' Aye Aye Tao RSTVEC X XC I Jo +
AYE X~21 Aye o AYE o AYE o Alp R6TYEC X C I PA D t ~22 ~21 I Aye aye Aye R9TVEC X C I
2 0 X~22 ~21 AYE AYE in Alp ~9TVEC X C D PA D t 2 1 t~22 ~21 0 Al- AYE Alp A9TVEC X C D D +
22 ZOO ZOO ' AYE ' Alp Gala Aye R9TVEC X I D D
23 ~2-~2ltl~0-/Al9 Aye AYE RStVEC OX to US t 24 AYE AYE Alto Allah Aye ~STVEc ' X ' I " Jo I' A D +
AYE " Tao Aye awoke DAIS AYE RSTVEC 9 X 9 C to PA D
2 6 AYE AYE Aye Alp Alp AYE - R9TVEC X C ED A D t 2 7 AYE Aye ' AYE AYE AYE tail RSTVEC X C D PA D t ~12 Aye X~20 to . Alp AYE n~TVEC X C D A D t 2 8 ~22 ZOO AYE AYE Aye A3TVEC X I D D
~22 Al AYE ZOO Alp Aye It9rVEC /X it A e c 31 AYE AYE Aye Alec Tao Allah R9TVEC X 3 I Jo ED A D +
22 ZOO ZOO ' AYE ' Alp Gala Aye R9TVEC X I D D
23 ~2-~2ltl~0-/Al9 Aye AYE RStVEC OX to US t 24 AYE AYE Alto Allah Aye ~STVEc ' X ' I " Jo I' A D +
AYE " Tao Aye awoke DAIS AYE RSTVEC 9 X 9 C to PA D
2 6 AYE AYE Aye Alp Alp AYE - R9TVEC X C ED A D t 2 7 AYE Aye ' AYE AYE AYE tail RSTVEC X C D PA D t ~12 Aye X~20 to . Alp AYE n~TVEC X C D A D t 2 8 ~22 ZOO AYE AYE Aye A3TVEC X I D D
~22 Al AYE ZOO Alp Aye It9rVEC /X it A e c 31 AYE AYE Aye Alec Tao Allah R9TVEC X 3 I Jo ED A D +
3 aye A 0 AYE Aye Aye TVCC X C ED Xtl D t AYE ZOO AYE Aye Aye I~STVEC X 4 C X0 D t 3 3 Z AYE Gil Aye ~J~17 R~TVEC X C it A Jo D t aye A21 AYE 18 A17 nSTVEC X C D A I D t 35~22 ~/~21 AYE it AT Aye Aye DTNZC X I 0 A I D
337 AYE 20 Audi 115TVC /X A B c 38~ a zoo 0 I ~0TVCC 9 X icky I A D t 39/~2 /A21 A~0 Ail Nat 0 AYE R~TV~C I X e ED PA or D t I AWOKE /~19 17 ' R9TVE~ X C ' ED
aye AYE /A~0 I. Ail ZOO ZOO F/6TVEC X 3 C I D PA D t 41. ZOO ' I ~20 3 XAlq l~Ala/Al7 3 RSrVEC , X C D A D t 42 ASSAY AUDI jail AYE ZOO IISTVEC t I D
I' , .
.
I
0 3 PAL EQUATE I OWNS FOR 2 5 6 k OH I P S
v v iA22 AYE ZEUS * ZOO RSTVEC XX
07 AYE ZOO AYE * ANY Gala * Aye RSTVEC * X XC ED A +
08 AYE ZOO Aye AYE * RSTVEC * X Y C ED PA +
ASSAY AYE Aye Alp RSTVEC X C pa A
9 ZOO Aye ZEUS ZOO RSTVEC { X C D PA
1 0 AYE Aye ' ZOO Alp RSTVEC X C B * A
1 1 ZOO ZOO ZOO Aye RSTVEC X XC D A
1 2 RCAS-I n 13 AYE ZOO ZOO Aye RSTVEC * XX A
ZOO ZOO Y Aye AYE ZOO Aye RStVEC X XC { ED A D
14 AYE AYE Aye Y Aye ' RSTVEC { X * C ED to D t AYE Aye ZOO AYE RSTVEC X C ' ED * A 0 1 6 AYE Aye * ZOO Aye RSTVEC X C * PA
ZOO Aye ASSAY foe RSTVEC X C Y n ^ A
17 AYE * ZOO t Aye * XAlq * RSTVEC X XC D A D
1 9 ZEUS NAZI Aye * AYE * RSTVEC XX * A B .+
2 n ZOO Tao Aye Aye aye Aye RSTVEC X I * ED A D t ZOO * Aye * AYE ZOO RSTVEC X C X3 * PA 3 t 21 ZOO Aye ZOO Aye RSTVEC X C v ED A D t 2 2 ZOO Aye Aye * AYE RSTVEC X C PA D
PA S Aye ASSAY Aye RSTVEC X C c D A D +
23 AYE AYE Aye Aye RSTVEC * X XC D * A D
r RCAS3 ZOO * NAZI Aye Aye * RSTVEC /X A B c -26 ZOO * Aye ZOO AYE DAIS Aye RSTVEC X i XC * ED { A D
AYE Aye ZOO Aye RSTVEC X C ED PA p ZOO Aye * Aye ZOO RSTVEC X C ED A D +
ASSAY Aye Aye Aye * RSTVEC X * C a PA 0 KIWI AYE AYE AYE RSTVEC * X * C D A
30 AYE Aye ZOO AYE * RSTVEC X I D A D
3 RCAS~ .
AYE;! Aye AYE AYE RSTV~C I- /X I A B c D +
32 ZOO ' Aye ZOO Alp AHAB Aye RSTVEC x I Jo A D +
3 3 AYE AYE Aye AYE it RSTVEC l! X C I PA I) +
34 AYE AYE Aye AYE t RSTVEC X I I A r D t Aye JOY Aye AYE l- RSTVEC X I RID PA o t Aye AYE AYE * Alp RSTVEC X C * A D +
AYE Aye q AYE I Alp I R5TVEC X I q O 'I A O
39 Operation of the preferred embodiment will be described with reference to Figures 1 and 2, and 41 TABLE 2, and considering a scenario in which 256k 42 chips are disposed in the By and By banks of main 43 memory module 1, and in the By bank of expander memory 44 module 2.
According to the preferred embodiment, 46 data bus 3 is a 16 bit data bus while the DRAM chips 47 are 1 bit devices. Hence, 16 DRAM chips are disposed 48 in each of the memory banks in order to generate 16 ~23~2~
01 bit data signals. pence, for the above mentioned 02 scenario, each bank contains 512k bytes of memory, 03 resulting in a total of 1 M bytes in main memory 04 module 1 and 512k bytes in the expander memory module 05 2, for a total system memory of 1.5 M bytes.
06 In response to a system reset or power-up, 07 an initialization routine is executed wherein the main 08 controller 5 generates logic low signals on the address lines AYE of address bus 4 (Figure 1), and 11 on the RSTVEC output and the RESET line of control bus 7 such that the the lQ-5Q outputs of register 10 and 14 the ADDRESS, CURL and RSTVEC inputs of PAL 9 have logic low level signals applied thereto, and the logic 17 low RSTVEC signal is latched into latch 8 under 18 control of signals on the address and control buses 4 and 7, in a well known manner. A logic high signal is then generated on the RSTVEC output and applied to 23 enable signal circuit PA. Hence, the RCAS0 output of 24 PAL 9 goes high, enabling 512k bytes of memory on the memory bank By of the main memory module 1.
I Enable signal circuit 6B remains disabled 28 as a result of RSTVEC being latched at a low logic 29 level in latch 8 (Figure 1). Thus, none of banks BOB of expander memory module 2 are enabled, thereby 31 avoiding contention on thy data bus 3 (Figure 1).
32 In order to determine whether or not DRAM
33 chips are connected to the memory bank By, a 34 predetermined memory location within the aforementioned enable 512k bytes is selected (as 36 described in detail below) and a hexadecimal data 37 signal is written thereto from the main controller 5 38 via data bus 3. The data signal is then read by the 39 main controller 5 in the event a DRAM chip is connected to the enabled memory bank By. however, in 41 the event of no DRAM chip being connected to the 42 enabled memory bank By, a default data signal of 23~
01 OF (hex) is received therefrom.
02 In order to determine the size of memory 03 (i.e., the number of memory banks BOB having DRAM
04 chips connected thereto), each of the memory banks is 05 successively enabled and checked in the manner 06 described above.
07 For example, in order to enable memory 08 bank By, the main controller 5 generates a logic high 09 signal or application to the lo input of register 10, and stored therein. A logic high signal (A) is 11 transmitted from register 10 to a corresponding one of 12 the control inputs (CURL) of PAL 9. Hence, with X, B, C and D at logic low levels and A at a logic high level, the RCASl output of PAL 9 goes to a logic low 16 level in response to an address signal 0001 being 17 generated on the Allah address fines, by the main controller 5, (see TABLE 2).
The logic low output signal from the cozily 21 output is applied to the first input of RAND gate 12.
22 The output of RAND gate 21 is normally at a logic high level, but goes to a logic low level in response to an active low REFRESH signal being inverted and applied 26 thereto via inventor 22, in conjunction with a logic 27 high signal being received on address line Aye.
28 Hence, the output of RAND gate 12 goes from a normally logic low level to a logic high level in response to 31 the RCASl output of PAL 9 going to a logic low level 32 or the output of RAND gate 21 going to a logic low 33 level (i.e., during DRAM refresh, discussed in further 34 detail below).
The logic high signal from RAND gate 12 is 36 applied to the first input of RAND gate 26. The 37 second input of RAND gate 26 receives a logic high signal in response to an active low address select signal AS being generated by the main controller 5 and 41 received and inverted in inventor 45 and applied to ~234;~
01 NED gate 26. The output of RAND gate 26 goes to a 02 logic low level in response to receiving the 03 aforementioned logic high signals on the inputs thereof, thereby generating a row memory select signal 06 R~Sl for enabling all rows of memory in the By memory 887 bank.
09 The active low RCASl signal output is inverted in NOT gate 17 and applied to the firs-t input 12 of RAND gate 31. The inverted AS signal is delayed by 13 approximately 80 nanoseconds in delay line 46, and 14 applied to the second input of NED gate 31. Hence, the output of RAND Nate 31 goes to a logic low level, 17 thereby generating a column memory select signal Cast 18 for enabling columns of memory in memory bank By approximately 80 nanoseconds after generation of the 21 Rasp signal, and thereby completely enabling the By 22 memory bank.
23 An approximately 80 nanosecond delay is I implemented between the row select and column select I outputs R~Sl and Cast in order to provide sufficient 27 time for 8 bit row address signals to be latched in 28 order to multiplex the address inputs of DRAM circuits 29 (i.e., there is a predetermined amount of capacitive loading associated with the DRAM chips), before 31 latching in 8 bit column address signals, in a well 32 known manner.
With memory bank By enabled in response to receiving the Rasp and Cast signals, the main 36 controller 5 writes and then reads the above mentioned 37 data signal to a predetermined memory location therein 38 as discussed above, in order to detect the presence of 39 DRAM memory chips connected to the By memory bank.
As discussed above, according to the ~:3~2~
01 present scenario the By and By memory banks of the 02 main memory module have DRAM chips connected thereto, 03 according to the present scenario thus the main 04 controller 5 thus detects the presence of the DRAM
05 chips and then proceeds to check the By memory bank.
06 In order to check the By memory bank, 07 logic low C, D and X signals are applied to the inputs I CURL of PAL 9, and logic high A and B signals are also applied thereto, such that the RCAS2 output 11 generates an active low logic signal in response to 12 address signal 0010 (hex) being generated by the Allah address lines, (TABLE 2 and Figure 2). The RASP and CAST outputs of RAND gate 27 and 32 go 16 respectively low in order to enable the memory bank 17 By. The main controller 5 writes to and attempts to 18 read a data signal from a predetermined location 19 within memory bank By, but reads instead a default signal OF (hex) since no DRAM chips are connected 21 thereto. Hence, the main controller 5 detects the 22 presence of DRAM chips on only the By and By memory 23 banks and generates a first control signals having a 24 logic high Do signal and logic low Dl-D3 signals for storage in register 10. Thus, register 10 generates a 26 control signal for application to the CTRI. inputs of 27 PAL 9 wherein the A control signal is at a logic high 28 level and the B, C and D signals are at logic low 29 levels. Consequently, only the By and By banks of the main memory module 1 are enabled in response to 31 receiving further address signals from the main 32 controller 5.
33 The main controller 5 then generates a 34 second control signal for storage in enable signal circuit 6B in order that address signals received on 36 the address lines AYE are remapped so as to 37 provide contiguity between the last valid memory 38 location on the main memory module 1 and the first 3g location on the expander memory module 2.
I
01 As discussed above, enable signal I generation circuits PA and 6B are of identical design 04 (as illustrated in Figure 2) but the RSTVEC input of I PAL 9 in circuit PA is connected directly to the 07 RSTVEC output of main controller 5, while the RSTVEC
08 input of PAL 9 in circuit 6B is connected to the 1 output of a latch 8 which has an input connected to 11 the RSTVEC output of main controller 5. Either of the 12 Pals 9 of circuits PA or 6B may be programmed 13 according to the equations of either TABLES 1 or 2, in 14 order to accommodate 64k or 256k DRAM chips.
The main controller 5 loads the above 16 mentioned second control signal into register 10 of 17 enable signal circuit 6B. According to the second 18 control signal the X and C signals are at logic high 19 levels and are applied to the control input (CURL) of PAL 9, and the A, B and D signals are at logic low I levels and are also applied thereto. The main controller then switches the latch 8 such that RSTVEC for module 6B goes to a logic high. The RCAS0 output of PAL 9 of 26 enable circuit 6B goes to an active logic low level in 27 response to address signal 0010 (hex) generated by the 28 Allah address lines, resulting in the third OR term 29 in the PAL equation thereof being true, (TABLE 2).
With reference to TABLE 2, it can be seen 31 that with bank By of main memory module 1 enabled, the 32 values of address lines Aye, Aye, Aye and Alp are all 33 0; with ban By thereof enabled, Aye, Aye, Aye and Alp I are 0, 0, 0 and 1 respectively; and with bank By of expander memory module 2 enabled, Aye, Aye, Aye and 36 Alp are 0, 0, 1 and 0 respectively. Hence, it is seen 37 that the starting address of memory in expander module I 2 has been made contiguous with the last address ~l23~
01 location in main memory module 1.
02 The main controller 5 writes and reads 03 data from a predetermined memory location in memory 04 bank By of the expander memory module 2, in order to 05 determine whether DRAM chips are connected thereto.
8q text, the By bank of expander memory 08 module 2 is enabled in response to the RCASl output of 109 PAL 9 of enable circuit 6B going to an active logic 11 low signal. The RCASl output goes active low in 12 response to a value of 0011 being applied to the Aye, Aye, Aye and Alp inputs of PAL 9, resulting in the third "OR" term of the RCASl equation in TABLE 2 16 being true. The By memory bank is written to for 17 determining whether DRAM chips are connected thereto, 18 and a value of OF is subsequently read therefrom, 19 indicating no DRAM chips in bank By.
As discussed above, the DRAM chips are periodically refreshed in response to generation of a 23 REFRESH signal by the main controller 5. Outputs of aye RAND gates 11-15 each go to logic high levels in 26 response to generation of the REFRESH signal and a 27 logic high signal on the Aye address line of the 28 address bus 4, (Figure 1). The outputs of RAND gates 29 25-29 go to logic low levels in response to the outputs of RAND gates 11-15 going to logic high levels and in response to reception of a logic high signal I from NOT gate 45 resulting from a logic low AS signal being generated. Hence, the RUSS row address 36 outputs of RAND gates 25-29 go to logic low levels 37 simultaneously for causing refresh of 2.5 M bytes of ~L234;~2~
01 memory, (or 640k bytes in the event 64k chips are 02 used).
03 In a successful prototype, the main memory 04 module 1 accommodated 6 memory sizes, depending on 05 whether 64k or 256k byte DRAM chips were utilized.
06 TABLE 3 lists the logic levels ox the A, B and C
07 signals conforming to the various memory sizes on the 08 main memory module 1, which are applied to the control 09 inputs (CURL) of PAL 9 of enable signal circuit 6B, in order to relocate the starting address so as to be 11 contiguous with the last valid memory location of the 12 main memory module 1.
14 C B ASIDE (bytes) 16 0 1 1512k 17 0 0 okay 18 1 0 0 lo 19 1 0 11.5M
21 1 1 12.5M
23 In order to utilize the present invention 24 properly, DRAM chips must be connected to adjacent memory banks of the memory module. For example, the 26 invention will not function properly in the event the 27 BOY By and By memory banks of the main memory module 1 28 have DRAM chips connected thereto but no chips are 29 connected to the By memory banks. In particular, the main controller 5 will only detect the presence of 31 chips connected to BY and By banks.
32 Variations or alternative embodiments may 33 now be conceived of by a person skilled in the art 34 understanding the present invention. For instance, main memory module 1 and expander memory module 2 can 36 be comprised of greater or less than 5 memory banks, 37 or a greater number ox memory modules and , . .
3~2;2~
01 corresponding enable signal circuits can be utilized, 02 and the memory chips connected thereto can be larger 03 or smaller than 64k and 256k bytes respectively, 04 suitable changes being made in the PAL equations shown 05 in TABLES 1 and 2.
06 Also, while the description herein refers 07 to DRAM chips, other memory circuits such as bubble 08 memory or static RAM, etc., can be utilized, 09 appropriate modifications being made to the enable signal generation circuits PA and 6B.
11 In addition, while it is preferred that 12 PAL circuits be utilized for implementing the enable 13 signal circuits of the present invention, other 14 programmable logic circuits may be used, such as programmable logic arrays (Plus), etc.
16 Other embodiments or variations in design 17 may be conceived of by a person understanding this 18 invention. All are considered to be within the sphere 19 and scope of the invention as defined in the claims appended hereto.
337 AYE 20 Audi 115TVC /X A B c 38~ a zoo 0 I ~0TVCC 9 X icky I A D t 39/~2 /A21 A~0 Ail Nat 0 AYE R~TV~C I X e ED PA or D t I AWOKE /~19 17 ' R9TVE~ X C ' ED
aye AYE /A~0 I. Ail ZOO ZOO F/6TVEC X 3 C I D PA D t 41. ZOO ' I ~20 3 XAlq l~Ala/Al7 3 RSrVEC , X C D A D t 42 ASSAY AUDI jail AYE ZOO IISTVEC t I D
I' , .
.
I
0 3 PAL EQUATE I OWNS FOR 2 5 6 k OH I P S
v v iA22 AYE ZEUS * ZOO RSTVEC XX
07 AYE ZOO AYE * ANY Gala * Aye RSTVEC * X XC ED A +
08 AYE ZOO Aye AYE * RSTVEC * X Y C ED PA +
ASSAY AYE Aye Alp RSTVEC X C pa A
9 ZOO Aye ZEUS ZOO RSTVEC { X C D PA
1 0 AYE Aye ' ZOO Alp RSTVEC X C B * A
1 1 ZOO ZOO ZOO Aye RSTVEC X XC D A
1 2 RCAS-I n 13 AYE ZOO ZOO Aye RSTVEC * XX A
ZOO ZOO Y Aye AYE ZOO Aye RStVEC X XC { ED A D
14 AYE AYE Aye Y Aye ' RSTVEC { X * C ED to D t AYE Aye ZOO AYE RSTVEC X C ' ED * A 0 1 6 AYE Aye * ZOO Aye RSTVEC X C * PA
ZOO Aye ASSAY foe RSTVEC X C Y n ^ A
17 AYE * ZOO t Aye * XAlq * RSTVEC X XC D A D
1 9 ZEUS NAZI Aye * AYE * RSTVEC XX * A B .+
2 n ZOO Tao Aye Aye aye Aye RSTVEC X I * ED A D t ZOO * Aye * AYE ZOO RSTVEC X C X3 * PA 3 t 21 ZOO Aye ZOO Aye RSTVEC X C v ED A D t 2 2 ZOO Aye Aye * AYE RSTVEC X C PA D
PA S Aye ASSAY Aye RSTVEC X C c D A D +
23 AYE AYE Aye Aye RSTVEC * X XC D * A D
r RCAS3 ZOO * NAZI Aye Aye * RSTVEC /X A B c -26 ZOO * Aye ZOO AYE DAIS Aye RSTVEC X i XC * ED { A D
AYE Aye ZOO Aye RSTVEC X C ED PA p ZOO Aye * Aye ZOO RSTVEC X C ED A D +
ASSAY Aye Aye Aye * RSTVEC X * C a PA 0 KIWI AYE AYE AYE RSTVEC * X * C D A
30 AYE Aye ZOO AYE * RSTVEC X I D A D
3 RCAS~ .
AYE;! Aye AYE AYE RSTV~C I- /X I A B c D +
32 ZOO ' Aye ZOO Alp AHAB Aye RSTVEC x I Jo A D +
3 3 AYE AYE Aye AYE it RSTVEC l! X C I PA I) +
34 AYE AYE Aye AYE t RSTVEC X I I A r D t Aye JOY Aye AYE l- RSTVEC X I RID PA o t Aye AYE AYE * Alp RSTVEC X C * A D +
AYE Aye q AYE I Alp I R5TVEC X I q O 'I A O
39 Operation of the preferred embodiment will be described with reference to Figures 1 and 2, and 41 TABLE 2, and considering a scenario in which 256k 42 chips are disposed in the By and By banks of main 43 memory module 1, and in the By bank of expander memory 44 module 2.
According to the preferred embodiment, 46 data bus 3 is a 16 bit data bus while the DRAM chips 47 are 1 bit devices. Hence, 16 DRAM chips are disposed 48 in each of the memory banks in order to generate 16 ~23~2~
01 bit data signals. pence, for the above mentioned 02 scenario, each bank contains 512k bytes of memory, 03 resulting in a total of 1 M bytes in main memory 04 module 1 and 512k bytes in the expander memory module 05 2, for a total system memory of 1.5 M bytes.
06 In response to a system reset or power-up, 07 an initialization routine is executed wherein the main 08 controller 5 generates logic low signals on the address lines AYE of address bus 4 (Figure 1), and 11 on the RSTVEC output and the RESET line of control bus 7 such that the the lQ-5Q outputs of register 10 and 14 the ADDRESS, CURL and RSTVEC inputs of PAL 9 have logic low level signals applied thereto, and the logic 17 low RSTVEC signal is latched into latch 8 under 18 control of signals on the address and control buses 4 and 7, in a well known manner. A logic high signal is then generated on the RSTVEC output and applied to 23 enable signal circuit PA. Hence, the RCAS0 output of 24 PAL 9 goes high, enabling 512k bytes of memory on the memory bank By of the main memory module 1.
I Enable signal circuit 6B remains disabled 28 as a result of RSTVEC being latched at a low logic 29 level in latch 8 (Figure 1). Thus, none of banks BOB of expander memory module 2 are enabled, thereby 31 avoiding contention on thy data bus 3 (Figure 1).
32 In order to determine whether or not DRAM
33 chips are connected to the memory bank By, a 34 predetermined memory location within the aforementioned enable 512k bytes is selected (as 36 described in detail below) and a hexadecimal data 37 signal is written thereto from the main controller 5 38 via data bus 3. The data signal is then read by the 39 main controller 5 in the event a DRAM chip is connected to the enabled memory bank By. however, in 41 the event of no DRAM chip being connected to the 42 enabled memory bank By, a default data signal of 23~
01 OF (hex) is received therefrom.
02 In order to determine the size of memory 03 (i.e., the number of memory banks BOB having DRAM
04 chips connected thereto), each of the memory banks is 05 successively enabled and checked in the manner 06 described above.
07 For example, in order to enable memory 08 bank By, the main controller 5 generates a logic high 09 signal or application to the lo input of register 10, and stored therein. A logic high signal (A) is 11 transmitted from register 10 to a corresponding one of 12 the control inputs (CURL) of PAL 9. Hence, with X, B, C and D at logic low levels and A at a logic high level, the RCASl output of PAL 9 goes to a logic low 16 level in response to an address signal 0001 being 17 generated on the Allah address fines, by the main controller 5, (see TABLE 2).
The logic low output signal from the cozily 21 output is applied to the first input of RAND gate 12.
22 The output of RAND gate 21 is normally at a logic high level, but goes to a logic low level in response to an active low REFRESH signal being inverted and applied 26 thereto via inventor 22, in conjunction with a logic 27 high signal being received on address line Aye.
28 Hence, the output of RAND gate 12 goes from a normally logic low level to a logic high level in response to 31 the RCASl output of PAL 9 going to a logic low level 32 or the output of RAND gate 21 going to a logic low 33 level (i.e., during DRAM refresh, discussed in further 34 detail below).
The logic high signal from RAND gate 12 is 36 applied to the first input of RAND gate 26. The 37 second input of RAND gate 26 receives a logic high signal in response to an active low address select signal AS being generated by the main controller 5 and 41 received and inverted in inventor 45 and applied to ~234;~
01 NED gate 26. The output of RAND gate 26 goes to a 02 logic low level in response to receiving the 03 aforementioned logic high signals on the inputs thereof, thereby generating a row memory select signal 06 R~Sl for enabling all rows of memory in the By memory 887 bank.
09 The active low RCASl signal output is inverted in NOT gate 17 and applied to the firs-t input 12 of RAND gate 31. The inverted AS signal is delayed by 13 approximately 80 nanoseconds in delay line 46, and 14 applied to the second input of NED gate 31. Hence, the output of RAND Nate 31 goes to a logic low level, 17 thereby generating a column memory select signal Cast 18 for enabling columns of memory in memory bank By approximately 80 nanoseconds after generation of the 21 Rasp signal, and thereby completely enabling the By 22 memory bank.
23 An approximately 80 nanosecond delay is I implemented between the row select and column select I outputs R~Sl and Cast in order to provide sufficient 27 time for 8 bit row address signals to be latched in 28 order to multiplex the address inputs of DRAM circuits 29 (i.e., there is a predetermined amount of capacitive loading associated with the DRAM chips), before 31 latching in 8 bit column address signals, in a well 32 known manner.
With memory bank By enabled in response to receiving the Rasp and Cast signals, the main 36 controller 5 writes and then reads the above mentioned 37 data signal to a predetermined memory location therein 38 as discussed above, in order to detect the presence of 39 DRAM memory chips connected to the By memory bank.
As discussed above, according to the ~:3~2~
01 present scenario the By and By memory banks of the 02 main memory module have DRAM chips connected thereto, 03 according to the present scenario thus the main 04 controller 5 thus detects the presence of the DRAM
05 chips and then proceeds to check the By memory bank.
06 In order to check the By memory bank, 07 logic low C, D and X signals are applied to the inputs I CURL of PAL 9, and logic high A and B signals are also applied thereto, such that the RCAS2 output 11 generates an active low logic signal in response to 12 address signal 0010 (hex) being generated by the Allah address lines, (TABLE 2 and Figure 2). The RASP and CAST outputs of RAND gate 27 and 32 go 16 respectively low in order to enable the memory bank 17 By. The main controller 5 writes to and attempts to 18 read a data signal from a predetermined location 19 within memory bank By, but reads instead a default signal OF (hex) since no DRAM chips are connected 21 thereto. Hence, the main controller 5 detects the 22 presence of DRAM chips on only the By and By memory 23 banks and generates a first control signals having a 24 logic high Do signal and logic low Dl-D3 signals for storage in register 10. Thus, register 10 generates a 26 control signal for application to the CTRI. inputs of 27 PAL 9 wherein the A control signal is at a logic high 28 level and the B, C and D signals are at logic low 29 levels. Consequently, only the By and By banks of the main memory module 1 are enabled in response to 31 receiving further address signals from the main 32 controller 5.
33 The main controller 5 then generates a 34 second control signal for storage in enable signal circuit 6B in order that address signals received on 36 the address lines AYE are remapped so as to 37 provide contiguity between the last valid memory 38 location on the main memory module 1 and the first 3g location on the expander memory module 2.
I
01 As discussed above, enable signal I generation circuits PA and 6B are of identical design 04 (as illustrated in Figure 2) but the RSTVEC input of I PAL 9 in circuit PA is connected directly to the 07 RSTVEC output of main controller 5, while the RSTVEC
08 input of PAL 9 in circuit 6B is connected to the 1 output of a latch 8 which has an input connected to 11 the RSTVEC output of main controller 5. Either of the 12 Pals 9 of circuits PA or 6B may be programmed 13 according to the equations of either TABLES 1 or 2, in 14 order to accommodate 64k or 256k DRAM chips.
The main controller 5 loads the above 16 mentioned second control signal into register 10 of 17 enable signal circuit 6B. According to the second 18 control signal the X and C signals are at logic high 19 levels and are applied to the control input (CURL) of PAL 9, and the A, B and D signals are at logic low I levels and are also applied thereto. The main controller then switches the latch 8 such that RSTVEC for module 6B goes to a logic high. The RCAS0 output of PAL 9 of 26 enable circuit 6B goes to an active logic low level in 27 response to address signal 0010 (hex) generated by the 28 Allah address lines, resulting in the third OR term 29 in the PAL equation thereof being true, (TABLE 2).
With reference to TABLE 2, it can be seen 31 that with bank By of main memory module 1 enabled, the 32 values of address lines Aye, Aye, Aye and Alp are all 33 0; with ban By thereof enabled, Aye, Aye, Aye and Alp I are 0, 0, 0 and 1 respectively; and with bank By of expander memory module 2 enabled, Aye, Aye, Aye and 36 Alp are 0, 0, 1 and 0 respectively. Hence, it is seen 37 that the starting address of memory in expander module I 2 has been made contiguous with the last address ~l23~
01 location in main memory module 1.
02 The main controller 5 writes and reads 03 data from a predetermined memory location in memory 04 bank By of the expander memory module 2, in order to 05 determine whether DRAM chips are connected thereto.
8q text, the By bank of expander memory 08 module 2 is enabled in response to the RCASl output of 109 PAL 9 of enable circuit 6B going to an active logic 11 low signal. The RCASl output goes active low in 12 response to a value of 0011 being applied to the Aye, Aye, Aye and Alp inputs of PAL 9, resulting in the third "OR" term of the RCASl equation in TABLE 2 16 being true. The By memory bank is written to for 17 determining whether DRAM chips are connected thereto, 18 and a value of OF is subsequently read therefrom, 19 indicating no DRAM chips in bank By.
As discussed above, the DRAM chips are periodically refreshed in response to generation of a 23 REFRESH signal by the main controller 5. Outputs of aye RAND gates 11-15 each go to logic high levels in 26 response to generation of the REFRESH signal and a 27 logic high signal on the Aye address line of the 28 address bus 4, (Figure 1). The outputs of RAND gates 29 25-29 go to logic low levels in response to the outputs of RAND gates 11-15 going to logic high levels and in response to reception of a logic high signal I from NOT gate 45 resulting from a logic low AS signal being generated. Hence, the RUSS row address 36 outputs of RAND gates 25-29 go to logic low levels 37 simultaneously for causing refresh of 2.5 M bytes of ~L234;~2~
01 memory, (or 640k bytes in the event 64k chips are 02 used).
03 In a successful prototype, the main memory 04 module 1 accommodated 6 memory sizes, depending on 05 whether 64k or 256k byte DRAM chips were utilized.
06 TABLE 3 lists the logic levels ox the A, B and C
07 signals conforming to the various memory sizes on the 08 main memory module 1, which are applied to the control 09 inputs (CURL) of PAL 9 of enable signal circuit 6B, in order to relocate the starting address so as to be 11 contiguous with the last valid memory location of the 12 main memory module 1.
14 C B ASIDE (bytes) 16 0 1 1512k 17 0 0 okay 18 1 0 0 lo 19 1 0 11.5M
21 1 1 12.5M
23 In order to utilize the present invention 24 properly, DRAM chips must be connected to adjacent memory banks of the memory module. For example, the 26 invention will not function properly in the event the 27 BOY By and By memory banks of the main memory module 1 28 have DRAM chips connected thereto but no chips are 29 connected to the By memory banks. In particular, the main controller 5 will only detect the presence of 31 chips connected to BY and By banks.
32 Variations or alternative embodiments may 33 now be conceived of by a person skilled in the art 34 understanding the present invention. For instance, main memory module 1 and expander memory module 2 can 36 be comprised of greater or less than 5 memory banks, 37 or a greater number ox memory modules and , . .
3~2;2~
01 corresponding enable signal circuits can be utilized, 02 and the memory chips connected thereto can be larger 03 or smaller than 64k and 256k bytes respectively, 04 suitable changes being made in the PAL equations shown 05 in TABLES 1 and 2.
06 Also, while the description herein refers 07 to DRAM chips, other memory circuits such as bubble 08 memory or static RAM, etc., can be utilized, 09 appropriate modifications being made to the enable signal generation circuits PA and 6B.
11 In addition, while it is preferred that 12 PAL circuits be utilized for implementing the enable 13 signal circuits of the present invention, other 14 programmable logic circuits may be used, such as programmable logic arrays (Plus), etc.
16 Other embodiments or variations in design 17 may be conceived of by a person understanding this 18 invention. All are considered to be within the sphere 19 and scope of the invention as defined in the claims appended hereto.
Claims (11)
1. A computer memory management system for connection to a plurality of memory modules each having a plurality of memory banks thereof, predetermined ones of which have one or more memory circuits connected thereto, comprised of:
(a) means for generating address signals, (b) means for receiving first ones of said address signals and detecting the presence of said memory circuits connected to said predetermined memory banks in response thereto, and (c) means for receiving and remapping further ones of said address signals and contiguously enabling said predetermined memory banks in response thereto, whereby variations in the number of memory circuits connected to said plurality of memory modules is automatically compensated for while addressing said modules.
(a) means for generating address signals, (b) means for receiving first ones of said address signals and detecting the presence of said memory circuits connected to said predetermined memory banks in response thereto, and (c) means for receiving and remapping further ones of said address signals and contiguously enabling said predetermined memory banks in response thereto, whereby variations in the number of memory circuits connected to said plurality of memory modules is automatically compensated for while addressing said modules.
2. A computer memory management system for connection to a plurality of memory modules each having a plurality of memory banks thereof, predetermined ones of which have one or more memory circuits connected thereto, comprised of:
(a) means for generating address signals, (b) means for receiving predetermined first ones of said address signals and generating enable signals for enabling successive ones of said plurality of memory banks in response thereto, (c) means for detecting the presence of memory circuits connected to predetermined ones of said successively enabled memory banks and generating one or more control signals in response thereto, and (d) means for receiving said control signals and further ones of said address signals, remapping said received further address signals and contiguously enabling said predetermined memory banks in response thereto, whereby variations in the number of memory circuits connected to said plurality of memory modules is automatically compensated for while addressing said modules.
(a) means for generating address signals, (b) means for receiving predetermined first ones of said address signals and generating enable signals for enabling successive ones of said plurality of memory banks in response thereto, (c) means for detecting the presence of memory circuits connected to predetermined ones of said successively enabled memory banks and generating one or more control signals in response thereto, and (d) means for receiving said control signals and further ones of said address signals, remapping said received further address signals and contiguously enabling said predetermined memory banks in response thereto, whereby variations in the number of memory circuits connected to said plurality of memory modules is automatically compensated for while addressing said modules.
3. A computer memory management system as defined in claim 2, wherein said means for receiving said further ones of said address signals and said control signals is comprised of one or more programmable logic circuits having inputs thereof connected to said means for generating address signals and said means for generating control signals, and outputs thereof connected to said plurality of memory banks.
4. A computer memory management system for connection to first and second memory modules each having a plurality of memory banks thereof, predetermined ones of which have one or more memory circuits connected thereto, comprised of:
(a) a main controller for generating address and control signals, and detecting the presence of memory circuits connected to said predetermined memory banks of the first memory module and generating first and second ones of said control signals indicative thereof, and (b) first and second programmable logic circuits, for connection to said main controller and said first and second memory modules, for receiving said first and second control signals respectively, and further ones of said address signals, and in response generating enable signals for contiguously enabling said predetermined memory banks, whereby variations in the number of memory circuits connected to said first and second memory modules is automatically compensated for while addressing said modules.
(a) a main controller for generating address and control signals, and detecting the presence of memory circuits connected to said predetermined memory banks of the first memory module and generating first and second ones of said control signals indicative thereof, and (b) first and second programmable logic circuits, for connection to said main controller and said first and second memory modules, for receiving said first and second control signals respectively, and further ones of said address signals, and in response generating enable signals for contiguously enabling said predetermined memory banks, whereby variations in the number of memory circuits connected to said first and second memory modules is automatically compensated for while addressing said modules.
5. A computer memory management system as defined in claim 4, further including:
(a) refresh control circuitry for periodically generating refresh signals, and (b) first and second row and column address decoding circuits connected to said refresh control circuitry, and to said first and second programmable logic circuits respectively, for generating row and column select signals for enabling rows and columns of said memory banks in response to receiving one or more of said refresh signals or said enable signals.
(a) refresh control circuitry for periodically generating refresh signals, and (b) first and second row and column address decoding circuits connected to said refresh control circuitry, and to said first and second programmable logic circuits respectively, for generating row and column select signals for enabling rows and columns of said memory banks in response to receiving one or more of said refresh signals or said enable signals.
6. A computer memory management system as defined in claim 5, wherein each of said row and column address decoding circuits is comprised of:
(a) an inverter connected to said main controller, for receiving a memory select control signal therefrom, (b) a delay circuit connected to said inverter, for delaying said received memory select control signal, (c) a first plurality of NAND gates having inputs connected to said refresh control circuitry and predetermined outputs of a corresponding one of said programmable logic circuits, (d) a plurality of NOT gates having inputs connected to said outputs of the corresponding one of the programmable logic circuits, for receiving and inverting said enable signals, (e) a second plurality of NAND gates having first inputs connected to outputs of said first plurality of NAND gates and second inputs connected to said inverter, for generating said row select signals in response to receiving said memory select signal and generation of one of said refresh or enable signals, and (f) a third plurality of NAND gates having first inputs connected to said NOT gates and second inputs connected to said delay circuit, for generating said column select signals in response to receiving a delayed version of said memory select signal and said inverted enable signals.
(a) an inverter connected to said main controller, for receiving a memory select control signal therefrom, (b) a delay circuit connected to said inverter, for delaying said received memory select control signal, (c) a first plurality of NAND gates having inputs connected to said refresh control circuitry and predetermined outputs of a corresponding one of said programmable logic circuits, (d) a plurality of NOT gates having inputs connected to said outputs of the corresponding one of the programmable logic circuits, for receiving and inverting said enable signals, (e) a second plurality of NAND gates having first inputs connected to outputs of said first plurality of NAND gates and second inputs connected to said inverter, for generating said row select signals in response to receiving said memory select signal and generation of one of said refresh or enable signals, and (f) a third plurality of NAND gates having first inputs connected to said NOT gates and second inputs connected to said delay circuit, for generating said column select signals in response to receiving a delayed version of said memory select signal and said inverted enable signals.
7. A computer memory management system as defined in claim 4, 5 or 6 wherein said programmable logic circuits are programmable array logic circuits.
8. A computer memory management system as defined in claim 4, 5 or 6 wherein said programmable logic circuits are programmable logic arrays.
9. A method of computer memory management for use in conjunction with one or more memory modules each having a plurality of memory banks, predetermined ones of which have one or more memory circuits connected thereto, comprising the steps of:
(a) generating address and control signals, (b) receiving first ones of said signals and detecting the presence of memory circuits connected to said predetermined memory banks in response thereto, and (c) receiving second ones of said signals and contiguously enabling corresponding ones of the predetermined memory banks in response to receiving said second signals and the detection of the presence of said memory circuits, whereby variations in the number of memory circuits connected to said memory modules is automatically compensated for while addressing said module.
(a) generating address and control signals, (b) receiving first ones of said signals and detecting the presence of memory circuits connected to said predetermined memory banks in response thereto, and (c) receiving second ones of said signals and contiguously enabling corresponding ones of the predetermined memory banks in response to receiving said second signals and the detection of the presence of said memory circuits, whereby variations in the number of memory circuits connected to said memory modules is automatically compensated for while addressing said module.
10. A method as defined in claim 9, wherein said step of detecting the presence of memory circuits is further comprised of the steps of:
(a) generating one or more data signals for storage in said memory banks, and (b) retrieving said stored data signals from said predetermined memory banks and retrieving default signals from other ones of said memory banks, and in response generating further control signals indicative of the presence of said memory circuits being detected.
(a) generating one or more data signals for storage in said memory banks, and (b) retrieving said stored data signals from said predetermined memory banks and retrieving default signals from other ones of said memory banks, and in response generating further control signals indicative of the presence of said memory circuits being detected.
11. A method of computer memory management, for use in conjunction with main and expander memory modules each having a plurality of memory banks, predetermined ones of which have one or more memory circuits connected thereto, comprising the steps of:
(a) generating first address signals for application to a first programmable logic circuit connected to said main memory module, and successively enabling the memory banks of said main memory module in response thereto, (b) detecting the presence of memory circuits connected to predetermined ones of said enabled memory banks of the main memory module, (c) generating and storing first and second control signals indicative of said memory circuits being connected to said predetermined memory banks of the main memory module, (d) applying said first control signal to said first programmable logic circuit, (e) applying said second control signal to a second programmable logic circuit connected to said expander memory module, and (f) generating further address signals for application to said first and second programmable logic circuits and contiguously enabling said predetermined memory banks of the main and expander memory modules in response thereto, whereby variations in the number of memory circuits connected to said main and expander memory modules is automatically compensated for while addressing said modules.
(a) generating first address signals for application to a first programmable logic circuit connected to said main memory module, and successively enabling the memory banks of said main memory module in response thereto, (b) detecting the presence of memory circuits connected to predetermined ones of said enabled memory banks of the main memory module, (c) generating and storing first and second control signals indicative of said memory circuits being connected to said predetermined memory banks of the main memory module, (d) applying said first control signal to said first programmable logic circuit, (e) applying said second control signal to a second programmable logic circuit connected to said expander memory module, and (f) generating further address signals for application to said first and second programmable logic circuits and contiguously enabling said predetermined memory banks of the main and expander memory modules in response thereto, whereby variations in the number of memory circuits connected to said main and expander memory modules is automatically compensated for while addressing said modules.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000482566A CA1234224A (en) | 1985-05-28 | 1985-05-28 | Computer memory management system |
| GB8526597A GB2175716B (en) | 1985-05-28 | 1985-10-29 | Computer memory management system |
| US06/794,695 US4860252A (en) | 1985-05-28 | 1985-11-04 | Self-adaptive computer memory address allocation system |
| IT22962/85A IT1185741B (en) | 1985-05-28 | 1985-11-22 | PROCESSOR MEMORY MANAGEMENT SYSTEM |
| JP60285367A JPS61273649A (en) | 1985-05-28 | 1985-12-17 | Memory management system for computer |
| CN198585109307A CN85109307A (en) | 1985-05-28 | 1985-12-26 | Computer memory management system |
| DE19863607092 DE3607092A1 (en) | 1985-05-28 | 1986-03-05 | STORAGE MANAGEMENT SYSTEM |
| FR8607161A FR2582829A1 (en) | 1985-05-28 | 1986-05-16 | SYSTEM FOR MANAGING COMPUTER MEMORY |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000482566A CA1234224A (en) | 1985-05-28 | 1985-05-28 | Computer memory management system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1234224A true CA1234224A (en) | 1988-03-15 |
Family
ID=4130575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000482566A Expired CA1234224A (en) | 1985-05-28 | 1985-05-28 | Computer memory management system |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4860252A (en) |
| JP (1) | JPS61273649A (en) |
| CN (1) | CN85109307A (en) |
| CA (1) | CA1234224A (en) |
| DE (1) | DE3607092A1 (en) |
| FR (1) | FR2582829A1 (en) |
| GB (1) | GB2175716B (en) |
| IT (1) | IT1185741B (en) |
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-
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- 1985-05-28 CA CA000482566A patent/CA1234224A/en not_active Expired
- 1985-10-29 GB GB8526597A patent/GB2175716B/en not_active Expired
- 1985-11-04 US US06/794,695 patent/US4860252A/en not_active Expired - Fee Related
- 1985-11-22 IT IT22962/85A patent/IT1185741B/en active
- 1985-12-17 JP JP60285367A patent/JPS61273649A/en active Pending
- 1985-12-26 CN CN198585109307A patent/CN85109307A/en active Pending
-
1986
- 1986-03-05 DE DE19863607092 patent/DE3607092A1/en not_active Withdrawn
- 1986-05-16 FR FR8607161A patent/FR2582829A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB2175716A (en) | 1986-12-03 |
| GB8526597D0 (en) | 1985-12-04 |
| FR2582829A1 (en) | 1986-12-05 |
| IT1185741B (en) | 1987-11-12 |
| DE3607092A1 (en) | 1986-12-04 |
| CN85109307A (en) | 1986-11-26 |
| US4860252A (en) | 1989-08-22 |
| GB2175716B (en) | 1989-07-19 |
| JPS61273649A (en) | 1986-12-03 |
| IT8522962A0 (en) | 1985-11-22 |
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