CA1226677A - Apparatus for encoding and decoding digital data to permit error correction - Google Patents

Abstract

APPARATUS FOR ENCODING AND DECODING DIGITAL DATA TO
PERMIT ERROR CORRECTION

ABSTRACT OF THE DISCLOSURE

Apparatus to punt the correction of a single bit error occurring in a sequence of data packets (e.g. bytes) comprising data bits. An encoder produces an error correction packet (e.g. byte), the value of which is determined algebraically from the value of bits in the data sequence. All data packets and the error correction packet have a predetermined parity. A decoder receives the sequence of data packets and error correction packet. If a single bit error in the data bits has occurred during transmission, one data packet is identified as having in it the bit in error. Algebraically the data bit in error is identified and corrected.

Description

Z2~ 7~7 Field of the Invention This invention relates to apparatus for correctincJ a single bit (i.e. binary digit) error occurring in a block ox data, consisting of a sequence of binary digits.

B ground of the invention In digital data communicatioll systems, a sequence of bits (i.e. a signal comprising binary digits) originates from a transmitter and is transmitted throllgh a communications channel to a receiver. If the communication channel were perfect, the sequence of bits received at the receiver would be identical to the transmitted data bits. However, communications channels are not perfect and, because of the presence of noise and other spurious signals, the received data may very well not he the same as the transmitted data. Accordingly, systems have been designed to detect and correct errors occurring in sequences of received data. Such systems determine if some of the bits of the received data differ from the transmitted data, and thereafter correct the error or errors. The coding system disclosed herein permits the detection and correction of a single error occurring in a block (i.e. sequence) of bits.
A bit error occurring in a block of received digital data in data communication systems such as the videotext information system known, in Canada, as Teledyne* (*an official mark of the Govern1nent of Canada, Ministry of Communications, for which notice has been given under Section Noah of the Canadian Trade larks Act) often results in noticeable and I.

7~7 unacceptable picture distortion which, in turn, necessitates requesting, at the receiver, retranslnission of that data block and waiting for some tire interval before the retransmitted data block is received. Both picture distortion and retransmission delays are undesirable and may contribute to user/subscriber dissatisfaction with the data system.
Consequently, it is desirable to be able to detect a bit error occurring in a block of received data bits and to correct the error within the receiver. Such error correction capability allows the correction of a bit error occurring in a block of data before the error results in picture distortion and eliminates having to wait for reception of the retransmitted data block.
Several single bit error correction methods are known; and many different apparatuses for encoding and decoding data blocks to permit the correction of a single bit error have been developed. For example, a group of data packets (e.g. bytes) may be horizontally and vertically parity encoded (i.e. non-algebraically encoded), denoted herein as the "Product Code" r by using one parity bit in each byte and one code byte for each block of data bytes. To encode a block of data bytes using the Product Code one parity bit is appended to each group ox 7 data bits to form parity encoded bytes. Then a hype (consisting of 8 bits), referred to as the Product Code byte, is detennined and inserted in the data block. Each bit (e.g. the 3rd bit) of the Product Code byte is determined from the corresponding bits (e.g. the 3rd bits) in cad- of the data ~2~7~

bytes and is set to either "0" or "l" according to the selected parity, i.e. the desired parity of those bits, talc en as a group. The Product Code is a well known data encoding method. For a more detailed description of this coding method, reference should be made to information theory or codirlg textbooks, or hot.
Another example of a single error correction method is known as the SAY code developed by GEE. Sequin, Pi Ballard and OK ~3hargava and described in A Class of High Nate Codes for Byte-Oriented Information SLY my, IRE Transactions on Communications, Vol. COMMA, No. 3, March 1983.
Two disadvantages of the single bit error correction methods known heretofore, and equipment developed to implement those methods, are (i) the range of the number of data bits which can be encoded, and therefore corrected, by them, is narrow and (ii) some have a relatively high probability of making a decoding error or decoding failure when the communications channel transmitting the data includes white Gaussian noise and/or short noise bursts. (A "decoding error"
may be defined as occurring when a bit correction is performed when the bit was correct or when a bit error is not corrected in the mistaken belief that no error occurred. A "decoding failure" may be defined as occurring when one or more errors are known to exist but where the erroneous hit(s) cannot be identified.) Consequently, it is desirable to develop a coding technique which can encode a wide range of numbers of data bits I I

and which performs satisfactorily in the presence of either white Gaussian noise or short noise bursts.

Summary of the Invention A data encoding and decoding system, suitable for use in a videotext information system, has been developed Whereby one data packet (comprising bits) is provided for each hock of data packets as redundant data and each data packet (including the redundant packet) is provided with one parity bit. This coding method has been called the Carleton Code. The bits of the redundant data packet are determined algebraically from the data packets comprising the data block. The Carleton Code enables the correction of a single bit error occurring in a block of data. (A word of caution is in order. The term "packet" is used in this application in a special sense and does not mean a 33 byte packet as in Teledyne* nomenclature.).
Definitions:
before providing a summary of the invention, it will be helpful, to ensure consistency, to define some of the terminology employed in the disclosure and claims.
lo A "bit" is a binary digit and has one or other of two values. For example, a bit may be either 0 or 1.

2. A "data packet" is a sequence of a fixed number of bits. The well known term "byte" is a data packet having 8 bits. Equally, (with some modification of the method and apparatuses herein disclosed) a data Do --7~7 packet could be selectee having 5, 9, lo or 87 bits, for example.

3. block of data packets is a sequence of a fixed number of data packets.

4. A parity check bit is an extra hit at a predetermined location in a sequence of bits and is used for error detection purposes. Suppose that a data packet has 7 bits. To that packet a bit can be append whose value depends on the number of l's in tile packet. As an example, if it is desired that all data packets have an even number of l's (even parity), the parity check bit is set as 0 or 1 depending on the number of l's in the packet. The parity check bit is 0 if there are an even number of l's in the packet and 1 if there are an odd number of l's in the packet.
Likewise a seven bit packet may be converted to an 8 bit packet having odd parity, referred to as an odd parity encoded data byte. The presence of a parity check bit permits the identification of a byte with a single bit error but does not identify the specific bit which is in error.
The present invention provides an apparatus for selecting an error correction data packet for transmission in a block of (L-l) data packets. The data packets and error correction data packet have M hits and a predetermined selected parity, one of which M bits is a parity cluck bit. The symbol Of is let to represent the binary value of the ilk bit in the I

data block. The ~egl~ence Con at, C2~ CON is let to represent- Lye binary values ox each of the hits ion a data block of length (Nil) bits, where N~l=ML. The sequence (C;

CjM-t-l' CjM+2' -- CjM~(M-l)) designate tile values of each of the bitts in the error correction data packet, j being a positive integer of value between n and L-l. The symbol represents a primitive elemellt: of a Allis Field GF(2P), eying a root of a primitive polynomial OX) of degree P, P being equal]. to M-l, here the arithmetic lo operation addition is performed using oddly 2 arithmetic.
The apparatus for selecting the error correction data packet (CjJ~1r Cam CjM+2' -- Cj My M-comprises:
jam -l . N
(1) means for computing T = Swig + Sue , lo it lo T having an expansion as a pattern of P bits; and, (2) means for selecting the error correction data packet (Cam jam -- CjM+(M-l)) such that:
j Al + ( I
(i) Solely; and My (ii) the parity of the error correction data packet is the same as the parity of the other (L-l) data packets of the data lock.
For the embodiment of the above encoding apparatus, the following selections are made: L = I M = 8; N = 223;
C = X7 + X3 + l; P = 7; and j = 0.

7'7 lo provided by the present invention is all apparatus for decoding a received data hock consisting of L
data pockets. One of the date packets is an [Carleton Code]
error correction packet, and each data packet has a predetermined parity and consists of M bits. The apparatus permits correction of a single bit error in the received data block, and comprises the following:
(l) means for determining the parity of each of L data packets in the data block and, if a parity error in a data packet is observed, recording the identity of the data packet having a parity error;
N

(2) means for calculating R = Roy where it r is the value of the ilk received bit of the received data block and Nil is the number of bits in the received data block; and (3) means for correcting the value of the gth bit in the (Closet data packet of the received data hock if each of the following events occur:
on (i) only one data packet in the received data block has been determined to have a parity error and the parity error occurred in the (Closet received data packet; and (ii) R=~9, where MY g MY + M-l.
For tile embodiment of the above decoding apparatus, the following selections are made: L = 28; M = 8; N = 223;
I = X7 + X3 + 1; P = 7; and j = 0.

The advantage of the present invention, which utilizes the Carleton Code, is that it allows a wide range of ~engtlls of data hits to he encoded so as to permit the correction of a single hit: error occurring in the data bits S upon transmission while still performing acceptably when the data Lutz have keen subjected to white Gaussian noise or noise bursts. The invention utilizes both a parity check bit per data packet and an algebraically ~3etennined check packet.

ROUGH D~XCRIPTION OF THY drawings . . .
The invention will now be described, by way of example only, with reference to the following drainages in which:
Figure 1 i s a portion of a table of Gulls f told elements contained in the Gulls Field GF(27), of 128 elements. Arithmetic using the field elements is performed module 2. Representations of some of the field elements tire. the first few) are provided in terms of the first seven elements of the field, the basis elements of the field, in Figure 1.
Figure 2 is a block diagram of a 7 bit feedback shift register capable of generating all non-zero elements of the Gulls f told GO ( 27 ) .
Figure 3 is a block diagram of a system utilizing the Carleton Code to permit single bit error correction in a block of data.

6~i7~

Figure 4 is a block diagraln of an apparatus for encoding a hock of data according to the Carleton code Figure 5 is a flow chart illustrating, in more detailed form, the process of Foggily I.
figure 5 is a block diagram of a process to encode a cyclones of data hits with a parity bit per byte and a Carleton Code error correction hype.
Figure 7 is a schematic diagram of an apparatus for encoding a sequence of data bits with a parity bit per byte and lo a Carleton Code error correction byte.
Figure 8 is a block diagram of an apparatus for decoding a block of data encoded with a Carleton Code error correction byte.
Figure 9 is a schematic diagram of an apparatus for decoding a block of data encoded with a Carleton Code error correction byte.
Figure lo is a block diagram of an alternative apparatus for decoding a block of data encoded with a Carleton Code error correction byte.
Figure if is a flow chart, illustrating in more detailed form, the steps of the process of Figure 8.

Description of the Preferred Embodiment In the following discussion, it is assumed that each data packet is a byte, consisting of eight bits and that a block of data consists of a sequence of twenty-eight bytes. Of the 28 bytes, 27 are data bytes and the Thea byte is selected 2tj~7~

according to the method dcscrihe~l herein. The Thea byte may be called the Carleton Coda error correction byte.
In easily byte, there aye seven data bits an one parity hit. 'I've parity bit, present in every byte, is necessary in the disclosed emhodiJnent.s of the present invention because the parity hit enables identification of the presence of an error in any received byte. As described hereafter, the error correction byte may result in the identification of more than one bit, in different bytes, which may contain an erroneous bit. Therefore it is necessary to be able to identify toe hype having the error in order to be able to choose which one of the possible erroneous bits is the erroneous bit. Furthermore, it its preferable to he able to identify a situation where more than one byte is erroneous (i.e. where there is more than just a single bit error), and such capability is provided by a parity bit in each byte.
The Thea byte is specially selected, as described in the following pages, so as to punt the identification of a single bit error in a 28 byte block of parity encoded bytes.
The Thea byte is the error correction byte.
Although it is not necessary that the error correction byte be transmitted as the first or last byte in the data block, it may be more convenient to do so, and may be necessary for use with the encoding or decoding equipment selected.
Likewise, the parity bit, of each byte, can be selected and fixed as any of the bits of the byte. However, it is us fly preferable for the parity cluck bit to be the last bit of a byte (i.e. tile Thea Kit of the byte).
To recapitulate, for the purpose only of explaining the invention, a 28 byte data block is considered. Each hype has 7 data bits and one parity check bit. Twenty-seven of the twenty eight bytes contain data. One of the bytes, the error correction byte, is specially chosen so that, in conjunction with the parity hit in every byte, single bit errors in a data block can be detected and corrected. The invention is not limited to 8 bit data packets and 28 byte data blocks, notwithstanding the selection of these parameters for explanation of the invention.
To assist the reader in visualizing a data block, numeral 22 in Figure 3 depicts a block of data and shows several bytes 40, each having eight bits 44 and a parity bit 42. Box 24 of Figure 3 illustrates the error correction byte comprising bits denoted as C0, Of, C2, C3, C4, C5, C6 and C7. Box 30 shows a data block which includes a Carleton Code error correction byte (i.e. bits C0 through to C7).
The present invention provides algebraic means for encoding and decoding blocks of data to permit single bit error correction. The number of bits available for the code is fixed and is the same as the number of bits in a data packet hereinafter selected to be a hype (i.e. having 8 bits), to permit incorporation of the code into a standard videotext information system requiring a predetermined number of reclund~nt error-correctin~ bitts an-l data hock structure. The standard adeptly in Canada for videotext information systems is the North American Presentation Level Protocol Standard (NAPLPS).
If a one error byte correction is to be al~ebrl~cally determined from number of data bytes each byte having a fixed number of bits, (i.e. 8) and, therefore, a fixed maximum value, (i.e. the numerical range available from 8 bits), it is necessary to establish a one-to-one relationship between the data hypes an elements of a finite field. Otherwise, algebraic manipulation of the data bytes might result in numbers (and, therefore, codes) having a magnitude which is not capable of being represented by an 8 bit number. It is necessary to conduct the required algebra within a finite field to ensure that each algebraic computation performed on an element (which is correlated to a data byte) results in another element within that field capable of being represented by a fixed number of bits. To appreciate this the reader might consider that the sum of the two-digit decimal numbers, 43 and 57, equal to 100, results in a three-digit decimal number in the infinite field of decimal real numbers which cannot be represented as a two-digit decimal number.
It is well known in coding theory that Gulls fields provide unique finite cyclic fields, having desirable algebraic properties, which can be usefully used to encode data algebraically. The following is a brief summary of the theory 2~Ç~7'7 used in the present invention which utilizes a Gulls field of 12~ ell?men~s, GF(27).

Comments on Gulls Fields:
It can be shown that there is a finite Gulls field ox 128 elements, GF(27), having elements capable of being represented as a sum of 7 basis elements and for which addition Ann multiplication can he defined. Each element can ye represented by a sequence of seven symbols each of which symbols has only one of two values (e.g. 0 or 1). Arithmetic is performed module 2. (i.e. 1-~0=0+1=1 and 0+0=0=1+1) In particular, there exists a finite field of 128 independent elements denoted as ,CXO, Cal, c~2 ..., ~126 where Axis defined as a root of a primitive polynomial of degree 7, namely, x7 x3 -I 1. Furthermore, because is a root, I OWE 1 = 0, and, C~7 - CX3 + 1 since arithmetic is module 2 (i.e. GF(27) over GO is chosen). Also the field is cyclic i.e.CX127 = 1. Every element of the field can be represented in terms of the first seven non-zero elements cluck, ...,5~6 (called basis elements).
Referring to Figure 1 there is illustrated a partial table of field elements of GF(27) and the corresponding (equivalent) representation of those elements by the first seven non-zero basis elements. For example, the entry in the table of Figure 1 forc~l2 ooze that the thirteenth (non-zero) element of GF(27) isCX12 which may be represented as I + +C~5 (i.e. 0 I + 1 I +

o-G~2 + 0 I I -I okay). This may be shown as follows:
clue = ~7.~5 = (c~3 + 1)~5 [Recall thatch = I + l]
= Go +C~5 -C~7-c~-~c~5 = (c~3 -I 1)C~+C~5 = Cal +C~4 I
The swig +C~4 ~CX5 can be written a owe + 1~G~1 +
o c~2 + O 3 -I 4 + l I + okay which in turn can be represented by the coefficients of that polynomial. That is,C~12 may be represented by the 7 bit number 0100110. Each of the bits is the value of the coefficient of the polynomial Cal + I Go The leftmost bit being the value of the coefficient of and the rightmost bit being the coefficient ofC~6.
Referring to Figure 2 there is illustrated a 7 bit feedback shift register which can be utilized to generate all of the 7 bit coefficient representations of the non-zero field elements of GF(27) for the primitive polynomial X7 + X3 +
1. To do so one loads the register initially withcxo (i.e. Lowe, where the l is placed in the least significant register element lo), as shown, and repetitively shifts the register one bit towards the most significant element (in this case to the right) to generate each successive field element.
Each shift of the register has the effect of multiplying the contents thereof by I. The appropriate configuration of binary ~6~7'7 adders) and register elements necessary to venerate the elements ox a given Gulls Field is well known. The conjuration illustrated in Figure 2 is the appropriate shift register configuration to generate the coefficients of the Thea degree polynomial representations of elements of GF~(27), using module 2 arithmetic.
cause every field element can be represented as a polynomial of the sixth degree (i.e. as zoo ill +
I + Z3~ -I I + z5~5 + z6~6)~ and as the Gulls Field is closed? any sum (or multiplication) of field elements is within the field and may be also represented as a sixth degree polynomial. Thus, the sum kiwi i JO
requires only seven coefficients and is, at most, a sixth degree polynomial.
Further the polynomial Z0 + Zlc~l + Z2 2 + z3 3 +
z4~ + z5~5 + z6~6 can be represented by the sequence of its coefficients as (Zoo Al' Z2' Z3~ Z4~ Z5~ Z6)~ it being appreciated that the coefficient in potion 6 is the multiplier for ~X6, and so forth.
It is to be noted that the foregoing comments are specifically directed to the Gulls Field GF(27) defined by the primitive polynomial X7 + X3 + 1. As a reference to many mathematics texts will show, Gulls field theory is general, not specific. The above is merely an example for descriptive purposes, assuming the use of module 2 arithmetic (i.e. the Gulls Field GF(27) is selected over GO).

ala Jo to 7 Encoding Introduction slaving described the properties ox a Gulls field, employing muddle 2 arithmetic, the selection of the error correction byte is next considered in a general fashion.
There are 224 bits in a 28 byte data block.
(8 x 28 = 224) Each byte has seven in~onnatlon hits and one parity cluck bit so that each byte has fixed parity, selectee hereafter to he odd parity. Let C0 denote the value of Tao first bit, Of the value of the second bit, and so forth. The bits of the data block can then be represented as the sequence [Co, Of, C2, ... C223]- Each Of, of course, has one of two values (either 0 or 1).
If it is assumed that the error correction byte is the first byte then the first byte is the sequence [Co, ...
C7], and C7 may be selected as the parity check bit of the error correction byte.

In the present invention, [C0, ... C7] are selected so that the polynomial sum Swahili equals i = O
zero, i.e. the sequence (0, 0, 0, 0, 0, 0, 0), and the bit sequence C0, ... C7 has the same parity as the data bytes The sum may be represented by a seven bit sequence, each bit representing a coefficient of the polynomial sum.
As a module 2 arithmetic is employed, this means

5 that: Sue = Seiko it it Restating thus essential point, bits C8 through to c223 are fixed because they contain either data or a parity bit. jut, bits C0 to C7 are open for selection and, for the reasons noted below, are chosen so that Sue= 0 i O
Decoding - Introduction -Suppose that a sequence of 224 hits, including parity bits and an error correction byte, is selected such that lo Sue = 0 at the transmission of the block of 224 it bits. Let n, for Owe, denote the received bits.
Decoding is a two step process.
First, the parity of each byte is examined. If a 15 single bit error has occurred, the parity bit will reveal which of the 28 bytes contains the error. Thus, checking the parity of each byte will locate that byte which has a bit error, but not which bit of the byte was wrongly received.
Denote the byte with the error as the ilk byte.
Second, assuming a single bit error, it is known that Swish = 0. Also, i-t is known that the ilk it byte contains one error. This means that tune error is in one of the bits r8j, r8j+l~ r8j+2' 8j+7 Therefore, 2~3 Roy equals one owe 8j,~ 8j l, ..... or ~8j 7 it because one n is incorrect. By computing 3 rip ' it it which, since only one byte (the Thea byte) has a purity failure, must be one and only one Ox ~8j, ~8j-~1.,.~ Jo the exact location of the error may he determined, being one of r8;' 8j+1' I r8j+7- Avon located the single bit, which has an error, the error is corrected by changing a received 1 to 0, or a received 0 to 1.
with the completion of the broad overview of the techniques for selecting the error correction byte, a detailed examination of the method and apparatus for choosing toe error correction hype follows.
Encoding To give one example of a method of encoding data according to the present invention, the data bits may be denoted such that each data byte contains 7 information bits in the least significant 7 bits of the byte and 1 parity bit in the most significant bit of the byte. Odd parity is selected.
Thus, if the first 7 data bits of the first byte are 1011011, the parity bit is 0, and the bits are denoted C8 to C
where C8 = 1, Cog = 0, Coo = 1, Oil = 1, C
= 0, C13 = 1, C14 = 1 and C16 (the parity bit) =
O.
The Carleton Code byte comprising bits C0 to C7 is selected, as discussed above, so that the following statements are true:
1. Of I = o (where the elements are the Gulls field elements i-0 described above, in 7 bit form.) i7~7 2. Thy pullout of the error correction cove hype is the same as the parity selected for the data bytes, (i.e. for the example disclosed herein, odd parity).
Consequently, since module 2 arithlnetic is used the sum it is equal to the 7 bit sum Sue.
it it Parity bit C7 is required such that Sue = 0 it remains true. Accordingly, if odd parity is desired and the parity of C0 to C6 is odd then C7 is selected as 0.
However, if the parity of Co to C6 is even C7 cannot ye selected simply as 1 without modifying C0 to C6 so that the sum Swahili retains Nero. An example will serve to it illustrate this. In both cases, an odd parity code is desired.
Case I
( Sue i has odd parity) i = 8 assume that Sue i is represented as 1010100 i = 8 (i.e. odd parity).
C0 to C7 are required so that:
1) Of I = 0 i = O
and, 2) C7 sets the parity of C0 to C7 to be odd.
(i.e. an odd number of l's).

~.2~tjfi7~

If we select CO to C6 as Lowe and C7 as O
the requirements ox (l) and (2) above are satisfy. This is so ~ecauscC~ I I are just the individual bit seqllellces, 1000000 to 0000001, Leo representing simply toe bit position, and do not add any information to the bits CO to C6. That is, COO = 1 x ]000000 = COO if cowl. However, this is not so for Cx7 which is represented by Lyle (i.e. none of Co to C6).
In toe case of odd parity Co to C6, C7 can be set to O since the addition of a O does not result in any chancre to the desired sup Sue, or thy it parity of Co to C6 (i.e. 1010100).
Case II
( Sue i has even parity) i = 8 Assume that 223 C i is represented by 1010101 (i.e. even parity).
i = 8 Again, CO to C7 are required so that:
1) I Of i = O
i = O
and, 2) C7 sets the parity of CO to C7 to be odd.
(i.e. an odd number of l's).
If CO to C6 were selected to be 1010101 (i.e. equal to the sum Of ) and C7 selected to be 1 (i.e. to set the overall parity of CO to C7 odd), the sum Sue would equal i = O

i'7'7 i.e. represented as 10010 n o . I c ordinal, since module arithlnetic applies, I Lowe, must be ad-led on to On to Oh if the recolored sum is to be zero. Therefore, instead of simply again a 1 for C7, lO()lOOl is added to the sum Sue, i Jo to produce the Carleton Code byte On C7. (It will he noted that Gin has even parity and therefore does not change the parity of Co to C6.) Conclusion of Case I and Case II (above):
-The code byte (i.e. C0 to C7) may be selected as follows so that the code hype, in this example, has odd parity:
Co to C6 are selected such that the sum it equals the sum Sue and it I
1) if the sum has odd parity, C7 is selected to be 0.
or 2) if the sum has even parity, C7 is selected to be 1 and 1001000 is added to C0 to C6.

Hornets Method-There exists another useful form of the equation 2~3 Sue = 0 which can be used to manipulate data it i'77 bytes rather than each delta but Of. It is also useful in that only one Gulls field elelnent is needed to determine the Carleton Code error correction Tut. That Gulls ruled element is assuming that 8 bit data bytes are considered). If there are 27 data bytes and l error correction byte is desire the bytes can be denote I to By Correspond to C0 to C223~ descried above. (i.e. I corresponds to the sequence [Coy Of ... C7~ and By corres~ollds to the sequence [clue to C223~ 9 demonstrates an alternative, algebraically deter milled font of the sum I Seiko = O
it If the Thea byte is By = (by I byway ' biro) then: (224-8i -I j) ill Jo ' (by I 23 + ..... -I by I 16) -I + (b28 I 7 + b28 0~)=
this can be rewritten as (by I + by I -I -- + by 0 Jo + (b I 7 + by 6 + -- -I by I Jo +

+ (b 7 + b28 I + -- + b28,0 = O
Hornets method of determining polynomials may be used to determine the above. Also similar to the case of summing each Seiko previously discord in detail) the code byte may be determined as follows:

28 By (I ) + By (I 8)26 -I + B (I Al ------(l) B28 = ( ( Blue + By + ..- -I B27)~ I

where, By = (byway 7 , by I ) >6t;7'7 It will be noted that the representation I as an 8 bit number, is the seine as the represelltatioll ox I as an 8 hit number. That: is, as an hit number byway if bit hi 7 equals 1, is represellted as Inn), arid, as an 8 bit nunnery, Lowe 7~7~ if bit hi 7 equals 1, is also represented as lOnOOnOn.
Ike correct parity of the code byte can be ob'.aine~l by using the appropriate field element: representation of I, where recolor. That is c~8 may he represented hyCX~ I
or I I I 1, since I ~C~3 -I 1 is equal to zero ho definition.
This couplets the discussion of encoding. Decoding is next considered in detail.

Since the Carleton Code error correction byte [Co, ...C7] has been selected so that the sum Shelley = O, and because every byte has a parity bit, it we can identify any single bit error in a data block at the receiver following transmission of the data block, and therefore correct it, by evaluating the sum and, if non-zero, correlating that sum to the corresponding Kiwi, i being the number of the erroneous bit. This is so because each bit, C0 to C223 has an I assigned to it. Thus it one bit, Of, is incorrect its representation I will appear as the sum Sue. Recall that single errors only are i JO

corrected.

It will eye noted that there is Gore thin one bit assigned the cle~ellt Kiwi, ncllnely, Of all Sue zinc there are more elelnelll-s in Lowe Shelley) data hock than Allis field elements in ~F(27). (That it, the data hock chosen has 22~ bits while the Gulls phyla has only l27 non-zt-~ro elements.) Accordingly if toe sup Sue equals S
it (S being a 7 bit number and therefore nece~c.arily equcll to some Kiwi), S may represent two bits. This indeterminance is eliminated by having each data byte parity encoded. That is, if there is only one bit error occurring in the data block there will be only one byte having incorrect parity.
The incorrect hit may be idelltified as the hit which is represented by the 7 bit sum, S, and which lies in a byte having incorrect parity. The process of decoding may he illustrated as follows.
Suppose that during transmission of the data block bit C127 in byte B12 is changed from a O to a 1 (due to noise in the communications channel for example). This means that ~127 = Cx, and represented as 1000000, will be added to what otherwise summed to zero and the sum Sue will correspond to Clue C~
i JO
Therefore the incorrect bit could be either of C0 Or I clue. If we check the parity of hype I (containing C0) and byte ~12 (containing C127) and find that I

only B12 ho a rarity pharaoh Tony Kit Clue is the erroneous hit and can he chclrlgcrl (i.e. corrected). (It hot hypes show incorrect parity then a rlecodin~J fuller has occurred and the bit errors cannot he corrected ho the resent code. That is the condition that at toe most: a single hit error has occurred is no satisfied.) A coding ,Cvsl,enl utilizing the Kiloton Charlie:
Referring to Figure 3 there is illustrated, in hock diagram forum, the general stews involved in the process of encoding and decoding data using a Carleton Code error correction hype 20, chosen as descried above.
The illustrated system involves a hock 22 of data bytes 40, each byte 40 comprising eight bits 44 and each byte 40 having one parity bit 42 being the most significant hit in the byte. The Carleton Code error correction byte 20 is then calculated 24 for the data block 22 and appended to the data block 22 to form an encoded data block 26 having twenty-eight bytes. The encoded data hock 30 is transmitted 28 and received 32. The data block is then decoded to identify, a single bit error occurring therein 34. If identified, the incorrect hit is corrected 36 resulting in a received data block identical to transmitted data block 22.

The Encoder -(i) An encoder which operates on data bytes successively:
Referring now to Figure 4 there is illustrated, in block diagram form, a process to encode a block of data hypes Al 2~i77 to permit sunnily hit error- corrector usir)cl a Carleton Code error correction hype. The Rex exemplified ho FicJure involves a hlocl; of data huts I each data hype having a parity hit. The Carleton code error correction byte 58 (designated as ~28) is ~eter,nin~cl I according) two Homer s method of evaluating the polynomial (2) ahc)ve [pace 22, line 28] an the Carleton code error correction byte 58 is then included with the bloc of elate bytes I to form an encoded hock of data 54.
Figure 5 illustrates a flow chart which identifies steps of a process which can he used with computation means, such as a microprocessor, to encode a block of data bytes to permit single hit error correction. This process utilizes the polynomial detel-~ination (2) above involving ornery s method.
In the example illustrated by Figure 5 the number of data hypes to be encoded is taken as 27 though- it will he appreciated that a multitude of numbers of data hypes might be encoded satisfactorily according to this process.
The process of Figure 5 begins with the step of setting two 8 bit registers. Register i is set to 1.
Register A is set to 0. Next, register X is given the value of the ilk data hype, that is, the value of I (which initially would be I Then register X, i.e. By is added to register A and multiplied by (the root of GF(27), descried above) eight times, successively. Multiplication by OX, using eight binary elements, may be efficiently accomplished by shifting, by one element, the binary elements towards the foe most si~ni~;cant clement (in Sonora fashion to the generation of field elelnents by the phallic shift resister i11ustral-ed in Figure 2 and descnil>ed alcove). It thy must si~3ni~icant bit is a 1 (i.e. if register contains the elementCX7 in its representation) then multiply ho I results in (equal to I + I) which must be keyword into toe value of the product of register A an I. To carry Go (if present) I is added to the product by adclincJ Oily to the product.
Since the representation offal as Al I has even parity, the equivalent representation, I 3 I + I having odd parity, is alluded to the product.
[Recall thought Go -I 1 = 0.] Iris is because it is desired that the Carleton code byte have odd parity; however, the operations noted above would indeterminately change the parity of register A if an odd parity representation of I
were not used. This is evident from the fang: Register begins with odd parity (i.e. 0) and 27 odd parity data bytes are added to register A, resulting in an odd parity number, but sometimes a 1 is shifted out of register A which will change its parity. Therefore, since is always added to register A when a 1 gets shifted out of the register, the parity change due to the loss of the 1 may be effectively concede by rehanging the parity when is added.
Accordingly, odd parity I is added because an odd parity number added to another number (of odd or even parity) will always result in a Norway having the other parity.

I

I(-llowinc~ multipl;ccltioll by eight times (i.e. multiplication Buick) the next allele Tut, the lath data hype, its added to resister and thy? steps of multiplying the value ox requester A hyCX~ are Wright. When the above is repeated for all of the elate hyt:ec; innately all of Thea data hypes have been added to register end multiplies Buick.
The result, in readjust I, is the Carleton cove error correction hype for the 27 data hypes. Appendix A illustrates a microprocessor program, written in assembly language for a MOTOROLA ~809 microprocessor, which substantially performs the steps of the flow chart of Figure 5, to determine a Carleton code byte for a data block.

(ii) An encoder which operates on data bits successively:
Referring now to Figure 6 there is illustrated, in block diagram form, a process to encode a block of data hits to permit single bit error correction using a Carleton Code error correction byte. The process exemplified by Figure 6 involves a block of data bits 27n consisting of 27 x 7 (i.e. 189) data I bits; however, the process disclosed may be applied to other bit numbers (e.g. 23 x 7 data bits, 30 x 7 data bits etc.).
The data bits in the block of data bits 270 to be encoded are received serially. The nwnber of "1" bits in each group of 7 received data bits is determined and the parity of the group of data bits is thereby identified 272. For example, if three "1" bits are present in the group of data hits, the foe group has offal laureate. If two "I" bits ore present on the grout of data hits, the gruel has even parity. Roy parity ox the grout-) of 7 data hits is l-hen set to the selected purity 272, for examl-1e, to odd parity, ho proclllcing an Thea hit and appending it to the group ox 7 data hits. The Thea hit is either "1" or "0" depen-lirlg upon the desired parity. For example, it odd parity is selected and the group of 7 data bits contains three "1" hits, the Thea laureate hit appended to the grout of 7 data bits is selected to he binary Nero i.e. a "0"
hit. If the group of 7 data hits contains two "1" hits, the Thea parity hit is selected to prowls an oddly nulnber of lo in the 8 bits (i.e. the 7 data hits plus the parity hit), and is therefore selected to he binary one i.e. a "1" bit. The resulting block of 27 8-bit hypes 274, each consisting of 7 lo data bits and 1 parity bit, is then encoded with à one byte Carleton codeword.
For convenience, individual bits of the 27 parity encoded bytes comprising data hock 274 are denoted C224 C223~ I where C217~ C2~9,.-- C8 are the parity bits and the relnaining Swiss (for icky) are data bits.
As descried in more detail above, to encode data bits Cog through to c223 With a one byte Carleton codeword, the sup Swahili is calculated 276, to it produce a Thea degree polynomial representation of the Gulls field element of GF(27), hying equal to the sum, one hit it re~reSerl~ing each suffusion of elf ~olyllo1nial. The l y l l Ox US C l SHEA inn crewelwork.

method of evcllu.lting a polynomial 27~. Ilowevc-r, since the sun is "quaff" at it cad, intermediate Of adder to l-he partial prodllct (~roduce~l using Horn2r's ~etilocl of evaluating a polynomial) mutt be mutinied ho I if the SUM
I
Seiko is to he produced and not the sum it in Sue. To overcome this effect of the it "cut-off" at it the sum L Sue is calculated it according to the relationship I
C223~8)~) + OX Cog .
The Carleton codeword, consisting of one hype, denoted C0 to C7, is determined 278 from the polynomial sum 2~3 Sue, represented by 7 hits, each bit corresponding it to a coefficient of the polynomial. The Carleton codeword consists of the 7 bit representation of the sum Sue, parity encoded with an Thea hit (i.e. C7) in it such a manner that the sum Swig equal Nero and the ion parity of the codeword is set to the selected parity of the data hypes. As explained above this is accomplish ho se]ectinc~ a n" parity hut folk the? Thea hit it the art of the 7 Kit re~r~sentatio1l of Sue is okay or, if the 7 i -n Kit representation hat even parity, ho adding muddle 2 the hit 1~lJ~1-er lnnlnnn] (i.e. I +C~3 -1-~7) two the 7 Kit sup, to fume the bit codeword.
The 8 bit Carleton codeword is tlle1l appended to the hock of parity encode-7 data ~ytcs 2~0 to form a I byte block 2~2 encoded With a one byte Carleton codeword lo aurora encoder:
Referring now to Figure 7 there is shown a diagram of a circuit which receives a block of data hits to he encoded with one parity bit per seven data hits and following the receipt of a hock of data bits, one Carleton codeword comprising l byte. It will be appreciated ho the reader that the embodiment of Figure 7 which im~leme1lts, the present invention is specific and just one example of circuitry capable of implementing the present invention. A multitude of equivalent circuit components might be used to accomplish the on task of one or more discrete circuit devices depicted in Figure 7 without departing from the scope of the present invention. The circuitry illustrated in Figure 7 and described below, is given by way of example only in recognition that variations thereof may be selected for different applications.
For the purpose of illustration and convenience, the number of data bits selected to be encoded ho the logic circuit of Figure 7 is 27 x 7 (i.e. ]89) data hits. Following each '7 glO~Ip 29~ of 7 data hits recc?ive(l a parity hit is producer and apl?ellded to the data bitts to produce an Thea hit, being a parity hit, which sews t he parity of t he hits to the selected parity. In the eliminate of figure 7, the parity selected is odd parity and thel-e~ore each grout of parity encoded data hits at the output 342 of the encoder has odd parity.
To encode each group of 7 received data hits 29~ with one purity bit a switch 306 is used together with circuitry which produces the appropriate parity bit for the group of 7 huts, the circuitry comprising binary adder no, resister 302 and inventor 304. Switch 3n6 remains in position 1 until 7 data hits have keen received. (The counter controlling switch 306 is not shown.) Initially register 302 is set to binary 0. As the 7 data bits ore received, binary adder Ann adequacy the value of the received hit to the values of toe previolJsly received bits in the group of 7 bits. The received bits are successively added together using module 2 arithmetic and the sum is stored in register 302. When the Thea data bit has been received, register 302 holds the module 2 sum of the values of the 7 received data bits, which sum is inverted by inventor 304 to produce the appropriate parity bit to set the parity of the group of 7 data hits plus the parity bit to odd parity.
For example, if there were 3 "1" bits in the 7 data hits, register 302 would contain a "1" following the receipt ox the Thea data hit and the output of inventor 304 would be "0", so that the group of hits (i.e. 7 data hits plus 1 parity ~.2~iÇi7~7 bit) have odd parity Mueller, if there were 4 "1" bits in the 7 eta wits, Roy ton 3n2 oriole contain a "0' fulling thy receipt of the Thea ala Iota anal the output of inventor 3~4 would be "l", so that the ~Jroul- Or bits (i.e. 7 data bits plus 1 parity lit) have odd parity. Switch 306 is swished to position 2 phony t-he receipt of the Thea Lotte hit so that the parity bit produced it the output of inventor 304 is received at switch on and is tllereaFter transmitted out of the encode- at switch 330, lo Register 3~2 is then reset to on zero and switch 3n6 reset to position 1 to receive the next 7 data bits in like manner and produce a second laureate bit in like wanner, and so on, until all data hits have been received and each group of 7 data bits has been encoded with a parity hit.
The feedback shift register 400, comprising registers 308, 310, 312, 314, 316, 318, and 320 and binary adders 322, 324, and 326, calculates the sum Sue for the it parity encoded data hypes received at switch 306.
The feedback shift register cycles as each data bit or parity hit is received at switch 3~6 ire. the value in each register 303, 310, 312, 314, 316, 318, 320 of the feedback shift register is shifted to the next register or (i.e. for register 32n) is fed back into a proceeding register. It will be recalled from the above discussion that the configuration comprising registers 3n8 to 320 and binary adder 324 is capable of generating successive elements of GF(27) when cycled (see 67~

also ire-? 2). binary aiders 322 and 326 effect the adulation ox CjC~ to the content-s of the fee ask ski it: resister as each hit, Sue hying either a "1" or a "0", is received at switch 332, so. rye con a a-l-lit:i~n of Sue to the shift register together with the cycling of the shift register as each lit is received at s--itcl- 3n6, lo (which colossus the contents thereof to be multiplied ho I) effects 1-he co~plltation L Sue' calculated according to ~lortler's method of J

I
evaluating the sup, as discussed above with respect to Figure 6.
switch 330 So is in position 1 until all data bits and parity bits for the kowtow hock 298 have keen received at switch 306, Sly Therefore, the data bits and parity bits received at switch 306, Sly are transit as part of the encoded data 342 output, comprising 27 parity encoded data bytes, i.e. C223 to Cog. (The Carleton code error correction byte will complete the encoded data output block.) Switch 328, So, is also in position 1 during this period, as on is switch 332, So. As data and parity bits are received at switch 332, So, the feedback shift register is cycled, which effectively multiplies the contents thereof byCX as described above. A "1" is added to registers 310 and 316 if the received bit, Of, is a "1", ho adding the received bit to adders 322 and 326 which feed into registers 310 and 316. since, as described above, registers 310 and 316 represent the Gulls field elements Cal anorak, respectively, and CX1 + CX4 is I

en , to o(lUCt I CUR icky; Allah] to the phallic shift- e-Jister if the receive-l bit is a "l" and tile pr(>(luct I = n is aided to the shift reg;stel- if the received hit is no Ilhell the asset: bit is received, hying hit C~3, a parity hit, the phallic shift register is shifted i.e. cycled, and COG is Audi to Lye feedback shift resister, felon which registers 3()8 to 32() contain the representation of the Sloan Sue (i.e. the it ] n coefficients of tile 7 degree polynomial corresponding to the sum) .
The parity of the 7 hits contained in registers 308 to 32n anal representing the sum Seiko is determined it by the combination of logic devices consisting of binary adder 336, register 338 end inventor 340. One input to adder 336 is the value of the feedback bit of the feedback shift register, the feedback bit hying the bit shifted out of register 320 and into register on upon each cycle of the feedback shift on register. The feedback bit is also added, by binary adder 324, to the contents of register 312 upon cad- cycle of the shift register. If the feedback hit is a "1" then a "L" is removed from the feedback shift register once (i.e. shifted out of register 32n) and added to the feedback shift register twice (i.e. the feedback bit shifted into register 308 and the feedback hit added module 2 to the contents of register 312 anal shifted into register 314). Thus" overall, one "1" (an odd of ' `-~

nunlher^ of l's) its added to the feedback shift register, causing the laureate of tile contents of the shift reg;steK to change (since an odd parity binary number added to any binary nu1nber results in a binary number of the opposite parity).
Consequently each change in the parity of the feedback shift register (which initially is set to 0, i.e. even parity) is monitored to determine the resulting parity of toe feedback shift resister wll~n it contains the representation of the sum Sue. The feedback bitts, one resulting upon each 10 it cycle of the shift register are added together by adder 336 to produce a bit in register 338 which corresponds to the parity of the contents of registers 308 to 320 (i.e. the parity of the binary number represented by the feedback shift register).
Register 338 is initially set to zero before the first data bit is received so that the first feedback hit shifted out ox register 320 is shifted into register 338. Upon each successive cycle of the feedback shift register, a feedback bit is added, by binary adder 33h, to the value in register 338 until the time at which all data bits and parity bits have been received at switch 332, So, when register 338 contains either a "1" (if the parity of the feedback shift register has changed an odd number of times and therefore has odd parity) or a no (if the parity of the feedback shift register has changed an even number of times and therefore has even parity). Inventor 340 inverts the hit in register 338 to produce a parity bit for - foe -the Carleton Colorado. This bit is a 1 if the sum Sue ho or I fly, or a no tile sum Sue has ode parity. switch 33n, So, switches I ion to position 2 felon the receipt of all data bits and parity bits at switch 332, So and the parity bit for the Carleton codeword, appearing at the output of inventor on is transmitted 342 (ire. bit C7 Of the encoded data bloc in Lyon switch 330, So, is in positioll 2 and the parity bit of the Carleton codeword is being transmitted, the feedback shift register is not cycled. That is the cycling of the shift register is skipped by 1 hit while the parity bit at switch 33n, So, position 2, is transmitted. Cycling of the feedl7ack shift register resumes following the transmission of the parity hit of the Carleton codeword and switch 330, So, is switched to position 3 at that time.
To complete the discussion of the process of calculating the parity o-E the shift register it should be mentioner that the parity of the shift register is never changed by the addition of Sue i.e. by the addition of the bit received at switch 332, So to registers 310 and 316 by binary adders 322 and 326. This is because the bit is added twice (i.e. an even number) to the shift register and two bits or two "0 bits added to a binary number does nut change the parity of that number since an even parity binary number added to any binary number z results in a binary number having i6~7 the seine parity as the nailer z. Consequently, it is unnecessary to monitor the hit received at switch 332 since it does not produce parity challtJes in the feedback shift register.
Following the receipt: of all data Ann rarity bits at switch- ~32, So, it which tine registers 3n8 to 32n represent the sun Sue, or, alternatively, hollowing the J

transmission of the Carleton code parity bit, switch 328, So, is swished to position 2 so that the contents of registers 3n8 to 32n are not modified ho the audition of the feedback bit from register 320 as the feedback shift register is cycled.
The feedback shift register is cycled following the transmission of the Carleton codeword parity hit, C7, causing the contents of register 320 to be transmitted 342. As the shift register shifts out the contents of register 320, switch 332, So, switches to position 2 and the value of the Carleton codeword parity hit at the output of inventor 340 is added TV
the value in register 308 and register 314, representing and C~3, respectively. As discussed earlier in more retail the addition of 1 +CX3 (i.e. equal to C~7), to the sum Sue, is necessary if the parity of the sum is it even, to ensure that the sum Swahili is zero. That it is, the addition of a "1" parity hit, C7, effectively adds the value CX7 to the codeword and so, adding C~7 again i77 effectively cancels the algebrclic effect of the edition o the l parity bit. Accordingly the value l ~C~3 is add to the feedback shift resister as the bit in resister 320 hit Oh of the Carleton- coc3eword is shuttle out.
Lyon bit I ox the Carleton codeword is shifted out of the phallic shift wrester switch 332 So is switched to position 3 so that lie contexts ox the feedback shift requester does not undercJo further aclditiolls. The shift register is theft cycled successively (six times) until the lo contents of registers 31n to 320 have keen shifted out and transmitted 3~2 as bits C5 through I of the Carleton codeword. Then bit C0 has been shifted out the feedback shift register the encoded data hloclc C2~3 to C0 has been transmitted 342 comprising 27 parity encoded data bytes and l Carleton code error correction byte.
Appropriate clocking means to operate the discrete logic devices and switches of Figure 7 and appropriate means to reset logic devices where necessary) are not illustrated in Figure 7 but can be c3esigned and implement-] by anyone skilled in the art according to the desired received data bit rate and circuit devices selected. Each of the circuit devices illustrated in Figure 7 are basic logic devices known to anyone skilled in the art and any such person is capable of selecting appropriate (i.e. compatible) devices available in the marketplace to produce appropriate circuitry according to that shown in Figure 7 end described above.

67'7 The ~ecofler _ _ (i) decoder keelhaul of utile _ no all elements of GF(2 ):
Referring to Figure there is illustrated, in bloc diagram form, an alerts to Dick a block of data hypes hovel one Carleton Code hype. In Phase I, 22~ data bits in form I are shifted into a data buffer 72. Contemporaneously each hit is fed into the following:
(l) counting means 74, to count the hypes (l to 28) correspolldin~ to each bit count;
lo (2) parity check means 78 to calculate the parity of each 8 hit sequence corresponAiJl~ to one hype;
and (3) feedback shift register means 82 to determine the 7 hit Gulls field element CXi, corresponding to each hit Of, and determine 2~3 the sum Sue.
i JO

The count of counting means 74 is stored 84 when the parity of the data byte is detennined ho means 80 to be I incorrect. After all of the data bits have been shifted into the data buffer 72 Phase II commences. The bits in data huller 72 are then successively shifted out of the buffer 72 so that the first hit shifted into the buffer 72 is also the first hit out of the huller 72 (i.e. FIFE) 98.
Felon the input of all of the data hits shifted into the huller 72 the sum held by the phallic shift register 82 contains n, if a single bit error has not occurred, ours it corresponding ~-~ Of or Swahili if a s;n(Jle bit error has occurred Foe? TO (data out phase) ox the decodinc3 meted of ire 6 is next: cons;dere(l. Inuring Phase II there us no data input to hoofer 72, counting meals 74, parity cheat< means 78 or shift resister 82 Inuring the subsequent register shifts, wherein the data hits are shifted out of Burr 72 and there is no inherit to feedhacl; shift register 82, the feedback shift register 82 is I cycled synchronously with the shi~tinc~ out of data hits from the huller 72 so that with each cycle tile contents of the register 82, being either () or owe, is multi] ted ho (i.e. surnmatation with a data hit is not performed). Comparing means 90 monitors the contents of register 82 and when it equals owe a flag is sent to means 94 to determine if the current output bit should be changed. Contemporaneously with said cycling of register 82, the counting means 74 counts bytes (1-28) corresponding to each 8 bits shifted out of buffer 72.
Comparing means 86 compares the byte number of the current output hit to the stored byte number of a hype having incorrect parity and a flag is sent to correction means 94 causing Sue means 94 to change the current output hit if the current byte number its the same as that having incorrect parity and the contents of register 82 i~sC~223 That is, both conditions must occur. It will he apparent to the reader that if register 82 holds the value of Eli when a] l data hits have been shifted into the buffer 72 (i.e. at the end of Phase I) then if the 67~

register 82 is suckle repetitively as successive bit are shifted out of toe buffer 72 until it roaches a vow of C~23, the bit hying shiftily out of hoofer 72 at that time is Of (i.e. the data hit correlated to I) because the first bit shifted into buffer I is also the -first hit shifted out in Foe Il.
To determine whether a decoding failure has occurred three deterlninat..ions are necessary in Phase II:
Al) means OR to count at least two Lutz having incorrect I parity and setting a decoding failure flag if the count its greater than l;
(2) comparing means 92 determines whether the value of the resister 82, sometime after all data bits have been shifted into buffer 72, is zero and determines from counting means 88 whether the number of bytes having incorrect parity is greater than or equal to one. Decoding failure is flagged when register 82 is Nero and the number of bytes having incorrect parity is greater than or equal to one; and (3) means 96 to determine whether a correction was made to a data bit (after all data bits have been shifted out of buffer 72) and means to determine if the value of register R2 is non-zero. If a correction was not jade and register 82 is non-zero a decoding failure flag is set.
It will be evident to the reader that there are many different circuit devices, or combinations thereof, made by a - I -multitude ox manufacturers, to perEor~l the operation; inadequately in figure 8. emhodilnent- of a decoder hill fllnctions according to the flow clarity of Faker is decal by the logic circuitry of Figure ') to decode a data hock of 224 hit;
encoded with a Carleton Code error correction hype.
Referring now Jo Figllre 9 a 224 hit shirt wrester 11n is selected as the data buffer 72 of Logger 8. A ] to 8 counter 112 is selected to count data bits as the hits are shifted intro registry 11n (Phase 1) and as they are sifted out of register 11n (Phase II), and a 1 to 28 counter 114 is selected to count data bytes as they are shifted into register 110 (Phase I) and shifted out of register 110 (Phase If), corresponding to hock 74 in Figure 8. During Phase I switch A
is closed so that a parity pharaoh occurring in a data bit triggers the binary registers 116, 118, 120, 122 an 124 and causes the count of counter 114 to he entered into said binary resisters 116, 118 120, 122 and 124 so that the number of a data byte having incorrect parity is stored in registers 116, 118, 12n, 122 and 124. (i.e. esters 116, 118, 120, 122 and 124 each represent 1 bit of a 5-bit number ranging from 1 to 28.) To determine the parity of the data hypes the circuitry selected comprises binary adder 142, binary register 148, AND gates 144 and 152 and inventors 146 and 15n. Binary adder 142 performs mud 2 arithmetic (i.e. 1 + 1 = 0). A
clock, synchronous with the shifting of data hits in and out of register 110, is used to drive the circuitry of Figure 9 it ego. the counters 112 an ll4) allele can easily be procluc~d accor-lin(l to known methods, warily the desirec7 equals ox the clock is the desired recJllency of Lyle hit shirts. Ire can assay that register 14~ is cleared, initially, so that it S contains zero and that the first input bit gets shifted into register l48 (having been aided ho binary adder lo to "n").
Ire eighth bit of counter 1]2 is low (i.e. a "n") until eight data hits have been counted and there have been eight bits shut inlay register ]48. Therefore, the input to AND gate in 144 from counter 112 is high (i.e. a "1") after bits 1 to 7, of cad- input elate hype, have keen shifted into register 148, having been inverted by inventor 1~6. Since the outright of inventor 146 is high for each input bit 2 to 8, of each input data byte, bits 1 to 8 are added to each other successively.
Also, when hits 2 to 8, of each input data byte, are shifted in the output of AND gate 144 will he equal to the last bit shifted in. That is, the value of register 148 will be the sup of bits in each 8 bit data byte which have been shifted in at that point in time. Once eight bits have been counted AND gate 14g goes low because the eighth bit of counter ll2 will be high and therefore the input to AND gate 144, being the output of inventor 146, will be low. Therefore, after eight data bits have been counted the value of the next data bit is input into register 148, having been added to zero. The above is then repeated so that as soon as each 8 bit data byte has teen shifted into register fin register 148 holds the value of the parity of that byte, namely, "1" if the hype had old parity or - I -

6~7~7 no the hype Howe evil parity. Sue no e ox ] laureate is chosen for tile data of figure 9, a "()" appearing on register l48 Philology the inlet of the eigl1tll bit of a data hype, indicates that that hype fled incorrect parity. Accor-ling1y, AN gate 152, which trigCJers registers 1l6, 118, 12n, 122 and 124, will become high at that time since the input to gate 152 is the value of register lQ8 inverted by inventor 150 and the value of the eighth bit of counter 112 which is high after each eighth data bit has boon counted. The current byte number of counter I 114 its then shifted into registers 116, 118, 120, 122 and 124 when No gate 152 is high due to the current byte having incorrect parity. If more than one data hype hays incorrect parity the previous. byte number in resters 116, 118, 120, 122 and 124 is replaced with the new byte number of a hype having incorrect parity and the previous number is not retained.
however, registers 156 and 158 provide means to store the occurrence of up to 2 bytes having incorrect parity. Registers 156 and 158 are triggered by A gate 152 and after a byte has been found to have incorrect parity a 1 will be shifted into register 156. If two bytes are found to have incorrect parity then both registers 156 an 158 will be high, the 1 in register 156 having been shifted into register 158 and a 1 shifted into register 156, an each can be tested to determine whether one or more data hits were received with incorrect parity.
The feedback shift register 82 of Figure 8, to I
calculate the sum Sue (Phase 1), is implemented by i on resters I Len l72 l76 l78, 1~0 an-l l82 and tuner adders 16~ an ]7-1 of figure 9. It will he apparent to the rearer that the haste fe~dh.lck shirt register colnprisin~l registers 168, 17n, 172, 176, 178, 18n and 182 together with 5 binary Adler 174 is the shift Roger configuration of Figure 2 liscussed above to Mattel the contents thereof ho Gwen each shift of the register. binary adc3er 1~6 functions to Adele (Molly 2) the input data bit, Of, to the 7 bit value represent ho registers 168 170 172 17~, 178 1~0 and 182 immediately fulling the multiplication of the contents of the shift register by I. Each such multiplication an addition occurs upon each cycle of the shift wrester (which occurs upon the input of a data bit, Of). That is, the sum 22~
Sue is determined by the equivalent means ( ((C223~ C222)C~-~ C221)~ Coy so that aster the last data bit has been shifted into register 110, hying hit C0, registers 168, 170, 172, 176, 178, 1~0 and 182 will represent the 7 bit sum Sue, being the I
Gulls field element,C~il of a bit, Of, being erroneous.
(Assuming a single bit error.) At the end of Phase I, registers 168, ..., 182 contain the representation of Guy if bit Of Or Swahili was received in error.
Following the input of all data hits into register 110, identified as Phase I in Figures 8 an 9, the await hits I

are shifted out ox wrester lo in the seine order that they were shiftily into the register (i.e. FIFO) identified c1.5 Phase Al in FiclllKc-s 8 and 9. DuL-incl Phase If the clock continues to cycle thereby causing registers 11~ l68 170 172 l7h 178 Len and 182 to shift upon each clock cycle Ann collators ll2 an ll4 to count the data hits as they are shifted out of resister fin. Switch is open during Phase II so that the value of resisters ilk 118 120 122 all 124 representing the last hype nulnl-er to show a parity failure is preserve-3.
If there has keen a bit error in the data hits the value of registers 168 170 172 176 178 180 and 182 will be non-zero and equal to I so that when registers 168 170 172 176 178 180 and 182 have shifted from the value CXi toCX223 (i.e. Only) the current bit being shifted out of register lo will be Of Corresponding to I and may be erroneous.
The output of AND crate 186 will become high when registers 168 170 172 176 178 18n and 182 hold the value CX223.
Also the output of NOR gate 136 will become high if the current byte number of counter 114 is equal to the number ox the last hype to have incorrect rarity which is stored in registers 116 118 120 122 and 124. That is the bitts of the stored byte number are added (my binary module 2 arithmetic) using adders 12h 12R 130 132 and 13~ to the hits of the current byte number so that it is only when the sum of each is zero (ire when they are all equal) that NO gate 136 goes high. If NOR gate 136 is high (i.e. the hype number of the current bit being shifted out of resister 11n is a byte having tj~.i77 incorrect parity) an-l Ann jut 186 is huge (i.e. resisters 16~, 17n, 172, 176, 178, Len anal l82 rel~resentC~223) then the current Kit toeing it'll out ox wrester fin is Chinook ho adding a l to it (i.e. n + 1 = I and 1 I = 0) using binary adder 192 To tleterfnine whether a decoding failure has occurred in accordance with bloc 102 of Figure 8 three tests are jade my OR gate Ann which will JO high if any test is positive (i.e. if any input to OR (Nate Ann is high). One input to OX
in gate no is the value of register 158, which is high if two or more data bytes were calculated to have haul incorrect parity.
Consequelltly, OR gate Ann ekes high if register 158 is high duo to more than one bit error having occurred. A second input to OR gate 200 is the output of AND gate 190 which is high if 223 5 the sum Swahili equals zero, i.e. if registers 168, i JO

17n, 172, 176, 178, 180 and 182 are all zero, and register 156 is high (i.e. if at least one data byte ha incorrect parity).
Inventor 128 reverses the output of OR gate 184. The output of OR gate 184 is low if registers 168, .... 182 are all zero.

A third input to OR gaze 2n0 is the output of AND gate 198 which is high if the sup Sue equals zero, i.e. if registers 168, 17n, ]72, 176, 178, 180 and 182 are all zero, and a data hit, Of, was correctly during Phase II. Inn a data hit, Of, is corrected during Phase II AND gate 14n is high and a 1 is shifted into register 194. The output of - I -inventor 19~ becolnex low after a hut, Of, has Harley correctly during Phase Il.
The OUtpllt lal~el.led "knockdown Failure" in Err 9 will he high felon the outright of the last data hit ox hits C223 to C0, if a deCo~in;J failure has occurred in the last hock ox data hits C223 to On- 'rho output lo "recoded Data Out" in Figure 9 provides the decoded data hock C223 to C0.

lo (ii) A decoder utilizing one one element of G~(27):
-Referring to Figure lo there its shown a process to decode a block of data encoded according to the Carleton code, which uses only one Gulls field element, ~X8, to decode the data block.
As illustrated in block 220 of Figure in a block of 28 data bytes, By to ~28~ is received wherein each hype has one parity bit and By is a Carleton code byte. Then the parity of each byte By to B28 is determined 222 and 223, the sum Swahili is calculated 224. The sum . it Cluck is calculated by means of the equivalent relationship ( . . . ( (Blake B2)~,8 + . . . + B27)c~8 B28 = R whereby each data byte is successively added to a cumulative value, as indicated, and multiplied by the Gulls field elementC~8. ho expansion was discussed at pave 22, line 28.) The sum is tested 226 to see if it is n and it it it is and no data bytes have shown incorrect parity thin there is no apparent error in the data hock 232. If thy? Swahili is n all at least one data byte had incorrect parity they'll there his keen a decoding failure 234. If the sum R is non-zeL-o it can 5 be correlated to I and the data bit(s) an data hype number corresponding to I are determined 22~. That is, if the so Sue is, say,CXl5n it could it represellt Swahili or ~l50-127 since there are only 127 non-zero Allis field elements and the assignment of Gulls field elements to data bitts was repeated, as described above.
Accordingly, it is possible that two data bytes and two data bits will correspond to the sum R. If the corresponding data byte(s) did not show incorrect parity 236 then a decoding failure has taken place. If one of the corresponding data byte(s) did show parity failure the corresponding data bit in that hype is changed 240, resulting in a decoded data block 2~2.
Referring now to Figure 11 there is shown a flow chart of a method for decoding 28 hypes encoded with one Carleton code byte, which might be implemented efficiently using a microprocessor in conjunction with readable memory accessible to a microprocessor. Three computations are necessary to decode the data in accordance with the method illustrated in Figure 11. It will he recognized by the reader that the computations might he accomplished using a variety of electronic logic circuits an a multitude of electronic Jo components; however, tile rural emhodi-n(?nt: includes a microprocessor and three look-up tales store-l in millionaire, the memory holding the result of the computation which are read by the microprocessor, Thor releasing computation time and tile number of electronic logic components required to perform the computations Appendix illustrates a se(Jmeitt of a computer program written in MOTOROLA 6809 microprocessor assembly Angie which can be incorporate-l into an appropriate software/hardware system to decode a block of data bytes having 1 n a Carleton code error correction byte.
Initially, three variables are set: ERROR, being the variable which will contain the number of a data byte having incorrect parity, is set to 0; i, being the variable which will count the data bytes, is set to l; and, A, being the variable which will hold the cumulative sum to form the sum R of block 224 in Figure 10, is set to 0.
The variable A is multiplied byCX8 using lockup table MULL of 128 bytes. As in the program of Appendix B the value of A might he used to address the appropriate lo in I tale MULL holding the product ox A andC~8. The 12~ bytes are necessary for tale MULL because Byway is a 7 bit element of GF(27) which means that 27 different values of I are possible (i.e. including 0). Next the "quasi-syndrome" of the data byte is added to the product of A
and . Again, the "quasi-syndrome" of the data hype may be obtained efficiently from a tale (e.g. OOZED in Appendix B) ;77 using the Data hype itself to addles the apl~ropriat~ Tahoe element. The "quasi-syndrolne~' of a data hype B; (where, By by I by 6' by I byway, byway, byway' bill' it consists of -the sum by j Jo in the first 7 bits of the "quasi-syndrome", and the most significant hit is the parity of the data byte By (i.e. "1"
for odd parity and "0" for even parity).
For example, the "quasi-syndro~e" of Byway) is the sum defiled above, equal to (n0~11011) plus a parity bit in the most significant bit (10nn0~n0), which equals (10011nll), where the most significant bit is the leftmost bit:
in the binary number. If By is received as Renewal) then the "quasi-syndrome" for that byte would he (00011001).
Accordingly, the Thea bit indicates that By has incorrect parity. It will be apparent to the reader that the "quasi-syndrome" of By is the equivalent 7 hit field element corresponding to By with a parity check bit in the unused Thea bit, By adding the "quasi-syndrome" of By to the product of A and Cx8 the sum Bit + Bill can be calculated an the parity of Bill determined at the same time. That is, Buick, a 7 hit number, will always have zero in the Thea bit, while the quasi-syndrome" of Bill Will have a 0 in the eighth hit only if Bill was received with incorrect parity. The Thea bit of the result of Bit + Bill is checked and if it is zero then the data byte By+] had incorrect parity and the byte number of the hype having incorrect parity is stored in variable ERROR, which stores -the 9~7'7 Norway of a byte heavenly incorrect parity. Then, the variable i containing the current Boyle nulllber us incremented anal the above process is repeater beginnincl with the product: of the current value of A andCX~, until i is equal to 29 (i.e. all data bytes have been processed). Tune value in variable when i is equal to 29 is the sum R described above. IF the value in A is zero and there has keen a data byte nulnher stored in the variable IRON due to an incorrect parity occurrillg in a data byte, there has been a decoding failure. If both A end Rowley in are zero then it is assumed that the data hock was received without error. If the value of A is non-zero hut a byte was not found to have incorrect parity a decodincJ failure hays occurred.
When A is zero and a byte number of a byte having incorrect parity has been stored in the variable ERROR the bit number (0 to 223) corresponding to the field element in A is calculated. To do so a lockup table may be used (e g. LOG in Appendix B), consisting of 127 elements, each element being -the logarithm to the base of a possible field element. Since A
contains a 7 bit field eliminates (0~i~126), there are 27-1 possible values of A for which log A (equal to i) exists. (As explained above corresponds to data bits Of Where 0'i~223; however, the sicknesses 0---i-12h, is repeater for C127 to C223 ) The value A may be use to address the appropriate element of a table of logarithms to determine the value i efficiently.

The lc>garithln of A is then matched to corresl)on-lin~

byte n~lm~-erx. Theft is, the l~ytec, conl-ainin(l Cluck Clue lo If to n~lm~)~r of ox twos yes I
equal to the number store-3 in the variable IRK of a byte having incorrect parity, then the bit Clog Or C(loc~A-~l27) Continue! in that byte is the bit in error and is chanted. If neither- byte number correspotldill~ to Of Or I 7) equals the hype number stoned in the variable ERROR there has keen a correction failure.
in The present invention, and embodiments Tory, described above permit correction of the sirlgle bit error occurring in a data block of bits which bloc includes a parity check hit in each data packet. If more than one bit error has occurred a recoding failure will be identifies] but correction of more than one error is not effected. The embodiments illustrated above to encode and decode data blocks enable efficient implementation of the present invention.
Those skilled in the art will recognize that there are a multitude of variations of Tao embodiments of the present invention, described in detail above. The examples illustrated are given only lo, teach the reader preferred embodiments of the present invention and not intended to limit the present invention to those illustrations. The illustrated emhodi-nents, an variations thereof, may be made without departing from the I scope of the present invention which is defined in the appended claims.

Claims (35)

I CLAIM,

1. An apparatus for selecting an error correction data packet for transmission in a block of data packets, said error correction data packet having M bits, one of which M bits is a parity check bit, wherein, (A) (i) said block of data packets consists of (L-1) data packets, each of said data packets having M
bits and a predetermined selected parity, one of said M bits of each of said (L-1) data packets being a parity check bit, and one error correction data packet;
(ii) the symbol Ci represents the binary value of the ith bit in said data block;
(iii) the sequence (C0 C1, C2, ...CN) represents the binary values of each of the bits in a data block of length (N+1) bits, where N+1=ML;
(iv) the sequence (CjM, CjM+1, CjM+2, ... CjM+(M+1)) designates the values of each of the bits in the error correction data packet, j being a positive integer of value between 0 and L-1;
(v) the symbol .alpha. represents a primitive element of a Galois Field GF(2P), being a root of a primitive polynomial 0(X) of degree P, P being equal to M-1, and where the arithmetic operation addition is performed using modulo 2 arithmetic;

said apparatus for selecting the error correction data packet (CjM, CjM+1, CjM+2, ...
CjM+(M-1)) comprising:

(1) means for computing T =
T having an expansion as a pattern of P bits; and, (2) means for selecting said error correction data packet (CjM, CjM+1, ... CjM+(M-1)) such that:

(i) Ci.alpha.i = T; and (ii) the parity of said error correction data packet is the same as the parity of the other (L-1) data packets of said data block,

2. The apparatus of claim 1, wherein:
L = 28;
M = 8;
N = 223;
O(X) = X7 + X3 1;
P = 7; and j = 0

3. The apparatus of claim 2, wherein each of said data packets had odd parity and the parity check bit in each data packet is the right most bit, including:
(a) means to select the sequence of bits (t0, t1, .., t6) such that T = ti.alpha.i;

(b) means to determine if (t0,t1, ... t6,) has odd parity and means to produce said error correction data packet (C0, ... C7) being equal to (t0, t1, t2, ...
t6, 0) if so; and (c) means to determine if (t0, t1, ... t6) has even parity and means to produce said error correction data packet (C0, ... C7) being equal to (t 0 + 1, t1, t2, t3 + 1, t4, t5, t6, 1), if so.

4. The apparatus of claim 1 including means for inserting said error correction data packet in said data block at the jMth through to the (jM+M-1)th bit positions.

5. An apparatus for decoding a received data block consisting of L data packets, one of said data packets being an [Carleton code] error correction packet, each data packet having a set parity and consisting of M bits, to permit correction of a single bit error in said received data block, comprising:
(1) means for determining the parity of each of L data packets in said data block and, if a parity error in a data packet is observed, recording the identity of the data packet having a parity error;

(2) means for calculating R = , where ri is the value of the ith received bit of said received data block and N+1 is the number of bits in said received data block; and, (3) means for correcting the value of the gth bit in the (K+1)st data packet of said received data block if each of the following events occur:
(i) only one data packet in said received data block has been determined to have a parity error and said parity error occurred in the (K+1)st received data packet; and (ii) R=.alpha.g, where MK ? g ? MK + M-1.

6. The apparatus of claim 5 wherein:
L = 28 M = 8 N = 223 O(X) = X7 + X3 + 1 P = 7; and j = 0.

7. The apparatus of claim 5 or 6 including means for declaring a decoding failure if any of the following events occur:
(a) the number of parity errors in said data block exceeds unity;
(b) R=0 and a parity error has been detected;
(c) R?0 and no parity error has been detected.

8. A device for encoding a data block consisting of (L-1) data packets, each data packet consisting of M bits including a parity check bit comprising:
(a) a Galois Field element generator for generating Galois field elements of a Galois field GF(2M-1), each of said generated elements represented in polynomial form, said polynomial having degree M-2;
(b) means for multiplying the value of each bit of said data block, designated as Ci, by the corresponding Galois Field element ?i to produce a product Ci?i;
(c) means for summing, using modulo 2 arithmetic, said products;
(d) means for storing M-1 binary coefficients of a polynomial representing the Galois Field element equal to the sum computed by said summing means;
(e) means for determining the parity of said (M-1) binary coefficients;
f) means for producing an M bit error correction data packet consisting of one parity check hit, the other M-1 bits being determined from said M-1 binary coefficients; and (g) means for producing a ML bit data block consisting of said (L-1) data packets and said M
hit error correction data packet.

9. An apparatus for correcting a single error in a data packet of a received data block consisting of data packets, the data block encoded with an [Carleton Code] error correction packet, and each data packet encoded with a parity bit, comprising:
(a) means for determining the parity of each of the L received data packets of said data block, (h) means for storing the identity of each received data packet having a parity error;
(c) a Galois Field element generator for generating Galois Field elements of a Galois field GF(2M-1) each of said generated elements represented in polynomial form, said polynomial having degree M-2;
(d) multiplier means for multiplying the value of each received bit of the data block by its corresponding Galois Field element to generate a product;
(e) means for summing, modulo 2, said products;
(f) means for storing the (M-1) binary coefficients of the Galois Field elements of said sum;
(g) means for declaring a decoding failure if:
(i) the number of parity failures exceeds unity; or (ii) said sum is zero but one parity failure was detected; or (iii) said sum is not zero but a parity failure was not detected;
(h) means for correcting the value of the received bit in the data packet for which a parity error was detected and which received bit position corresponds to said sum.

10. In or for use with a data transmission system wherein blocks of data are transmitted as a series of data packets, each data packet comprising a series of bits of data, wherein the value of the bit in a preselected sequence position in each of said data packets is determined according to the desired parity of said data packet, the improvement comprising generating, for each transmitted block of data packets, an error correction data packet for transmission in a preselected sequence position relative to the other data packets in such block, said error correction data packet having M bits, wherein, (A) (i) said block of data consists of (L-1) data packets, each of said data packets consisting of M
bits and having a predetermined parity, one of said M
bits of each of said (L-1) data packets being a parity check bit, and said error correction data packet, (ii) the symbol Ci represents the binary value of the ith hit in said data block;
(iii) the sequence (C0, C1, C2, ...CN) represents the binary values of each of the hits in said block of data of length (N+1) bits, where N+1 =ML;
(iv) the sequence (CjM, CjM+1, CjM+2, ... CjM+(M-1)) designates the values of each of the bits in the error correction data packet, j being a positive integer of value between 0 and L-1;
(v) the symbol ? represents a primitive element of Galois Field GF(2P), being a root of a primitive polynomial Q(X) of degree P, P being equal to M-1 and where the arithmetic operation addition is performed using modulo 2 arithmetic;
An apparatus for generating the error correction data packet (CjM, CjM+1 CjM+2, ... CjM+(M-1)) comprising:
(1) means for computing T = Ci?i + Ci?i, T having an expansion as a pattern of P bits;
(2) means for generating said error correction data packet (CjM, CjM+1, ... CjM+(M-1)) such that:
(i) Ci?i = T; and (ii) the parity of said error correction data packet is the same as the parity of the other (L-1) data packets of said data block.

11. The apparatus of claim 10, wherein:
L = 28;
M = 8;
N = 223;
Q(X) = X7 + X3 + 1;
P = 7; and j = O

12. The apparatus of claim 11, wherein each of said data packets had odd parity and the parity check bit in each data packet is the right most hit, including:
(a) means to select the sequence of bits (t0, t1, ... t6) such that T = ti.alpha.i (b) means to determine if (t0, t1, ... t6,) has odd parity and means to produce said error correction data packet (C0, ... C7) being equal to (t0, t1, t2, ...
t6, 0) if so; and (c) means to determine if (t0, t1, ... t6) has even parity and means to produce said error correction data packet (C0, ... C7) being equal to (t0 + 1, t1, t2, t3 + 1, t4, t5, t6, 1), if so.

13. The apparatus of claim 10 including means for inserting said error correction data packet in said data block at the jMth through to the (jM+M-1)th bit positions.

14. An apparatus for encoding a sequence of data bits to permit correction of a single bit error occurring therein comprising:
(a) means to receive a signal, said signal comprising a sequence of data bits;
(b) means to determine the parity of a group of said received data bits of said signal, said group consisting of i data bits;
(c) means to produce a parity bit and to incorporate said parity bit into said group of data bits to produce a parity encoded data packet, the value of said parity bit being selected such that the parity of said data packet is set to a predetermined selected parity state;
(d) means to produce a digital signal] having i bits, each of said bits of said signal representing a coefficient of a polynomial of degree i-1, said polynomial being of the form a0.alpha.0 + a1.alpha.1 + ... ai-1.alpha.i-1 and representing an element of the Galois field, GF(26), having 2i elements, said element being equal to the sum Ck.alpha.K, where the value of a0, ..., ai-1 is either "0" or "1", .alpha. is a root of a primitive polynomial of degree i, j is the number of said data packets, and Ck, i+1 ? K ? j(i+1)-1, is the value of the Kth bit in said data packets, said bits being received by said means to produce said digital signal in the sequence Cj(i+1)-11, Cj(i+1)-2, ..., Ci+1; and, (e) means to parity encode said digital signal to produce an [Carleton Code] error correction packet having the same predetermined parity as said data packets, comprising:
(i) means to determine the parity of said signal;
(ii) means to produce a bit and to append said bit to said signal; and (iii) means to produce a number of data hits and and modulo 2 said data bits to said signal, so that the sum CK.alpha.K is equal to zero, where i, j and CK, i+1 ? K ? j(i+1)-1, are defined as in paragraph (d) above, and CK, 0 ? K ? i+1, are the values of said hits in said [Carleton Code] error correction packet.

15. An apparatus as in claim 14, wherein said data packets are comprised of 8 data bits and said value of i is 7.

16. An apparatus as in claim 15, wherein said means to produce said digital signal representing an element of GF(2i) equal to the sum CK.alpha.K includes:

(i) a feedback shift register including i single element registers and at least one primary binary adder, said registers and primary adders combined in such manner that said feedback shift register can represent elements of the Galois field GF(2i) and multilply said represented element by .alpha., to produce the representation of the product (CK.alpha.i+1) ; and, (ii) at least one secondary binary added combined with said feedback shift register, said secondary binary adders being able to add modulo 2 the representation of CK.alpha.i+1, i+1 = K j(i+1)-1, to said single element registers of said feedback; shift register concurrent with or following each said multiplication by .alpha.; where, i, j,.alpha., CK are defined as in claim 1.

17. An apparatus for encoding a block of data comprised of a number of data packets, each packet consisting of bits, wherein the value of the bit in a preselected sequence position in each of said data packets is determined according to the desired parity of said data packet, to permit subsequent correction of a single bit error occurring therein, comprising:
(a) means for receiving a block of data comprising a sequence of data packets, each data packet comprising a sequence of data bits;
(b) means to multiply one of said data packets by the Galois field element, .alpha.i, defined as the ith power of the root (.alpha.) of a primitive polynomial, where i is the number of bits per packet and the degree of said polynomial is i-1, to form a partial product so that said product contains a like number of bits as said data packets;

(c) means to add, by binary arithmetic, one of said data packets to said partial product to form a partial syndrome;
(d) means to multiply said partial syndrome by the Galois field element .alpha.i, defined as in part (b) above to form a partial product so that said product contains like number of hits as said data packets; and, (e) means to repetitively engage said means of paragraphs (c) and (d) above until all of said data packets have been added to one of said partial products to form a resultant syndrome and said resultant syndrome has been multiplied by the Galois field element .alpha.i according to paragraph (d) above to form a resultant product wherein said resultant product has the same parity as said data packets, said resultant product being the [Carleton Code] error correction packet of said block of data.

18. Apparatus according to claim 17 including means to store said data packets of said block of data.

19. Apparatus according to claim 18 wherein said data packets are comprised of 8 data bits and said value of i is 8.

20. Apparatus according to claim 19 wherein said means to store and identify said data packets includes a microprocessor.

21. Apparatus according to claim 19 wherein said means to multiply said data packet, or said partial syndrome, by said Galois field element, .alpha.i, includes a microprocessor having arithmetic logic capability.

22. Apparatus according to claim 19 wherein said means to add said data packets to said partial products includes a microprocessor having arithmetic logic capability.

23. An apparatus for decoding a block of data, wherein said block consists of a number of data packets, each packet comprising hits, to permit correction of a single hit error occurring in said block of data comprising:
(a) means to receive a signal said signal comprising a block of data comprised of a sequence of data packets wherein each data packet is of fixed parity and contains one parity bit, and one data packet is an [Carleton Code] error correction packet;
(b) means to determine the parity of each data packet;
(c) means to identify a packet having incorrect parity;
(d) means to store an identifier of a packet having incorrect parity;
(e) means to store the received data block;
(f) means to create representative digital data signals being the elements of a Galois field which can be correlated to the data bits according to bit number, wherein said Galois field has 2(i-1) elements and the elements of said Galois field may he represented by i-1 bits, where i is the number of bits... per data packet;
(b) means to determine the sum of said representative digital data signals whereby a representative data signal is included in said sum if said correlated data bit is one value and not included in said sum if said correlated data bit is not said value, said value being fixed; and (h) means to identify an erroneous bit of said data block comprising means to identify the bits which are correlated to said sum of said representative digital data signals (said sum being one of said Galois field elements representing said data bits) and means to identify one of said bits which is contained in a data packet having incorrect parity.

24. An apparatus as in claim 23 wherein said data packets are comprised of 8 hits, said Galois field contains 27 elements, each element capable of being represented by a 7 bit number, and said [Carleton Code] error correction packet is the first data packet received.

25. An apparatus as in claim 24 wherein said means to determine the elements of said Galois field, which can be correlated to said data bits, and said means to sum a number of said elements, includes a 7 bit feedback shift register including means to add the output of the most significant bit of the register to the received correlatable data bit and input the result to the least significant bit of the register, and means to add the output of the most significant bit in the register to the output of the third least significant bit in the register and input the result to the fourth significant bit in the register.

26. An apparatus as in claim 25 wherein said means to identify an erroneous hit in said data block includes:
(a) said 7 bit feedback shift register containing said sum of representative Galois field elements;
(b) means to cycle said register repetitively as each bit of the stored data block is transmitted;
(c) counting means to identify the data packet number of said transmitted bit;
(d) logic means to compare said data packet number with said stored data packet identifier of a data packet having incorrect parity; and (e) means to change the transmitted bit when the register holds the representation of the last received bit and said stored packet identifier is equivalent to the data packet number of the bit being transmitted.

27. The apparatus of claim 26 wherein said means to determine the parity of said received data packets includes a counter to count from 1 to 8 repetitively at substantially the rate at which data bits are received so that said 8 counts corresponds to a received data bit and said corresponding data bits comprise one data packet, logic means to sum each data bit in a data packet to determine whether the sum is equal to "1", corresponding to odd parity or "0", corresponding to even parity, and a register to store the number of the data packet having incorrect parity.

28. The apparatus of claim 26 including logic means to produce a signal which flags that there has been a correction failure including:
(a) means to count at least two data packets having incorrect parity and means to produce a signal which sets a first correction failure flag if two of said received data packets have incorrect parity;
(b) logic means to compare the value of said means to count the number of data packets having incorrect parity and said sum of representative Galois field elements, and means to produce a signal which sets a second correction failure flag when the number of data packets having incorrect parity is at least 1 and said sum is 0; and (c) logic means to set a correction flag when a data bit has been corrected, logic means to compare the value of said correction flag and the value of said sum of representative Galois field elements and means to produce a signal which sets a third correction failure flag when a bit has not been corrected and said sum is not 0.

29. The apparatus of claim 27 including logic means to produce a signal which flags that there has been a correction failure including:
(a) means to count at least two data packets having incorrect parity and means to produce a signal which sets a first correction failure flag if two of said received data packets have incorrect parity; , (b) logic means to compare the value of said means to count the number of data packets having incorrect parity and said sum of representative Galois field elements, and means to produce a signal which sets a second correction failure flag when the number of data packets having incorrect parity is at least 1 and said sum is 0; and (c) logic means to set a correction flag when a data bit has been corrected, logic means to compare the value of said correction flag and the value of said sum of representative Galois field elements and means to produce a signal which sets a third correction failure flag when a bit has not been corrected and said sum is not 0.

30. An apparatus according to claim 28 or claim 29 including means to produce a signal to set a fourth correction failure flag if any of said 3 correction failure flags have been set.

31. An apparatus for decoding a block of data wherein said block consists of a number of data packets, each packet comprising bits, to permit correction of a single bit error occurring in said block of data comprising:
(a) means for receiving and storing a sequence of data packets comprising a block of data, wherein each data packet is of fixed parity and contains one parity bit, and one data packet is an [Carleton Code] error correction packet;
(b) means to multiply one of said data packets by the Galois field element .alpha.i, defined as the ith power of the root (.alpha.) of a primitive polynomial where i is the number of bits per packet and the degree of said polynomial is i-1, to form a partial product so that said product contains like number of bits as said data packets;
(c) means to add, by binary arithmetic, one of said data packets to said partial product to form a partial syndrome;
(d) means to multiply said partial syndrome by the Galois field element .alpha.i, defined in part (b) above, to form a partial product so that said product contains like number of bits as said data packets;
(e) means to determine the parity of said data packets;
(f) identification means to identify a data packet having incorrect parity;
(g) means to store an identifier of a data packet having incorrect parity;
(h) means to repetitively engage said means of (c) and (d) above, ending with said means of paragraph (c), until all of said data packets have been added to said partial product to form a resultant syndrome;
(i) means to identify the incorrect data bit occurring in said block of data comprising;
(i) means to calculate the logarithm (u) of said resultant syndrome wherein said logarithm (u) is the number of a suspect data bit correlated to the Galois field element .alpha.u, of GF (2i-1), where .alpha. and i are defined as in (b) above;
(ii) means to identify the bit number(s) of said suspect bit(s);
(iii) means to determine the suspect data packet number(s) containing said suspect bit(s); and (iv) means to compare said suspect data packet number(s) with said stored identifier of a data packet having incorrect parity; and, (j) means to correct said incorrect data bit comprising;

(i) means to select a data packet having incorrect parity and being a suspect data packet; and, (ii) means to change the incorrect data bit being the data bit corresponding to said suspect bit which is in said selected data packet of paragraph (j) (i) above.

32. The apparatus of claim 31 wherein said data packets are comprised of 8 bits and said value of i is 8.

33. The apparatus of claim 32 wherein said means to multiply a data packet by said Galois field element .alpha.i includes a microprocessor having arithmetic logic capability and capable of accessing memory form which said partial product can be read and readable memory comprising at least 128 bytes said bytes containing said partial products.

34. The apparatus of claim 33 wherein said means to calculates said logarithm (u) of said resultant syndrome includes a microprocessor capable of accessing memory from which said logarithm (u) can be read and readable memory comprising at least 127 bytes said bytes containing all possible values of said logarithm (u).

35. The apparatus of claim 34 wherein said means to add said data packets to said partial product and said means to determine the parity of said data packets includes a microprocessor having arithmetic logic capability and capable of accessing memory, and readable memory comprising at least 256 bytes said bytes containing all possible values of said data bytes and having correct parity, whereby said partial syndrome can be calculated and said parity can be determined contemporaneously by adding the appropriate one of said memory bytes to said partial product.