CA1218162A - Multilevel controller for a cache memory interface in a multiprocessing system - Google Patents
Multilevel controller for a cache memory interface in a multiprocessing systemInfo
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- CA1218162A CA1218162A CA000451184A CA451184A CA1218162A CA 1218162 A CA1218162 A CA 1218162A CA 000451184 A CA000451184 A CA 000451184A CA 451184 A CA451184 A CA 451184A CA 1218162 A CA1218162 A CA 1218162A
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- control store
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
Abstract
MULTMULTILEVEL CONTROLLER FOR A CACHE MEMORY
INTERFACE IN A MULTIPROCESSING SYSTEM
ABSTRACT OF TIRE INVENTION
A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities.
INTERFACE IN A MULTIPROCESSING SYSTEM
ABSTRACT OF TIRE INVENTION
A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities.
Description
MOTIVE CONTROLLER FOR A CACHE MEMORY
INTERFACE IN A MULTIPROCESSING SYSTEM
RELATED PATENT APPLICATION
A patent application directly or indirectly related to the subject application and assigned to Burroughs Corporation is the following:
Application No. 451,183-2 filed April 3, 1984 (Thomas M. Stockier) and entitled Hierarchy of Control Stores for Over-lazed Data Transmission BACKGROUND OF THY INVENTION
Field of the Invention This invention relates to a multilevel controller and more particularly for such controller for a cache memory interface between a data processor and another processing system each of which have different operating speeds as well as memory addressing requirements.
Desert lion of the Prior Art P _ _ In the interfacing of two different data processing systems, particularly of different I.
- ~218~
INTERFACE IN A MULTIPROCESSING SYSTEM
RELATED PATENT APPLICATION
A patent application directly or indirectly related to the subject application and assigned to Burroughs Corporation is the following:
Application No. 451,183-2 filed April 3, 1984 (Thomas M. Stockier) and entitled Hierarchy of Control Stores for Over-lazed Data Transmission BACKGROUND OF THY INVENTION
Field of the Invention This invention relates to a multilevel controller and more particularly for such controller for a cache memory interface between a data processor and another processing system each of which have different operating speeds as well as memory addressing requirements.
Desert lion of the Prior Art P _ _ In the interfacing of two different data processing systems, particularly of different I.
- ~218~
-2-performance rates, a number of incompatibilities are encountered. Such incompatibilities include differences in memory access times, the different clock frequencies at which the respective processors are operated, different command structures and memory addressing capabilities of the respective processors .
The present invention is directed toward interfacing one or more commercially available entry level data processors shah as Burroughs B5900 with a large multiprocessing system, which entry level data processors serve as auxiliary processors for the purposes of handling off-loaded chores and also maintenance routines where required. The performance and throughput of the system is thus greatly enhanced by relieving the main data processing units of such tasks.
Incompatibilities must be resolved due to the fact that the large multiprocessing system clock rate can be different ken that of the entry level data processor, and the main memory system is 128 times the capacity of the entry level system. This in turn, requires memory control words which contain more bits than does the entry level system. Further, because the main memory system is a hundred twenty-eight times that for which the entry level data processor was designed, its access time is larger than that of the entry level processor.
The system interface of the present invention resolves these incompatibilities in a number of ways. The system interface resolves the difference in memory access capabilities by providing a cache mechanism for storing a number of data and code words at a time, which words are fetched
The present invention is directed toward interfacing one or more commercially available entry level data processors shah as Burroughs B5900 with a large multiprocessing system, which entry level data processors serve as auxiliary processors for the purposes of handling off-loaded chores and also maintenance routines where required. The performance and throughput of the system is thus greatly enhanced by relieving the main data processing units of such tasks.
Incompatibilities must be resolved due to the fact that the large multiprocessing system clock rate can be different ken that of the entry level data processor, and the main memory system is 128 times the capacity of the entry level system. This in turn, requires memory control words which contain more bits than does the entry level system. Further, because the main memory system is a hundred twenty-eight times that for which the entry level data processor was designed, its access time is larger than that of the entry level processor.
The system interface of the present invention resolves these incompatibilities in a number of ways. The system interface resolves the difference in memory access capabilities by providing a cache mechanism for storing a number of data and code words at a time, which words are fetched
-3-from the main memory system while the auxiliary processor it working with the data and code words currently in the cache mechanism. The use of such a cache mechanism as a buffer between a large but relatively slow memory system and a data processor and the provision for accessing a large backup memory should a requested data element not be present in the cache mechanism is disclosed in the Barton US. Patents No. 3,292,152 and No. 3,292,153. Such techniques are employed in many commercially available data processing systems such as the IBM System 360/370 series.
In addition, the system interface anticipates and prophecies from the main memory system those segments or "pages" of code which would normally be next required by the auxiliary processor The system interface is also adapted to convert the auxiliary processor's commands into memory control words as well to synchronize the clocks of the main memory system and the auxiliary processor respectively.
It will be appreciated from the above, that the system interface must control a number of different actions occurring between the auxiliary processor and the main memory system, which actions are requested and occur independently of one another, and since the auxiliary processor and the main memory system with which it communicates have independent controls, the system interface requires a multilevel control unit to control the various independent operations without denying access to portions of cache memory currently being used by the auxiliary processor.
It is then, an object of the present invention to provide an improved system interface * Trade Mark I
between an auxiliary processor and a large multiprocessing system having different data rates, memory capacity and control word format.
According to the present invention there is provided a system interface unit fox transmission of data and code between a processor and a main memory system, said interface unit comprising memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system; cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having input means and output means coupled to provide control signals to said cache mechanism means and said memory inter-face means respectively; said first control store input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a command code to address said second control store; each control store input means being provided with program counter means to increment a previous address to address the respective control store us-less a new address is received.
An embodiment of the present invention will now be described, by way of example, with reference to the accompany-in drawings in which:-Figure 1 is a schematic diagram of a multiprocessing system;
Figure 2 is a schematic diagram of an auxiliary processor and its connection to a system interlace;
Figures I and B are a schematic diagram of the system interface employed in this embodiment; and Figure 4 is a schematic diagram of the two-level microprogram controller.
I
This embodiment is directed toward the interfacing of an entry level data processor into a large multiprocessing system which entry level processor serves as an auxiliary processor to handle off-loaded chores to enhance the perform mange and throughput of the system as a whole. The present embodiment is embodied in a system interface which resolves differences in memory access capabilities, data rates and clock frequencies by providing a cache memory mechanism and a main memory interface mechanism which operate in overlap fashion under control of a two-level microcontroller.
Such multiprocessing system is illustrated in Figure 1 and may be of the type described in the Molt et at US. Patent No. 3,319,Z26. The system includes a plurality of main processing units 10 and one or more I/O processors 11 each of which can communicate with any one of a plurality of memory modules 12. In addition, the system includes a plurality of auxiliary processors 13, which may be just a commercially available entry level processor which never the-less has a slower clock frequency and less memory address-in capabilities. For example, in the embodiment of the present invention, the entry level or auxiliary level pro-censor has a clock rate of 4 MISS while the rest of the system has a clock rate of 8 MISS. Furthermore, an Audi-fiery processor is capable of addressing only a million I words of memory while, in the present embodiment, four main memory modules 12 are capable of storing 12~3 million words of data and code. However, because of the size of the main memory system in Figure 1, the memory access time is typical-lye 1600 nanoseconds while the auxiliary processors 13 are designed for memory access time of only 600 nanoseconds.
A typical auxiliary processor and the system interface for the present embodiment are illustrated in Figure 2 where the auxiliary processor is a modular two primary bus system that includes data processing module aye, program control module 14b, stored logic controller module 14c and an Input/Output module 14d which communicate with one another via CUBS 15 and BUS 16. CUBS 15 is used to broadcast control information from stored logic control-for 14c to all the other modules while BUS 16 is used to transfer data and address information to the various modules of the auxiliary processor. DUBS is illustrated as being employed locally within data processing module aye.
In addition, auxiliary processor of Figure 2 would include a memory control module to access the local memory of one million words. However, since the auxiliary process son is to interface with a much larger system, such controller is replaced in Figure 2 by system interface unit 17 which communicates with the rest of the auxiliary processor by way of CUBS 15 and USE 16.
A diagram of the functional units of the system interface of the present embodiment is provided in Figure 3 which illustrates the various functional units of the cache mechanism, main memory interface mechanism, and the two level microcontroller 20 for providing control of a cache mechanism and main storage interface mechanism in an overlap manner in accordance with the present embody-mint. Data and addresses are supplied to the cache memory mechanism by way of BUS 16 of Figure 2. Data for storage in main memory system is passed through the cache motion-is to main memory interface mechanism for transmission to the main memory system. Data and code received from the main memory system is received by the main memory interface mechanism and transmitted to the cache memory mechanism for subsequent transmission to the auxiliary processor on BUS 16. Individual data words can also be transmitted directly from the main memory interface mechanism to the BUS 16. Commands are received by microcontroller 20 from CUBS 15 of Figure 2 to drive the respective cache and main memory interface control stores to activate their corresponding units. The main memory interface mechanism also receives commands from CUBS 15 or the generation of main memory control words for the accessing of data in main memory.
DETAILED DESCRIPTION
Cache Memory Mechanism The principle function of the cache memory mechanism is to reduce memory access times from approxi-mutely 1600 nanoseconds for the large main memory system to the 600 nanosecond access time of the auxiliary processor. In addition, the cache mechanism includes an efficient cache purge mechanism _ -/ /
/
... .. , . , . . .
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I
I
requiring only a few clock times. All stores to the cache mechanism from the auxiliary processor are to be immediately passed onto the main memory system.
In addition, the cache memory mechanism also performs S program code prefetching as will be more thoroughly described below. Referring again to Figure 3, the principle element of the cache mechanism is data array 31 which is a random access memory of 256 word locations or registers of 52 bits each. The array is divided such that program code occupies 128 words and data occupies 128 words. The segregation of program code from data allows prevention of random data accesses from overwriting code loops which may be captured in the cache as well as facilitates the selective purging of data without purging useful program code and also allows for the program code prefetching mechanism to be more further described below.
Each of the 128 word groups is divided into 16 eight word wages so as to allow all fetches to the main memory system to be eight word operations.
Addressing data array 31 is accomplished by passing the seven least significant bits I page bits and three word bits) of the requested 20 bit address to the data array. The most significant address bit is generated by the cache control unit which determines from the requested operation whether to access the program code or the data portion of the data array.
Translation table 24 of Figure 3 is organized as 32 word locations of 13 bits each. Each word location corresponds to an 8 word page in data array 31. There are 16 word corresponding to program code entries and I words corresponding to data entries ~Z~8~
g in the data array. The I bit word in the translation table is a 13 most significant address bits of the data held in the corresponding page of data array 31.
The translation table is addressed by 4 page bits of the requested 20 bit address. The most significant address bit of the translation table is generated by a control unit 20. When the output of translation table 24 compares with the 13 high ardor bits of the requested address, address comparator 27 signals hit detection unit 28~
Valid bit array 23 is used to indicate the validity or proper entry of an address in translation table 24. It is arranged as two 4 by 4 register files containing one bit for every entry in lo translation table 24. This arrangement allows the cache to be purged in 4 clock times instead of 32 since all that is necessary to purge the cache is to reset the valid bits in the valid bit array. The valid bit array is addressed by the page bits of the requested 20 bit address. As in the case of data array 31 and translation table 24, the most significant address bit for the valid bit array is generated by control unit 20.
Page used array 22 has one bit corresponding to every entry in the program code portion of the translation table 24. It also is implemented in a physically separate 4 by 4 register file. Thy page used array 22 is employed by the program code look-ahead or prefetch algorithm. It is managed by control unit 20.
The cache mechanism is activated by receipt by address register 25 of a 20 bit address from BUS 16 which address is simultaneously supplied to translation table 24, valid bit array 23, address comparator 27, 8~6~
page used array 22 and data array 31. If control unit 20 has also received a fetch command from CUBS 15, the output of translation table 24 is compared by hit detection unit 28 with the 13 most significant bits of the requested 20 bit address. If they are equal and valid bit corresponding to the translation table entry is true, the data now present at the output of data array 31 is the requested data. Otherwise, the requested data is not present in the cache mechanism and must be requested from main memory. If the fetch request is for program code, the prefetching algorithm described below is also invoked.
When control unit 20 receives a store command from CUBS 15, the translation table 24 is compared with the 13 most significant bits of the requested 20 bit address and, if they are equal and the valid bit corresponding in the translation table entry is true, hit detection unit 27 signals control unit 20 causing it to generate a write signal to the data array. The data is also sent to the main memory interface mechanism for transmission to main memory.
The prefetch algorithm is essentially as follows:
When code is requested by the auxiliary processor, the cache mechanism determines whether the requested page is present in data array 31.
If the requested page is present in data array 31, the requested word is transmitted to the auxiliary processor. If the Page Used Bit associated with tune requested page is set, the operation terminates. If the Page Used Bit associated with the requested pave ~L2~L81~
is not set, a prefetch operation is initiated. The control unit calculates the address of the "NEXT" eight word page. This address is presented to the cache mechanism which determines whether the "NEXT" page is present in data array 31. If it is present, the Page Used Bit associated with the requested page is set and the operation terminates. If it is not present, the cache control unit directs the memory interface control unit to initiate a main memory request for the "NEXT"
lo page. At this time, the Page Used Bit associated with the requested page is set and the cache control unit goes to the idle state thereby making it available to service auxiliary processor requests. Meanwhile, the memory interface control unit maintains communication with the main memory system. When the main memory system responds with the "NEXT" page data, the memory interface control unit directs this data to the appropriate location in data array 31. The memory interface control unit resets the Page Used Bit associated with the "NEXT" page and enters the idle state thereby completing the prefetch operation.
If the requested page is not present in data array 31, a main memory request is initiated. When tune main memory system returns the requested page, the data is directed to the appropriate location in data array 31.
Simultaneously the requested word is directed to the auxiliary processor. At this time the control unit calculates the address of the "NEXT" eight word page.
This address is presented to the cache mechanism which determines whether the "NEXT" page is present in data array 31. If it is present, the Pave used Bit associated with the requested page is set and the operation terminates.
If it is not present, the cache control unit directs the memory interface control unit to initiate a main memory request for the "NEXT" page At this time, the Page Used Bit associated with the requested page is set and the cache control unit goes to the idle state thereby making it available to service auxiliary processor requests. Meanwhile, the memory interface control unit maintains communication with the main memory system.
When the main memory system responds with the "TEXT"
page data, the memory interface control unit directs this data to the appropriate location in data array 31.
The memory interface control unit resets the Page Used Bit associated with the "NEXT" page and enters the idle state thereby completing the prefetch operation.
Main Memory Interface Mechanism The remaining functional elements in Figure 3, except for control unit 20, form the main memory interface mechanism of the present invention.
These functional units include memory bus interface unit 34, memory interface register 32, bypass register 33 and control word generator 21. With these units, the main memory interface mechanism interfaces the auxiliary processor to the main multiprocessing system.
More specifically, it interfaces the four main memory units 12 of Figure 1 with the above-described cache memory mechanism and thus the auxiliary processor.
Bus interface unit 34 is capable of selectively listening to any one but only one of the four memory modules 12 in Figure 1 and it is capable of broadcasting to all such memory modules simultaneously. The buses between bus interface unit 34 and the respective memory modules is basically a bidirectional 52 bit wide bus.
In addition, the bus interface unit includes a handshake unit snot shown) which is responsible for sending and receiving control signals to and from the four memory modules. The primary control lines to the respective Emory modules, in addition to the 52 bit wide bus include a requester to memory request line, a requester to memory data valid line, a memory to requester acknowledge line, and the memory to requester fail line.
Control word generator 21 takes commands from the auxiliary processor by way CUBS lo and converts them into main memory module control words.
This unit is responsible for the extended address gape ability required to address the main memory system. Control words are 52 bits in width and are of two different formats. One format is the memory operation request which is used or normal memory operations such as fetch and store and contains four different fields plus the fifth field which is not employed. The four fields are a twenty bit address field supplied by the auxiliary processor from BUS 16 by way of address register 25 and address bus 38; an extended address field which is obtained from one of two base registers (not shown) in control word generator 21; a length field which specifies whether one data or code word is to be fetched from memory or eight such data or code words; an opaqued field which contains a main memory defined opaqued consistent with the operation being performed with one of the main memory modules.
The two base registers, which provide the extended address field during a fetch from main memory, are "data environment register" and a "code environment data register" which are respectively being used according to whether or not data or code is being received from one of the main memory modules. Finally, parity is generated for the overall control word and inserted into a parity field.
The other control word format is a memory management request control word which is used to request special memory management operations. It is 52 bits in width and contains an opaqued field similar to the one described in the memory operation request control word; a length field which is always one and a variant field which is generated by the auxiliary processor to create variations of basic requests, thus reducing the number of opcodes required.
Cache bypass register 33 is employed to provide a direct path from the main memory modules to BUS 16. When data returning from one ox the main memory modules is not going to update the cache mechanism, bypass register 33 is used to channel the data directly to the auxiliary processor. When the data returning from the main memory module is destined to update the cache mechanism and is required by the auxiliary processor, that data is copied by the bypass register 33 while simultaneously being supplied to memory interface register 32 to data array 31 by way of BUS 37.
A word counter register (not shown) is provided as a three bit register which is the memory interface mechanism's ability to generate "word addresses"
for purposes of updating the cache memory. When a requested data or program code data item is not present in the cache, the address of that item is sent, by way of interface mechanism, to one of the main memory modules. However, instead of requesting just thaw item, the entire page (8 words) where that ~Z1816~
item resides is requested. The page, however, is requested such that the requested word returns first from main memory module. For example, if the desired word is the fifth word in a given eight word page, the data returns from the selected memory module in the following sequence: word 5, word 6, word 7, word 0, word 2, word 3 and word 4. This scheme allows the desired word to return, on the average, four clock times faster than would occur if the pages were returned always starting with word 0.
The word counter captures the word bits (least significant bits) from the requested address. When the eight word page returns from memory module the word counter is incremented, module 8, to generate the Ward address bits n 50 the cache mechanism can be updated.
Two level Control Store Control unit 20 of Figure 3 is illustrated in Figure 4 and is comprised of two control stores arranged in a hierarchy with the first control store supplying control signals for the cache memory mechanism described above and also addresses to the second control store which supplies control signals to the main memory interface mechanism described above.
This control mechanism was designed with two overriding purposes. One consideration is the provision of a flexible mechanism which would allow changes in existing operations and the addition of new operations by providing control stores that can be configured or replaced. The other consideration is to allow program code prefetching that does not interfere with normal cache mechanist operation. The second consideration requires two microprogram controllers for keeping track of two asynchronous, ~35 simultaneous operations.
I
In Figure 4, the cache memory controller is comprised ox control store 40 which is addressed by the contents ox both register counters aye and 44b.
The contents of register counter aye include an address received by way of multiplexer aye from CUBS 15 of Figures 2 and I. This initial address is the first state of the routine which forms the requested cache mechanism operation. This first state knows the address of the next state, places the next state address on the next state field lines back to multiplexer aye. It also changes the control of the next state multiplexer aye selecting the next state field as an input to microprogram counter aye. As the sequence continues, each routine state points to the next until the routine end is encountered At this point, the control to toe next state multiplexer aye is changed so that CUBS 15 provides the next address to program counter aye. Hence, the controller of Figure 4 is available for the next auxiliary processor request and, if no request is present, CUBS will pass the appropriate signals to the controller.
In addition to straight line sequencing, control store 40 can "test" two conditions by way of the low order address bits received by multiplexer 43b which passes the desired condition bits to condition register 44b~ The conditions are examined during the next routine state. The inclusion of the condition testing allows for a more flexible micro control store.
:~Z~8~
Conditions tested by the cache memory control store include:
availability of the main memory interface control store to accept an operation;
availability of a clock or clock cycle for data transfer to ox from the processor;
translation table parity error;
presence of a requested address in the cache mechanism;
currently addressed code page has been previously accessed (see prefetch algorithm above);
cache address limit error; and last cache memory cycle awarded to main memory interface control store.
Control store 41 provides control signals for the main memory interlace mechanism and is identical to cache control store 40 except that it receives the initial address (opaqued) from cache control store 40 instead of the CASEY. In addition, it can test three conditions instead of two. Both control stores 40 and 41 respectively provide control signals to the cache memory mechanism and the main memory interface mechanism.
They also provide shared commands by way of arbitration logic 42 for data array 31, translation table 24, address bus 38, BUS 37 and bus interface unit 34. It is to be remembered that controls 40 and 41 operate asynchronously and arbitration logic 42 is provided to accept control signals from one or the other of the control stores.
Conditions tested by the main memory interface control store include:
acknowledgment ox main memory available for last memory request;
I
an acknowledge signal has been received for more than one main memory module (an error condition);
an error detected in a control word presented to main memory;
an interface parity error;
memory Jo requester data valid;
main memory system has detected an internal failure;
general purpose counter overflow;
failure of main memory to respond to a request within a reasonable amount of time; and memory to requester operation complete.
In the controller of Figure 4, the control flow is from the auxiliary processor CUBS to the cache mechanism control store 40 to the main memory interface control store I with each control store notifying the other of its current state. That is to say, the main memory interface control store sends a signal to the cache control store when it is idle an the cache control store notifies the auxiliary processor when it is not idle. This handshaking action prevents the driving control store from issuing another operation before the driven control store has computed a previous operation.
With the controller of Figure 4, the cache mechanism control store can request a program code prefetch operation from main memory interface mechanism and, when the main interface control strop is bus communicating with main memory r the cache mechanism control store is free Jo service auxiliary processor requests for code or data in the cache memory.
EPILOGUE
A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. Such a controller allows for communication between the auxiliary processor and a cache mechanism in the system interface to be carried on independently of main memory accesses required to update the cache mechanism in an overlapped manner.
There has been described a system interface with a multilevel control unit to control independently initiated actions across the interface which nevertheless synchronizes independently requested actions across the interface.
In the described embodiment the system interface resides between an auxiliary processor and a main memory system of a multiprocessing system. The interface is divided into two portions or modules: a cache mechanism module and a main memory interface module. The cache mechanism module performs normal cache functions of receiving data and code words from main memory at a slower frequency but higher clock rate and supplies those words to the auxiliary processor at a faster frequency jut slower clock rate. The memory interface module initiates requests for main memory accesses in response to requests from the auxiliary processor. Both modules are under the control of the microprogram controller; however, since the functions of both modules overlap, the controller is formed of two control stores for the cache mechanism module and the main memory interface module, respectively. The cache mechanism control store receives code information from the auxiliary processor as well as condition signals and supplies commands to that mechanism and also addresses to the main memory interface control store, that in turn, supplies commands to the main memory interface module as well as notifying the cache mechanism control store of its current state for the purposes of synchronization.
A feature then, of the embodiment resides in a microprogram controller for a system interface between an auxiliary processor and a main memory system which con-troller includes two control stores, one to control the functions of a cache mechanism and the other to control the functions of main memory accessing where the first control store provides addresses or commands to the second control store that in turn notifies the first control store of its current state.
I
In addition, the system interface anticipates and prophecies from the main memory system those segments or "pages" of code which would normally be next required by the auxiliary processor The system interface is also adapted to convert the auxiliary processor's commands into memory control words as well to synchronize the clocks of the main memory system and the auxiliary processor respectively.
It will be appreciated from the above, that the system interface must control a number of different actions occurring between the auxiliary processor and the main memory system, which actions are requested and occur independently of one another, and since the auxiliary processor and the main memory system with which it communicates have independent controls, the system interface requires a multilevel control unit to control the various independent operations without denying access to portions of cache memory currently being used by the auxiliary processor.
It is then, an object of the present invention to provide an improved system interface * Trade Mark I
between an auxiliary processor and a large multiprocessing system having different data rates, memory capacity and control word format.
According to the present invention there is provided a system interface unit fox transmission of data and code between a processor and a main memory system, said interface unit comprising memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system; cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having input means and output means coupled to provide control signals to said cache mechanism means and said memory inter-face means respectively; said first control store input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a command code to address said second control store; each control store input means being provided with program counter means to increment a previous address to address the respective control store us-less a new address is received.
An embodiment of the present invention will now be described, by way of example, with reference to the accompany-in drawings in which:-Figure 1 is a schematic diagram of a multiprocessing system;
Figure 2 is a schematic diagram of an auxiliary processor and its connection to a system interlace;
Figures I and B are a schematic diagram of the system interface employed in this embodiment; and Figure 4 is a schematic diagram of the two-level microprogram controller.
I
This embodiment is directed toward the interfacing of an entry level data processor into a large multiprocessing system which entry level processor serves as an auxiliary processor to handle off-loaded chores to enhance the perform mange and throughput of the system as a whole. The present embodiment is embodied in a system interface which resolves differences in memory access capabilities, data rates and clock frequencies by providing a cache memory mechanism and a main memory interface mechanism which operate in overlap fashion under control of a two-level microcontroller.
Such multiprocessing system is illustrated in Figure 1 and may be of the type described in the Molt et at US. Patent No. 3,319,Z26. The system includes a plurality of main processing units 10 and one or more I/O processors 11 each of which can communicate with any one of a plurality of memory modules 12. In addition, the system includes a plurality of auxiliary processors 13, which may be just a commercially available entry level processor which never the-less has a slower clock frequency and less memory address-in capabilities. For example, in the embodiment of the present invention, the entry level or auxiliary level pro-censor has a clock rate of 4 MISS while the rest of the system has a clock rate of 8 MISS. Furthermore, an Audi-fiery processor is capable of addressing only a million I words of memory while, in the present embodiment, four main memory modules 12 are capable of storing 12~3 million words of data and code. However, because of the size of the main memory system in Figure 1, the memory access time is typical-lye 1600 nanoseconds while the auxiliary processors 13 are designed for memory access time of only 600 nanoseconds.
A typical auxiliary processor and the system interface for the present embodiment are illustrated in Figure 2 where the auxiliary processor is a modular two primary bus system that includes data processing module aye, program control module 14b, stored logic controller module 14c and an Input/Output module 14d which communicate with one another via CUBS 15 and BUS 16. CUBS 15 is used to broadcast control information from stored logic control-for 14c to all the other modules while BUS 16 is used to transfer data and address information to the various modules of the auxiliary processor. DUBS is illustrated as being employed locally within data processing module aye.
In addition, auxiliary processor of Figure 2 would include a memory control module to access the local memory of one million words. However, since the auxiliary process son is to interface with a much larger system, such controller is replaced in Figure 2 by system interface unit 17 which communicates with the rest of the auxiliary processor by way of CUBS 15 and USE 16.
A diagram of the functional units of the system interface of the present embodiment is provided in Figure 3 which illustrates the various functional units of the cache mechanism, main memory interface mechanism, and the two level microcontroller 20 for providing control of a cache mechanism and main storage interface mechanism in an overlap manner in accordance with the present embody-mint. Data and addresses are supplied to the cache memory mechanism by way of BUS 16 of Figure 2. Data for storage in main memory system is passed through the cache motion-is to main memory interface mechanism for transmission to the main memory system. Data and code received from the main memory system is received by the main memory interface mechanism and transmitted to the cache memory mechanism for subsequent transmission to the auxiliary processor on BUS 16. Individual data words can also be transmitted directly from the main memory interface mechanism to the BUS 16. Commands are received by microcontroller 20 from CUBS 15 of Figure 2 to drive the respective cache and main memory interface control stores to activate their corresponding units. The main memory interface mechanism also receives commands from CUBS 15 or the generation of main memory control words for the accessing of data in main memory.
DETAILED DESCRIPTION
Cache Memory Mechanism The principle function of the cache memory mechanism is to reduce memory access times from approxi-mutely 1600 nanoseconds for the large main memory system to the 600 nanosecond access time of the auxiliary processor. In addition, the cache mechanism includes an efficient cache purge mechanism _ -/ /
/
... .. , . , . . .
.
I
I
requiring only a few clock times. All stores to the cache mechanism from the auxiliary processor are to be immediately passed onto the main memory system.
In addition, the cache memory mechanism also performs S program code prefetching as will be more thoroughly described below. Referring again to Figure 3, the principle element of the cache mechanism is data array 31 which is a random access memory of 256 word locations or registers of 52 bits each. The array is divided such that program code occupies 128 words and data occupies 128 words. The segregation of program code from data allows prevention of random data accesses from overwriting code loops which may be captured in the cache as well as facilitates the selective purging of data without purging useful program code and also allows for the program code prefetching mechanism to be more further described below.
Each of the 128 word groups is divided into 16 eight word wages so as to allow all fetches to the main memory system to be eight word operations.
Addressing data array 31 is accomplished by passing the seven least significant bits I page bits and three word bits) of the requested 20 bit address to the data array. The most significant address bit is generated by the cache control unit which determines from the requested operation whether to access the program code or the data portion of the data array.
Translation table 24 of Figure 3 is organized as 32 word locations of 13 bits each. Each word location corresponds to an 8 word page in data array 31. There are 16 word corresponding to program code entries and I words corresponding to data entries ~Z~8~
g in the data array. The I bit word in the translation table is a 13 most significant address bits of the data held in the corresponding page of data array 31.
The translation table is addressed by 4 page bits of the requested 20 bit address. The most significant address bit of the translation table is generated by a control unit 20. When the output of translation table 24 compares with the 13 high ardor bits of the requested address, address comparator 27 signals hit detection unit 28~
Valid bit array 23 is used to indicate the validity or proper entry of an address in translation table 24. It is arranged as two 4 by 4 register files containing one bit for every entry in lo translation table 24. This arrangement allows the cache to be purged in 4 clock times instead of 32 since all that is necessary to purge the cache is to reset the valid bits in the valid bit array. The valid bit array is addressed by the page bits of the requested 20 bit address. As in the case of data array 31 and translation table 24, the most significant address bit for the valid bit array is generated by control unit 20.
Page used array 22 has one bit corresponding to every entry in the program code portion of the translation table 24. It also is implemented in a physically separate 4 by 4 register file. Thy page used array 22 is employed by the program code look-ahead or prefetch algorithm. It is managed by control unit 20.
The cache mechanism is activated by receipt by address register 25 of a 20 bit address from BUS 16 which address is simultaneously supplied to translation table 24, valid bit array 23, address comparator 27, 8~6~
page used array 22 and data array 31. If control unit 20 has also received a fetch command from CUBS 15, the output of translation table 24 is compared by hit detection unit 28 with the 13 most significant bits of the requested 20 bit address. If they are equal and valid bit corresponding to the translation table entry is true, the data now present at the output of data array 31 is the requested data. Otherwise, the requested data is not present in the cache mechanism and must be requested from main memory. If the fetch request is for program code, the prefetching algorithm described below is also invoked.
When control unit 20 receives a store command from CUBS 15, the translation table 24 is compared with the 13 most significant bits of the requested 20 bit address and, if they are equal and the valid bit corresponding in the translation table entry is true, hit detection unit 27 signals control unit 20 causing it to generate a write signal to the data array. The data is also sent to the main memory interface mechanism for transmission to main memory.
The prefetch algorithm is essentially as follows:
When code is requested by the auxiliary processor, the cache mechanism determines whether the requested page is present in data array 31.
If the requested page is present in data array 31, the requested word is transmitted to the auxiliary processor. If the Page Used Bit associated with tune requested page is set, the operation terminates. If the Page Used Bit associated with the requested pave ~L2~L81~
is not set, a prefetch operation is initiated. The control unit calculates the address of the "NEXT" eight word page. This address is presented to the cache mechanism which determines whether the "NEXT" page is present in data array 31. If it is present, the Page Used Bit associated with the requested page is set and the operation terminates. If it is not present, the cache control unit directs the memory interface control unit to initiate a main memory request for the "NEXT"
lo page. At this time, the Page Used Bit associated with the requested page is set and the cache control unit goes to the idle state thereby making it available to service auxiliary processor requests. Meanwhile, the memory interface control unit maintains communication with the main memory system. When the main memory system responds with the "NEXT" page data, the memory interface control unit directs this data to the appropriate location in data array 31. The memory interface control unit resets the Page Used Bit associated with the "NEXT" page and enters the idle state thereby completing the prefetch operation.
If the requested page is not present in data array 31, a main memory request is initiated. When tune main memory system returns the requested page, the data is directed to the appropriate location in data array 31.
Simultaneously the requested word is directed to the auxiliary processor. At this time the control unit calculates the address of the "NEXT" eight word page.
This address is presented to the cache mechanism which determines whether the "NEXT" page is present in data array 31. If it is present, the Pave used Bit associated with the requested page is set and the operation terminates.
If it is not present, the cache control unit directs the memory interface control unit to initiate a main memory request for the "NEXT" page At this time, the Page Used Bit associated with the requested page is set and the cache control unit goes to the idle state thereby making it available to service auxiliary processor requests. Meanwhile, the memory interface control unit maintains communication with the main memory system.
When the main memory system responds with the "TEXT"
page data, the memory interface control unit directs this data to the appropriate location in data array 31.
The memory interface control unit resets the Page Used Bit associated with the "NEXT" page and enters the idle state thereby completing the prefetch operation.
Main Memory Interface Mechanism The remaining functional elements in Figure 3, except for control unit 20, form the main memory interface mechanism of the present invention.
These functional units include memory bus interface unit 34, memory interface register 32, bypass register 33 and control word generator 21. With these units, the main memory interface mechanism interfaces the auxiliary processor to the main multiprocessing system.
More specifically, it interfaces the four main memory units 12 of Figure 1 with the above-described cache memory mechanism and thus the auxiliary processor.
Bus interface unit 34 is capable of selectively listening to any one but only one of the four memory modules 12 in Figure 1 and it is capable of broadcasting to all such memory modules simultaneously. The buses between bus interface unit 34 and the respective memory modules is basically a bidirectional 52 bit wide bus.
In addition, the bus interface unit includes a handshake unit snot shown) which is responsible for sending and receiving control signals to and from the four memory modules. The primary control lines to the respective Emory modules, in addition to the 52 bit wide bus include a requester to memory request line, a requester to memory data valid line, a memory to requester acknowledge line, and the memory to requester fail line.
Control word generator 21 takes commands from the auxiliary processor by way CUBS lo and converts them into main memory module control words.
This unit is responsible for the extended address gape ability required to address the main memory system. Control words are 52 bits in width and are of two different formats. One format is the memory operation request which is used or normal memory operations such as fetch and store and contains four different fields plus the fifth field which is not employed. The four fields are a twenty bit address field supplied by the auxiliary processor from BUS 16 by way of address register 25 and address bus 38; an extended address field which is obtained from one of two base registers (not shown) in control word generator 21; a length field which specifies whether one data or code word is to be fetched from memory or eight such data or code words; an opaqued field which contains a main memory defined opaqued consistent with the operation being performed with one of the main memory modules.
The two base registers, which provide the extended address field during a fetch from main memory, are "data environment register" and a "code environment data register" which are respectively being used according to whether or not data or code is being received from one of the main memory modules. Finally, parity is generated for the overall control word and inserted into a parity field.
The other control word format is a memory management request control word which is used to request special memory management operations. It is 52 bits in width and contains an opaqued field similar to the one described in the memory operation request control word; a length field which is always one and a variant field which is generated by the auxiliary processor to create variations of basic requests, thus reducing the number of opcodes required.
Cache bypass register 33 is employed to provide a direct path from the main memory modules to BUS 16. When data returning from one ox the main memory modules is not going to update the cache mechanism, bypass register 33 is used to channel the data directly to the auxiliary processor. When the data returning from the main memory module is destined to update the cache mechanism and is required by the auxiliary processor, that data is copied by the bypass register 33 while simultaneously being supplied to memory interface register 32 to data array 31 by way of BUS 37.
A word counter register (not shown) is provided as a three bit register which is the memory interface mechanism's ability to generate "word addresses"
for purposes of updating the cache memory. When a requested data or program code data item is not present in the cache, the address of that item is sent, by way of interface mechanism, to one of the main memory modules. However, instead of requesting just thaw item, the entire page (8 words) where that ~Z1816~
item resides is requested. The page, however, is requested such that the requested word returns first from main memory module. For example, if the desired word is the fifth word in a given eight word page, the data returns from the selected memory module in the following sequence: word 5, word 6, word 7, word 0, word 2, word 3 and word 4. This scheme allows the desired word to return, on the average, four clock times faster than would occur if the pages were returned always starting with word 0.
The word counter captures the word bits (least significant bits) from the requested address. When the eight word page returns from memory module the word counter is incremented, module 8, to generate the Ward address bits n 50 the cache mechanism can be updated.
Two level Control Store Control unit 20 of Figure 3 is illustrated in Figure 4 and is comprised of two control stores arranged in a hierarchy with the first control store supplying control signals for the cache memory mechanism described above and also addresses to the second control store which supplies control signals to the main memory interface mechanism described above.
This control mechanism was designed with two overriding purposes. One consideration is the provision of a flexible mechanism which would allow changes in existing operations and the addition of new operations by providing control stores that can be configured or replaced. The other consideration is to allow program code prefetching that does not interfere with normal cache mechanist operation. The second consideration requires two microprogram controllers for keeping track of two asynchronous, ~35 simultaneous operations.
I
In Figure 4, the cache memory controller is comprised ox control store 40 which is addressed by the contents ox both register counters aye and 44b.
The contents of register counter aye include an address received by way of multiplexer aye from CUBS 15 of Figures 2 and I. This initial address is the first state of the routine which forms the requested cache mechanism operation. This first state knows the address of the next state, places the next state address on the next state field lines back to multiplexer aye. It also changes the control of the next state multiplexer aye selecting the next state field as an input to microprogram counter aye. As the sequence continues, each routine state points to the next until the routine end is encountered At this point, the control to toe next state multiplexer aye is changed so that CUBS 15 provides the next address to program counter aye. Hence, the controller of Figure 4 is available for the next auxiliary processor request and, if no request is present, CUBS will pass the appropriate signals to the controller.
In addition to straight line sequencing, control store 40 can "test" two conditions by way of the low order address bits received by multiplexer 43b which passes the desired condition bits to condition register 44b~ The conditions are examined during the next routine state. The inclusion of the condition testing allows for a more flexible micro control store.
:~Z~8~
Conditions tested by the cache memory control store include:
availability of the main memory interface control store to accept an operation;
availability of a clock or clock cycle for data transfer to ox from the processor;
translation table parity error;
presence of a requested address in the cache mechanism;
currently addressed code page has been previously accessed (see prefetch algorithm above);
cache address limit error; and last cache memory cycle awarded to main memory interface control store.
Control store 41 provides control signals for the main memory interlace mechanism and is identical to cache control store 40 except that it receives the initial address (opaqued) from cache control store 40 instead of the CASEY. In addition, it can test three conditions instead of two. Both control stores 40 and 41 respectively provide control signals to the cache memory mechanism and the main memory interface mechanism.
They also provide shared commands by way of arbitration logic 42 for data array 31, translation table 24, address bus 38, BUS 37 and bus interface unit 34. It is to be remembered that controls 40 and 41 operate asynchronously and arbitration logic 42 is provided to accept control signals from one or the other of the control stores.
Conditions tested by the main memory interface control store include:
acknowledgment ox main memory available for last memory request;
I
an acknowledge signal has been received for more than one main memory module (an error condition);
an error detected in a control word presented to main memory;
an interface parity error;
memory Jo requester data valid;
main memory system has detected an internal failure;
general purpose counter overflow;
failure of main memory to respond to a request within a reasonable amount of time; and memory to requester operation complete.
In the controller of Figure 4, the control flow is from the auxiliary processor CUBS to the cache mechanism control store 40 to the main memory interface control store I with each control store notifying the other of its current state. That is to say, the main memory interface control store sends a signal to the cache control store when it is idle an the cache control store notifies the auxiliary processor when it is not idle. This handshaking action prevents the driving control store from issuing another operation before the driven control store has computed a previous operation.
With the controller of Figure 4, the cache mechanism control store can request a program code prefetch operation from main memory interface mechanism and, when the main interface control strop is bus communicating with main memory r the cache mechanism control store is free Jo service auxiliary processor requests for code or data in the cache memory.
EPILOGUE
A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. Such a controller allows for communication between the auxiliary processor and a cache mechanism in the system interface to be carried on independently of main memory accesses required to update the cache mechanism in an overlapped manner.
There has been described a system interface with a multilevel control unit to control independently initiated actions across the interface which nevertheless synchronizes independently requested actions across the interface.
In the described embodiment the system interface resides between an auxiliary processor and a main memory system of a multiprocessing system. The interface is divided into two portions or modules: a cache mechanism module and a main memory interface module. The cache mechanism module performs normal cache functions of receiving data and code words from main memory at a slower frequency but higher clock rate and supplies those words to the auxiliary processor at a faster frequency jut slower clock rate. The memory interface module initiates requests for main memory accesses in response to requests from the auxiliary processor. Both modules are under the control of the microprogram controller; however, since the functions of both modules overlap, the controller is formed of two control stores for the cache mechanism module and the main memory interface module, respectively. The cache mechanism control store receives code information from the auxiliary processor as well as condition signals and supplies commands to that mechanism and also addresses to the main memory interface control store, that in turn, supplies commands to the main memory interface module as well as notifying the cache mechanism control store of its current state for the purposes of synchronization.
A feature then, of the embodiment resides in a microprogram controller for a system interface between an auxiliary processor and a main memory system which con-troller includes two control stores, one to control the functions of a cache mechanism and the other to control the functions of main memory accessing where the first control store provides addresses or commands to the second control store that in turn notifies the first control store of its current state.
I
Claims (8)
1. A system interface unit for transmission of data and code between a processor and a main memory system, said interface unit comprising:
memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system;
cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having input means and output means coupled to provide control signals to said cache mechanism means and said memory interface means respectively;
said first control store input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a command code to address said second control store;
each control store input means being provided with program counter means to increment a previous address to address the respective control store unless a new address is received.
memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system;
cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having input means and output means coupled to provide control signals to said cache mechanism means and said memory interface means respectively;
said first control store input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a command code to address said second control store;
each control store input means being provided with program counter means to increment a previous address to address the respective control store unless a new address is received.
2. A system interface unit according to claim 1 wherein:
said second control store is coupled to said first control store to signal said first control store of the availability of the second control store to receive a command code.
said second control store is coupled to said first control store to signal said first control store of the availability of the second control store to receive a command code.
3. A system interface unit according to claim 1 wherein:
said cache mechanism includes a random access memory having two sections, one for code segments and one for data segments, said sections being divided into a plurality of groups of said respective segments.
said cache mechanism includes a random access memory having two sections, one for code segments and one for data segments, said sections being divided into a plurality of groups of said respective segments.
4. A system interface unit according to claim 3 including:
an address register coupled to said processor to receive a memory address, said address being divided into a word identification field, a group address and a segment address; and a table of locations coupled to said address re-sister to receive segment identification fields of segments stored in said random access memory.
an address register coupled to said processor to receive a memory address, said address being divided into a word identification field, a group address and a segment address; and a table of locations coupled to said address re-sister to receive segment identification fields of segments stored in said random access memory.
5. A system interface unit according to claim 4 further including:
comparison detection means coupled to said address register and to said table of locations to compare word identification fields in said table with the word identifi-cation field of an address received by said address register and to signal said first control store when a comparison occurs.
comparison detection means coupled to said address register and to said table of locations to compare word identification fields in said table with the word identifi-cation field of an address received by said address register and to signal said first control store when a comparison occurs.
6. A system interface unit according to claim 1 wherein:
said main memory system includes a plurality of memory units; and said memory interface means includes bus inter-face means coupled between said cache mechanism and said plurality of memory units.
said main memory system includes a plurality of memory units; and said memory interface means includes bus inter-face means coupled between said cache mechanism and said plurality of memory units.
7. A system interface unit according to claim 6 further including:
a bus coupling said bus interface means to said cache mechanism means; and a bypass register coupled between said memory bus interface means and said processor to bypass the cache mechanism means.
a bus coupling said bus interface means to said cache mechanism means; and a bypass register coupled between said memory bus interface means and said processor to bypass the cache mechanism means.
8. A system interlace unit according to claim 6 further including:
a control word generation means coupled between said processor and said bus interface means to receive a code from said processor and to concatenate additional control bits to said code for addressing said main memory system.
a control word generation means coupled between said processor and said bus interface means to receive a code from said processor and to concatenate additional control bits to said code for addressing said main memory system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000518338A CA1233908A (en) | 1983-04-05 | 1986-09-16 | Multilevel controller for a cache memory interface in a multiprocessing system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/482,237 US4586133A (en) | 1983-04-05 | 1983-04-05 | Multilevel controller for a cache memory interface in a multiprocessing system |
| US482,237 | 1983-04-05 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000518338A Division CA1233908A (en) | 1983-04-05 | 1986-09-16 | Multilevel controller for a cache memory interface in a multiprocessing system |
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| Publication Number | Publication Date |
|---|---|
| CA1218162A true CA1218162A (en) | 1987-02-17 |
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| CA000451184A Expired CA1218162A (en) | 1983-04-05 | 1984-04-03 | Multilevel controller for a cache memory interface in a multiprocessing system |
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| EP (1) | EP0121373B1 (en) |
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| DE (1) | DE3483166D1 (en) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BR8406089A (en) * | 1983-11-30 | 1985-09-24 | Fujitsu Ltd | PROCESS TO CONTROL INTERMEDIATE MEMORY IN DATA PROCESSING DEVICE |
| US4794521A (en) * | 1985-07-22 | 1988-12-27 | Alliant Computer Systems Corporation | Digital computer with cache capable of concurrently handling multiple accesses from parallel processors |
| US4802086A (en) * | 1987-01-09 | 1989-01-31 | Motorola, Inc. | FINUFO cache replacement method and apparatus |
| US4851993A (en) * | 1987-04-20 | 1989-07-25 | Amdahl Corporation | Cache move-in bypass |
| US4839793A (en) * | 1987-07-01 | 1989-06-13 | Baytec, Inc. | Multiple computer interface |
| CA1302584C (en) * | 1987-07-30 | 1992-06-02 | Alliant Computer Systems Corporation | Parallel processing computer in which memory access priorities are varied |
| US5008816A (en) * | 1987-11-06 | 1991-04-16 | International Business Machines Corporation | Data processing system with multi-access memory |
| US4912631A (en) * | 1987-12-16 | 1990-03-27 | Intel Corporation | Burst mode cache with wrap-around fill |
| US5032985A (en) * | 1988-07-21 | 1991-07-16 | International Business Machines Corporation | Multiprocessor system with memory fetch buffer invoked during cross-interrogation |
| DE68923863T2 (en) * | 1989-01-13 | 1996-03-28 | Ibm | I / O cache storage. |
| US5202973A (en) * | 1990-06-29 | 1993-04-13 | Digital Equipment Corporation | Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus |
| US5291442A (en) * | 1990-10-31 | 1994-03-01 | International Business Machines Corporation | Method and apparatus for dynamic cache line sectoring in multiprocessor systems |
| CA2086386C (en) * | 1991-12-31 | 1997-04-29 | Daniel F. Daly | Interface chip for a voice processing system |
| US5813030A (en) * | 1991-12-31 | 1998-09-22 | Compaq Computer Corp. | Cache memory system with simultaneous access of cache and main memories |
| US5749090A (en) * | 1994-08-22 | 1998-05-05 | Motorola, Inc. | Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor |
| US5875462A (en) * | 1995-12-28 | 1999-02-23 | Unisys Corporation | Multi-processor data processing system with multiple second level caches mapable to all of addressable memory |
| US5946710A (en) * | 1996-11-14 | 1999-08-31 | Unisys Corporation | Selectable two-way, four-way double cache interleave scheme |
| US5960455A (en) * | 1996-12-30 | 1999-09-28 | Unisys Corporation | Scalable cross bar type storage controller |
| US5875201A (en) * | 1996-12-30 | 1999-02-23 | Unisys Corporation | Second level cache having instruction cache parity error control |
| US6122711A (en) | 1997-01-07 | 2000-09-19 | Unisys Corporation | Method of and apparatus for store-in second level cache flush |
| US5860093A (en) * | 1997-01-21 | 1999-01-12 | Unisys Corporation | Reduced instruction processor/storage controller interface |
| US6014709A (en) * | 1997-11-05 | 2000-01-11 | Unisys Corporation | Message flow protocol for avoiding deadlocks |
| US6049845A (en) * | 1997-11-05 | 2000-04-11 | Unisys Corporation | System and method for providing speculative arbitration for transferring data |
| US6052760A (en) * | 1997-11-05 | 2000-04-18 | Unisys Corporation | Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks |
| US6092156A (en) * | 1997-11-05 | 2000-07-18 | Unisys Corporation | System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
| US6314501B1 (en) | 1998-07-23 | 2001-11-06 | Unisys Corporation | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
| US6687818B1 (en) | 1999-07-28 | 2004-02-03 | Unisys Corporation | Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system |
| US6665761B1 (en) | 1999-07-28 | 2003-12-16 | Unisys Corporation | Method and apparatus for routing interrupts in a clustered multiprocessor system |
| US7512395B2 (en) * | 2006-01-31 | 2009-03-31 | International Business Machines Corporation | Receiver and integrated AM-FM/IQ demodulators for gigabit-rate data detection |
| US8184110B2 (en) | 2007-11-05 | 2012-05-22 | Seiko Epson Corporation | Method and apparatus for indirect interface with enhanced programmable direct port |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50156833A (en) * | 1974-06-06 | 1975-12-18 | ||
| US4038643A (en) * | 1975-11-04 | 1977-07-26 | Burroughs Corporation | Microprogramming control system |
| US4168523A (en) * | 1975-11-07 | 1979-09-18 | Ncr Corporation | Data processor utilizing a two level microaddressing controller |
| US4075686A (en) * | 1976-12-30 | 1978-02-21 | Honeywell Information Systems Inc. | Input/output cache system including bypass capability |
| JPS6049332B2 (en) * | 1977-01-31 | 1985-11-01 | 株式会社東芝 | Microprogram control method |
| US4156278A (en) * | 1977-11-22 | 1979-05-22 | Honeywell Information Systems Inc. | Multiple control store microprogrammable control unit including multiple function register control field |
| US4179736A (en) * | 1977-11-22 | 1979-12-18 | Honeywell Information Systems Inc. | Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit |
| US4354232A (en) * | 1977-12-16 | 1982-10-12 | Honeywell Information Systems Inc. | Cache memory command buffer circuit |
| US4307445A (en) * | 1978-11-17 | 1981-12-22 | Motorola, Inc. | Microprogrammed control apparatus having a two-level control store for data processor |
| US4313158A (en) * | 1978-12-11 | 1982-01-26 | Honeywell Information Systems Inc. | Cache apparatus for enabling overlap of instruction fetch operations |
| US4268907A (en) * | 1979-01-22 | 1981-05-19 | Honeywell Information Systems Inc. | Cache unit bypass apparatus |
| US4217640A (en) * | 1978-12-11 | 1980-08-12 | Honeywell Information Systems Inc. | Cache unit with transit block buffer apparatus |
| JPS5671139A (en) * | 1979-11-13 | 1981-06-13 | Nec Corp | Microprogram parallel processing computer |
| US4376976A (en) * | 1980-07-31 | 1983-03-15 | Sperry Corporation | Overlapped macro instruction control system |
| JPS5748139A (en) * | 1980-09-04 | 1982-03-19 | Nec Corp | Microprogram control device |
| US4433374A (en) * | 1980-11-14 | 1984-02-21 | Sperry Corporation | Cache/disk subsystem with cache bypass |
| JPS5846440A (en) * | 1981-09-11 | 1983-03-17 | Nec Corp | Microprogram control system |
| JPS5967319A (en) * | 1982-10-08 | 1984-04-17 | Nippon Steel Corp | Manufacture of steel plate for extremely deep drawing |
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1983
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1984
- 1984-03-19 DE DE8484301838T patent/DE3483166D1/en not_active Expired - Fee Related
- 1984-03-19 EP EP84301838A patent/EP0121373B1/en not_active Expired
- 1984-04-03 CA CA000451184A patent/CA1218162A/en not_active Expired
- 1984-04-03 JP JP59067318A patent/JPH0630060B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS603043A (en) | 1985-01-09 |
| US4586133A (en) | 1986-04-29 |
| EP0121373B1 (en) | 1990-09-12 |
| EP0121373A3 (en) | 1988-03-02 |
| JPH0630060B2 (en) | 1994-04-20 |
| EP0121373A2 (en) | 1984-10-10 |
| DE3483166D1 (en) | 1990-10-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |