CA1216962A - Mos device processing - Google Patents

Mos device processing

Info

Publication number
CA1216962A
CA1216962A CA000485874A CA485874A CA1216962A CA 1216962 A CA1216962 A CA 1216962A CA 000485874 A CA000485874 A CA 000485874A CA 485874 A CA485874 A CA 485874A CA 1216962 A CA1216962 A CA 1216962A
Authority
CA
Canada
Prior art keywords
ions
source
silicon
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000485874A
Other languages
French (fr)
Inventor
Hussein M. Naguib
Iain D. Calder
Vu Q. Ho
Abdalla A. Naem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA000485874A priority Critical patent/CA1216962A/en
Priority to US06/813,232 priority patent/US4683645A/en
Application granted granted Critical
Publication of CA1216962A publication Critical patent/CA1216962A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/14—Schottky barrier contacts

Abstract

MOS DEVICE PROCESSING
Abstract of the Disclosure In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which recrystallizes silicon under the designated source and drain regions and so minimizes dopant diffusion. To render the source and drain of desired conductivity type, an ion implantation of a non neutral ion can be performed.
- i -

Description

~2~
This invention relates to a process for the fabrication of MOS semiconduc-tor devices using silicide contacts.
Modern very large scale integrated (VLSI) circuits are composed of semiconduc-tor devices of extremely small dimensions. In particular, the source and drain junctions must be shallow, while still retaining the low resistivity, contact resistance, and leakage current of large scale devices. These requirements can be met by the use of a barrier metal over the sources and drains which, as a metal, lowers resistivity, and by acting as a barrier to silicon/metal (usually aluminum) interdi~fusion, maintains a low leakage current even for a shallow junction. One type of ma-terial commonly used to Form ohmic con-tac-ts is a silicon/refractory metal compound, or silicide. These refractory metal silicides may be either deposited (usually by sput-tering) as a compound, or the metal may be deposited onto the silicon, followed by a chemical reaction to form the silicide. The reaction may be performed by heating the specimen to a high tempera-ture, or ion beam bombardment may be used to mix the constituents and assist or even carry out the reaction to completion (D.L. Kwong, D.C. Meyers, and N.S. Alvi, IEEE Electron Dev. Let-t.
EDL-6, 244-246, 1985; H. Okabayashi, M. Morimoto, and E. Nagasawa, IEEE Trans. Electron Dev. ED-31, 1329-1334, 1984i and M.Y. Tsai, C.S.
Petersson, F.M. D'Heurle, and ~. Maniscalco, Appl. Phys. Le-tt. 37, 295-298, 1980). Lateral growth of silicide during the reaction can be a problem, but is controlled by the use of rapid thermal annealing or ion beam mixing or both (S.D. Lester and N.W. Cheung, to be published in "Ion Beam Processes in Advanced Electronic Ma-terials and Device Technology", ed. by F./H. Eisen, T.W. Sigmon, and B.R. Appleton Ma-terials Research Society, Pittsburgh 1985). If the specimen temperature is maintained at a high level, greater than 300C during ion implantation then the reaction will occur in situ. At lower temperatures ion beam mixing will assist the later thermal reac-tion by causing intermixing of the me-tal and silicon at their mutual interface, thereby destroying any intervening film (such as a thin natural SiO2) that would retard the reaction.
It is known in the fabrication of silicon MOS devices to simultaneously form an n+p junction and a TiSi2 contact layer by ion implantation of As+ ions which cause mixing of Ti and Si and act as an n-type dopant in the underlying silicon (H. Okabayashi, M.
Morimoto, and E. Nagasawa, IEEE Trans~ Electron Dev. ED-31, 1329-1334, 1984; M.Y. Tsai, C.S. Petersson, F.M. D'Heurle, and V. Maniscalco, Appl. Phys. Lett. 37, 295~298, 1980).
There are three disadvantages to this technique.
Firstly, it is not applicable to a p+n junction since arsenic is used; secondly, rapid damage-assisted diffusion of arsenic has been observed, preventing the formation of an acceptably shallow junction (M. Finetti, E. Gabilli, G. Lulli, R. Lotte, P.G. Merli, and R.
Nipoti, to be published in "Ion Beam Processes in Advanced Electronic Materials and Device Technology", ed. by F.H. Eisen, T.W. Sigmon, and B.R. Appleton, Materials Research Society, Pittsburgh 1985). Thirdly, because an oxide side wall spacer is required to separate -the metal over the gate from that over the drain, there are two different ion implantation steps required: doping (before spacer formation), and mixing (after metal deposition).
In the present invention, use of germanium as a mixing ion is proposed. Germanium is suitably heavy -to efficiently perform mixing and it is electrically inert in silicon so it can be used for either p+n or n+p junctions.
In certain embodiments of the invention, germanium, either alone or in conjunction with a silicon implant will also amorphize the silicon substrate, thereby preventing enhanced dopant diffusion, and allowing a shallow junction to be formed. The silicon ions may also assist with the ion beam mixing.
An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:-Figures la to 1c marked PRIOR ART, show processingsteps in a conventional -technique for forming silicide ohmic contacts;
and Figures 2a to 2f show stages in a fabrication process according to the present invention for producing a PMOS transistor.
Referring in detail to Figure 1, there is illustrated a partially comple-ted MOSFET structure in which a polysilicon gate lO
and silicon dioxide side wall spacer structures 12 have been patterned. A film 14 of some refractory metal (typically titanium) has then been deposited, usually by sputtering. In a well-known technique, titantium silicide 15 is formed by a thermal reaction between the titanium and underlying silicon in source, drain and ga-te regions respectively 16, 18 and 20, Figure lb, (T.P. Chow and A.J.
Steckel, IEEE Trans. Elec-tron Dev. ED-30, 1480-1497, 1983). Then as seen in Figure 1c, unreacted titanium which sits on side wall oxide regions 12 is removed by a selective etch, resulting in a self-aligned silicidation process. This reac-tion proceeds only with diFficulty iF

3~i~
there is any contamindtion at metal/silicon interface 22. The reaction may be completely undesirable because of unwanted di-f-fusion occuring at the high temperatures needed (For example, about 800C for titanium and greater than l,O00C for molybdenum). One solution to these problems is to impldnt the surface of the structure illus-trated in Figure la with heavy ions (typically arsenic, As+) in order to mix the atoms at the metal-silicon interface 22. If this process is carried out at room temperature, then the contaminating layer is dispersed and the subsequent thermal reaction can proceed smoothly.
If the implantation is carried out at elevated temperatures (typically greater than 300C) then the titanium and silicon may be mixed completely -to form a titanium silicide film without a high tempera-ture step. However some annealing is still required to remove ion implantation damage in the silicon.
For PMOS transistors, boron is far too light a p-type dopant to produce significant ion beam mixing. Even the use of a heavier molecule such as BF2 is not worthwhile since the molecule breaks up on impact in the metal films.
By the invention, an electrically inert ionic species germanium is used, the germanium ion being relatively heavy and therefore very efficient for mixing. ~~he germanium ion may be used alone to effect mixing a-t the silicon/refractory metal interface together with a measure of amorphization of the silicon. However it is also useful to use a lighter ionic species such as silicon in combination with the germanium in some process sequences. In particular the processes of ion beam mixing and silicon substrate amorphization which is necessary for -the formation of shallow ;2 junctions, may be combined by using the same ions for both purposes.
The value of the silicon implan-tation is its much greater penetration depth into a subs-trate at reasonable implantation energies.
A specific example of the invention is now described with reference to Figure 2. The device fabricated in the process seguence shown in Figure 2 is a PMOS transistor. Initally a field oxide layer 26 is thermally grown in a patterned structure using a well-known LOCOS process. Then a gate oxide layer 28 is gro~n, typically to a thickness of 25 nanometers using a standard process, and a polysilicon film is deposited at 625C using a standard low pressure chemical vapour deposition (LPCVD) process. The polysilicon film is doped with phosphorus by diFFusion from a POC13 source to increase conductivity. The polysilicon layer is patterned to produce a gate 30 (Figure 2a) and the polysilicon gate 30 and source and drain regions, respectively 32 and 34, are oxidized in dry oxygen to a total thickness of 100 nanometers.
The wafer is then anisotropically reactively ion etched to remove the oxide over the gate, source and drain areas while oxide 36 on the gate walls remains because of its greater thickness in the vertical direction (Figure 2b). Next titanium metal 38 is deposited by sputtering to a thickness of about ~0 nanometers (Figure 2c)~
Subsequently, three separate ion implan-tation steps are performed in succession: (i) 5 x 1015 28Si+/cm2 at an energy oF
120 keV; (ii) 3 x 1015 11B+/cm2 at 25 keV, and finally (iii)
2 x 1015 73Ge+/cm2 at 90 keV. The primary function of the silicon implant is to amorphize silicon at the source and drain regions. The amorphous silicon is resistant to dopant di-Ffusion and $~:~69~
therefore channelling of -the subsequen-tly implan-ted boron ions beyond the shallow junc-tion depth desired can be prevented. The boron ion implant is performed to render the source and drain regions p-type.
The germanium implant is performed at an elevated temperature (greater than 300C) to promote both mixing and formation of titanium silicide at regions 40. Annealing of the resulting titanium silicide is carried out by rapid thermal annealing for 10 seconds at 600C in nitrogen, this anneal serving both to improve silicide quality and to recrystallize the amorphous silicon at the junc-tion regions by solid phase epitaxy.
Unreacted ti-tanium 42 on the field oxide and side wall oxide regions is then removed using a solution of ammonium hydroxide (NH4oH) and hydrogen peroxide (H202) leaving the structure shown in Figure 2e.
The chip is subsequently processed in a relatively conventional manner. Passivation layers of, for example, a 200 nanometer silicon dioxide (silox) layer 44 followed by an 800 nanometer borophosphosilicate glass (BPSG) layer 46 are then deposited by LPCVD at 350CC using gas mixtures of SiH4/o2 and SiH4/o2lpH3/B2H6 respectively. The BPSG is then caused to reflow by a rapid thermal heat treatment at 1100C for 10 seconds.
This thermal step also anneals any remaining implantation damage in the silicon and activates the dopant. The remainder of the process is conventional. Contact windows are opened in the BPSG/silox by a standard photollthographic step, using reactive ion etching, and then an optional barrier metal layer 48, such as Ti, TiN or Ti~, and an Al/1%Si film are deposited onto the substrate, patterned photoliyhographically, and sintered at 450C in H2. Finally a 4~P
phosphosilica-te glass (pyrox) film 50 is deposited and pat-terned to provide scratch protection. The completed device structure is illustrated in Figure 2f.
Although the above describes the fabrication of a PMOS
device, an NMOS transistor can be fabricated in a similar manner by replacement of the B+ implantation by an As+ implant in which case the silicon pre~amorphiza-tion step is optional. The arsenic implantation is carried out at or near room temperature -to avoid damage enhanced diffusion problems.
It will be realized that there are several possible variations of the basic process described herein, the key process steps being side wall oxide growth or spacer formation, me-tal deposition, ion-beam mixing, amorphization (optional), implan-tation doping, metal/silicon reaction (optional), selective etching of unreacted metal, and thermal activation of the dopant. Thus the process sequence could vary, condi-tional on (1) the side wall oxide spacer formation preceding metal deposition; (2) the metal deposition preceding ion beam mixing, which in turn precedes the metal/silicon reaction; (3) amorphizaton preceding doping, and these two processes not being separa-ted by the metal/silicon reac-tion; (4) selective metal etching following the metal/silicon reac-tion; and (5) dopant activation following the doping process.

Claims (13)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:-
1. A process for the fabrication of an MOS
semiconductor devices comprising:-forming on a silicon substrate regions of field oxide;
forming at a region not occupied by field oxide a gate oxide layer;
forming a device gate over a region of said gate oxide layer;
designating source and drain areas and removing gate oxide at said source and drain areas;
depositing a refractory metal on the silicon substrate at said source and drain regions; and implanting germanium ions at the source and drain areas to mix silicon and the refractory metal at an interface therebetween.
2. A process as claimed in claim 1 in which, following implantation of said germanium ions, silicon ions are implanted to a depth greater than the germanium ions whereby to cause amorphization of the silicon.
3. A process as claimed in claim 1 in which, following implantation of the germanium ions, ions of a different type are deposited to render the source and drain regions p-type.
4. A process as claimed in claim 3 in which the ions of said different type are boron ions.
5. A process as claimed in claim 1 in which, following implantation of the germanium ions, ions of different type are implanted whereby to render the source and drain regions n-type.
6. A process as claimed in claim 5 in which the ions of said different type are arsenic ions.
7. A process as claimed in claim 2 in which, following implantation of the silicon ions, ions of a different type are deposited to render the source and drain regions p-type.
8. A process as claimed in claim 7 in which the ions of said different type are boron ions.
9. A process as claimed in claim 2 in which, following implantation of the silicon ions, ions of a different type are implanted whereby to render the source and drain regions n-type.
10. A process as claimed in claim 9 in which the ions of said different type are arsenic ions.
11. A process as claimed in claim 1 further comprising, prior to ion implantation, forming a further oxide layer over an upper surface of the gate, over side walls of the gate, and over the source and drain regions and vertically etching the further oxide layer whereby to remove the oxide over the gate upper surface and the source and drain regions but to leave said side wall oxide regions.
12. A process as claimed in claim 11 wherein during deposition of the refractory metal, the refractory metal is deposited simultaneously over the source and drain regions, the gate and the side wall oxide,
13. A process as claimed in claim 2 in which, following implantation of the silicon ions, the wafer is subjected to thermal annealing.
CA000485874A 1985-06-28 1985-06-28 Mos device processing Expired CA1216962A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA000485874A CA1216962A (en) 1985-06-28 1985-06-28 Mos device processing
US06/813,232 US4683645A (en) 1985-06-28 1985-12-24 Process of fabricating MOS devices having shallow source and drain junctions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000485874A CA1216962A (en) 1985-06-28 1985-06-28 Mos device processing

Publications (1)

Publication Number Publication Date
CA1216962A true CA1216962A (en) 1987-01-20

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