CA1216359A

CA1216359A - Failure diagnostic processing system

Info

Publication number: CA1216359A
Application number: CA000457000A
Authority: CA
Inventors: Hitoshi Kasai; Yasuyoshi Asagi; Toshihiro Hattori; Hideo Saito; Katsuya Shishido
Original assignee: Fujitsu Ltd; Isuzu Motors Ltd
Current assignee: Fujitsu Ltd; Isuzu Motors Ltd
Priority date: 1983-06-30
Filing date: 1984-06-20
Publication date: 1987-01-06
Also published as: AU2989384A; JPH0619666B2; EP0130827A1; US4635214A; JPS6011907A; EP0130827B1; AU549232B2; ES533839A0; DE3460766D1; KR850000707A; ES8602223A1; KR890002531B1

Abstract

FAILURE DIAGNOSTIC PROCESSING SYSTEM
ABSTRACT OF THE DISCLOSURE
A failure diagnostic processing system comprising a first element for achieving a diagnostic check with respect to sensors so as to produce first and second diagnostic signals regarding each sensor, which first and second diagnostic signals indicate whether or not a failure condition stands, respectively; a second element for achieving a count up and a count down selectively in response to the first and second diagnostic signals, respectively; a third element for providing an alarm indication in accordance with the count number of the second element; and a fourth element for creating a history of failure by recording the count number of the second element where the count number exceeds a prede-termined reference number for starting the record.

Description

FAILURE DIAGNOSTIC PROCESSING SYSTEM

sAcKGRouND OF THE INVENTION
1. Field of the Invention The present invention relates to a failure diagnostic processing system, more particularly to a system for performing a diagnostic search in a computer controlled apparatus, for example, an electronic controlled auto-matic transmission apparatus for use in automobiles.

2. Description of the Prior Art Obviously, the present invention can be also applied to other similar apparatus, such as computer controlled data processing or data communication systems, and the like. However, to facilitate a better understanding of the present invention, the following explanation will be made by taking the aforesaid electronic controlled automatic transmission apparatus as a preferred example.
Automobiles are equipped with automatic transmission to eliminate difficult clutch operation by automatically effecting the so-called gear changes, thus making the operation of the automobile easy even for an unskilled driver. Various apparatuses are known and used for this purpose and, recently, there is a trend toward realizing such an automatic transmission with the aid of a micro-computer, i.e., an electronic controlled automatic transmission. In the electronic controlled automatic transmission, control is achieved through various information signals or data, such as engine speed, rotational input-shaft speed, gear position, clutch stroke, etc., and this necessitates the use of various sensors for detecting the above-mentioned control information signals. Where such sensors are used, it is important to manage these through the appropriate diagnostic searches, in order to maintain a high relia-bility in the operation of the automobile.
In the prior art, the following diagnostic search method, for example, has been proposed. In this prior

3~3 art method, particular memory bits are allotted, in advance, in a certain memory for each individual sensor. IE a failure is detected in any one of -the sensors, the corresponding memory bit allot-ted to that sensor is changed from, for example, "0"
to "1", so that an alarm is raised indicating the occurrence oE
the failure with the logic "1" bit. However, the prior art method con-tains problems in that, firs-t, undesired flashing of the failure indication oE-ten occurs due to a failure which is not continual but intermittent, and second, that it is difEi-cult to investigate failures which occurred in the pas-t but not at present. That is, -the prior ar-t method is inherently not available for investigating a history of failures regarding each of the sensors mentioned above.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a failure diagnostic processing system which ean suppress -the aforesaid undesired flashing of the failure indieation so that a highly reliable diagnostic search can be performed and, in addition, can provide a history of failures for each of the sen-sors mentioned above.
In accordance with one particular embodiment of the pre-sent invention, there is provided a failure diagnostic pro-cessing sys-tem for an apparatus supervised by sensors which detect individual eonditions of the apparatus, the system eom-prising eheeking means, operatively eonnected to the sensors, Eorachieving diagnostic checks with respect to the sensors to pro-duce first and second diagnostic signals regarding each of the sensors, the first and second diagnostie signals indicating that a failure condition exists and does not exist, respec-tively;

:.

3~3~
- 2a -counting means, operatively connected -to the checking means, for generating a count number by incrementing and de-crementing selec-tively in response to the :Eirst and second diag-nostic signals, respec-tively;
alarm means, operatively connected to -the counting means, for providing an alarm indication in accordance with the count number of the coun-ting means; and recording means, operatively connected to the counting means, for creating a history of failures by recording the count number of the counting means after the count number exceeds a first predetermined reference number.
In accordance with another particular embodiment of the present invention, there is provided a failure diagnostic method using data sensed by sensors, comprising the steps of:
(a) checking the sensors periodically to detect whether a failure condition exists;
tb) counting in dependence upon the checking by incrementing a count number if the failure condition exists and decrementing the count number if the failure condition does not exist; and (c) indicating an alarm in dependence upon the count number.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more apparent from the ensu-ing description with reference to the accompanying drawings, wherein:

, Fig. 1 is a schematic block diagram of a known electronic controlled automatic transmission apparatus provided in a body of an automobile;
Fiy. 2 is a schematic diagram of a map used for determining a suitable gear position;
Fig. 3 is a general view of a failure diagnostic processing system according to the present invention;
Fig. 4 is a circuit diagram showing details of a failure diagnostic pro^essing system according to an embodiment of the present invention shown in Fig. 3;
Fig. 5 is a flow chart of procedure performed by the error counter shown in Fig. 4;
Fig. 6 is an explanatory graph used for showing an arbitrary example of procedure performed in a major part of the system shown in Fig. 4; and Fig. 7 illustrates a modification of the failure diagnostic processing system according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Before describing the preferred embodiments of the present invention, an explanation will be given of a known automatic transmission apparatus, as an example, to which the present invention can be advantageously applied.
Figure 1 is a schematic block diagram of a known electronic controlled automatic transmission apparatus provided in a body of an automobile. In Fig. 1, reference numeral 1 represents an accelerator pedal, 2 a throttle motor for adjusting a throttle valve 2', 3 an engine, 4 a clutch, 5 a transmission, 6 solenoid valves for driving a clutch actuator 4' and a trans-mission actuator 5', 7 a drive wheel, 8 a mode selector provided with a transmission lever 8', for manually selecting a drive mode such as drive (D), neutral (N), and reverse (R), 9 a control unit, constituted by a microprocessor, for controlling the throttle motor 2, the solenoid valves 6 and producing a hill start aid ~$~

output (HSA), and 10 an indicator for displaying the present status of the transmission 5.
The control unit 9 receives, at respective input ports, a lever position signal PSL from the selector 8, an accelerator position signal PSA from the accelerator pedal 2, i.e., throttle angle signal, an engine speed indication signal ISE from the output side of the engine 3, a clutch position signal PSC from the clutch 4, a rotational input-shaft speed indication signal ISs , an automobile speed indication signal ISA , and so on. Note, the above-mentioned input signals PSL ~ PSA , PSC ~ ISE , ISs , and so on (not shown) are detected by and output from individual suitable sensors, and that these sensors are widely known in the art.
The control unit 9 receives and processes the individual input signals from these sensors to produce output signals, at the respective output ports, thereby controlling the engine speed through the throttle motor 2, engagement or disengagement of the clutch 4 through the clutch actuator 4', and gear changes in the transmission 5 through the transmission actuator 5'.
That is, the engagement or disengagement of the clutch 4 is determined by the control unit 9 in response to the engine speed indication signal ISE and the rotational input-shaft speed indication signal ISS. The gear change in the transmission is controlled in response tO the accelerator position signal PSA , indicating the throttle angle, and the engine speed indication signal ISE , with reference to a map (FigO 2).
Figure 2 is a schematic diagram of a map used for determining a suitable gear position. The map determines the gear position best suited for the running of the automobile in accordance with the throttle angle TH in %
and the automobile speed AS in km/h. A TH of 100%
represents a condition wherein the throttle valve is fully open, while a TH of 0~ represents a condition wherein the throttle valve is closed. In the map shown i3~

in Fig. 2, numerals 1, 2, 3, 4, and 5 denote individual gear positions. The curves indicated by solid lines represent gear change borders during acceleration of the automobile, while the curves indicated by broken lines represent gear change borders during deceleration of the automobile.
As mentioned above, in the electronic controlled automatic transmission apparatus, various input signals L ' A ~ PSC ~ ISE , ISS , and the like are needed for operation of the running of the automobile.
If these input signals could be always guaranteed to be correct, diagnostic searches would not be necessary.
However, in actuality, failures may be expected to occur in the related sensors and their peripheral circuitries.
The present invention is available to cope with such failures.
Figure 3 is a general view of a failure diagnostic processing system according to the present invention.
The system is generally comprised of a first block Bl for achieving a diagnostic check with respect to each of the sensors Sl, S2 ... Sn, a second block B2 for counting pulses upward or downward in accordance with a resultant determination given by the first block sl, a third block B3 for indicating an alarm in accordance with the number o~ signals counted, and a fourth block B4 for recording a history of failures, such failures to be recorded selectively when failures of the sensors Sl, S2 ... Sn, if any, are judged to be important in view of the number counted in the second block s2.
Figure 4 is a circuit diagram, showing details of a failure diagnostic processing system 20 according to an embodiment of the present in~ention shown in Fig. 3.
In Fig. 4, reference numeral 11 represents a self-diagnostic check element (DGN) which is identical to block Bl of Fig. 3, and 12 an error counter (CNT) which corresponds to the second block B2 of Fig. 3. Reference numeral 13 represents an alarm indication part (ALM) 3,~

which forms, together with a comparator (CMP) 18, block B3 of Fig. 3. Reference numeral 14 represents a history recording element (REC) which forms block B4 of Fig. 3 by cooperating with a comparator (CMP) 19, a coincidence determining element (CND) 17, an inverter 16, and an AND logic gate 15. Note, each sensor, i.e., Sl through Sn , is allotted an exclusive system 20 for the purposes of the diagnostic check, except for the DGN
element 11. That is, the system 20 is operated with respect to an individual sensor, i.e., the sensor Sk among the sensors Sl through Sn of Fig. 3. Therefore, there are other systems each identical to system 20, except for the common DGN element 11, but these are not shown in Fig. 4 for simplicity. Most preferably, all the functions to be achieved in the system 20 are equivalently attained by processing executed in the control unit 9 of FigO 1, i.e., the microprocessor.
The DGN element 11 is triggered periodically with a constant time interval. At each periodic diagnostic check, the DGN element 11 determines whether a predeter-mined failure condition stands for each sensor, including its peripheral circuitry. If the failure condition stands, the DGN element 11 produces a signal T indicating "true", if the condition does not stand it produces a signal F indicating "false". No further detailed expla-nation of the DGN element 11 itself is given, since the DGN element 11 per se does not feature the essential point of the present invention. Also the construction of the DGN element 11 should be varied to allow the use of the system 20. For example, with reference to Fig. 1, when the sensor produces the logic "1" signal P5C
indicatinq that the clutch 4 is engaged, both the sensors must produce the corresponding signals ISE and ISS , if the sensors have not failed. If, however, the signal ISS
is not generated it will be assumed by the DGN element 11 that the ISS sensor has failed so long as the clutch 4 is normal.

In Fig. 4, the error counter 12 operates to count up the signal T if the signal T is generated. Conversely, the counter 12 operates to count down the signal F, if the signal F is generated and, at the same time, the AND
logic gate 15 is opened. The element 15 is open if the inverter 16 produces a logic "1". This logic "1" is produced when the coincidence determining element 17 produces a logic "0", indicating that the count number output N from the counter 12 does not coincide with rO~
or rn~ . The number rO~ denotes a lower limit number of the counter 12. The coincidence determining element 17 operates to stop downcounting by the error counter 12, even if the signal F is generated, only where the count number decreases and coincides with a predetermined reference number rnJ to hold the count number at a level not lower than this reference number r~ and also, where the count number, which has not exceeded this reference number, decreases and coincides with r0~.
The counter 12 stops counting the signal F lf the count number reaches a predetermined upper limit number N2; this count stop is achieved by the counter 12 itself. Thus, in general, the error counter 12 is operative to count signals T and F upward and downward, respectively.
The number rnl also denotes a reference for starting a record of failures as a failure history record. That is, when the comparator 19, as a record controlling part, determines that the number N exceeds the reference number rn,, the output from the comparator 19 activates the history recording element 14 to record each number N
via a line Ll. On the other hand, if the output N from the counter 12 does not coincide with any one of the numbers rOJ through rn-~ , the coincidence determining element 17 produces a logic "1", and therefore, the AND
logic gate 15 is closed, via the inverter 16, so that the counter 12 stops the count down. Thus the block B4 of Fig. 3, i.e., elements 14, 15, 16, 17, and 19 in 3~

Fig. 4, is operative to record the failure number N if the number N exceeds the reference number rnl .
The comparator 18 operates to determine whether the count number N from the counter 12 exceeds a number Nl.
The number Nl denotes a reference for activating the alarm indication element 13. If Nl is exceeded, the alarm indication element 13 starts restoring the failure concerned immediately, since such a failure is serious.
For example, the alarm indication element 13 starts flashing an alarm lamp (not shown) to inform the operator or driver that the related apparatus to be supervised by the system 20 must be stopped. The alarm indication part 13 may also produce and transfer a predetermined safeguard signal to a predetermined element in the microprocessor. The restoration method for such serious failures is not a feature of the present invention, and no furthex explanation of this is given herein. Thus, in general, the elements 13 and 18 (corresponding to the block B3 of Fig. 3) operate to provide the alarm indi-cation only for a serious failure.
As previously mentioned, all the functions perform~dby each element of the failure diagnostic processing preferably can be attained with the use of thè micro-processor, corresponding to the control unit 9 of Fig. 1.
Of these functions, the function to be attained by the error counter 12 of Fig. 4 is more important than the other functions, for the present invention, as will be specifically clarified with reference to Fig. 6 herein-after.
Figure 5 is a flow chart of the procedure performed in the error counter 12 of Fig. 4. Every time the DGN
element 11 of Fig. 4 produces the signal T or F, the flow shown in Fig. 5 starts, as follows.
In step a, whether or not a failure has occurred is determined, i.e., whether or not the abnormal condition stands. If "Yes", the flow continues to step d, while if "No', the flow goes to step b. In step b, whether or .3~
_ g _ not the count number N coincides with rOJ or rnJ is determined. If "Yes", the flow continues to step f, while if "No", the flow goes to step c. In step c, the countdown operation by the signal F is carried out and the flow then goes to step f.
Returning to step a, if the answer is "Yes", the flow goes to step d. In step d, whether or not the count number N has reached the predetermined upper limit number N2 is determined. If "Yes", the flow goes to step f, while if "No" the flow continues to step e. In step e, the count up operation by the signal T is carried out, and the flow then goes to step f.
In step f, whether or not the count number N reaches and exceeds the reference number Nl for activating the alarm indication element 13 is determined. If "Yes", the flow continues to step g, while if "No" the concerned procedure is completed.
In step g, an alarm indication device, such as an alarm lamp, is rendered to be continuously flashing.
This is then followed by step h. In step h, a suitable backup treatment is performed for restoring the failure concerned, and the flow of the procedure then reaches its END.
As previously mentioned, the steps g and h follow only when the system 20 discriminates the occurrence of a serious failure. In this case, the manner in which steps g and h are dealt with is outside the subject of the present invention. This can be carried out in various ways.
The thus operated system 20 can be applied to the supervision of abnormalities in various kinds of computer controlled apparatuses, such as the electronic controlled automatic transmission apparatus shown in Fig. 1. Taking this automatic transmission apparatus as an example, the error counter 12 maintains its count number N at all times except when the battery of the automobile is removed or the power source plug thereof is removed. If 3~

such an exception occurs, the counter 12 is initialized to rO~. Further, the counter 12 deals with 4 bit data and, therefore, has a number counting capacity in a range between rO~ and ~5l. The number rl~ corresponds to the aforesaid upper limit number N2 ~ i.e., N2 = 15 in this case, as shown in Fig. 6.
Figure 6 is an explanatory graph showing an arbitrary e~ample of the procedure performed in a part of the system 20 shown in Fig. 4. In the graph, the ordinate denotes the count number N from the error counter 12 and the abscissa denotes the signal T or F from the DGN
element 11. Every time the signal T is produced, i.e., the predetermined failure condition stands, the count number N is increased clock by clock. In Fig. 4, the characters CLK represent the clock, while in Fig~ 6, the pulse width thereof is represented by ~LK. If the count number N is lower than the reference number n for starting the record of failure, i.e., n = 8 in this case, the count number N is disregarded and is not recorded in the history recording element 14 (Fig. 4). Usually, a pseudo signal F occurs at random intervals due to various factors, such as external noise, vibration, mechanical shock, and so on. These factors can be called soft failures. Soft failures usually do not occur continu- -ally, but irregularly, and therefore, the count number N, responding thereto, seldom increases linearly. On the other hand, a real signal F due to a hard error, such as a short circuit, open circuit, and so on, usually occurs continually. Accordingly, the count number N usually increases linearly. An intermediate signal F, which is situated between the pseudo signal F and the real signal F, will probably mature into the real signal F.
Therefore, it is important to watch such an inter-mediate signal F after it has occurred. This watch can be performed by recording past failures in the failure history recording element 14 (Fig. 4). Thus, in Fig. 6, a count number N lower than r8J is not -- 1.1 --recorded (NONRECORD), but a count number N equal to or higher than r8~ is recorded (RECORD). To c:reate the failure history record, once the number N exceeds r8J~
the number N is compulsorily held to be not lower than r8~ (n). This corresponds to a "HISTORY CREATION STATE"
in Fig. 6. During states other than the "HISTORY
CREATION STATE", the count number N is reduced in response to the signal F.
If the count number N is equal to or higher than the reference number Nl for activating the alarm indication element 13 IFig. 4), i.e., Nl = 14 in this case, the comparator 18 (Fig. 4) determines that a certain serious failure has occurred, i.e., a hard error, and immediately activates the alarm indication element 13 so as to continually flash the alarm lamp, during the "ALARM
STATE" of Fig. 6.
When the constant periodic diagnostic check by the DGN element 11 (Fig. 4) is set to be equal to the frequency of the clock CLK, a maximum of fourteen time clocks are needed to detect a serious failure, as exemplified in Fig. 6. However, once the count number N
is brought into the history creation state, the number N
will be increased not from rOJ but from r8~ even in the worst case, with respect to the regeneration of the same failure, because the number N, which is now higher than 8 in any event, is stored in the recording element 14 (Fig. 4). This means that the system 20 can determine such recurrences of the same failure in a time as short as within seven time periodic diagnostic checks, at most. Further, when the count number N is brought into the alarm state, i.e., N = rl4~ or rl~ , the alarm state can be speedily restored within two time periodic diagnostic checks, if the signal F is produced again continually, due to, for example, a self-restoring ability, if any.
The following table shows the relationship, as an example, of the diagnostic check period CP in seconds S

;3~

(as in the following), the maximum failure detection -time DT, and the maximum restoration time RT. The time DT is classified into two cases; that is, case Cl where no history record has been created, and case C2 where the history record has been created.

Table DT s CP s RT s Cl C2 0.1 1.4 0.70.2 0.2 2.8 1.40.4 0.4 5.6 2.80.8 0.8 11.2 5.61.6 1.6 22.4 11.23.2 3.2 44.8 22.46.4 6.4 89.6 44.812.8 .

Figure 7 illustrates a modification of the failure diagnostic processing system according to the present invention. The modified system 30 of Fig. 7 is different from that of Fig. 4 in that a flip-flop (FF) 29 and an AND logic gate 28 are employed, instead of the comparator 19 of Fig. 4. In ~he thus modified system 30, the failure history recording element 14 is not activated until the count number N is once brought into the alarm state, i.e., N = 14 or 15. Once the number N reaches rl~ , at least, the flip-flop 29 enables the failure history recording element 14 to record. Accordingly, the element 14 records information concerning more serious failures than those recorded by the system 20.
Returning to Fig. 4, it is possible to replace the r 11 ~ 13 -reference number rn~ for the coincidence determining element 17 with numbers rxJ and the replace the number rn~ for the comparator l9 with YJ, as shown by x and y in Fig. 6. This means that a relatively wide range of the number N is taken into consideration for monitoring, however, the numbers N to be recorded are of a relatively small range. ~lso the recorded numbers N
indicate relatively serious information regarding failures.
Further, although the periodic diagnostic check is performed with the CLK interval, it may also be possible to perform the same with the k CLK's interval, where k is a positive integer larger than 2~. For example, if the system 20 or 30, except for the DGN element ll, is allotted to a sensor for detecting an engine temperature, it is not necessary to perform the diagnostic check so frequently, because any change in the engine temperature is usually very slow. Note, the systems 20 or 30 must begin operating only after a short time has passed since power on, when initially driven by the power, so as to wait till the output voltage thereof is stabilizied.
As previously mentioned in detail, a highly reliable and precise diagnostic check can be performed by the present invention in a computer controlled apparatus.

Claims

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A failure diagnostic processing system for an appara-tus supervised by sensors which detect individual conditions of the apparatus, said system comprising:
checking means, operatively connected to the sensors, for achieving diagnostic checks with respect to the sensors to produce first and second diagnostic signals regarding each of the sensors, the first and second diagnostic signals indicating that a failure condition exists and does not exist, respec-tively;
counting means, operatively connected to said check-ing means, for generating a count number by incrementing and decrementing selectively in response to the first and second diagnostic signals, respectively;
alarm means, operatively connected to said counting means, for providing an alarm indication in accordance with the count number of said counting means; and recording means, operatively connected to said count-ing means, for creating a history of failures by recording the count number of said counting means after the count number exceeds a first predetermined reference number.

2. A system as set forth in claim 1, further comprising a clock, operatively connected to said checking means and said counting means, and wherein said checking means performs the diagnostic checks periodically with a predetermined constant interval in synchronism with said clock of said system.

3. A system as set forth in claim 2, wherein the prede-termined constant interval is individually predetermined for each of the sensors.

4. A system as set forth in claim 2, wherein said count-ing means comprises an error counter in said system, counting upward every time the predetermined constant interval passes when the first diagnostic signal is being produced and, other-wise, counting downward every time the predetermined constant interval passes when the second diagnostic signal is being pro-duced.

5. A system as set forth in claim 4, wherein said error counter generates the count number within a range between a lower limit of 0 and an upper limit number.

6. A system as set forth in claim 5, wherein said alarm means comprises:
a first comparator, operatively connected to said error counter, for comparing the count number from said error counter to a second predetermined reference number and produc-ing a signal; and an alarm indication element, operatively connected to said first comparator, activated by the signal produced by said first comparator when the count number is higher than the second predetermined reference number.

7. A system as set forth in claim 6, wherein said alarm indication element comprises an alarm lamp, operatively con-nected to said first comparator, for flashing an alarm.

8. A system as set forth in claim 6, wherein said record-ing means comprises:
a history recording element, operatively connected to said error counter, for recording the count number from said error counter;
a record controlling element, operatively connected to said error counter and said history recording element, for producing an output for activating said history recording ele-ment; and a coincidence determining element, operatively con-nected to said error counter, for stopping the decrementing of said error counter, even if said second diagnostic signal is being produced, when the count number decreases and coincides with a third predetermined reference number, thus holding the count number to be at least as large as the third predetermined reference number and also for stopping the decrementing of the count number, when the count number has not exceeded the third predetermined reference number, once the count number coincides with 0.

9. A system as set forth in claim 8, wherein said record controlling element comprises a second comparator, operatively connected to said error counter and said history recording ele-ment, for producing an output for activating said history re-cording element when the count number exceeds the first prede-termined reference number.

10. A system as set forth in claim 8, wherein said record controlling element comprises:
a flip flop, operatively connected to said first com-parator, for producing a logic value "1" once said first com-parator produces the signal for activating said alarm indica-tion element; and an AND logic gate, operatively connected to said error counter, said flip flop and said history recording ele-ment, for allowing passage of the count number therethrough to said history recording element when said flip flop produces the logic value "1".

11. A system as set forth in claim 9, wherein the fourth predetermined reference number is set to be higher than the third predetermined reference number.

12. A failure diagnostic method using data sensed by sen-sors, comprising the steps of:
(a) checking the sensors periodically to detect whether a failure condition exists;
(b) counting in dependence upon said checking by incrementing a count number if the failure condition exists and decrementing the count number if the failure condition does not exist; and (c) indicating an alarm in dependence upon the count number.

13. A method as set forth in claim 12, further comprising step (d) recording the count number.

14. A method as set forth in claim 13, wherein step (b) comprises the step of (bi) stopping said incrementing when the count number coincides with a maximum count number.

15. A method as set forth in claim 14, wherein step (d) comprises the step of starting said recording when the count number coincides with a recording start number, and wherein step (b) further comprises the steps of:
(bii) stopping said decrementing of the count number when the count number coincides with zero and the count number has remained less than the recording start number; and (biii) stopping said decrementing of the count number when the count number coincides with the recording start number after the count number has been incremented to a value at least as large as the recording start number.