CA1215456A - Method for sputtering a pin amorphous silicon semi- conductor device having partially crystallized p and n-layers - Google Patents

Method for sputtering a pin amorphous silicon semi- conductor device having partially crystallized p and n-layers

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Publication number
CA1215456A
CA1215456A CA000461877A CA461877A CA1215456A CA 1215456 A CA1215456 A CA 1215456A CA 000461877 A CA000461877 A CA 000461877A CA 461877 A CA461877 A CA 461877A CA 1215456 A CA1215456 A CA 1215456A
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mtorr
ranging
sputtering
argon
layer
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French (fr)
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H. Paul Maruska
Theodore D. Moustakas
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ExxonMobil Technology and Engineering Co
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Exxon Research and Engineering Co
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02367—Substrates
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    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

ABSTRACT OF THE DISCLOSURE

A high efficiency amorphous silicon PIN
semiconductor device having partially crystallized (microcrystaline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting en-hanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down proce-dure.

Description

~ r~
2 The present invention relates to hydro-
3 genated amorphous silicon and more particuiarly to a
4 method for reactively sputtering a PIN amorphous sili-con semiconductor device havin~ partially crystallized 6 P and N layers.

7 Amorphous silicon has been used in a number 8 of semiconductor devices, the most promising of which 9 is the PIN structure. Such devices were first fabri-cated by the method of glow discharge decomposition of 11 silane and described in a technical publication by 12 D. E. Carlson, J. Non-Crystalline, 35-36, tl980~
13 p. 707. The P and N layers in this method are 14 deposited by mixing approximately 1 to 2~ of B2H6 or PH3 in the silane discharge. The principal deficiency 16 of this device, as noted by Carlson, is that the P-17 layer which forms the major semiconductor junction 18 with the I-layer, is both poorly conductive and 19 absorbs the incident light energy without signifi-cantly contributing to the collection of photogener-21 ated charge carriers in the device. Because the 22 N-layer absorbs much less light than the P-layer, 23 Carlson has shown that illumination from the N-side 24 leads to higher solar cell efficiency.

A further improvement to the efficiency of 26 this device has been described in a technical publica-27 tion by Y. Uchida et al., Japanese Journal of Applied 28 Physics, _ , (1982) p~ L586. These authors fabricated 29 the N-layer by glow discharge decomposition of a mix-ture of SiH4-H2-p~3 and high power in the discharge.
31 Under these conditions, they claim that the N-layer is 1 partially crystallized (microcrystalline) and there-2 fore it is both highly conductive and highly trans-3 parent in the visible part of the spectrum~ This type 4 of N-layer is ideal as a "window" material and leads to a 13% improvement in the short-circuit current of 6 the solar cell. The devices reported by Uchida have 7 the configuration stainless steel/PIN/ITO with the P
8 and I~layers being amorphous and the N-layer being 9 microcrystalline~

PIN semiconductor devices have also been 11 fabricated by the method of reactive sputtering and 12 described in a technical publication by T. D.
13 Moustakas and R. Friedman, Appl. Phys. Lett~ 40, 14 (1982) p. 51S. The I-layer of these devices was fabri-cated by sputtering from an undoped silicon target in 16 an atmosphere of Argon containing 10-20~ H2. The P and 17 N-layers were fabricated by adding approximately 0.1 18 to 1% of B2H6 or PH3 in the Ar-H2 discharge. The 19 hydrogen content for the l'window" (P-layer) was increased to approximately 20 to 40% in order to im-21 prove its transparency to visible light. All three 22 layers (P, I, N) if this device are amorphous.

23 In view of the improvements of the solar 24 cell efficiency of PIN devices produced by glow dis-charge decomposition of silane employing a micro-26 crystalline N-contact as a "windowD layer, it is 27 important to fabricate such device~ by the method of 28 RF sputtering.

_ The invention is directed to a method for 31 depositing by RF sputtering an amorphous PIN Semi-32 conductor device, having the "window" (P or N) or both 4~

1 contacts deposited under conditions which lead to 2 partially crystallized (microcrystalline) material.
3 The method of the present invention shall be illus-4 trated and described w;th respect to a PIN device. It is to be understood~ however, that the method of the 6 present invention applies equally well to a NIP
7 device.

8 A microcrystalline N-layer is deposited by 9 RF sputtering from an undoped silicon target in an atmosphere containing hydrogen, argon and phosphine at 11 a total pressure larger than 20 mTorr with H2/Ar l 12 and phosphine content approximately 0.1 to 1% of the 13 argon content. The power in the discharge is adjusted 14 to lead to DC bias target voltage of between -800 to -2000 volts and the substrate temperature to between 16 200 to 400C. An intrinsic layer is also reactively 17 sputtered from an undoped target in an atmosphere of 5 18 to 15 mTorr of argon containing 10 to 20~ hydrogen.
19 The target voltage and the substrate temperature are the same as during the deposition of the N-layer. This 21 I-layer is amorphous. A microcrystalline P-layer is 22 reactively sputtered from an undoped silicon target in 23 an atmosphere containing hydrogen, argon and diborane 24 at a total pressure larger than 20 ~Torr with ~2/Ar l and diborane content approximately 0.1 to 1~ of the 26 argon content. The target voltage and the substrate 27 temperature vary in the same range as those of the N
28 and I-layers. The contact (P or N) which is deposited 29 on the top of the I-layer is preferably deposited at lower target voltage ( -800 volts) in order to avoid 31 surface damage of the I-layer. [The three layers are 32 deposited sequentially in three interlocked chambers 33 in order to avoid cross contamination between the 34 layers. If they are deposited in the same chamber the chamber has to be purged and sputtercleaned between _ 4 - ~2~
1 the first doped and the intrinsic layer.] Transparent 2 electrodes and metallic grids are also sputter de-3 posited which permits the entire deposition to be 4 accomplished in one sputtering apparatus and in one vacuum pump-down. When the P and N layers are fabri-6 cated in microcystalline form, the PIN sGlar cells 7 have an open circuit voltage of about 0.1 to 0.20 V
8 higher than entirely amorphous PIN solar cells and 10 9 to 20% higher short circuit current due to the better blue response of these solar cells~

12 Figure 1 shows a greatly enlarged side view 13 of a semi-conductor device constructed in accordance 14 ~ith the teaching of the present invention.

Figure 2 shows the I-V characteristics of a 16 sputtered PIN solar cell having microcrystalline P and 17 N layers.

18 Figure 3 shows the increase in the collec-19 tion efficiency in the blue portion of the spectrum of a PIN Cell by using a microcrystalline P-layer for the 21 front contact and a ~icrocrystalline N-layer as the 22 rear contact compared to one having a~orphous P-layer 23 and N-layer.

The sputtered amorphous silicon PIN device 26 of the present invention, as illustrated in Figure 1, 27 includes a substrate 10 which generally comprises a 28 physically supportive substrate for the overlying 29 sputter deposited layers. Substrate 10 includes a - 1 major area coating surface which is substantially free 2 from voids or protrusions of the order (in size) of 3 the thickness of the overlying layers to avoid pin 4 holes therethrough~

In one embodiment, substrate 10 may comprise 6 a non-electroconductive material such as glass or 7 ceramic for which an overlying layer of an electro-8 conductive material 11 is required. Alternately, sub-9 state 10 may comprise a metal concurrently serving as a supportive substrate and an electrode contact to the 11 overlying layers. In either instance, the coating ; 12 surface of the substrate is thoroughly cleaned to 13 remove unwanted contamination of the coating surface.
14 In a preferred embodiment, electrode 10 comprises a metal known to form an ohmic contact to N-doped sili-16 con such as molybdenum or stainless steel for example.
17 In the case where substate 10 comprises a nonelectro-18 conductive material it is preferred that layer 11 19 comprise a layer of metal known to form an ohmic con-tact to N-doped microcrystalline silicon; examples are 21 molybdenum or chromium thin films of approximately 22 1,000 to 2,000 ~ thick or a transparent conductive 23 oxide such as ITO, SnO2 or cadmium stannate approxima-24 tely 1000 ~ thick.

The substrates are fastened to the anode 26 electrode of a conventional RF diode sputtering unit 27 which is adapted to provide controlled partial pres-28 sures of hydrogen, argon, phosphine and diborane as 29 detailed hereinafter. The term secured is intended in this application to mean both the physical securing of 31 the substrate to the anode electrode and more impor-32 tantly the electrical contacting oE the conducting 33 coating surface to the anode electrode. In this manner 34 the coating surface is maintained at the approximate P

1 electrical potential of the anode electrode~ The anode 2 electrode is either electrically grounded or supplied 3 with a positive or negative bias of approximately ~50 4 volts. The sputtering system is further adapted to provide for controlled temperature heating of the 6 substrates. The deposition temperature as recited 7 hereinafter is measured by a thermocouple embedded in 8 the anode electrode.

9 It is to be recognized that the temperatures recited hereinafter are measured accordingly and the 11 actual temperature of the depositing film may differ.

12 ~he sputtering system is evacuated to a base 13 pressure of about 1 x 10~7 Torr by conventional 14 mechanical and turbomolecular pumping means. An 15 N-layer of hydrogenated microcrystalline silicon, 12, 16 is sputter deposited by first heating substrate to a 17 monitored temperature ranging from about 200C to 18 about 400C. A sputtering target comprising a poly-c-19 rystalline undoped silicon disc about 5" in diameter is secured to the cathode electrode being located 21 about 4.5 cm from the substrate platform tanode elec-22 trode). Consistent with the condition H2/Ar l and 23 total pressure > 20 mTorr, as described abo~e, the 24 sputtering atmosphere comprises a partial pressure of 25 hydrogen ranging from about~ 20 mTorr to about 80 mTorr 26 and argon ranging from about 3 mTorr to about 10 27 mTorr. For the best microcrystalline material, a pre-28 ferred combination of parameters should be H2/Ar > 10 29 and H2 + Ar > 40 mTorr. To dope the hydrogenated 30 microcrystalline silicon layer N an amount of phos-31 phine (PH3) is added to the partial pressures of hy-32 drogen and argon. In one embodiment, the argon source 33 contains 0.2 - 1 atomic % of phosphine. The sputtering 34 is accomplished at an RF power of about 100 to 200 - 7 ~
1 watts resul~ing in an induced DC bias of about -800 to 2 2000 volts relative to the electrically grounded 3 substrate platform (anode). The deposition rate of the 4 films depends on the relative amounts of H2 to Ar in the discharge. These conditions lead to deposition 6 rates between 10 to 40 2/sec. These lower deposition 7 rates of the microcrystalline material as compared to 8 amorphous material are caused by the higher concentra-9 tion of H2 which leads to the etching of the deposited film and thus competes with the deposition process of 11 siliconO The sputtered deposition continues for a time 12 ranging from a minimum of 2.5 min. to about 10 mins.
13 resulting in a thickness of N-layer, 12, ranging from 14 about 100 angstroms to about 400 angstroms. Alterna-tively, the N layer can be produced in a graded form 16 extending 500 to 1000 ~. This can be accomplished by 17 progressively reducing the amount of PH3 in the disch-18 arge. The substrate heating described heretofore con-19 tinues throughout the deposition to maintain the moni-tored substrate temperature within the indicated 21 range. This results in a proper level of hydrogenation 22 Of the depositing microcrystalline silicon which was 23 found to be about 3-4~ by unfrared spectroscopy.

24 An intrinsic layer of hydrogenated silicon 14 is sputter deposited from an undoped silicon target 26 in an atmosphere containing pure argon and hydrogen.
27 This layer 14 is amorphous. The sputtering atmosphere 28 for depositing the intrinsic layer ranges from about 3 29 mTorr to about 15 mTorr of pure argon and from about 0.3 mTorr to about 1.5 mTorr of hydrogen. The RF power 31 conditions, cathode and anode configuration, and sub-32 strate temperature are substantially identical to that 33 described for the sputter deposition of the N-layer.
34 Under these conditions, a layer of intrinsic amorphous
5~

1 silicon ranging from about 0.2 microns to about 1.5 2 microns in thickness is deposited at a rate ranging 3 from 60A/min to lOOOA/min.

4 A P-do~ed layer of hydrogenated microcrys-5 talline silicon 16 is sputtered deposited fro~ an
6 atmosphere of argon, hydrogen and diborane. Consistent
7 with the condition H2/Ar l and total pressure > 20
8 mTorr, as described above, a sputtering atmosphere
9 comprising argon and hydrogen having partial pressures ranging from about 3 mTorr to about 10 mTorr and about 11 20 mTorr to about 80 mTorr respectively, includes a 12 level of diborane dopant sufficient to dope the micro-13 crystalline silicon P-type. For the best microcrys-14 talline material, a preferred combination of param-eters should be H2/Ar > 10 and H2 + Ar > 40 mTorr. In 16 one embodiment, the argon source contains about 0.2 to 17 ~ atomic % of diborane (B2~6). The sputtering power 18 conditions, monitored substrate temperature ranges, 19 and con~iguration of the anode and cathode electrodes are substantially identical to those described for the 21 deposition of the N and I layers. The deposition rate 22 of the film depends on the relative amounts cf H and 23 Ar in the discharge. These conditions lead to deposi-24 tion rates of lOA/min to 40A/min. The thickness of the P-layer, as compared to the thickness of the intrinsic 26 and N-doped layers is smaller, ranging from about 80 27 to about 150 angstroms. As presently understood, the 28 P-layer functions to form a potential barier with the ~9 I-layer. The P and N layers fabricated according to the descriptions given above were found by X-ray and 31 Raman spectroscopy to be partially crystallized with 32 crystallite size of 50-60A. Furthermore, the index of 33 refraction of these P and N layers in the visible 34 spectral region are about 3.0 while that of the amor-phous silicon is about 4Ø The P and N layers were ~4 _ 9 _ 1 also found to be about one half an order of magnitude 2 less absorbing to visible light than the corresponding 3 amorphous layers. In addition, they have conductivi-4 ties between 1 and 10 (Qcm)~l while the corresponding 5 amorphous P and N layers have conductivities of 10-2 6 to 10-3 (~cm) 1 A current collection electrode 18, 7 comprises an electroconductive material which is semi-8 transparent in the spectral region ranging from about 9 3,500 angstroms to about 7,000 angstroms, which con-stitutes the principal absorption region of the under-11 lying amorphous silicon film layers. Further, elec-12 trode 18 must form a substantially ohmic contact to 13 the contiguous P-doped microcrystalline silicon. In 14 one embodiment, electrode 18 may comprise a semi-transparent conductive oxide such as indium tin oxide, tin oxide or cadmium stannate. In such an embodiment, 17 the thickness of the conductive oxide may be tailored 18 to provide an anti-reflection coating to the underly-19 ing amorphous silicon surface. These conductive oxides are deposited by RF sputtering from corresponding 21 targets. It is desirable that the oxide be deposited 22 on the solar cell at temperatur~s between 250 and 23 300C to anneal any induced sputtering damage on the 24 solar cell and to improve the sheet resistance which 25 was found to be about 50~/DThe index of refraction of 26 these oxides is about 2 to 2.2. Therefore, the index 27 o~ refraction of the P and N layers of about 3 is an 28 intermediate value between that of the oxide and that 29 of the I layers. This gradual transition of the in-dices of refraction is desirable for better collection 31 of light. In an alternative embodiment, electrode 18 32 may comprise a relatively thin metallic layer, also 33 being semitransparent and forming an ohmic contact to 34 P-doped microcrystalline silicon. An example is plat-inum.

`4t~:~S

1 To further assist in the collection of 2 current generated by the photovoltaic device, a grid 3 electrode 20 may be patterned on the surface of elec-4 trode 18. The electroconductive grid, generally con-5 figured to minimi~e the area of coverage and concur-6 rently minimize the series resistance of the photo-7 voltaic cell, may be constructed by several alternate 8 techniques well known in the art.

g Those skilled in the art recognize that the
10 use of a glass or other similarly transparent sub-
11 strate 10, having an transparent electroconductive
12 layer 11 (e~g. ITO or SnO2), permits illumination of
13 the device through the substrate. Furthermore, the
14 deposition sequence of P and N layers may be reversed to deposit a layer of P microcrystalline silicon onto 16 an ITO coated substrate, having the intrinsic and N
17 layers deposited thereupon.

18 It is to be recognized that the several 19 layers comprising the photovoltaic device described heretofore, may be accomplished by sputtering tech-21 niques facilitating the construction of this device in 22 a singular vacuum sputterîng unit and in a singular 23 vacuum pump down. It should further be recognized that 24 the sputtering techniques used in the construction of a photovoltaic device of the present invention result 26 in enhanced physical integrity and adherance of the 27 deposited films. The method manifests in an ability to 28 sputter deposit a layer of semi-transparent conductive 29 oxides such as indium tin oxide onto a relatively thin P doped layer, 16, without deteriorating the junction 31 forming characteristics of the underlying silicon 32 layers. Essentially the cell can be illuminated either ~s~s~

1 from the substrate side or the side opposite the sub-2 strate because of the superior properties of the 3 sputtered microcrystalline N and P layers.

Figure 2 shows the I-V characteristics of a 6 sputtered amorphous silicon PIN solar cell structures 7 employing microcrystalline P and N layers. Note that 8 the short circuit current in this device is 13mA/cm2 9 and the open circuit voltage is 0.86 volts. The sub-strate in this structure is mirror polished stainless 11 steel. This substrate was ultrasonically cleaned and 12 degreased before it was fastened to the anode elec-1~ trode of the previously described diode sputterinq 14 unit. The vacuum chamber was evacuated to a base pres-sure of 1 x 10-7 Torr and the substrate was heated to 16 325C. The three active layers of the device were 17 deposited under the conditions and order described 18 below:

19 The partially crystallized N-layer was depo-sited in an atmosphere of 40 mTorr of H2 ~ Ar + PH3.
21 The par~ial pressures of these gases were 36 mTorr of 22 hydrogen and 4 mTorr of argon. The phosphine was con-23 tained in the cylinder of argon at a concentration of 24 0.2 atomic %. Therefore, during the deposition of this layer the ratio of H2/Ar was much larger than one and 26 the total pressure was larger than 20 mTorr~ Both of 27 these condi~ions were found to be necessary for the 28 deposition of partially crystallized N-layer. The 29 polycrystalline undoped silicon target, 5" in di-ameter, was supplied with an RF power of 100 watts 31 leading to a target voltage of -1200 volts. The depo-32 sition lasted for 6 min. leading to a film of approxi-1 mately 200 ~ thick. As mentioned earlier this film has 2 a conductivity of about 10 (Q cm)~l and is far more 3 transparent than the corresponding amorphous N-layer.

4 At this point the substrate with the N-layer was transferred in another clean chamber for the depo-6 sition of the intrinsic I-layer. This layer was depo-7 sited in an atmosphere of 5 mTorr of Ar + H2. The 8 hydrogen content in this discharge was approximately 9 18% of the argon content. The 5" polycrystalline undoped silicon target was supplied with an RF power 11 of 80 watts leading to a bias voltage of -1000 volts.
12 The deposition for this layer lasted 60 min. leading 13 to an I-layer about 4000 ~ thick. The substrate 14 temperature during this deposition was maintained at 325C.

16 The partially crystallized P-layer was depo-17 sited next in an atmosphere of 40 mTorr of H2 + Ar 18 B2H6. The partial pressures of these gases wera 36 19 mTorr of hydrogen and 4 mTorr of argon. The ~2H6 was contained in the cylinder of argon at a concentration 21 of 0~2 atomic ~. Under these conditions the P-layer is 22 par~ially crystallized having a conductivity of about 23 2 tQ cm) 1 and high transparency. The polycrystalline 24 undoped silicon target, S~ in diameter, was supplied with an RF power of 60 watts, leading to a target 26 voltage of -800 volts~ The deposition of this layer 27 lasted for 3 min., leading to a P-layer of 100 28 thicknesS~

29 At this point-the substrate with the three active layers (N,I,P) was moved to another sputtering 31 chamber for the deposition of an ITO (Indium Tin 32 Oxide) layer on the top of the P-layer. This layer was 33 deposited from an ITO target in an atmosphere of I
13 ~ 54S~
l argon. The target voltage during this deposition was 2 maintained at -600 volts and the thickness of this 3 layer was chosen to be 600 to 700 ~ A metal grid 4 made of silver was deposited on the top of the ITO.

Claims (10)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE
IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method for producing an amorphous silicon PIN semi-conductor device having partially crystallized (microcrystalline) P and N-layers comprising:
providing a substrate having at least a surface region comprising an electroconductive material which forms an ohmic contact to doped microcrystalline silicon;
reactively RF diode sputtering a layer of microcrystalline silicon doped with one type of charge carrier in partial pressures of hydrogen ranging from about 20 mTorr to about 90 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr onto at least said surface region of the substrate;
reactively RF diode sputtering a layer of amorphous intrinsic, I, silicon onto said layer of silicon doped with said one type of charge carrier;
reactively RF diode sputtering a layer of microcrystalline silicon doped with the opposite type of charge carrier in partial pressures of hydrogen ranging from about 20 mTorr to about 90 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr onto said I layer;
sputtering an electroconductive material onto at least a region of said layer of microcrystalline silicon doped with said opposite type of charge carrier, which material forms an ohmic contact thereto.
2. The method of claim 1 wherein said one type of charge carrier is N
type and said opposite type of charge carrier is P type.
3. The method of claim 1 wherein said one type of charge carrier is P
type and said opposite type of charge carrier is N type.
4. The method of claim 2 or 3 wherein said reactive sputtering of N doped microcrystalline silicon comprises sputtering microcrystalline silicon in partial pressures of hydrogen, ranging from about 20 mTorr to about 80 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr, said partial pressure of argon including about 0.2 to 1 atomic % of phosphine (PH3).
5. The method of claim 2 or 3 wherein said reactive sputtering of N doped microcrystalline silicon comprises sputtering microcrystalline silicon from an undoped polycrystalline silicon target in partial pressures of hydrogen, ranging from about 20 mTorr to about 80 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr, said partial pressure of argon including about 0.2 to 1 atomic % of phosphine (PH3).
6. The method of claim 2 or 3 wherein said reactive sputtering of N doped microcrystalline silicon comprises sputtering microcrystalline silicon from an undoped polycrystalline silicon target in partial pressures of hydrogen, ranging from about 20 mTorr to about 80 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr, said partial pressure of argon including about 0.2 to 1 atomic % of phosphine (PH3), and wherein an RF sputtering power of about 100 watts to 200 watts is coupled to the plasma, resulting in a target dc voltage of about -800 volts to about -2000 volts.
7. The method of claim 2 or 3 wherein said reactive sputtering of N doped microcrystalline sili-con comprises sputtering microcrystalline silicon from an undoped polycrystalline silicon target in partial pressures of hydrogen, ranging from about 20 mTorr to about 80 mTorr, and argon ranging from about 3 mTorr to about 10 mTorr, said partial pressure of argon including about 0.2 to 1 atomic % of phosphine (PH3), and wherein an RF sput-tering power of about 100 watts to 200 watts is coupled to the plasma, resulting in a target dc vol-tage of about -800 volts to about -2000 volts.
8. The method of claim 2 or 3 wherein said reactive sputtering of the intrinsic, I, layer of silicon comprises sputtering silicon in partial pres-sures of hydrogen, ranging from about 0.3 mTorr to about 1.5 mTorr, and argon, ranging from about 3 mTorr to about 15 mTorr.
9. The method of claim 2 or 3 wherein said reactive sputtering of the P layer of microcrystalline silicon comprises sputtering microcrystalline silicon in partial pressures of hydrogen, ranging from about 20 mTorr to about 80 mTorr, and argon, ranging from about 3 mTorr to about 10 mTorr, said argon containing about 0.2 to 1 atomic % of diborane, B2H6.
10. The method of claim 2 or 3 wherein said electroconductive material, sputtered onto said P-doped microcrystalline silicon is a thin film of material selected from the group consisting of indium tin oxide, tin oxide or cadmium stannate.
CA000461877A 1983-09-26 1984-08-27 Method for sputtering a pin amorphous silicon semi- conductor device having partially crystallized p and n-layers Expired CA1215456A (en)

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