CA1212723A - System for transmitting digital information signals - Google Patents
System for transmitting digital information signalsInfo
- Publication number
- CA1212723A CA1212723A CA000420040A CA420040A CA1212723A CA 1212723 A CA1212723 A CA 1212723A CA 000420040 A CA000420040 A CA 000420040A CA 420040 A CA420040 A CA 420040A CA 1212723 A CA1212723 A CA 1212723A
- Authority
- CA
- Canada
- Prior art keywords
- word
- synchronizing
- frame
- circuit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
Abstract
ABSTRACT
In a system for transmitting digital information-signals, more particularly for digital sound-transmission through satellites, wherein a synchronizing word precedes the data-sequences, the data-sequence is divided into frames of equal length and each frame is divided into two part-frames.
Each part-frame comprises a synchronizing word of the same or equivalent type of equal length. A correlator is provided in each case for chronological recognition of the frame. Code-words are used for synchronization, the code-words comprising a definite maximum of autocorrelation function for the moment T = 0 and the autocorrelation function for all moments T ? 0 being quantita-tively minimal.
In a system for transmitting digital information-signals, more particularly for digital sound-transmission through satellites, wherein a synchronizing word precedes the data-sequences, the data-sequence is divided into frames of equal length and each frame is divided into two part-frames.
Each part-frame comprises a synchronizing word of the same or equivalent type of equal length. A correlator is provided in each case for chronological recognition of the frame. Code-words are used for synchronization, the code-words comprising a definite maximum of autocorrelation function for the moment T = 0 and the autocorrelation function for all moments T ? 0 being quantita-tively minimal.
Description
D ~r 4 ~
The invention relates to a system for transmitting digital information-signals, more particularly for digital transmission through satellites, wherein the data-sequences are arranged in a frame chronologically one after the other, a synchronizing word with several bits being transmitted at the start of a limited data-sequence.
In a bit-series data-transmission, the data-blocks, consisting of code-words, namely frames and possibly part-frames, are periodically repeated.
If the data-blocks are to be correctly decoded, the chronological position of the frame must be known. If self-synchronizing codes are used, the band-width of the transmission is increased by increased redundancy requirements. A so-called point-code prevents any appreciable increase in band-width. Especially in the case of a 4-phase CPSK modulation, data-regeneration is ensured by a point-code on the basis of the frame-structure.
In this connection, each transmission-block contains a prefixed code-word, the synchronizing word, serving to recognize synchronization. This is generally followed by a sequence of data-code-words which also contain testing information.
Time and amplitude-errors may arise in the transmission path under consideration. In timing regeneration, time-errors produce so-called bit-slips.
Amplitude-errors, i.e. bit-inversions, vitiate data and synchronizing words.
Where a 4-phase CPSK modulation is used, the ambiguity of phase-demodulation must be compensated for in the data-regeneration. The relevant literature (BARKER, MAURY~ discloses synchronizing words in which a small number of bit-errors in a synchronizing word do not impair unambiguous synchronizing-word recognition.
~lowever, known synchronizing words are not suitable for the purposes of the present inv~ntion, especially if time- and amplitude-errors occur simul-taneously.
- 1 - ~:
~,Z~
It is therefore the purpose of the invention to provide synchroniz-ing words for transmitting digital information-signals, by means of which recognition of the chronological position of the data-flow is improved and the influence of time-errors, amplitude-errors and phase-ambiguity can be compen-sated for.
According to a broad aspect of the invention there is providecl a system for transmitting and receiving digital information signals, particularly for digital sound transmission via satellites, wherein the data sequences are arranged in a frame chronologically behind one another and wherein in a receiver the frame is divided into time parallel part frames representing the data sequences, characterized in that each part frame comprises a synchronizing word of the same or equivalent type of equal length, that a correlator is used for each part frame for chronological recognition, that code words are used for synchronization, said code words comprising a definite maximum of their autocorrelation function for the moment T = O, and that the autocorrelation function for all moments T ~ O is quantitatively minimal.
Using the synchronizing words according to the invention makes it possible to recognize the chronological position of the frame with sufficient reliability. The synchronizing word is relatively short as compared with the length of the part-frame and the redundancy associated therewith is minimal.
The synchronizing words are selected in such a manner that a synchronization failure occurs much less frequently than an uncorrectable error in the formation, If the synchronizing words are to be recognized at the receiving end, the said words must be consldercd in a outstanding chronological position in correlators. The synchronizing words according to the invention contain, in the unshifted position of the autocorrelation function, i.e. for the moment T = O, a pronounced maximum. The autocorrelation function eor all moments T ~ O is quantitatively minimal.
72~
A CPSK modulation exhibits phase-ambiguity. This may lead to the synchronizing word reaching the receiver in the inverted position. The synch-ronizing words according to the invention therefore exhibit a very small difference between autocorrelation function and inverted autocorrelation func-tion. The synchronizing words may therefore also be reliably recognized in the inverted position.
The ambiguity in CPSK demodulation may be compensated for by evaluat-ing the correlation function, formed in the receiver, between the stored and the received synchronizing word. The chronological position of the beginning of the frame is determined by the result of the value determined in the correla-tor, and of a subsequent threshold-value logic, in that the control-signals derived from both correlators are fed to a logic circuit which is interrogated in a specific time-window.
For the purpose of correcting time-errors, which may lead to a bit-slip, it is proposed to check the cross-correlation function in a slightly widened time-window. In conjunction with the position of the maximum cross-correlation function within this time-window, an immediate conclusion can be drawn as to the appearance and magnitude of a bit-slip, and a correction can be made for the next frame. To this end, the cross-correlation function for the moment T = 0 must be quantitatively greater than that for the moment T ~ O, but this is possible only as far as a maximal number of bit-errors in the synchroniz-ing word. The longer the synchronizing word, the greater the maximal permissible number of bit-errors. A satisfactory compromise has been reached between the two requirements for less redundancy and greater residual-error probability.
In the case of a synchronizing word 16 bits in length, the synchroniz-ing words according to the invention make it possible to accept up to 3 bit-errors of any kind in one synchronizing word while still maintaining unambiguous synchronizing-word recognition. If the width of the window for checking the synchronizing word is more than 1 bit, it must be borne in mind that the synch-ronizing word can be impaired by bit-errors produced by the disturbed channel and adjacent data.
With the synchronizing words according to the invention, and a window-width of five timing pulses, bit-slips of up to ~ 2 timing steps can be recognized by a threshold-value logic and the chronological shift can be elimi-nated. In order to meet the criterion that synchronization failure must occur less frequently than it is predetermined by the maximal permissible residual-error-probability for uncorrectably impaired information, it is proposed that, with the main frame divided into two part-frames (bit-planes A and B), the same or an equivalent pattern of the same length be provided for synchronization in both part-frames. With one correlator for each part-frame A and B, both synch-ronizing words can be checked simultaneously, whereby the chronological position of the frame can be recognized and phase-demodulation eliminated. When this system for frame-synchronization is used, synchronization-errors occur only if both synchronizing words are distu-rbed by four bit-errors.
The invention is described hereinafter in greater detail in conjunc-tion with an e~ample of embodiment and the drawings attached hereto, wherein:
Figure 1 is a block circuit-diagram for evaluating the synchronizing words in part-frames A and B;
Figure 2 is a block circuit-diagram for determining the cross-correlation function;
Figure 3 is a bridge circuit;
Figure ~ is a table;
7~3 Figure 5 is a circuit for determining the position of the synchroniz-ing word;
Figure 6 is a sequence-control.
Figure 1 shows a block circui~ diagram for recognizing synchronizing words. The signal arriving at terminal 1 is fed to a 4-phase demodulator 2 ~CPSK). The data-flow is divided into two bit-planes A and B. Since the demodulation in CPSK demodulator 2 is ambiguous, signals A and B may appear inverted or non-inverted, i.e. there are two possibilities for each bit-plane.
The data from each bit-plane are passed to shift-registers 3,4. The cross-correlation function is formed in stages 5 and 6 by comparing the data read into shift-register 3,4 with the synchronizing word hard-wired by a circuit arrangement 44 ~Figure 2). Stages 5 and 6 are storage-modules which are divided into two parts. By adding the contents of the storage-addresses called up in adding stages 7,8, the respective value of the cross-correlation function can be determined. A subsequent threshold-value logic 9,lO ascertains, from the cross-correlation value fed in, whcther the sync-word, its inversion, or no sync-word has been received. The chronological position of the synchronizing word is determined in stage 11 and the internal frame-pulse is adjusted if necessary. It can also be determined whether part-data-flows A and B have been received in the inverted, non-inverted and/or transposed position. The part-data-flows are corrected if necessary by means of bridge-circuit 12.
~igure 2 is a circuit diagram for determining the cross-correlation function. The data-flow passes from terminal 13 in series into shift-register 3. A sequence of 16 bits lies at each of the parallel outputs from shift-register 3. 8 bits at a time from the data-word lying at the parallel outputs from shift-register 3 are compared, through an exclusive OR-gate 47 - 49, 50 -52, with the corresponding part-code-word of the synchronizing word. The out-~A.2~P;~
puts from the exclusive OR-gate are passed to a PROM (= programmable read-only memory) 14,15. The data-pattern lying in each case at the eight outputs from exclusive OR-gates 47 - 40, 50 - 52 provides an address in PROM-circuit 14 or 15. The contents of the PROM-circuit storage positions called up are passed to an adder 7. Depending upon the code-word lying at the outputs from shift-register 3, specific addresses are called up in PROM-circuits 14,15. These call up a binary-coded storage content between - 4 and -~ 4 corresponding to the relevant number of matches. The addition in adder 7 gives the value of the cross-correlation func~ion (- 8 to ~ 8). The two highest-order bits of the storage contents lying at the outputs from PROM-circuits 14,15 are passed to an exclusive OR-gate 16. The output from exclusive OR-gate 16, and the highest-order position of the output from adder 7, lead to another exclusive OR-gate 17, the output from which represents the highest-order bit of the cross-correlation value in the two's complement lying at the output from adder 7. The output from adder 7, together with the output from exclusive OR-gate 17, constitutes the ascertained value of the cross-correlation function represented in the two's complement.
In this connection, the output signal from exclusive OR-gate 17 is the highest-order bit and thus represents the sign of the cross-correlation function.
A further PROM-circuit 18 is activated by the values at the output from adder 7 and from exc]usive OR-gate 17.
If the address-code-words lying at PROM-circuit 18 quantitatively exceed, in their significance, a predetermined threshold, the storage positions pertaining thereto are identified with a logic "1". A called-up storage-content logic "1", released from terminal 19, indicates recognition of a synchronizing word. Whether the position is inverted or non-inverted is shown at the status of terminal 22.
7~3 Figure 3 shows a bridge circuit controlled by signals E and F at terminals 22,23.
Signals E and F arrive from the correlators for bit-planes A and B
and correspond to the relevant highest-order bits in the A and B correlation-signal. The circuit according to Figure 3 has the following structure:
C = (E.F+E.F) . (A.E-~A.E~ + (E-~+F-E) (B-F~B-F) D = (E.F+E.F) . (B.F+B.F) ~ (E.F~E.F) (A-F+A-F) Output signals C and D at terminals 2~ and 25 of the bridge-circuit according to Figure 3 are produced in the case of an input-signal A and B at terminal 20 and 21, depending upon the control-information at terminal 22 and 23. This circuit permits two data-flows to be either transposed and/or inverted (see Figure ~).
Figure 5 shows a circuit for recognizing the position of the synch-ronizing pattern in the frame. Signals from the storage-positions in a PROM-circuit 18, as shown in Figure 2, are passed to terminals 19 and 27. A shift-register 28, 29 is provided for each part-frame. Shift-registers 28, 29 each contain 5 bit-positions, to the average values of which an AND-gate 30 is con-nected. Also present are "strobe"-inputs 31,32. Parallel outputs from shift-registers 28,29 run to a 102~ x ~ PROM-circuit 33. The content of the addressed storage-positions in PROM-circuit 33 passes to an adder 3~ to which counter-states from a pre-programmable frame-counter 26,36 are also passed. In the example shown, each counter counts up to an address 320. As soon as the counter has reached its end-address, a pulse is fed to load-input 37 thereof and the counter is set back again to the pre-programmable starting state.
A signal is fed to restart-input 39 for initial search of the frame-timing, the said signal resetting counter 36. At the same time, strobe-inputs 31,32 and shift-registers 28,29 are addressed through OR-gate 40. Since the outputs from shift-registers 28,29 run to PROM-circuit 33, a specific address in that circuit is addressed each time. The outputs from the correlator threshold-value logic in bit-planes A and B are connected, through terminals l9 and 27, to the series inputs to shift-registers 28 and 29.
The position of the time-window, obtained from the sequence-control lies at terminal 38. It is passed through STROBE-gate 40 to strobe-inputs 31,32.
The information read into shift registers 28,29, after 5 timing pulses appear in the time-window, is then evaluated with the aid of the content of PROM-circuit 33. The content of the stora~e-position of the address called up tells adder 34 how far the present timing pulse is from the frame-timing.
Located in the nominal position of the synchronization pulse is the pulse in the central cells of shift-registers 28,29. A pulse is released to terminal 41 through AND-gate 30 connected thereto. A pulse is passed, through terminal 39, to load-input 37 through a connected evaluation logic shown in Figure 6.
Counter 36 thus begins to count again. If the nominal position is not reached, e.g. through a bit-slip, the total in counter 36 is altered by calling up another address in PROM-circuit 33. This causes the clock-synchronization of the frame to shift correctly.
Figure 6 shows an evaluation logic for controlling ~he sequence of the search-and-hold procedure. Positional information regarding the synchroniz-ing word is passed to terminals 22,23 from the two part-frames A and B. As soon as the synchronizing word is in its correct chronological position, input terminal 31 receives a pulse from AWD-gate 30. The search-mode is initiated by a state-change to logic 1 at terminal 38 leading to OR-gate 40. ~ pulse at ~L2~ 3 terminal 39 passes, through an OR-gate, to load-input 37 of counter 36 and restarts frame-counter 36. The signal at load-input 37 also represents the frame-timing.
PROM~circuit 33 passes a pulse to terminal 43 only if no synchroniz-ing word is found. The pulse at termi.nal 43 passes to an OR-gate 45 to terminal 46 of which a pulse may be passed in order to initialize the whole circuit for the ~irst time. PROM-circuits 18 in the circuit according to ~igure 2 for both part-frames appear at terminal 42, so that the threshold values for the cross-correlation function~ obtained with the aid of PROM-circuits 18, may be switched over.
The invention relates to a system for transmitting digital information-signals, more particularly for digital transmission through satellites, wherein the data-sequences are arranged in a frame chronologically one after the other, a synchronizing word with several bits being transmitted at the start of a limited data-sequence.
In a bit-series data-transmission, the data-blocks, consisting of code-words, namely frames and possibly part-frames, are periodically repeated.
If the data-blocks are to be correctly decoded, the chronological position of the frame must be known. If self-synchronizing codes are used, the band-width of the transmission is increased by increased redundancy requirements. A so-called point-code prevents any appreciable increase in band-width. Especially in the case of a 4-phase CPSK modulation, data-regeneration is ensured by a point-code on the basis of the frame-structure.
In this connection, each transmission-block contains a prefixed code-word, the synchronizing word, serving to recognize synchronization. This is generally followed by a sequence of data-code-words which also contain testing information.
Time and amplitude-errors may arise in the transmission path under consideration. In timing regeneration, time-errors produce so-called bit-slips.
Amplitude-errors, i.e. bit-inversions, vitiate data and synchronizing words.
Where a 4-phase CPSK modulation is used, the ambiguity of phase-demodulation must be compensated for in the data-regeneration. The relevant literature (BARKER, MAURY~ discloses synchronizing words in which a small number of bit-errors in a synchronizing word do not impair unambiguous synchronizing-word recognition.
~lowever, known synchronizing words are not suitable for the purposes of the present inv~ntion, especially if time- and amplitude-errors occur simul-taneously.
- 1 - ~:
~,Z~
It is therefore the purpose of the invention to provide synchroniz-ing words for transmitting digital information-signals, by means of which recognition of the chronological position of the data-flow is improved and the influence of time-errors, amplitude-errors and phase-ambiguity can be compen-sated for.
According to a broad aspect of the invention there is providecl a system for transmitting and receiving digital information signals, particularly for digital sound transmission via satellites, wherein the data sequences are arranged in a frame chronologically behind one another and wherein in a receiver the frame is divided into time parallel part frames representing the data sequences, characterized in that each part frame comprises a synchronizing word of the same or equivalent type of equal length, that a correlator is used for each part frame for chronological recognition, that code words are used for synchronization, said code words comprising a definite maximum of their autocorrelation function for the moment T = O, and that the autocorrelation function for all moments T ~ O is quantitatively minimal.
Using the synchronizing words according to the invention makes it possible to recognize the chronological position of the frame with sufficient reliability. The synchronizing word is relatively short as compared with the length of the part-frame and the redundancy associated therewith is minimal.
The synchronizing words are selected in such a manner that a synchronization failure occurs much less frequently than an uncorrectable error in the formation, If the synchronizing words are to be recognized at the receiving end, the said words must be consldercd in a outstanding chronological position in correlators. The synchronizing words according to the invention contain, in the unshifted position of the autocorrelation function, i.e. for the moment T = O, a pronounced maximum. The autocorrelation function eor all moments T ~ O is quantitatively minimal.
72~
A CPSK modulation exhibits phase-ambiguity. This may lead to the synchronizing word reaching the receiver in the inverted position. The synch-ronizing words according to the invention therefore exhibit a very small difference between autocorrelation function and inverted autocorrelation func-tion. The synchronizing words may therefore also be reliably recognized in the inverted position.
The ambiguity in CPSK demodulation may be compensated for by evaluat-ing the correlation function, formed in the receiver, between the stored and the received synchronizing word. The chronological position of the beginning of the frame is determined by the result of the value determined in the correla-tor, and of a subsequent threshold-value logic, in that the control-signals derived from both correlators are fed to a logic circuit which is interrogated in a specific time-window.
For the purpose of correcting time-errors, which may lead to a bit-slip, it is proposed to check the cross-correlation function in a slightly widened time-window. In conjunction with the position of the maximum cross-correlation function within this time-window, an immediate conclusion can be drawn as to the appearance and magnitude of a bit-slip, and a correction can be made for the next frame. To this end, the cross-correlation function for the moment T = 0 must be quantitatively greater than that for the moment T ~ O, but this is possible only as far as a maximal number of bit-errors in the synchroniz-ing word. The longer the synchronizing word, the greater the maximal permissible number of bit-errors. A satisfactory compromise has been reached between the two requirements for less redundancy and greater residual-error probability.
In the case of a synchronizing word 16 bits in length, the synchroniz-ing words according to the invention make it possible to accept up to 3 bit-errors of any kind in one synchronizing word while still maintaining unambiguous synchronizing-word recognition. If the width of the window for checking the synchronizing word is more than 1 bit, it must be borne in mind that the synch-ronizing word can be impaired by bit-errors produced by the disturbed channel and adjacent data.
With the synchronizing words according to the invention, and a window-width of five timing pulses, bit-slips of up to ~ 2 timing steps can be recognized by a threshold-value logic and the chronological shift can be elimi-nated. In order to meet the criterion that synchronization failure must occur less frequently than it is predetermined by the maximal permissible residual-error-probability for uncorrectably impaired information, it is proposed that, with the main frame divided into two part-frames (bit-planes A and B), the same or an equivalent pattern of the same length be provided for synchronization in both part-frames. With one correlator for each part-frame A and B, both synch-ronizing words can be checked simultaneously, whereby the chronological position of the frame can be recognized and phase-demodulation eliminated. When this system for frame-synchronization is used, synchronization-errors occur only if both synchronizing words are distu-rbed by four bit-errors.
The invention is described hereinafter in greater detail in conjunc-tion with an e~ample of embodiment and the drawings attached hereto, wherein:
Figure 1 is a block circuit-diagram for evaluating the synchronizing words in part-frames A and B;
Figure 2 is a block circuit-diagram for determining the cross-correlation function;
Figure 3 is a bridge circuit;
Figure ~ is a table;
7~3 Figure 5 is a circuit for determining the position of the synchroniz-ing word;
Figure 6 is a sequence-control.
Figure 1 shows a block circui~ diagram for recognizing synchronizing words. The signal arriving at terminal 1 is fed to a 4-phase demodulator 2 ~CPSK). The data-flow is divided into two bit-planes A and B. Since the demodulation in CPSK demodulator 2 is ambiguous, signals A and B may appear inverted or non-inverted, i.e. there are two possibilities for each bit-plane.
The data from each bit-plane are passed to shift-registers 3,4. The cross-correlation function is formed in stages 5 and 6 by comparing the data read into shift-register 3,4 with the synchronizing word hard-wired by a circuit arrangement 44 ~Figure 2). Stages 5 and 6 are storage-modules which are divided into two parts. By adding the contents of the storage-addresses called up in adding stages 7,8, the respective value of the cross-correlation function can be determined. A subsequent threshold-value logic 9,lO ascertains, from the cross-correlation value fed in, whcther the sync-word, its inversion, or no sync-word has been received. The chronological position of the synchronizing word is determined in stage 11 and the internal frame-pulse is adjusted if necessary. It can also be determined whether part-data-flows A and B have been received in the inverted, non-inverted and/or transposed position. The part-data-flows are corrected if necessary by means of bridge-circuit 12.
~igure 2 is a circuit diagram for determining the cross-correlation function. The data-flow passes from terminal 13 in series into shift-register 3. A sequence of 16 bits lies at each of the parallel outputs from shift-register 3. 8 bits at a time from the data-word lying at the parallel outputs from shift-register 3 are compared, through an exclusive OR-gate 47 - 49, 50 -52, with the corresponding part-code-word of the synchronizing word. The out-~A.2~P;~
puts from the exclusive OR-gate are passed to a PROM (= programmable read-only memory) 14,15. The data-pattern lying in each case at the eight outputs from exclusive OR-gates 47 - 40, 50 - 52 provides an address in PROM-circuit 14 or 15. The contents of the PROM-circuit storage positions called up are passed to an adder 7. Depending upon the code-word lying at the outputs from shift-register 3, specific addresses are called up in PROM-circuits 14,15. These call up a binary-coded storage content between - 4 and -~ 4 corresponding to the relevant number of matches. The addition in adder 7 gives the value of the cross-correlation func~ion (- 8 to ~ 8). The two highest-order bits of the storage contents lying at the outputs from PROM-circuits 14,15 are passed to an exclusive OR-gate 16. The output from exclusive OR-gate 16, and the highest-order position of the output from adder 7, lead to another exclusive OR-gate 17, the output from which represents the highest-order bit of the cross-correlation value in the two's complement lying at the output from adder 7. The output from adder 7, together with the output from exclusive OR-gate 17, constitutes the ascertained value of the cross-correlation function represented in the two's complement.
In this connection, the output signal from exclusive OR-gate 17 is the highest-order bit and thus represents the sign of the cross-correlation function.
A further PROM-circuit 18 is activated by the values at the output from adder 7 and from exc]usive OR-gate 17.
If the address-code-words lying at PROM-circuit 18 quantitatively exceed, in their significance, a predetermined threshold, the storage positions pertaining thereto are identified with a logic "1". A called-up storage-content logic "1", released from terminal 19, indicates recognition of a synchronizing word. Whether the position is inverted or non-inverted is shown at the status of terminal 22.
7~3 Figure 3 shows a bridge circuit controlled by signals E and F at terminals 22,23.
Signals E and F arrive from the correlators for bit-planes A and B
and correspond to the relevant highest-order bits in the A and B correlation-signal. The circuit according to Figure 3 has the following structure:
C = (E.F+E.F) . (A.E-~A.E~ + (E-~+F-E) (B-F~B-F) D = (E.F+E.F) . (B.F+B.F) ~ (E.F~E.F) (A-F+A-F) Output signals C and D at terminals 2~ and 25 of the bridge-circuit according to Figure 3 are produced in the case of an input-signal A and B at terminal 20 and 21, depending upon the control-information at terminal 22 and 23. This circuit permits two data-flows to be either transposed and/or inverted (see Figure ~).
Figure 5 shows a circuit for recognizing the position of the synch-ronizing pattern in the frame. Signals from the storage-positions in a PROM-circuit 18, as shown in Figure 2, are passed to terminals 19 and 27. A shift-register 28, 29 is provided for each part-frame. Shift-registers 28, 29 each contain 5 bit-positions, to the average values of which an AND-gate 30 is con-nected. Also present are "strobe"-inputs 31,32. Parallel outputs from shift-registers 28,29 run to a 102~ x ~ PROM-circuit 33. The content of the addressed storage-positions in PROM-circuit 33 passes to an adder 3~ to which counter-states from a pre-programmable frame-counter 26,36 are also passed. In the example shown, each counter counts up to an address 320. As soon as the counter has reached its end-address, a pulse is fed to load-input 37 thereof and the counter is set back again to the pre-programmable starting state.
A signal is fed to restart-input 39 for initial search of the frame-timing, the said signal resetting counter 36. At the same time, strobe-inputs 31,32 and shift-registers 28,29 are addressed through OR-gate 40. Since the outputs from shift-registers 28,29 run to PROM-circuit 33, a specific address in that circuit is addressed each time. The outputs from the correlator threshold-value logic in bit-planes A and B are connected, through terminals l9 and 27, to the series inputs to shift-registers 28 and 29.
The position of the time-window, obtained from the sequence-control lies at terminal 38. It is passed through STROBE-gate 40 to strobe-inputs 31,32.
The information read into shift registers 28,29, after 5 timing pulses appear in the time-window, is then evaluated with the aid of the content of PROM-circuit 33. The content of the stora~e-position of the address called up tells adder 34 how far the present timing pulse is from the frame-timing.
Located in the nominal position of the synchronization pulse is the pulse in the central cells of shift-registers 28,29. A pulse is released to terminal 41 through AND-gate 30 connected thereto. A pulse is passed, through terminal 39, to load-input 37 through a connected evaluation logic shown in Figure 6.
Counter 36 thus begins to count again. If the nominal position is not reached, e.g. through a bit-slip, the total in counter 36 is altered by calling up another address in PROM-circuit 33. This causes the clock-synchronization of the frame to shift correctly.
Figure 6 shows an evaluation logic for controlling ~he sequence of the search-and-hold procedure. Positional information regarding the synchroniz-ing word is passed to terminals 22,23 from the two part-frames A and B. As soon as the synchronizing word is in its correct chronological position, input terminal 31 receives a pulse from AWD-gate 30. The search-mode is initiated by a state-change to logic 1 at terminal 38 leading to OR-gate 40. ~ pulse at ~L2~ 3 terminal 39 passes, through an OR-gate, to load-input 37 of counter 36 and restarts frame-counter 36. The signal at load-input 37 also represents the frame-timing.
PROM~circuit 33 passes a pulse to terminal 43 only if no synchroniz-ing word is found. The pulse at termi.nal 43 passes to an OR-gate 45 to terminal 46 of which a pulse may be passed in order to initialize the whole circuit for the ~irst time. PROM-circuits 18 in the circuit according to ~igure 2 for both part-frames appear at terminal 42, so that the threshold values for the cross-correlation function~ obtained with the aid of PROM-circuits 18, may be switched over.
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A system for transmitting and receiving digital information signals, particularly for digital sound transmission via satellites, wherein the data sequences are arranged in a frame chronologically behind one another and wherein in a receiver the frame is divided into time parallel part frames representing the data sequences, characterized in that each part frame comprises a synchronizing word of the same or equivalent type of equal length, that a correlator is used for each part frame for chronological recognition, that code words are used for synchronization, said code words comprising a de-finite maximum of their autocorrelation function for the moment T = 0, and that the autocorrelation function for all moments T ? 0 is quantitatively minimal.
2. A system according to claim 1, characterized in that the correlator is also used for compensation of the phase positions of the part frames.
3. A system according to claim 1, characterized in that one of the following synchronizing words, the inversion, reflection, or inverted reflec-tion thereof is used, wherein 0 represents logic 0 and 1 represents logic 1:
1. 0110100001110111 3. 0100100010001111 4. 0100010010111100
1. 0110100001110111 3. 0100100010001111 4. 0100010010111100
4. A system according to claim 1, characterized in that a circuit arrangement is present for recognizing the chronological position of the synch-ronizing word and for correcting the chronological position of the frame.
5. A system according to claim 1, characterized in that a circuit for transposing the incoming data-flows is provided and is controlled by a synch-ronizing-word-recognition circuit.
6. A system according to claim 1, characterized in that for the purpose of initial or subsequent determination of the synchronization state, the presence of the synchronizing word is checked twice.
7. A system according to claim 1, characterized in that two operating states are provided, in one of which the presence of the synchronizing pattern is checked twice, and in that, if the synchronizing pattern is recognized, a change-over is made to the second operating state, in which the phase-position of the data-sequence is checked to ? 2 bit-timings in the normal state, a chronological correction being made directly in the next frame in the event of any deviation from the normal state.
8. A system according to claim 1, characterized in that, in order to determine the synchronizing word, two storage-modules are used, outputs there-from giving, through an adding circuit, the value of the cross-correlation between the agreed and the received synchronizing word.
9. A circuit according to claim 1, characterized in that a threshold-value logic is present and contains a storage-module in which an address is associated with each cross-correlation value, the representative value for the states: sync-word present, inverted sync-word present, and no sync-word present, being stored under the said address.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3201934A DE3201934A1 (en) | 1982-01-22 | 1982-01-22 | SYSTEM FOR TRANSMITTING DIGITAL INFORMATION SIGNALS |
| DEP3201934.3 | 1982-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1212723A true CA1212723A (en) | 1986-10-14 |
Family
ID=6153660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000420040A Expired CA1212723A (en) | 1982-01-22 | 1983-01-21 | System for transmitting digital information signals |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0084787B1 (en) |
| JP (1) | JPS58131767A (en) |
| AT (1) | ATE19450T1 (en) |
| CA (1) | CA1212723A (en) |
| DE (2) | DE3201934A1 (en) |
| DK (1) | DK161234C (en) |
| NO (1) | NO161350C (en) |
| SG (1) | SG64788G (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993020627A1 (en) * | 1992-03-31 | 1993-10-14 | The Commonwealth Of Australia | Demultiplexer synchroniser |
| US5899931A (en) * | 1996-06-04 | 1999-05-04 | Ela Medical S.A. | Synchronous telemetry transmission between a programmer and an autonomous device |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6038957A (en) * | 1983-08-11 | 1985-02-28 | Nec Corp | Elimination circuit of phase uncertainty of four-phase psk wave |
| DE3333714A1 (en) * | 1983-09-17 | 1985-04-04 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | CIRCUIT ARRANGEMENT FOR FRAME AND PHASE SYNCHRONIZATION OF A RECEIVING SAMPLE CLOCK |
| FR2568073B1 (en) * | 1984-07-20 | 1990-10-05 | Telecommunications Sa | DEVICE FOR LOSS AND RESUMPTION OF FRAME LOCK FOR A DIGITAL SIGNAL. |
| DE3500363A1 (en) * | 1985-01-08 | 1986-07-10 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Arrangement for the synchronisation of a digital data receiver |
| JPH0681131B2 (en) * | 1985-12-28 | 1994-10-12 | ソニー株式会社 | Sync detection circuit for digital broadcasting receiver |
| NZ220548A (en) * | 1986-06-18 | 1990-05-28 | Fujitsu Ltd | Tdm frame synchronising circuit |
| US4808937A (en) * | 1986-07-15 | 1989-02-28 | Hayes Microcomputer Products, Inc. | Phase-locked loop for a modem |
| EP0343189B1 (en) * | 1987-02-02 | 1993-10-27 | Motorola, Inc. | Tdma communications system with adaptive equalization |
| DE3719659A1 (en) * | 1987-06-12 | 1988-12-29 | Standard Elektrik Lorenz Ag | DEVICE FOR FAST FRAME AND PHASE SYNCHRONIZATION |
| US4912706A (en) * | 1988-11-18 | 1990-03-27 | American Telephone And Telegraph Company | Frame synchronization in a network of time multiplexed optical space switches |
| IT1256471B (en) * | 1992-12-10 | 1995-12-07 | Italtel Spa | METHOD FOR ACQUISITION OF SYNCHRONISM BETWEEN STATIONARY STATION AND PORTABLE TELEPHONE IN A DIGITAL CORDLESS TELEPHONE SYSTEM |
| SE514809C2 (en) * | 1994-07-13 | 2001-04-30 | Hd Divine Ab | Method and apparatus for synchronizing transmitters and receivers in digital system |
| DE102011122978B3 (en) | 2011-05-17 | 2022-01-13 | Rohde & Schwarz GmbH & Co. Kommanditgesellschaft | Method and device for determining demodulation parameters of a communication signal |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4968606A (en) * | 1972-11-06 | 1974-07-03 | ||
| US3879580A (en) * | 1972-11-24 | 1975-04-22 | Hughes Aircraft Co | Data terminal for use with TDMA processing repeater |
| DE2653968A1 (en) * | 1976-11-27 | 1978-06-01 | Licentia Gmbh | Data correlation system for comparing parallel and serial data - has switched shift register with subtraction and adder stages |
| JPS5853810B2 (en) * | 1977-09-30 | 1983-12-01 | 富士通株式会社 | Retraction phase identification method |
| DE2811851C2 (en) * | 1978-03-17 | 1980-03-27 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Method for frame synchronization of a time division multiplex system |
| JPS55135450A (en) * | 1979-04-10 | 1980-10-22 | Mitsubishi Electric Corp | Synchronous signal formation for digital transmission signal |
-
1982
- 1982-01-22 DE DE3201934A patent/DE3201934A1/en not_active Withdrawn
-
1983
- 1983-01-08 AT AT83100125T patent/ATE19450T1/en not_active IP Right Cessation
- 1983-01-08 EP EP83100125A patent/EP0084787B1/en not_active Expired
- 1983-01-08 DE DE8383100125T patent/DE3363107D1/en not_active Expired
- 1983-01-18 DK DK019183A patent/DK161234C/en not_active IP Right Cessation
- 1983-01-20 JP JP58006741A patent/JPS58131767A/en active Pending
- 1983-01-21 CA CA000420040A patent/CA1212723A/en not_active Expired
- 1983-01-21 NO NO830204A patent/NO161350C/en unknown
-
1988
- 1988-09-29 SG SG647/88A patent/SG64788G/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993020627A1 (en) * | 1992-03-31 | 1993-10-14 | The Commonwealth Of Australia | Demultiplexer synchroniser |
| US5539751A (en) * | 1992-03-31 | 1996-07-23 | The Commonwealth Of Australia Of C/-The Secretary Of Defence | Demultiplexer synchronizer |
| US5899931A (en) * | 1996-06-04 | 1999-05-04 | Ela Medical S.A. | Synchronous telemetry transmission between a programmer and an autonomous device |
Also Published As
| Publication number | Publication date |
|---|---|
| ATE19450T1 (en) | 1986-05-15 |
| DK19183A (en) | 1983-07-23 |
| NO161350C (en) | 1989-08-02 |
| NO161350B (en) | 1989-04-24 |
| DK161234B (en) | 1991-06-10 |
| DE3363107D1 (en) | 1986-05-28 |
| DE3201934A1 (en) | 1983-08-04 |
| EP0084787A1 (en) | 1983-08-03 |
| DK19183D0 (en) | 1983-01-18 |
| DK161234C (en) | 1991-11-25 |
| EP0084787B1 (en) | 1986-04-23 |
| NO830204L (en) | 1983-07-25 |
| SG64788G (en) | 1989-04-14 |
| JPS58131767A (en) | 1983-08-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |