CA1207393A - Battery saver for a paging receiver or the like - Google Patents
Battery saver for a paging receiver or the likeInfo
- Publication number
- CA1207393A CA1207393A CA000429101A CA429101A CA1207393A CA 1207393 A CA1207393 A CA 1207393A CA 000429101 A CA000429101 A CA 000429101A CA 429101 A CA429101 A CA 429101A CA 1207393 A CA1207393 A CA 1207393A
- Authority
- CA
- Canada
- Prior art keywords
- digital
- code
- control signal
- bit
- predetermined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004044 response Effects 0.000 claims abstract description 17
- 238000001514 detection method Methods 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000007864 suspending Methods 0.000 claims description 5
- 230000000875 corresponding effect Effects 0.000 claims 2
- 229920000136 polysorbate Polymers 0.000 claims 2
- 230000003252 repetitive effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B5/00—Near-field transmission systems, e.g. inductive loop type
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
- H04W52/0283—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
- H04W88/022—Selective call receivers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
ABSTRACT
There is provided a battery saving circuit for use in a portable radio communication apparatus. The circuit comprises a receiver section for receiving a carrier wave which is modulated with a preamble and a subscriber identification signal, a power supply for supplying power to the receiver section in response to a first control signal and a decoder responsive to the output of the receiver section for detecting the received preamble and the received identification signal and selectively providing the first control signal to the power supply. The decoder periodically begins the provision of the first control signal to the power supply means, suspends the provision of the first control signal in response to a second control signal, continues provision of the first control signal in response to a third control signal, immediately produces the second control signal in the absence of the preamble signal, and produces the third control signal for a first predetermined period of time in response to detection of the preamble signal. The invention improves battery saving efficiency and avoids erroneous operation due to noise.
There is provided a battery saving circuit for use in a portable radio communication apparatus. The circuit comprises a receiver section for receiving a carrier wave which is modulated with a preamble and a subscriber identification signal, a power supply for supplying power to the receiver section in response to a first control signal and a decoder responsive to the output of the receiver section for detecting the received preamble and the received identification signal and selectively providing the first control signal to the power supply. The decoder periodically begins the provision of the first control signal to the power supply means, suspends the provision of the first control signal in response to a second control signal, continues provision of the first control signal in response to a third control signal, immediately produces the second control signal in the absence of the preamble signal, and produces the third control signal for a first predetermined period of time in response to detection of the preamble signal. The invention improves battery saving efficiency and avoids erroneous operation due to noise.
Description
'739~3 BATTERY SAVER FOR ~ PAGING RECEIVER OR THE LIKE
BACKGROUND OF THE INVENTION
The present invention relates to a battery saving circuit circuit for use in a communication apparatus, such as a portable pager receiver.
In communication apparatuses including ~obile radio units, for instance, a radio paging receiver, there is used the so-called battery saving system, which periodically supplies and cuts off power to their receiver sections with a view to saving power consumption.
For instance, a transmitted signal in a paging system contains a preamble signal preceding a plurality of subscriber identification (ID) signals so that the receiver can he placed in a bat~ery saving mode. The receiver, periodically repeating turning on and off the power supply, receives 1~ signals during each time period (Tonl) that the power is on and does during each time period (Toff) that the power is off. If a preamble signal is detected during Tonl, the ensuing time period of "power on" (Ton2) will be extended to receive the subscriber ID signal that is to follow.
In this system, since the preamble signal is detected only once, erroneous operation may be caused by noise or same other signal, resulting in low reliability. Moreover, the erroneous detection of the preamble signal deteriorates the battery saving efficiency because erroneous detection . ~
~LZ~73~3 unnecessarily extends the power-on time period (Tonl).
One example of battery saving system.s to eliminate the foregoing disadvantages is disclosed in the United States Patent No. 4,181,893, issued to E.L. Ehmke January 1, 1980. According to this battery saving system, the receiver, to detect the ID
signal, extends power supply to the receiver section in response to the multi-detection of the preamble signal. This multi-detec-tion prevents the receiver from causing erroneous operation, improving the battery saving efficiency.
To carry out the first detection of the preamble, how-ever, this battery saving system supplies power to the receiver section for a prescribed period of time regardless of the result of the flrst detection of the preamb:Le signal. Therefore, this system yet has a disadvantage of lower battery saving efficiency.
S~MMAR~ OF THE INVENTION
An object of the present invention~ therefore, is to pro-vide a battery saving circuit which ~31iminates the foregoing disadvantages and Eurther improves the efficiency of battery saving.
~ccording to one aspect of the present invention, there is provided a battery saving circuit for use in a portable radio communication apparatus, said apparatus including receiver sec-tion means for receiving a carrier wave which is modulated with a digital preamble and a digital identification code, and power supply means for supplying power to said receiver section means in response to a first control signal, said battery saving cir-cuit including decoder means responsive to the output of said ,.
~2~ 3~3t3 receiver section means for respectively detecting a first coincid-ence between the received preamble code and a first predetermined code and a second coincidence between the received identifica-tion code and a second predetermined code, and selectively pro-viding said first control signal to said power supply means, wherein said decoder means further includes: means for detecting said first coincidence on a bit-by-bit basis, means for period-ically transmitting said first control signal, means for suspen-ding said transmission of said firs~ control signal in response to a second control signal, means for continuing said transmis-sion of said first control signal in response to a third controlsignal, means for immediately producing said second control signal when said first coincidence is not detected, and means for produ-cing said third control signal for a irst predetermined period o~
time in response to detection of said first coincidenceO
According to another aspect of the present invention, there is provided a method for selectively supplying power to a receiver section of a digital communication apparatus, said receiver section receiving a carrier wave which is modulated with a digital preamble and a digital identification code, said method comprising periodically beginning the supply of power to said receiver section detecting a first coincidence between the re-ceived digital preamble and a first predetermined code on a bit-by-bit basis; stopping said supply of power if it is determined that the error number of the bit-by-bit basis detection exceeds a predetermined number; and continuing said supply of power for a first predetermined period of time if said error number is less than said predetermined number.
~C3 7393 -3a-BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the present invention will become more apparent from the detailed descrip-tion hereunder taken in conjunction with the accompanying draw-ings, wherein:
FIGS. lA and lB are time charts illustrating a trans~
mitted signal for a paging system to which the battery saving circuit according to the invention is applicable and a typical battery saving operation of the receiver of the system;
, ., '7Q~9~
FIG. 2 is a block diagram of a paging receiver into which a battery saving circuit according to the invention is incorporated;
FIG. 3 is a more detailed block diagram of the decoder section of the receiver illustrated in FIG. 2, and FIGS. 4A and 4B are flow charts for describing the operations of the battery saving circuit according to the invention.
DETAILED DESCRIPTION OF THE PREFERR~D EMBODIMENT
Referring to FIG. lA, in a transmitted signal for a paging system, a preamble signal is positioned before a plurality o subscriber ID signals. The xeceiver, as illustrated in FIG. lB, iS intermittently actuated for receiving operation only during time periods Tonl.
If a preamble signal is detected in one of these time periods Tonl, the duration of power supply will be extended so that the subscriber ID signal can be detected during the next time period Ton .
According to the present invention, the battery saving efficiency (Tonl/Toff) can be improved without deteriorating ; the capability o~ the preamble signal detection.
Referring now to FIG. 2, a radio carrier wave received by an antenna I is amplified and demodulated by a receiver section 2. The carrier wave is modulated with a preamble and subscriber ID codes or signals. The demodulated signal is converted by a waveform shaper 3 into a pulse signal , . . .
~26 t~93 decipherable by a decoder 4. The decoder 4 feeds a power supply control section 7 with a control signal for turning on and off power supply to the receiver section 2 and to the waveform shaper 3. When the control signal is at a high level, the power supply control section 7 turns on power supply to the receiver section 2 and to the waveform shaper 3. When, on the other hand, the control signal is at a low level, the control section 7 turns power supply off.
When the power supply is on, the decoder 4 accomplishes decoding and, if necessary, extends the duration of the power supply.
The decoder 4 compares, during its decoding operation/
a demodulated ID signal from the waveform shaper 3 with the call number of the receiver stored in advance into a programmable read only memory (P--ROM) 5. If the demodulated signal is found identical with the call number, the decoder 4 supplies a tone signal to an amplifier 6 ~o drive a sp~aker 8 to thereby alert the bearer of the receiver. A quartz oscillation element 9 is intended for generating a clock signal to actuate the decoder 4. A battery 10 is a power source for driving the whole receiver.
Next, the operation of the decoder 4 will be described in greater detail with reference to FIGS. 3, 4A and 4B.
A preamble signal here consists of repetitions of 1 and 0, and is so composed as can be used for clock synchronization as well. The decoder 4 is a single-chip central processing unit (CPU), which may be ~PD7502 or ~PD7503 7;393 manufactured and marketed by NEC Corporation. A sequence of commands on decoding operation is written into a program memory 401, whose content at an address corresponding to the count of a program counter 402 is supplied to a control section 403. The control section 403 sends control signals C
to different parts of the decoder 4 according to the commands written in the memory 401. The program counter 402 normally adds ~1 every time a content of the program memory 401 is sent to the control section 403, but it will follow any jumping command or the like that may be given. Interface between external circuits and a data bus 40~ is achieved through an input port 404, an output 405, an output port 406 and an inpu-t port 407. The data bus 408 is further conmected to the program counter 402, a data memory 409, an 15 accumulator 410 and an arithmetic and logic unit ~ALU) 411 ~or transferring data. A synchr~nizing clock signal required for taking data in is generated by the quartz oscillation element 9, an oscillator 413 and a timer 4120 FIGS~ 4A and 4B are flow charts for describing the signal receiving and battery saving operations of the decoder 4. In the descrlption hereunder, reference numerals to steps in the flow charts will be parenthesized after the corresponding phrases or clauses thereof. When the decoder 4 is turned on (101), it stands by until the preparation for data writing-in is completed tlO2). This is a necessary step where the waveform shaper 3 (FIG. 2) includes an integrator circuit having a time constant, for generating the reference ~23:~7;31~3 voltage of a pulse detection comparator. Such a waveform shaper is disclosed in the Japanese Patent Application No. 51-37961 (Japanese Patent Application Disclosure ~ ~c`~ O~ oc~b~
No. 52-1207~8)/, assigned to the present applicantO
Upon completion of the preparation for data writing-in (102), a first timer having a time duration Tl is started (103) to moni~or data transit points (VTPs) (104). Pursuant to the monitor, the decoder is synchronized with input data so ~hat the leading or trailing edge of the clock pulse which is generated by the timer 412 for data writing-in, is placed at the center between DTPs (105). This step is continued until the first timer completes its time duration Tl (106). The last bit which is supplied at the completion timing of the first timer is stored into the decoder, and it is checked whether or not the bit is "1" (107). If it is not "1", the decoder 4 will wait one bit (108).
After step 107 or 108, a second timer having a time duration T2 is started (109) to detect the preamble signal.
First one bit of data is written in to be checked whether ~0 or not it is "0" (111) and, if it is "~", the process will move on to the writing-in of the next bit of data (112).
If it is not "0", +1 is added to an error counter Cl (115), and if the error counter C1 overflows (116), the power ;~ supply is suspended (119). If it does not overflow, the next bit of data is written in (112). The error counter Cl is intended fox correcting any error in data. If the error counter Cl is so set as to overflow at "3" for example, it can correct two bits of error.
. .
~2()739;~
A third timer with time duration T3 starts after the power supply is suspended, the process, if the duration T3 lapses, returns to step 100 (120 to 122). The time duration T3 corresponds to the time duration Toff in FIG. 1.
At the next writing-in of a bit of data (112), it is checked whether or not the bit is "1" (113). If it is "1", the time duration T2 is counted, and upon completion of the time duration T2, the decoder 4 will move on to the next step to write in data (110). If it is not "1", like at the previous data writing-in, +1 is added to the error counter Cl (117). If the error counter Cl overflows (118), the power supply is turned of~ (119), or if it does not overflow, the process will move on a~ain to the next data writing-in step.
In the oregoing mannerl the decoder detects the coincidence between the received pream~le signal and a I~O
pattern on a blt-by-bit basis. If -the coincidence ceases to be detected while the timer T2 is at work, the power supply is immediately suspended (119), and the third timer (T3) is started (120). Upon completion of the time duration T3 (121), the process returns to the step 101.
If the coincidence, e.i.~ the I/O pattern is consecutively detected while the second timer (T2) is in operation, after the completion of the time duration T2 (114), the decoder 4 will shift to the next step to receive the subscriber ID
signal or call signal (123).
g The time duration T2 corresponds to the time during Tonl of FI~. lB and has to be long enough to avoid erroneous operation due to noise or some other signal. ~lowever, according to the above-mentioned process the power supply is immediately suspended when the preamble signal ceases to be detected during the timing operation by this second timer (T2).
Therefore, the period during which the power supply is actually on is much shorter than the time during T2 without sacrificing immunity to erroneous operation due to noise or the like~ In this embodiment of the invention, the period during which the power supply is on without any signal being received is mostly determined by the duration of stand-by to prepare for data writing-in tlO2) and that (Tl) of the first timer's GperatiOn (103). Accordingly, the period from the start of preamble signal detection until the power turning-off upon confirmation of the absence of the preamble siynal have to be no longer than one or two bits of data unless any error has to be corrected.
As hitherto descri~ed, the present invention obviates the limitation o~ the conventional system which necessarily requires a considerable length of time until the detection ; of the preamble signal and which accordingly the period .
during which the power supply is on cannot be substantially ~` reduced. With this obviation, the battery saver circuit of the invention can improve i.ts battery saving efficiency.
. Furthermore, as it permits the period during which the preamble signal is detected to be extended, erroneous operation owing to noise or some other signal can be prevented as well.
Although a digital code is taken up in the foregoing description as an example of selective signal, the present invention can obviously be applied to a tone signal with equally sat:isfactory results.
BACKGROUND OF THE INVENTION
The present invention relates to a battery saving circuit circuit for use in a communication apparatus, such as a portable pager receiver.
In communication apparatuses including ~obile radio units, for instance, a radio paging receiver, there is used the so-called battery saving system, which periodically supplies and cuts off power to their receiver sections with a view to saving power consumption.
For instance, a transmitted signal in a paging system contains a preamble signal preceding a plurality of subscriber identification (ID) signals so that the receiver can he placed in a bat~ery saving mode. The receiver, periodically repeating turning on and off the power supply, receives 1~ signals during each time period (Tonl) that the power is on and does during each time period (Toff) that the power is off. If a preamble signal is detected during Tonl, the ensuing time period of "power on" (Ton2) will be extended to receive the subscriber ID signal that is to follow.
In this system, since the preamble signal is detected only once, erroneous operation may be caused by noise or same other signal, resulting in low reliability. Moreover, the erroneous detection of the preamble signal deteriorates the battery saving efficiency because erroneous detection . ~
~LZ~73~3 unnecessarily extends the power-on time period (Tonl).
One example of battery saving system.s to eliminate the foregoing disadvantages is disclosed in the United States Patent No. 4,181,893, issued to E.L. Ehmke January 1, 1980. According to this battery saving system, the receiver, to detect the ID
signal, extends power supply to the receiver section in response to the multi-detection of the preamble signal. This multi-detec-tion prevents the receiver from causing erroneous operation, improving the battery saving efficiency.
To carry out the first detection of the preamble, how-ever, this battery saving system supplies power to the receiver section for a prescribed period of time regardless of the result of the flrst detection of the preamb:Le signal. Therefore, this system yet has a disadvantage of lower battery saving efficiency.
S~MMAR~ OF THE INVENTION
An object of the present invention~ therefore, is to pro-vide a battery saving circuit which ~31iminates the foregoing disadvantages and Eurther improves the efficiency of battery saving.
~ccording to one aspect of the present invention, there is provided a battery saving circuit for use in a portable radio communication apparatus, said apparatus including receiver sec-tion means for receiving a carrier wave which is modulated with a digital preamble and a digital identification code, and power supply means for supplying power to said receiver section means in response to a first control signal, said battery saving cir-cuit including decoder means responsive to the output of said ,.
~2~ 3~3t3 receiver section means for respectively detecting a first coincid-ence between the received preamble code and a first predetermined code and a second coincidence between the received identifica-tion code and a second predetermined code, and selectively pro-viding said first control signal to said power supply means, wherein said decoder means further includes: means for detecting said first coincidence on a bit-by-bit basis, means for period-ically transmitting said first control signal, means for suspen-ding said transmission of said firs~ control signal in response to a second control signal, means for continuing said transmis-sion of said first control signal in response to a third controlsignal, means for immediately producing said second control signal when said first coincidence is not detected, and means for produ-cing said third control signal for a irst predetermined period o~
time in response to detection of said first coincidenceO
According to another aspect of the present invention, there is provided a method for selectively supplying power to a receiver section of a digital communication apparatus, said receiver section receiving a carrier wave which is modulated with a digital preamble and a digital identification code, said method comprising periodically beginning the supply of power to said receiver section detecting a first coincidence between the re-ceived digital preamble and a first predetermined code on a bit-by-bit basis; stopping said supply of power if it is determined that the error number of the bit-by-bit basis detection exceeds a predetermined number; and continuing said supply of power for a first predetermined period of time if said error number is less than said predetermined number.
~C3 7393 -3a-BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the present invention will become more apparent from the detailed descrip-tion hereunder taken in conjunction with the accompanying draw-ings, wherein:
FIGS. lA and lB are time charts illustrating a trans~
mitted signal for a paging system to which the battery saving circuit according to the invention is applicable and a typical battery saving operation of the receiver of the system;
, ., '7Q~9~
FIG. 2 is a block diagram of a paging receiver into which a battery saving circuit according to the invention is incorporated;
FIG. 3 is a more detailed block diagram of the decoder section of the receiver illustrated in FIG. 2, and FIGS. 4A and 4B are flow charts for describing the operations of the battery saving circuit according to the invention.
DETAILED DESCRIPTION OF THE PREFERR~D EMBODIMENT
Referring to FIG. lA, in a transmitted signal for a paging system, a preamble signal is positioned before a plurality o subscriber ID signals. The xeceiver, as illustrated in FIG. lB, iS intermittently actuated for receiving operation only during time periods Tonl.
If a preamble signal is detected in one of these time periods Tonl, the duration of power supply will be extended so that the subscriber ID signal can be detected during the next time period Ton .
According to the present invention, the battery saving efficiency (Tonl/Toff) can be improved without deteriorating ; the capability o~ the preamble signal detection.
Referring now to FIG. 2, a radio carrier wave received by an antenna I is amplified and demodulated by a receiver section 2. The carrier wave is modulated with a preamble and subscriber ID codes or signals. The demodulated signal is converted by a waveform shaper 3 into a pulse signal , . . .
~26 t~93 decipherable by a decoder 4. The decoder 4 feeds a power supply control section 7 with a control signal for turning on and off power supply to the receiver section 2 and to the waveform shaper 3. When the control signal is at a high level, the power supply control section 7 turns on power supply to the receiver section 2 and to the waveform shaper 3. When, on the other hand, the control signal is at a low level, the control section 7 turns power supply off.
When the power supply is on, the decoder 4 accomplishes decoding and, if necessary, extends the duration of the power supply.
The decoder 4 compares, during its decoding operation/
a demodulated ID signal from the waveform shaper 3 with the call number of the receiver stored in advance into a programmable read only memory (P--ROM) 5. If the demodulated signal is found identical with the call number, the decoder 4 supplies a tone signal to an amplifier 6 ~o drive a sp~aker 8 to thereby alert the bearer of the receiver. A quartz oscillation element 9 is intended for generating a clock signal to actuate the decoder 4. A battery 10 is a power source for driving the whole receiver.
Next, the operation of the decoder 4 will be described in greater detail with reference to FIGS. 3, 4A and 4B.
A preamble signal here consists of repetitions of 1 and 0, and is so composed as can be used for clock synchronization as well. The decoder 4 is a single-chip central processing unit (CPU), which may be ~PD7502 or ~PD7503 7;393 manufactured and marketed by NEC Corporation. A sequence of commands on decoding operation is written into a program memory 401, whose content at an address corresponding to the count of a program counter 402 is supplied to a control section 403. The control section 403 sends control signals C
to different parts of the decoder 4 according to the commands written in the memory 401. The program counter 402 normally adds ~1 every time a content of the program memory 401 is sent to the control section 403, but it will follow any jumping command or the like that may be given. Interface between external circuits and a data bus 40~ is achieved through an input port 404, an output 405, an output port 406 and an inpu-t port 407. The data bus 408 is further conmected to the program counter 402, a data memory 409, an 15 accumulator 410 and an arithmetic and logic unit ~ALU) 411 ~or transferring data. A synchr~nizing clock signal required for taking data in is generated by the quartz oscillation element 9, an oscillator 413 and a timer 4120 FIGS~ 4A and 4B are flow charts for describing the signal receiving and battery saving operations of the decoder 4. In the descrlption hereunder, reference numerals to steps in the flow charts will be parenthesized after the corresponding phrases or clauses thereof. When the decoder 4 is turned on (101), it stands by until the preparation for data writing-in is completed tlO2). This is a necessary step where the waveform shaper 3 (FIG. 2) includes an integrator circuit having a time constant, for generating the reference ~23:~7;31~3 voltage of a pulse detection comparator. Such a waveform shaper is disclosed in the Japanese Patent Application No. 51-37961 (Japanese Patent Application Disclosure ~ ~c`~ O~ oc~b~
No. 52-1207~8)/, assigned to the present applicantO
Upon completion of the preparation for data writing-in (102), a first timer having a time duration Tl is started (103) to moni~or data transit points (VTPs) (104). Pursuant to the monitor, the decoder is synchronized with input data so ~hat the leading or trailing edge of the clock pulse which is generated by the timer 412 for data writing-in, is placed at the center between DTPs (105). This step is continued until the first timer completes its time duration Tl (106). The last bit which is supplied at the completion timing of the first timer is stored into the decoder, and it is checked whether or not the bit is "1" (107). If it is not "1", the decoder 4 will wait one bit (108).
After step 107 or 108, a second timer having a time duration T2 is started (109) to detect the preamble signal.
First one bit of data is written in to be checked whether ~0 or not it is "0" (111) and, if it is "~", the process will move on to the writing-in of the next bit of data (112).
If it is not "0", +1 is added to an error counter Cl (115), and if the error counter C1 overflows (116), the power ;~ supply is suspended (119). If it does not overflow, the next bit of data is written in (112). The error counter Cl is intended fox correcting any error in data. If the error counter Cl is so set as to overflow at "3" for example, it can correct two bits of error.
. .
~2()739;~
A third timer with time duration T3 starts after the power supply is suspended, the process, if the duration T3 lapses, returns to step 100 (120 to 122). The time duration T3 corresponds to the time duration Toff in FIG. 1.
At the next writing-in of a bit of data (112), it is checked whether or not the bit is "1" (113). If it is "1", the time duration T2 is counted, and upon completion of the time duration T2, the decoder 4 will move on to the next step to write in data (110). If it is not "1", like at the previous data writing-in, +1 is added to the error counter Cl (117). If the error counter Cl overflows (118), the power supply is turned of~ (119), or if it does not overflow, the process will move on a~ain to the next data writing-in step.
In the oregoing mannerl the decoder detects the coincidence between the received pream~le signal and a I~O
pattern on a blt-by-bit basis. If -the coincidence ceases to be detected while the timer T2 is at work, the power supply is immediately suspended (119), and the third timer (T3) is started (120). Upon completion of the time duration T3 (121), the process returns to the step 101.
If the coincidence, e.i.~ the I/O pattern is consecutively detected while the second timer (T2) is in operation, after the completion of the time duration T2 (114), the decoder 4 will shift to the next step to receive the subscriber ID
signal or call signal (123).
g The time duration T2 corresponds to the time during Tonl of FI~. lB and has to be long enough to avoid erroneous operation due to noise or some other signal. ~lowever, according to the above-mentioned process the power supply is immediately suspended when the preamble signal ceases to be detected during the timing operation by this second timer (T2).
Therefore, the period during which the power supply is actually on is much shorter than the time during T2 without sacrificing immunity to erroneous operation due to noise or the like~ In this embodiment of the invention, the period during which the power supply is on without any signal being received is mostly determined by the duration of stand-by to prepare for data writing-in tlO2) and that (Tl) of the first timer's GperatiOn (103). Accordingly, the period from the start of preamble signal detection until the power turning-off upon confirmation of the absence of the preamble siynal have to be no longer than one or two bits of data unless any error has to be corrected.
As hitherto descri~ed, the present invention obviates the limitation o~ the conventional system which necessarily requires a considerable length of time until the detection ; of the preamble signal and which accordingly the period .
during which the power supply is on cannot be substantially ~` reduced. With this obviation, the battery saver circuit of the invention can improve i.ts battery saving efficiency.
. Furthermore, as it permits the period during which the preamble signal is detected to be extended, erroneous operation owing to noise or some other signal can be prevented as well.
Although a digital code is taken up in the foregoing description as an example of selective signal, the present invention can obviously be applied to a tone signal with equally sat:isfactory results.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A battery saving circuit for use in a portable radio communication apparatus, said apparatus including receiver section means for receiving a carrier wave which is modulated with a digital preamble and a digital identification code, and power supply means for supplying power to said receiver section means in response to a first control signal, said battery saving circuit including decoder means responsive to the output of said receiver section means for respectively detecting a first coincidence between the received preamble code and a first predetermined code and a second coincidence between the received identification code and a second predetermined code, and selectively providing said first control signal to said power supply means, wherein said decoder means further includes: means for detecting said first coincidence on a bit-by-bit basis, means for periodically transmitting said first control signal, means for suspending said transmission of said first control signal in response to a second control signal, means for continuing said transmission of said first control signal in response to a third control sig-nal, means for immediately producing said second control signal when said first coincidence is not detected, and means for produ-cing said third control signal for a first predetermined period of time in response to detection of said first coincidence.
2. A battery saving circuit as claimed in claim 1, where-in said decoder means further includes means for continuing trans-mission of said first control signal after the lapse of said first period of time so that said decoder means can detect said second coincidence.
3. A battery saving circuit as claimed in claim 1, where-in said digital preamble code is a repetitive code of logic "1"'s and "0"'s and said decoder means further includes: (a) means for synchronizing the clock of said battery saving circuit with a digital output from said receiver section means; (b) first means for determining, after the establishment of synchronization, whether or not said digital output is "l"; (c) means for starting a timer having a first timer period after waiting one bit if said first determining means gives a negative result or immediately if it is in the affirmative; (d) second means for determining, after the start of said timer, whether or not said digital out-put is "0"; (e) third means for determining after the second determining means has made its determination, whether or not said digital output is "1"; (f) means for causing said second and third determining means to once again make their determina-tions; and (g) means for producing said second control signal to suspend the transmission of said first control signal to said power supply means when the number of negative responses produced by said second and third means have exceeded a predetermined number.
4. A battery saving circuit as claimed in claim 3, where-in said decoder means further includes means for producing said third control signal to continue transmission of said first con-trol signal to said power supply means if the number of negative responses produced by said second and third determining means do not exceed said predetermined number and said first timer period of the timer has elapsed, so that said second coincidence can be detected.
5. A method for selectively supplying power to a receiver section of a digital communication apparatus, said receiver sec-tion receiving a carrier wave which is modulated with a digital preamble and a digital identification code, said method compri-sing: periodically beginning the supply of power to said receiver section; detecting a first coincidence between the received digi-tal preamble and a first predetermined code on a bit-by-bit basis;
stopping said supply of power if it is determined that the error number of the bit-by-bit basis detection exceeds a predetermined number; and continuing said supply of power for a first predeter-mined period of time if said error number is less than said pre-determined number.
stopping said supply of power if it is determined that the error number of the bit-by-bit basis detection exceeds a predetermined number; and continuing said supply of power for a first predeter-mined period of time if said error number is less than said pre-determined number.
6. A method as claimed in claim 5 further comprising con-tinuing said supply of power after the lapse of said first pre-determined period of time for a second predetermined period of time so that said apparatus can detect a second coincidence be-tween the received digital identification code and a second pre-determined code.
7. A battery saving circuit for use in a portable radio communication apparatus, said apparatus including receiver sec-tion means for receiving a carrier wave which is modulated with a digital preamble code of logic "1"'s "0"'s and a digital iden-tification code, waveform shaper means for producing a digital output signal representative of said digital preamble and said digital identification codes, power supply means for supplying power to said receiver section means in response to a first con-trol signal, and a clock means, said battery saving circuit in-cluding decoder means responsive to the output of said receiver section means for respectively detecting a first coincidence between the received preamble code and a first predetermined code and a second coincidence between the received identification code and a second predetermined code, and selectively providing said first control signal to said power supply means, wherein said decoder means further includes: (a) means for synchronizing the clock of said battery saving circuit with a digital output from said waveform shaper means; (b) means for detecting said first coincidence on a bit-by-bit basis, said detecting means including:
(i) first means for determining, after the establishment of syn-chronization, whether or not said digital output is a "1" bit;
(ii) timer means for producing a first timer period; (iii) means for starting said timer means after waiting one bit if said first means for determining signifies said digital output is a "0" bit and for immediately starting said timer if said digital output is a "1" bit; (iv) second means for determining, after the start of said timer, whether or not said digital output is a "0" bit;
(v) third means for determining, after the start of said timer and after determining if said digital output is a "0" bit, whether or not said digital output is "1"; (vi) means for causing said second and third determining means to repeat their operations at least one time; and (c) means for suspending the provision of said first control signal to said power supply means when said second and third determining means of said detecting means indicate at least a predetermined number of negative responses.
(i) first means for determining, after the establishment of syn-chronization, whether or not said digital output is a "1" bit;
(ii) timer means for producing a first timer period; (iii) means for starting said timer means after waiting one bit if said first means for determining signifies said digital output is a "0" bit and for immediately starting said timer if said digital output is a "1" bit; (iv) second means for determining, after the start of said timer, whether or not said digital output is a "0" bit;
(v) third means for determining, after the start of said timer and after determining if said digital output is a "0" bit, whether or not said digital output is "1"; (vi) means for causing said second and third determining means to repeat their operations at least one time; and (c) means for suspending the provision of said first control signal to said power supply means when said second and third determining means of said detecting means indicate at least a predetermined number of negative responses.
8. In a portable radio communication apparatus responsive to a digital preamble code and a digital identification code and having at least a receiving section, a power source and a battery saving circuit which produces a control signal to control the sup-ply of power from the power source to the receiving section, said battery saving circuit including a decoder means comprising a digital data processor for detecting a first coincidence be-tween the digital preamble code and a first predetermined digital code, and a second coincidence between the digital identification code and a second predetermined digital code, and for selectively providing said first control signal, a method for detecting said ~irst coincidence between said digital preamble code and said first predetermined digitally code and selectively providing said control signal comprising the steps of: comparing said digital preamble code on a bit-by-bit basis with said first predetermined digital code; producing an error signal each time corresponding bits of said digital preamble code and said first predetermined digital code do not coincide; adding a produced error signal to previously produced error signals as soon as the error signal is produced to provide a continuously updated count of the error sig-nals produced during the bit-by-bit comparison between the digital preamble code and the first predetermined digital code; suspending provision of said control signal as soon as counted error signals reach a preset number; maintaining said control signal for a pre-determined time when each bit of said digital preamble code coin-cides with each bit of said first predetermined digital code; and comparing said digital identification code with said second pre-determined digital code, after coincidence between said digital preamble code and said first predetermined digital code has been determined.
g. In a portable radio communication apparatus responsive to a digital preamble code and a digital identification code and comprising, a receiver section, a power supply means, and a bat-tery saving circuit, said battery saving circuit including decoder means selectively producing a control signal to control the supply of power from said power supply means to said receiver section, said decoder means comprising means for comparing the digital preamble code on a bit-by-bit basis with a first predetermined digital code; means for producing an error signal each time corres-ponding bits of said digital preamble code and said -first predeter-mined digital code do not coincide; means for adding each produced error signal to previously produced error signals as soon as the error signal is produced to provide a continuously updated count of error signals produced during the bit-by-bit comparison of the digital preamble code with the first predetermined digital code, means for suspending said control signal as soon as the count of said error signals reaches a preset number; means for maintaining said control signal for a predetermined time when each bit of said digital preamble code coincides with each bit of said first pre-determined digital code; and means for comparing said digital identification code with a second predetermined digital code after detecting coincidence between said digital preamble code and said first predetermined digital code.
g. In a portable radio communication apparatus responsive to a digital preamble code and a digital identification code and comprising, a receiver section, a power supply means, and a bat-tery saving circuit, said battery saving circuit including decoder means selectively producing a control signal to control the supply of power from said power supply means to said receiver section, said decoder means comprising means for comparing the digital preamble code on a bit-by-bit basis with a first predetermined digital code; means for producing an error signal each time corres-ponding bits of said digital preamble code and said -first predeter-mined digital code do not coincide; means for adding each produced error signal to previously produced error signals as soon as the error signal is produced to provide a continuously updated count of error signals produced during the bit-by-bit comparison of the digital preamble code with the first predetermined digital code, means for suspending said control signal as soon as the count of said error signals reaches a preset number; means for maintaining said control signal for a predetermined time when each bit of said digital preamble code coincides with each bit of said first pre-determined digital code; and means for comparing said digital identification code with a second predetermined digital code after detecting coincidence between said digital preamble code and said first predetermined digital code.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57090649A JPS58207733A (en) | 1982-05-28 | 1982-05-28 | Battery saving circuit |
| JP90649/L982 | 1982-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1207393A true CA1207393A (en) | 1986-07-08 |
Family
ID=14004355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000429101A Expired CA1207393A (en) | 1982-05-28 | 1983-05-27 | Battery saver for a paging receiver or the like |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4506386A (en) |
| EP (1) | EP0095750B1 (en) |
| JP (1) | JPS58207733A (en) |
| KR (1) | KR860001461B1 (en) |
| AU (1) | AU552697B2 (en) |
| CA (1) | CA1207393A (en) |
| DE (1) | DE3379372D1 (en) |
| HK (1) | HK19291A (en) |
| SG (1) | SG8191G (en) |
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|---|---|---|---|---|
| US6069929A (en) * | 1991-04-26 | 2000-05-30 | Fujitsu Limited | Wireless communication system compulsively turning remote terminals into inactive state |
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-
1982
- 1982-05-28 JP JP57090649A patent/JPS58207733A/en active Granted
-
1983
- 1983-05-24 US US06/497,638 patent/US4506386A/en not_active Expired - Lifetime
- 1983-05-27 CA CA000429101A patent/CA1207393A/en not_active Expired
- 1983-05-27 DE DE8383105276T patent/DE3379372D1/en not_active Expired
- 1983-05-27 AU AU15033/83A patent/AU552697B2/en not_active Ceased
- 1983-05-27 EP EP83105276A patent/EP0095750B1/en not_active Expired
- 1983-05-28 KR KR1019830002373A patent/KR860001461B1/en not_active IP Right Cessation
-
1991
- 1991-02-18 SG SG81/91A patent/SG8191G/en unknown
- 1991-03-14 HK HK192/91A patent/HK19291A/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069929A (en) * | 1991-04-26 | 2000-05-30 | Fujitsu Limited | Wireless communication system compulsively turning remote terminals into inactive state |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6330818B2 (en) | 1988-06-21 |
| SG8191G (en) | 1991-04-05 |
| EP0095750A2 (en) | 1983-12-07 |
| EP0095750B1 (en) | 1989-03-08 |
| AU1503383A (en) | 1983-12-01 |
| US4506386A (en) | 1985-03-19 |
| HK19291A (en) | 1991-03-22 |
| KR840004993A (en) | 1984-10-31 |
| KR860001461B1 (en) | 1986-09-25 |
| EP0095750A3 (en) | 1984-07-18 |
| AU552697B2 (en) | 1986-06-12 |
| DE3379372D1 (en) | 1989-04-13 |
| JPS58207733A (en) | 1983-12-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20030708 |