CA1206530A - Transmitter and receiver for controlling the coding in a transmitter and receiver - Google Patents

Transmitter and receiver for controlling the coding in a transmitter and receiver

Info

Publication number
CA1206530A
CA1206530A CA000434390A CA434390A CA1206530A CA 1206530 A CA1206530 A CA 1206530A CA 000434390 A CA000434390 A CA 000434390A CA 434390 A CA434390 A CA 434390A CA 1206530 A CA1206530 A CA 1206530A
Authority
CA
Canada
Prior art keywords
receiver
transmitter
lbi
code
address code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000434390A
Other languages
French (fr)
Inventor
Frank J. Liotine, Jr.
Joseph W. Twardowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chamberlain Manufacturing Corp
Original Assignee
Chamberlain Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chamberlain Manufacturing Corp filed Critical Chamberlain Manufacturing Corp
Application granted granted Critical
Publication of CA1206530A publication Critical patent/CA1206530A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G08SIGNALLING
    • G08CTRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00Electric signal transmission systems
    • G08C19/16Electric signal transmission systems in which transmission is by pulses
    • G08C19/28Electric signal transmission systems in which transmission is by pulses using pulse code

Abstract

ABSTRACT
Transmitters and receivers for controlling remote elements which use a synchronous serial transmission format and which allows changes in coding to be automatically made between the receiver and transmitter and wherein the code is stored in memories of the transmitter and receiver and wherein the receiver can generate and transmit a new code with a light emitting diode so as to change the code in the transmitter. The transmitter and the receiver use micro-computers which are suitably programmed and include non-volatile memories.

Description

lZ~53C~

SPECIFICATION
This invention relates in general to a novel coding system fo~ tran~mitters and receivers.
Remote control transmitters and receivers are known as, for example, for garage door openers and other devices. Initially, a different carrler frequency was utilized for each pair o~ transmitters and receivers so as to isolate them from other units. Also, various coding schemes have been utilized to encode data into digital form. Certain of such transmitters and receivers include a plurality of multi-position switches which control the coding for the ~ransmitter and receiver and in such systems the codes can be changed by manually changing the positions o the switches to different positions and assuring that the position of the switches in the transmitter and receiver are the same.
The present invPntion comprises a novel multi-channel transmitter and receiver for controlling a plural~.ty of functions and includes the featuse of changing the code in the receiver and transmitter to one of a large number of codes in an automatic manner. A
pulse length digital code is utilized.
When it is desired to change the identification code, a program mode switch is closed in the receiver and the micro-computer recalls from the non-volatile memory the last stored code. Using this code as a start, it perfo~ms a random number generation algorith and stores the newly generated code in the non-volatile memory and immediately transmits the new code through a light emitting diode. The transmission format with the l~$Q~S30 light emitting diode at the receiver continues until the pro-gram mode switch is turned off. During the energization of the light emitting diode in the receiver, the transmitter is placed in close proximity to the receiver so that it detects the code from the light emitting diode and the new code is then stored in the memory of the transmitter which then produces a flashing ready signal to indicate to the operator that the programming cycle has been completed. Although in this specification the code is shown as being generated in the receiver, it is to be realized that the code could also be generated in the transmit-ter and furnished to the receiver.
The novel transmitter and receiver can be used to re-motely control a garage door, for example. Other applications are for security system where one or more transmitters monitor different areas which energize the receiver which actuates an alarm when the areas are invaded by intruders. Another applica-tion is for furnace control where one or more transmitters have te~perature sensors and the transmitters are periodically keyed to transmit the temperature in a particular zone to the receiver which controls the furnace. The system of the invention can also be used to control electrical lights and appliances which are connected to the receiver. The invention can also be used to control television receivers and video tape recorders and in these applications sonic and/or infrared radiation may be used.
In summary, the present invention provides apparatus for controlling a radio frequency receiver with a remote radio frequency transmitter comprising a first memory means in said receiver for storing at least one address code, infrared trans-mitting means in said receiver, a first microcomputer in said receiver capable of accessing said first memory means and for generating a random address code and storing it in said first ~ .

12~S30 memory means, a program mode switch means in said radio fre quency receiver for energizing said first microcomputer to ~.
generate said random access address code and for energizing said infrared transmitting means to transmit said address code, an infrared receiving means in said transmitter for receiving said address code, a second memory means in said transmitter for storing said address code, radio frequency radiating means in said transmitter for radiating said address code, radio fre-quency receiving means in said receiver for receiving said transmitted code, said first microcomputer in said receiver xeceiving and comparing the received address code with the address code stored in said first memory, and an output circuit energized by said first computer when said addresses are the same.
It is seen that the present invention provides -2a-12C~S30 an improved remote control system that can be used for a number of channels and allows for automatic change of the address coding be~ween the transmi~ter and receiver.
Another object of the invention is to provide transmitters and receivers which have a large number of possible codes so as to eliminate interference between closely spaced transmitters and receiver systems.
Yet another object of the invention is to provide an improved transmitter and receiver system for a remote control device.
Other objects, features and advantages of the invention will b^ readily apparent from the following description of certain preferred embodiments thereof taken in conjunction with the accompanying drawings although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure and in which:
ON THE DRAWI~GS
Figure 1 comprises a block diagram of the 20 transmitter;
Figure 2 comprise6 a flow chart for the transmitter;
Figure 3 comprises a block diagram for the receiver;
Figure 4 comprises a flow chart for the receiver;
Figure 5 illustrates a transmission signal format;
Figure 6A illustrates a sync header waveform;
Figure 6B illustrates a terminating header waveform;

~2~53(~

Figures 7A and 7B comprise a schematic diagram of the transmitter;
Figures 8A and 8B comprise a chematic d~ag~am of the receiver; and Figure 9 illustrates a typical pulse train.
Figure l illustrates in block form the trans~itter of the invention which comprises an antenna 10, an RF transmitter section 11 connected to the antenna and a micro-computer 12 supplying an input signal to the RF transmitter 11. The micro-computer is connected to a memory 13 which may be a non-vola~ile type memory and a number of channel select inputs 16, 17, 18 and 19 are connected to a channel selector unit 14 and supply inputs to the micro-computer 12.
A power supply comprises a battery E and a transmit switch 22 such that when the transmit switch 22 is closed the transmitter is energized by applying power to the various units of the transmitter. A programming signal receiver 21 is connected to the micro-computer and provides means for selecting the code in the transmitter.
Figure 2 comprises the transmitter flow chart and when power is turned on the micro-computer 12 determines whether a valid programming signal is present.
Figure 3 is a block diagram of the receiver 30 which comprises an antenna 31 for receiving radiation from the transmitter 9. The receiver 30 includes an RF section 32 which is connected to the output of the antenna 31 and the RF receiver section 32 supplies an input to a micro-computer 33. A memory 34 such as a non-volatile type is connected to the micro-computer 33. A program mode switch 41 is connected to the lZ~S3~) micro-computer and output channel leads 37, 38, 39 and 40 supply operating signals for various apparatus or functions which are to be controlled as, for example, channel 1 might comprise a garage door opener. Channel
2 might comprise a security control channel. A
programming signal transmitter 36 is connected to the micro-computer 33 for programming the ~ransmitter 9.
Figure 4 comprises a flow chart for the receiver.
The transmitter and receiver of the invention eliminate the dip switches for code selection which are required in prior art devices and allows the expansion of channels so that a number of channels can be utilized to control different functions. Faster response times are obtained than prior art control transmitters and receivers. A specific em~odiment of the invention was constructed wherein a four-bit sin~le r~hip micro-computer was utilized rather than custom discrete logic integrated circuit for performing the encoding and decoding of the algorithm. ~n addition, a non-volatile memory is used rather than a multiple three position switch for storing the custom code for each transmitter and receiver system.
The use of a single chip micro-computer rather than a discrete logic integrated circuit allows system flexibility for additional ~xpansion and for various other radio controlled applications in addition to garage door opener systems without the requirement of major and exhaustive redesign efforts or custom integrated circuits. For such subsequent changes, a simple micro-program change in ~he self-contained mask ROM is all that is required and thus only software lZ~5~30 changes are necessary.
By using non-volatile memories rather than the dip switches used in the transmitters and receivers of the prior art devices requires that the randomly selected code be supplied from the receiver to the transmitter.
Because of Federal Communication Commission rules and regulations, the transmission of radio frequency signals for this purpose cannot be used since the transmission of a coding signal for defining the code in the transmitter would not be within the Rules for actuating a garage door opener. This would comprise the transmission of a message containing information. This means that 1) during the programming mode transfer of code information from the receiver to the transmitter, the transmitter and receiver would have to be hard wired together or 2) the transfer of ~uch data occurs by using infrared transmitters and receivers. The use of infrared transmitting and receiving means requires no physical contact between the system~.
In the present invention a synchronous serial transmission data format i8 utilized because 1) the equivalent replacement of the prior art nine pole three-position switch with a non-volatile memory requires that the electrical inputs be binary and 2) the present design allows additional channel expansion and identification.
In a particular embodiment constructed according to the invention, the maximum number of channel~ was selected to be sixteen and allow 216 possible code combinations or 65,536.

~2~i30 The transmission format used in the invention utilizes security and privacy and is binary and uses pulse position modulation as the decoding format for data transmission. Figures 5 and 6A and 6B illustrate the data format used. As shown in Figure 5, a synchronization header frame of two bits is used for synchronization at the receiver. The first word 1 is a channel identification block of four-bits in length which contains the binary coded information that identifies the transmitting channel and this selection limits the maximum number of channels to sixteen.
Words 2 through 5 are data blocks and comprise four words each of four-bits containing binary coded information that can represent the code for a particular channel (216 possible code combinations or 65,536).
Alternatively, other forms of digital information as, for example, the output of a transducer can be included in these words.
Word 6 is a checksum block and is an error checking format which is derived by the binary addition of the identification block with data blocks 1 through 4 and eliminates any carry bits. For example:
MSB LSB
BLOCK _ Bit 4 Bit 3 Bit 2 Bit 1 Channel Identificat~on Block ~ 1 1 0 Data Block 1 1 1 0 ' 25 Data Block 2 1 0 0 Data Block 3 1 1 1 0 Data Block 4 1 1 0 Checksum Block = 0 binary sum of all blocks less any carry bits 12~i~530 Then a termination header which is two-bits in length indicates to the receiver that the current information transmission train has terminated. Then there is a blan~ing period of 28 bits which in a specific embodiment comprises 28msec and then the data format is repeated again.
An example of word 1 is shown in exploded form in Figure 5 comprising four-bits of a typical word and a logic 1 comprises a pulse of 0.75 msec and a 0.25 period of no signal. A logic 0 comprises a signal of 0.25 and then no signal for 0.75msec.
Figure 3 illustrates ~he receiver block diagram and the software flow chart for the receiver is illustrated in Figure 4. When the power is turned on, the receiver software first turns on the complete hardware system.
It first interrogates the program mode switch input. If the program mode switch 41 is closed, the micro-computer 33 proceeds to access the non-volatile memory 34 to recall the last stored code. Using this code as a start, it then performs a random number generation algorithm and stores the newly generated code in the non-volatile memory and immediately transmits this new code through the light emitting diode 36. The transmitter g is placed in close proximity to the receiver 30 such that the programming signal receiver 21 receives the info~mation from the light emitting diode 36. The transmission signal format of the receiver is as shown in Figure 5 except that it does not need the channel identification block and uses a shorter blanking time equal to 5msec.
The receiver continues to transmit the code until the lZ~53~

program mode switch 41 is opened af~er which the receiver monitors the receiver input port from the RF section and antenna.
The receiver algorithm contains a software phase lock loop to lock it on the receiver sync header.
All timing information required to perform the remainder of the algorithm is contained in the pulse width of the sync pulse. A software timing loop times out the pulse and stores this value in the memory. For each consecutive negative to positive transition, the micro-computer samples the input at the time interval it calculated from the sync pulse, as illustrated in Figure 9.
After all of the bits are sampled and stored in the memory, a comparison is made with the code stored in the non-volatile memory for a valid match. If a match is found, the appropriate channel output is identified by an appropriate light emitting diode to identify that particular channel.
Figure 1 comprises a block diagram of the transmitter and Figure 2 illustrates the software flow chart of the transmitter. The transmitter upon power up interrogates the input photo-transistor 21 for a period of about lOmsec for indication of a valid programming ~ignal. If no programming ~ignal is available within the flrst ten milliseconds, the transmitter software assumes that the presently stored code is accurate and the transmitter proceeds to transmit such code.
It accesses the stor~d code from the non-volatile memory, reads the chsnnel identification number, computes the checksum and then transmits all the information using the format illustrated and described.
_g_ ~ 2 ~ ~5 30 If a programming signal is received, the transmitter decodes the incoming information and if the checksu~ is correct stores the new code in its non-volatile memory 13 and outputs a flashing ready signal to indicate that the programmin~ cycle has been completed.
All output transmission timing is based on an ideal instruction execution time of 20msec. Since the software is fixed, the only parameters that affect output timing are the resistor capacitor tolerances and any input tolerance variations between different micro-computers.
A software pseudorandom number generator is utilized at the receiver to generate the different codes.
The use of software to generate random values results in a paradox. The fact that an algorithm exists for a process implies that the process outputs are not! truly random because the algorithm can be used to predict the output sequence. True random values can only be generated by the use of systems such as "memory garbage" or "human reaction time". The use of human reaction time requires additional hardware and expense which is undesirable in the high volume electronic industry. In the presen~ invention, the use of "memory garbage" to start the system "initiation" or starting value is used on a one time basis.
In the algorithm used every time a random number is required a new sixteen bit configuration will result from the ~eed or initi~tion value used. Continuous recall for sufficient number of times will result in all lZ0~530 the possible sixteen bit configurations. However, the outputs will appear random if the sequence of outputs are considered and it is impossible to prove that the program is not producin~ true random numbers. The distribution of outputs is uniform over the range of possible outputs although all possible sixteen bit values appear before any repetition occurs. In the present invention 65,536 outputs will occur before any repetition occurs.
The algorithm used words as follows. The random code is stored in four blocks of memory each four-bits wide for a sixteen bit word. This allows a binary representation of 65,536 discrete numbers. However, for the random number generator algorithm to work, the all zero state must not be used therefore there are only 65,535 numbers that can be used.

¦ bLK ~ ¦ UK 2 ¦ 8LK 3 ¦ BL~ ~ l ~ B" B~--8~ 8~-B~- B~o B~ 3~ B~ B~ B~ B~ ~ B~¦
~D ---Whenever the program calls for random number, the previous value or "6eed" i8 recalled. Each bit is shifted left one position. Bits 14 and 15 are exclusive or-ed and the result is shifted into the first position of block 4. In this manner, all possible 65,535 combinations will result before the pattern repeats.
The program for the transmitter micro-processor 12 and the program for the receiver micro-processor 33 are attached.

lZ~53~

Figures 7A and 7s illustrate the electrical schematic of the transmitter 9, the antenna 10 is connected to the RF transmitter 11 which receives an output on lead 50 from output terminal SO of the micro-computer 12. The micro-computer 12 may be a National type 404LP, for example. The non-volatile memory 13 may be a XICOR
type X-2210 and is connected by leads 51 through 57 to the micro-processor 12 as illustrated. An octal latch 26 is connected to the micro-computer 12 by leads 58 through 66 and might be a type 74C373. A EPROM 27 might be a type 2716 available from INTEL, a Trademark, and is connected by leads 58 through 69 to the micro~computer 12 and is further connected to the octal latch 26 by leads 70 through 77. The power supply E and transmit switch 22 are connected to a regulator 23 which produces the drive voltage ~Vcc. Infrared sensor 90 is connected by lead 91 to the micro-computer 12. A ready indicator 92 is connected by lead 93 to the micro-computer 12. Channel selector switches 94 through 97 are connected to channel selector leads 16, 17, 18 and 19 which are connec~ed to the micro-computer 12. ~ lead 101 is connected from the memory 13 to the reset terminal of the micro-computer 12.
Figure 8 illustrates the receiver in schematic form. The micro-computer 33 may be a type 404LP available from National Corporation. The antenna 31 is connected to the RF receiver 32 and by lead 105 to the micro-computer 33. The programming LED 36 is connected through a resistor and a transistor Tl to lead 107 which is connected to the micro-computer 33.
A non-volatile memory 34 which might be a type X2210 lZ~53V

available from XICOR is c~n~ected by leads 110 through 119 to the micro-computer 33. A reset circuit 121 is connected by leads 122 and 123 to the reset of the micro-computer 33 and the memory 34. An octal latch 8 which might be type 74C373 is connected by leads 125 through 133 to the micro-computer 33. An EPROM 7 which may be a type 2715 is connected to the octal latch 8 and to the computPr 33 by leads 125 through 136. The EPROM 7 and octal latch 8 are connected together by leads 137 through 144. The program switch 41 is connected to the micro-computer 33 by lead 200. The cha-nel indicator lights 250, 251 and 252 are connected to the micro-computer by leads 150, 151 and 152 and illustrate which channel is energized.
Another modification for changing and encoding the code in the transmitter and receiver comprises instead of using the signal transmitter 36 in the receiver and the signal receiver 21 in the transmitter is to provide that transmitter and receiver be electricahly connected together. For example, in the receiver 30 an electrical plug could be mounted in place of the signal transmitter 36 and a mating plug could be installed in the transmitter g in place of the signal receiver 21 and when the plugs are joined the code can be furnished by the receiver 30 to the transmitter 9 when the program mode switch 41 is closed. After the code has been transmitted and stored the transmitter can be unplugged from the receiver and the system operated with the new code.
Although the invention has been described lZ~)~530 with respect to preferred embodiments, it is not to be so limited as changes and modifications can be made which are within the full intended scope of the invention as defined by the appended claims.

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205 OD3 ~D ~IB O
206 OD~ 39 LBI CNTROL ;S~O~ alNT~L IIORD
207 oaq 77 STII 7 CCP CP~ ASSE~lER P~GE: 5 IIAIH~R

,~ .
209 ODD 19 LBJ lDI~I ;READ UIANNEL ID Illff:ER
~10 ODE 332E lNL
211 CALCIILA~E CHECKSl~ll OF DATA ~LOCKS ~WD ID ~R

213 OEI 19 Ul ID~

.

lZ~530 217 OE5 IB L~J ELK2 2~8 tE~ 3~

220 OE~ 31 ADD
221 OE9 ID IBI E~

m 03 IE LBI CKS~ iSIOR CHECKSUI~ lN a~
224 OES Ob X O
225 ; TRAN~IJT SYND PULSE
22~ OED 3B IHITX; L~l a~l i INITIL12E I~ARE REGISTER
227 GEE ~8 STII 8 22q OFO 3B LBI CO~
230 OFI 33~9 LEI 9 ;SET E~l, 50~1 231 OF3 51 Bkl9 Al~ I il~AN8~11T LO~IC I
232 OF4 21 SKE ~tO~ 5W USEC.
233 OF5 F3 ~P BRI9 2~ OF6 33~1 LEI I ;S~ EN~O, SO=O
235 OF8 3B L81 ~lPI ~TR~IIT LOGIC O
23~ CF9 7D 'STII 13 ~FGR 1.5 ~ISEG

238 OFB 3B LBI CO~IPI
m OFC 51 8R20: AISI:: I
2~0 OFD ~4 241 OFE 21 ~KE

2U OFF 4CFC J~P BR20 2~3 101 ~
2~4 102 U NO~
245 ~lR~llT DATA BLO~
24~ 103 æ u~ T i INIIIALIZE BD POIN~ER T0 -- . . . _ .. ... .. . _ ~ .

12~530 24~ 105 3A LBl CtlMP2 iDaTA tO ~E Tk~S~llTTED
24s 10~ 70 5T11 0 25n 1~ 3C NXBYTE: ~BI 8 25~ IOS 50 I~
253 lOA ~361 LEI I ;SET EN3 0,S~0 254 I~C ~3 Sl~ ' 3 iC~ECr~ LOGIC STA~US OF Bll 3 255 IOD D0 JP ~12t ;~ B~I
25~ 1~E 32 RC ;RA11 E3~0 257 lOF Dl JP ER22 2~ 0 22 ~R2I S~

COP CROSS ASSEtlPlER ~AGE:
~IAINP~

259 111 ~9CB PR22: JSR TX~IIT
2~0 113 3E LBl SC~ATC ; I~J USEC. DEL~Y
2~ 7E S~ll 14 2~2 II5 3E LBI S~hATC
2~ X 0 2~5 ll3 ~7 R .-I

~5 S3(1 2~7 IIA 3C LBI BDPNT
2~8~Z5 LD2 2~ llC 50 CA~
270 IID 33~1 LE~ 1 ;SET EN3=O.S4=0 271 IIF 03 SK~Bi 2 ;oHEC~ LOGIC STATUr~ OF EIT 2 272 120 E3 JP ER2~ ~k~ B2=1 273 t21 32 RC iRA~ B2=0 27~ 122 E~ JP Bfi24 275 123 22 ~R~3: SC
a7B 124 69CB PR24 JSR ~X~.IT
m 12~ 3E L81 SCRATC ;160 USEG DELAY

279 128 3 LEI SC~ATC
2ao 12~ 0~ X O

282 12B EA JP .-1 283 ~2C 44 NCP
28~ 12D 3C LB~ BDPNn 28~ t2F 50 ~ CA~
2B7 130 3361 LEI I ~SET fiK~ O.SO50 288 132 11 S~MBZ I ICHECK LOGIC STATUS OF BIT I
289 133 f~ R BR25 ~Rol1 Bl=l 290 13~ 32 RC lRAn Bl~O
2~1 135 F7 JP BR2~
m 13~ 22 ~s sc 2g3 137 ~9CB ER2~: J6R TXIIlT
294 ~3~ 3 LBl SCP~C
295 13~ 7E STlt 14 29~ 13S 3E LBt SCRATC
29T 13C 0~ X û ;1~0 USEC. DELAY
29813D 51 aïsc 1 12i~)~530 301 !~1 3L LBI 6 302 14t 25 L~ 2 303 ~42 50 C~B
30~ 543 ~41 LEI i ;SE~ EH3~0.5~0 305 145 0I S~rEZ O it~Et~ LtlGlC SldTU6 OF BIT O
3~1~6 C9 R IIR27 iR~ BO=I
307 t4~ 3? RC i~ =t 3t~ 14~ t~ JP BR'~
149 Z~ eR27 ~C
3~0 I~ J

I:OP t~S ASSEME LER PAGE: 7 rAlNPR

. .

311 1~ 3C LBI EDPNT ; INCREIIE~IT ED POI~JTEk 31214D 05 1.0 0 3131~1E Sl A~SC I
314 I~F U NtP
315 ~50 t~ X O

~17152 3A LF' COMP2 ;LAST IIE~IORY L06ATION
,27 126~530 ~31'~ 61b7 J~IP NY~YTE iNn 3.~0 15~ 44 I~OP ;YE5 321 157 33~1 LEI I
322 15~ 3B LBI C~PI
323 l5A 78 STl l 8 32515C 3B L~l a~PI
32~ 15D ~4 ~OP
32~ 15E 44 NOF
328 i ~k~lT ~ERMINhT~
329 15F 38 LEI CO~lPl 3B0 1~0 78 STII 8 331 161 00 a.rA
33'~ 1~2 3E Lel UJtlPI
33~ 163 336'7' LEI q iSE~ EN3~
~t34 165 51 e~L'7'' AISC 1 iTNWSMlT L~IG 1 FOR 500 l~EG.
~5 t~
33~ 167 E5 .P ~'2~
337 1~8 33~1 LEI I ;SET Ehl3~0,S~O
33B iTRA~llT ELANK TI~E ~F 28 ~EC.
l C~P2 ; INITIALI'E C~ RE REGISTE~
~40 16e 7~ STII 2 C 7~ STII 6 342 l~ 2C LBI allNTl ~RESET ClilJTEk ~GISTERS

f 10 STII 0 345 l70 h9~2 JSR TI~Eh 3~ 172 U~ P INITX iRETRAiJ~llT DATA
347 ;su~nll~s 3~8 ~ SWROUTIK ~Q1PLE
349 ~ ZC S~UlPLE: LBI COUJTl 350 175 00 CLRA ;SETlP ~LING VN UE
-,2~
_ - ~26~530
4 IIOP
35j` 17B 21 SI~E
354 17~ F6 JP S11Bl 355 I-A ~1 SN~E7 0 ;~aD INPUT

357 27E 22 SC ;JNPUT IS A U)GIC O

35817F 6182 .~P SUE8 359 le~ 32 51JE2: Re ~INPUT ~e ~ LOGIC
3~ 182 48 SUB3 RET

C~ C1~; A5~EllELER PAGE: 8 lN~R

361 ~
3U 183 3B ~1: LBI C4tPI ~ INITIALIZE e~ ~E~hY POINTER
3U 184 7F STII 15 ~ID alMPAF.E REGIBTER

3~ 187 25 LD 2 ;OUTPUT aDD~LSS POINTED TO
3~7 188 51 al5C 1 ~BY C~RARE RE415~ER

2~

i2~;530 3~9 IB;I 33~E ~16D
3~0 1~ 39 LBt ~TROL i0TPUT Ct~lTROL ~Rb TO
371 I~D ~3A O~IG i~OhY
372 18F OE ~ LAGI ia~ECK FOR ~`EAD OR ~kITE
373 190 Ol SI~E2 O iFLAG
374 191 DB ~ SUP4 iREAD FLAG
375 192 3C LBI E~ lRITE FLAG
37~ 193 25 LD 2 377 194 50 aE
37B 195 OO CL~A
379 19~ 3~ CPJ~ ;I~RITE TO N~1 3ao 19B 3365 LEI S iEH~BLE L DRIVERS
3E1 19A El JP Sl~
382 t9B 3E SUE14: LBI e~T

385 19E 3~2E INL ikEAb FR~l M~AM
3B~ IAO 0~ X O
387 IAI 3F gJ~: LBl HllUSE ;INITIATE a DESELECT
3B8 IA2 7F ;STII 15 389 1A3 3F LBI I~ISE
3~0 IA~ 333A OI~G
391 IA6 3361 LEI 1 ;DISAEEE L D~IYERS
392 lA8 3C LBI BOFNT
3~ IA9 05 LD O
394 l~q 51 AlSt: I
395 10~ 06 X O ;STIX~E NEl~ YaLUE FOR
39~ LD O ;~Y POl~JA
397 IAD 3B Ul COllPI ;LAST I~E~Y L~ATI~
398 IAE 21 SKE iaCCESSED?
399 1A ~186 JP SUE~ ;ND
400 lB1 ~8 IET ;YES

.. . . . . . . . . . .

12~S3~
.402 IB2 2D TlnEF;: LBl C~IT0 408 1E~ 00 CLk~
404 lB4 51 AISC I
405 IE~ F4 JP .-1 i~0 ~;EC. DELAY L04t 406 1~ 06 LD O ;COlW~4 C~TENTS T0 AtW
407 le7 51 AISC 1 iADD 1 T0 ~Cll B FD ~ LFI
~bS ;ST~E ZER0 11~ CaMt ~10 IEiq 05 LD 0 ;DEa~E~ENT T0 CQUITI
~11 166 51 AISC I ;ADD I T0 C~JNTI
~12 IBC 4~ t 4181~D0~ Ul: X0 414 16E Bb Ltl a~ ;C019PARE COUITERS T0 COP CROSS ASSErELE~ PAqE: 9 AlNM

415 IBF 0~ L~ O iCOMtAR~ REG~S~R5 41~ 1~ 2C LBI CPNII
J17 ICI 21 S~:E ;SKJP lF ~T S1GtJ C~NT
~18 IC2 ~IB2 JIP 11~ ~EI~UALS COtlP2 ~19 IU ~8 L81 C~P~
420 IC5 0~ LD 0 3(~

~422 .IC7 .I Sl;E ; ElXlALS- C~IT4 J23 11~ olE~ J~f TJ~E~ iN0, lUSTlTliTE ANtlTHE~ CVCLE

425 i TR/~;I~JT SUBRCUTII~
J2~ IC8 3B ~I!IIT: L81 CCMP1 4~7 ICC 73 STJI 3 ~291CE 3B LBJ CO~IF'I
~30 1CF 44 NOF
`~3l ID0 33~9 LEI ~ ~SET EH~I,SD=I
U2 1~2 51 INCI AlSt. 1 ;250 U~t:. LODP
`~33 11~. 2~
4~ lD4 D2 R lNCI
435 1~5 20 SKC iT~lT A Ltt31C l, ~1 U~ P TR~IS0 iT~AN;'jMlT A LO~IC 4, S0=0 437 ID7 3B LBI CO~IF'I
U8 ID~ 74 STII 4 439 lD9 3L LBI CO~IPl Ul 1D~ 51 INC2: Alæ I ~240 USFC. LOOP
U2 11~: 21 S~E

U5 ICF 3~1 ~MN50: LEI I ISET El~O
U6 tEI 38 L81 COIIPI

U8 IE3 3B LBI C~PI
U9 1E~ 00 CLRA
JS~ IE5 Sl 11~3: AISC 1 ~1~/ USEC LO~D
451 IE~ 21 ~KE
452 lE7 ES .P INC3 ~ t'': -3~

S3~

~P ~ A~BL~ PA~: 10 rAlNPR

IIIPN~ 003D IBEOItl 0025 ilLI~I oole BLK2 oolc ~ 3 OOID ~K4 OOIE E~l 0015 BRI0 007~
aRIt 007A ~ i 8R13 ooa9 ~R14 0094 R15 00~ ~RIh OO~ 17 OO~A ~R18 OOEC
8R19 OOF3 ~R2 001B ~20 OOFC ~R21 0110 BR~2 O~ fU3 0~ PQ24 0124 ~R'S ~1~
~h 0137 ~RZ7 01~9 ER2B 014A a'~29 01~5 .. . . .. .. . . . . .. ..

12~S30 Be7 OO~F aR8 00$7 BR'~ e ~PNT 003E
~KSUl OOlF CNTROI 003A ~111P1 003C CO~IP2 003B
C~T0 Q0; COUJTI W2D C~lPlT2 002C ~ FLAGI OOOF
lDl~J11 OOIA lNCl OSDX IN~2 OlD~ IHC3 OlE~
INITX OOED IRIH 002F L001-1 003~ LPt OIBD
~,IOUSE 0030 INR~ 0183 ~ YTE OIC~ REPEAT 005e S~PLE 017~ S1~7C 003F ~TART OOOE 8TRTX OOD0 SlJE:I 017~ ~2 0181 ~ 018~ ~4 019B
sues OIAl SU~6 Olg~ TI~IER OlP2 ~NS0 OIDF
1TXIIIT OlCe r~ E~' LI~IES

COP 420 ~SSEt~LY

SWRC C~ SUl = 50C2 ~ECT CHEa~ OCP2 11~ FILE CE~ER: JI~. SP~C Vll:

O~ECT FILE CENJSER ~H Ln .. .

~2~S30 CDP cRrJss RSSE~BLE~ p~riE: 1 ~AIN~

I ~ RECEIVER SOFTWARE LlSTING

4 i ~COPYRIGHT 1982 S CHAME:EkLAIN ~ANUFACTURING COh~PORATION
6 ALL RIGHTS RESERVED"

g OOIF CK8UM - 1-15 ~CHECKSUM
11 001E BLK4 - 1-14 IINFOR~ATION ELOCK 4 12 001D BLK3 - 1-13 ~INFORMATJON BLOCK 3 13 OOIC ELK2 - 1-12 ~INFORMATION BLOCK 2 14 OOIB BLK1 ~ INFORMATION BLorK 1 OOIA IDNUM - 1.10 ~I. D. NU~EER
16 002F IRIN - 2,15 ~INFRARED INPUT COUNTER
17 002E COUNTO ~ 2.14 ~GP COUNTER O
18 OOZD COUNTI ~ 2.t3 IGP COUNTER I
19 002C COUNT2 - 2.12 ~GP COUNTER 2 003F SCRATC ~ 3.1S ISCR~T~ PAD REGISTER
21 003E BRPNT ~ 3.t4 .' I-BR ~EMORY POINTER
22 ooæD ~DPNT ~ 3.13 ~BD MFMORY POlNTEk 23 003C CO~PS ~ 3-12 sCOMPAkE REGISTER I
24 003B COMP2 - 3.11 ~COMPARE REGISTER 2 2S 003A CNTROL - 3-10 ~CONTRol WnRD REGISTER
~6 00~- NOl ~ er~a~r~ P~rl RE~TC.T~R

.

.

;~5 ~Z~53~

,~7 Cit)tlF ~C1~5U~ ' O,t~
2S OOOE kELK4 - 0,14 29 00~ RE:LK3 - 0,13 OOOC RBL~2 - 0,12 31 OOOR RBL.Kl - 0,11 32 OOOA RIDNU~ ~ 0,10 33 0009 ~LAGl 0,9 34 ;INITIALIZATION

3~ 001 3E LBI SCRATC

38 003 40 cn~P
39 004 3E LBI SCRAT~ .
40 005 333Q OMEi ;INITJALIZE Ç PORT
41 007 333C CAM~J IINlTlALIzE L PORT
42 009 3360 LEI O ~TRI~TATE L PORT
43 OOB 50 CAr: ~SET Sl AS SHIFT REG15TER
44 OOC 333E OBD ~SET 50 - O
- ~INITIALIZE D PORT
4~ OOE OB LEI FLAGl 47 OOF 4D S~E O ~SET RE~ FROM NVRA~ FLAG
48 010 39 LBI CNTROL iSTORE CONTROL WnRD

50 012 3387 LBI 0,7 ~INSTITUTE AN ~RRAY RECALL
~1 014 333E oBn CVCLE
S2 016 OE LBI 0,15 ,. : '' .. ,, _ . . _ _ .. .. .. __ . _ _._ . _ .. . . ..

3~

12q~i~530 CtP CRnss ASSE~PLEk PPtiE: 2 MAINPR

53 017 333E bED

55 OIB 3F START: LBl NOUSE ;CHECt FOR PROGRAM 5WITCH
5~ OlC 332E INL ~CLOSURE

S OIF ~OFI JMP BFCJN iNn. MONITOF RECEI~F INPUT
59 021 08 N~EN: LBI FLABI ;YES PRnCRAM SWTTGH CLO:ED
~0 0~2 47 S~B I ;SET PRnBRAM FLA~
61 n23 3F LBJ NOUSE ~CHECK FOR ALL ZERO INPUTS

~3 025 06 X O
64 0:r6 IA LBJ ELKI
65 027 21 SKE iBLKI~O
~6 O-r8 FS JP BRl 67 029 IB LBI E~LK2 ~8 02A 21 SKE ~BLK2-0 69 02B F8 ~ JP BRI

71 02D 21 SKE ,FtLK3~o 72 02E F JP ~RI
73 02F ID LBI PlK4 74 030 21 SKE ~ I-BLK4~0 76 032 OA LBI 0 ~1 ~ALL BLOCKS EQUAL O
77 033 7F CTII 15 ~STORE DEF~ULT NUMEER
7~ 034 7E . ST1I 14 7~ n35 7n 8TIT 13 . _ . . . .. . . . .

~ zq~30 r~ 0~ C~

2 03 ~A3D BR~: JSR ~ANrlOM l8ENERATE NEW kAtJDOM Nllt1rER
B3 03A 0~ BR2: Lel 0~ TRAN~:FER 8ENERATEII NUMF.ER
B4 03~ i5 LD I iTO BLOCl'i I ~HRU 4 BS 03C Ok X O
B6 03D or~ LEI 0 a 87 03E ~5 LO I

90 04l 15 LD 1 91 04~ ~ X O
92 043 OD LF:I O t4 93 044 l5 LD I
94 04S )6 X t) 95 046 08 LBI FLAG1 IPROGRAM NEW COrlE
96 047 4C RM~ O ~TO NVRAM

99 04A ~9D7 JSR NVRAM
100 04C 3F Lel NOUSE ~ lNSTlTUTE A STORE COMMAND
101 04n ~r~ ~ 5TII ~3 lOZ 04E 3F LBJ NOIISE
103 04F 333A OM~
104 051 3F L~I NOUSE

. , .

~8 lZl~G530 COP ~055 ~':SEMELER PAGE: 3 ~AI~PR

10~ 052 7F STII ~5 ;TEk~lNATÆ STO~E COM~AND
10~ 063 3F LBI NOUSE

108 ........... ICALCULATE DATA BLOCK SHESKSUM
~09 05~ 00 CLRA
110 057 IA LBI eLlt l 112 059 IE LkI 8LK2 113 O~A 31 ArlB

116 05D lD LBI BLK4 117 OSE 31 hDD

~19 060 06 X rJ
12b I TRANS~IT SYNC PULSE
121 061 3B INlTX: LBI CO~PI IINITILIZE COMPARE REGISTER

124 064 3B LkI COMPl 12S 06S 3369 LEI 9 ~SET EUr~-l, SO~I
126 067 51 8R19 AISC I ITRANS~IT LOGIC I
127 063 21 SKE ~FnR 500 USEC.
128 069 E7 JP Bkl9 129 06A 3361 LEI ~ iSET EN3-0~ SO=O
130 06C 3E LEI COMPI ITRA~BMJT LOCIC fl ~ 7n ~T~T ~. ' ;Fn~ FC
.... .. _. _ __.. ~ __ ._ .. ._ . ., _ _.. . . . . . .
, "' ',. ' ,' ;' '''' '' ~ ' .

lZ0~53~

13~ f)~F ~ I.fiii 133 04F :~r; LeJ OOMPI
~4 070 5t e~70: A~O
13'~ 071 44 NOP
13~ 072 21 SKE
i37 073 6070 J~P r~20 139 Q7b C4 NOP
140 iTRANSMlT rJATA BLOCK
~41 077 3C LBI S~PNT ~IN7TIALIZE BD POINTER TO
142 07~ 7B STII 11 IFlfiST ANk LAST LQCaTl~lN OF
143 079 3A Lel COMP2 iDATA TO eE TRANC.MJTTE~

145 07B 3C NXBVTE: LBI 8nPNT
14h 07C 25 L~ 2 147 07n so oAr:
148 07E 3.3hl LEI 1 ~SET EN3'0,SO~O

149 080 13 SKMSZ 3 ICHEcK L~GIO STATUS nF r~JT 3 150 081 84 JP ~RZI ;RQM B3-1 151 OB2 32 RC i RAM B3~0 152 083 8S JP Bk22 ~3 084 22 bR2~: ~C
IS4 085 6AlF 8R22: JSk TXMIT
155 087 3E L.kI SCRQ'rC ~140 USEC. OELAY
15h 088 7E STII 14 . .

, .

. S~

'lf~53'0 , ~OF C`P~!SS A55EM~LER PA~E: 4 M~JNPfi 157 Og9 3E LBI SCRATC
156 06A 0~ X O
1S9 08B Sl AISC I
1~0 08C ~e ~P .-1~1 08D 44 ~op 1~2 08E 3C LBJ BDPNT
163 08F 25 L~ 2 1~5 091 3361 LEi I ISET EN3-O,SCI=C) lb~ 093 03 SKMeZ 2 iCHEt:~'. LOGJC '.TATUS OF E:IT 2 167 094 97 JP BRZ3 ~kAM B'~l l~Bi 095 32 RC ~RAM ~2CO
1~9 09~ 98 ~ JP BR24 17~ 097 22 ~3: SC
171 09g ~AlF BkZ4: JSR TXMIT
172 09A 3E LBI SrRATC~ 0 U.SEC. DELAY

174 09C 3E LBI SCkATC
S75 09D 0~ X O
17~ OYE 51 AISC I
177 09F 9E JP .
17~ OAO 44 NOP
~79 OAl 3C l.BI PDPNT
l~n OA2 25 LD 2 ~81 OA3 SO CAB
182 OA4 33~1 LEI 1 ~SET EN3~0,5CISO
lg~ KM~7 ~ HFr:l lnr~ T~T~C nF ~I
.. ...... _... .... . . ..

~f~

3.ZG3 ~530 1:5 OAB 32 kC ~RAM Bl=O
IB~ OA~ AE JP BR26 187 OAA 22 BR25: ~C
188 OAB ~AlF BR26: JSR TXM}T
1:9 OAr~ 3E LBI SCRATÇ
190 O~E 7E STII 54 191 OAF 3E Lfl SCRATC
192 OBO 0~ X O ;16C) U~EC. DELAV
193 OEI 51 hlSC I
194 OB2 Bl UP .-1 1~5 OS~ 4~ NnP
196 OB4 3C LeT BnPNT
197 or~s 25 l~ 2 19 0~ 50 c~r~
199 OE7 33~1 LEI 1 iSET EN3~-J,SO=O
200 OE~ 01 SN'~BZ O ~CHECI' LOGIC STATU': OF BIT O
201 OBA BD JP BR27 IRA~ BO'l 202 or~B 32 RC ;RAM BO~O
203 OBC BE JP BR;~3 '~04 oBrJ 22 BR27: SC
205 OEE ~AlF BR2: JSR TX~IT

Z06 OCO 3C LBI BrlRNT ~INCREMENT B~ POINTER
207 nCI b5 LD O
~08 OC2 5~ ~ISC I

. _ _. . .. _ .. _ _ ._ _ . ... .. ..... . . .

-~20i~S30 .

COP CRO.C.5 ASSEilElEk PA~E: 5 MAlNPr~

20~ OC3 44 NOP
2~0 OC4 06 ~ o 2~1 ~C5 05 L~ O
212 OC6 3A LRI COMP2 iLAST ~FMOkY LDCATJON
213 OC7 21 ~KE ;TRANSMJTTFD
2~4 OC8 ~o7e .JMF NXBYTE ;Nr~
215 OCA 44 NnP ~y~c 21B OC:R 33hl LEJ I
2~7 ocrl 3R L.BI COMP~

219 OCF 00 CLkA
220 ODO 3R LF:J COMPI

222 on2 44 NOP
223 ~TkANSMJT TEkMlNATOk 225 orl4 78 STJI
226 OD5 00 CL~A
227 ODh 3~ LBI COMPl 228 OD7 33~9 LEI i ~SET EN3-1. SO-I
229 OD9 51 BR29: AISC 1 ITkANS~lT LO~ilC I Frlk SO(I USF
230 OnA 21 S~F

232 ODC 3361 LEI ~ ISET EN3~0.SO-O
233 TRANSMIT BLAN~ TJME OF 5 MSEC
234 OnE 3A LBI cnMp2 ilNJTIALIzF CO~PAkE RE~ilSTFR
~ nF 7n ~T7 ~ ~) , _ . .. . , .. . .. .. . .. _ _ .. . ... .
. ' , ' ,' . ' ,' , '' "' . ' ' ,' .

.

.
~L3 :~2C~530 ,L ~ r l 7 s 237 OEI 2C LE~I COUNTl ~RESET COIINTF~ REril';TERS
~3' t.)E2 7b STII O
23~ OE3 70 6TII O
240 OE4 6At.)6 JSR ~IMEk 241 OE~ 3F LBI NOUSE ~CHECh' FtlR PPtlGRQM
242 OE7 332E lNL ~SWITCH CLOSUkE
243 OE9 13 Sl ME:Z 3 244 OEA Fl JP EFr;lN ~SWITCH NDT CLOSED
24S OEB oe LEI FLA~ WJTCH OLOSED
246 OEC 11 SI~MB7 1 ~ IS PRO~RAM FLAn SET'~
247 OED 6061 IMP lNlTX ~VES ~F.TRAN ;MIT DATA
248 OEF 602~ JMP N~EN i tJrl GENFR~iTE NF~ RANrltlM NuMr:F.
249 OFl ori BEtiIN L.BI FIAri~

2~1 OF3 3362 LEI 2 252 OF5 3C LkI kDPNl ;INITIAL~7E kFCElVFrl DATA
253 OF6 7A STll ~0 IMFM lR~ POlNTEk 254 OF7 2n LBJ CnlltJTt. ;PFSET CnUNTER IklN
255 OF8 70 STIl O
256 OF9 70 STll O

25B OFB 70 BTlS O
259 OFC 70 STIl O
2~0 OFD ~104 JMP JT4 _ . .. . _ .. _. .. . . . . . .

, , ' .

.

120~i530 COP cPrlSS ASS~M~IEP Pb~E:
~AINPR

262 100 336r.~ LE} O
2~3 102 601k JMP START
264 104 70 JT4: STI1 0 266 106 70 STIT o 2~7 107 70 ST17 0 268 108 2r, LkI CrlUNTC) 26~ 10~ 3-~0~. S~GBZ O ~ IS iNPl!T A LOCilC 1 'f 270 ~Ok CF JP LOCIK1 iYES
271 10C 60F1 JMP BECiIN ;Nrl 27~ 10~ 00 LOn~1: CL~A

274 110 3301 Bh'5 SKGB7 0 ~J5 INPLIT STILL A LO~iIC; 1 ?
275 1i2 D5 JP 8R4 . ~YES
Z76 i13 60F1 JMP r~EGIN ~ND
277 11S 51 ~BR4: AISC 1 278 116 no JP BR5 27~ 117 06 X O

Z~ 06 X O

284 11C 610E JMP L~OK1 Z8S 11E 2E LRI IRIN ~VaLID 10 MSEC. BLANK TIME
286 1lF 00 CLRA
287 120 3301 ~(riRZ O ,IIS INPUT A LOGlt; O ?
.. , .,, ., ... . .. _ .. ~.. ... . .. .

/~5 ~2~s30 .

289 123 51 BR6: aJ.5t; i ;YES
~0 124 ~nl s~n~z o .7S INF~UT STJLL a LtltiIo o -, 291 1~6 E JP Bk7 ~Nn, RI~JNri TkAN~,ITJtJN rlETFt:TI
292 J27 E3 JP Bkh ~YES
293 128 0~ BR7: X O ;STOkE r:OllNT IN 7kJN
294 129 05 LD O ;SllBTRAC:T CORRECTJClN FAt;TOR
295 12A 5E AISC 14 lFOh ~A~PLE VALUE
296 12B 44 NnP
297 12C 2C LBI COUNT1 lSTORE SA~PlE VALUE
Z98 lZD 06 X O ~IN COUNTEk 1 299 12E ZE LBI IRIN ~CHEW FOF. OVEkFLtlW
300 12F 00 ClhA

302 1~1 F4 JP REPEbT ~NO OVEhFLOW
303 1~2 601E JMF' Ç:TAFT Jn~ERFLOW EXISTÇ.
304 134 ~01 hEPEAT: ~KrEZ O ;CHFr:l~ FOR FALLJNr.i TRANC;JTlO
305 136 F4 JP -2 iINPllT STILI HltiH
306 137 69Cf; JSR SPMPLE ~Fbl.LIN~ TkANSITION BETErTE~
307 13~ 3C LE~I BnPNT ~POINT TO RE'CEIVE r~ATA POINTE
30g 13b 35 L~ 3 3~o 13C ~0 ~ S~'C
311 13n 6140 J~P'Bh8 ,, , ' '~ I
~ .

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314 142 C4 IP RR~ ~INPUT 8TILL HJGH
315 143 CO JP RPk IINPUT ~TILL LOW
316 144 3301 BR9: ~K~BZ O
317 146 C4 JP .-2 ;INPUT STILL HIGH
31B 147 ~C~: JSR S~PLE ;F~LLJNri T~ANs~Tln~ IIETECTED
31~ 14~ ~r. LBI BnPNT ipr!TNT TCI kEOEIVE DATA POJNTEi 321 14B 50 CAB~

3~ 14n ~F ~P r~R
324 14E 4~ ~r ~
32S 14F 330~ BRIO: 8KC~Z O ~LonK FOR FALLING TkANSlTJON
32~ 151 D3 JP BRII INPUT STILL HIGH
327 15Z CF JP BRIO IINPUT ~TILL LOW
328 153 3301 BRII: SKLBZ o 32~ 155 D3 JP .-2 ~JNPUT STILL HJGH
330 ISb 6~C~ JSR SAMPLE IFALLING TkAN~:lTlON DETECTEB
331 ISB 3C LBI PDPNT ~P4INT TO REr:Flv~ rl~TA POINTF
332 IS~ 3C Ln 3' 333 15A 50 CAB , .-334 as~ ~o ~;KC: ~' 33~ 15D 47 ~M8 1 337 ISE 3301 BR12: cKriBZ o ILOOIC FOR FALLING TkANSlTlON
33B 160 E2 JP eR13 ~INPIJT STJII HI~iH
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.

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34C~ 16Z 33AI BR1;.: ~ 8B. o 341 164 E2 ~P .-Z ~T~PUT STlLL HlriH
342 16'. 6~C8 J.Sh~ SAMPLE iFALLlNC TRA~SITICIN DETEt,TEl;
343 167 3C LBI Br~PNT ~PO~NT Tb kECElVE rJATA pr-~Jhl--346 1~ 20 SKr-347 14B ED JP Bfil4 348 14C 4D s~r~ O
349 16D 3C BR14: LBI BnpNT ~INCkE~ENT BD POlNTFk 351 16F 51 AJSC I ILAST ME~tlRY Ktlr-ATltlN FILLF' 352 170 F2 .1P RklS INb 353 171 F8 JP 8rkl6 lYFS
354 172 0~ r~k~5: X O
355 173 3301 BR17: SKtiEZ O ~Lonh FnR FPLLlNCi TkANSIT
3~6 175 4134 .l~P RFPEAT 11NPllT STlLL Hl~H
3S7 177 F3 JP BR57 llNPUT STILL LOW
35g iCALCULATE RFr:ElvErl DATa CHECKSU~
359 178 00 8kl6: CLkA
360 179 09 LEI klDNl1 361 l7A 31 Anr~
3hZ 17B OA LBI RBIK1 3h4 17D OE L8I RBLK2 3hg 17E 31 ADD
3h6 17F OC LBI kWI~3 .

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3~7 180 31 anr.
3b8 181 OD LBI RFILK4 3b9 182 3I flDD
370 t83 OE LBI RCKSUM
371 IR4 2I Sl E ~ CI~FCK5IJM CllRR~CT
372 tt. 601B .IMF START ~ C~lFCKSl.I~-1 INr.rIriREC:T
:373 It;7 b~: I.BI FLAC;I
374 1 8æ 4rl SMk O SET REArJ FRrll~l NVRAM FLA8 :375 189 3$ LB7 CNTi;nl I :TI hE CnNTfirll- wr k 37~ 18A 77 STJ T 7 :377 18B 33~7 LBI ( 7 ~ INC;TlTUTr AN AfiRAY RECALL378 18rJ 333E OBD i CVCLE
379 lBF OE LBI 0 15 3t l 192 69D7 JSR NVkAM
385 194 IA ~ LgI F:LK1 ~ Cl-lECh FOR RANDOM
383 15~5 1~5 LD I i NIJMBER PlATCil 386 199 IB LBI P:LK2 -38F1 191~ 21 SKE
3B9 19C bOIB JrP 8TART
390 19E IC Lel E~LK3 3i l 19F 1 LD I
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399 lA~ 473 SMb` 3 400 lAA or, LD O
401 lAfi 40 COMP
402 lAC 333C EAM~
403 lAE 33~4 LEI 4 404 lEO 3A LEI COMP-~ TNITILJZE C:nMF'AkE FkErilsTEF~.c;
405 lEI 7F STIJ IS
406 IR~ 7F STTT 1'~
407 lF.:~ 2F Lr~:7 IR7N
4n~: Ir~4 70 æTlI O
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412 lE~ ~A06 JSk TIMEk 413 IBA 2E LBI IkIN
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415 IBC 51 ' AISC I
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420 lC4 3360 JT3: LEI O
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429 I cn CA JP fiUEI
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439 ID9 7E ~iTII 11 440 lDA 3C iUB6: LEI EnPNT
441 lnk 25 Ln 2 iOUTPUT ADDRESS POJNTErl TO
447 lnr -,1 AJ~r: 1 i~ rn~PARF PFriTc~TFR

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490 Z13 05 LD O ICOMPARE RE~ISTERS
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S31 I FCik A NFW kANnO1~1 NIIMRER GEl~iEkhTErl IN bNrl sTtlRi-rl IN
532 i~O,II) THkU ~0,14) 533 23~ 3C RANDOM: LEI E:nPNT
534 23E 7E ~;TJ J 14 S35 23F IA LWJ EL~I ; XOR BJTS 1 AN~ 2 OF ELKI

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S39 243 02 XOk S40 244 3F LRI NOllSE .-.
S41 245 0~ X 0: ' S42 24~ 03 ~t'.MEZ 2 S44 24S' ~7255' ~1P SUE11 S45 24R 3C SUEI~: LWJ I~DPNT ~ SHIFT LEFT BLOCt~S I Tl;RU
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54~ 24F 4F XAS ISlCiNlFlCANT BIT OF ELk'4 55t'~ 2S0 4F XAS
551 251 17 xns 1 553 253 3C LBI BnPNT
554 2~t 2~ ~ 2 S57 2S7 625E JnP SUE10 558 259 IA SUEJlt: LCI l.ll IXOR OPERATION - C
559 25A 3~3E OkD ~FORCF LEA~T SlGN.r~TT ON
S60 25C 6261 .It1P SUB~ 3 ISHIFT REtil~TEk TO O
5hl 25E IE SUB~C: LEI 1, 15 ~XOR OPEkATlON I
5~2 25F 333Æ OBD FnRCE LEAST SJ~iN EJT nN
563 2~,1 3C SUBI3: LE~J BDPNT ~fi~TFT RE~ISTEh~ TO 1 565 2~3 55 AlfiC 5 S6h 2~4 E7 ~P SUE14 S67 265 624B J~P 8Uel2 ICONTINUE UNTIL FINISHED

S~

572 1 ~COPYklti~T 1982 .-.

' """ '" .-'.'''" ' '' ' , 5~

, c~oss ASSF~riLER RAGE: 12 JNPR

S73 ~ C~AMBERLAIN ~ANUFAC~URINC CORPORATION
574 ~ ALL R~ S RESERVE~"
~75 S7~ ~
577 `.END

.

.. . .

.

.

. .

Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. Apparatus for controlling a radio frequency receiver with a remote radio frequency transmitter comprising a first memory means in said receiver for storing at least one address code, infrared transmitting means in said receiver, a first microcomputer in said receiver capable of accessing said first memory means and for generating a random address code and storing it in said first memory means, a program mode switch means in said radio frequency receiver for energizing said first microcomputer to generate said random access address code and for energizing said infrared transmitting means to transmit said address code, an infrared receiving means in said transmitter for receiving said address code, a second memory means in said transmitter for storing said address code, radio frequency radiating means in said transmitter for radiating said address code, radio frequency receiving means in said receiver for receiving said transmitted code, said first microcomputer in said receiver receiving and comparing the received address code with the address code stored in said first memory, and an output circuit energized by said first computer when said addresses are the same.
2. Apparatus according to claim 1 wherein when said program mode switch means is closed in said receiver said first microcomputer accesses said first memory means and recalls the address stored therein and uses such address as a start to generate said new random access address code.
3. Apparatus according to claim 1 including a second microcomputer in said transmitter connected to said infrared receiving means and said second memory means.
CA000434390A 1982-09-23 1983-08-11 Transmitter and receiver for controlling the coding in a transmitter and receiver Expired CA1206530A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US422,451 1982-09-23
US06/422,451 US4529980A (en) 1982-09-23 1982-09-23 Transmitter and receiver for controlling the coding in a transmitter and receiver

Publications (1)

Publication Number Publication Date
CA1206530A true CA1206530A (en) 1986-06-24

Family

ID=23674946

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000434390A Expired CA1206530A (en) 1982-09-23 1983-08-11 Transmitter and receiver for controlling the coding in a transmitter and receiver

Country Status (4)

Country Link
US (1) US4529980A (en)
JP (1) JPS59160398A (en)
CA (1) CA1206530A (en)
DE (1) DE3332667A1 (en)

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JPS59160398A (en) 1984-09-11
JPH0260120B2 (en) 1990-12-14
DE3332667A1 (en) 1984-03-29
US4529980A (en) 1985-07-16

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