CA1195751A - Apparatus for routing data between low order terminals and high order communications - Google Patents

Apparatus for routing data between low order terminals and high order communications

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Publication number
CA1195751A
CA1195751A CA000411944A CA411944A CA1195751A CA 1195751 A CA1195751 A CA 1195751A CA 000411944 A CA000411944 A CA 000411944A CA 411944 A CA411944 A CA 411944A CA 1195751 A CA1195751 A CA 1195751A
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Canada
Prior art keywords
string
router module
information
routing
units
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CA000411944A
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French (fr)
Inventor
Steven W. Schieltz
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NCR Voyix Corp
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NCR Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q40/00Finance; Insurance; Tax strategies; Processing of corporate or income taxes
    • G06Q40/02Banking, e.g. interest calculation or account maintenance

Abstract

APPARATUS FOR ROUTING DATA
BETWEEN LOW ORDER TERMINALS AND HIGH ORDER COMMUNICATIONS

Abstract of the Disclosure A router module controls interfaces to (a) low order terminals, (b) high order communications to a host system, and (c) a permanent storage device like a digi-tal cassette. The router module utilizes routing logic including a decision table to effect the routing through the interfaces named. The low order terminals include data entry terminals and a printer module and the router module enables several data entry terminals to utilize the printer module. The router module is located on a substrate which can be mounted in one of the data entry terminals to utilize the associated power supply.

Description

X7~i~

APPARATUS FOR ROUTING DATA BETWEEN
LOW ORDER TERMINALS AND HIGH ORDER COMMUNICATIONS

Background of the Invention This invention relates to an apparatus for routing data among low order terminals and a host computer system and for use as a concentrator.
In certain environment3 such as banking or retailing, for example, it is desirable to share certain peripherals with a group of terminals. For example, in an effort to reduce the cost of small banking systems, it was desirable to provide one printing peripheral or module for several financial terminals. This is especially true for small bank branches. A common method of providing one printer for several financial terminals was to provide a mini-computer system which provided the communications interfaces among the several financial terminals. The mini-computer system was housed in a separate cabinet, requiring its own power supply and had a random access memory (RAM) which had to be programmed. ~his necessitated a system analyst at each bank to develop the necessary software which was unique for each bank.

Summary of the Invention In accordance with one aspect o the invention, there is provided in combination, a host system; a plurality of terminal units including first units, at least said first units having means for entering at least routing data thereon; said routing data including a logical origin address (LOA3 which indicates the origin of a string of information to be routed and a logical destination address (LDA) WhiCh indicates the intended destination of said string of information; a router module for receiving a said string of information including said routing data and for routing said string of information to selected `7 c~

- la -ones of said plurality of units or to said host system in accordance with said routing data; said router module comprising: first coupling means for coupling said router module with said host system for transferring said string of information to and from said host system; second coupling means for coupling said router module with said plurality of terminal units for transferring said string of information from one of said terminal units to at least another one of said terminal units; and routing logic including a decision table which utilizes said routiny data to route said string of information in accordance with said routing data.
Some of the advantages of the router module of this invention are:
1. It provides a low-cost concentrator in environments in which the number of terminals or peripheral devices is approximately 12 or less.
2. It has the capability of being attached to a variety of communications protocols.
3, It provides message routing capabilities within the low order link to enable several terminals to share a peripheral device such as a printer.
4. It provides an interface to enable a data recorder such as a digital cassette recorder to be /
___ _ _ _ ~ __ .. _ ~._ ..... ., .. . _ . ... _ _ ~7~

attached at a concentration point within the system for data capture, program load, program dump, and data re-entry.

Brief Description of the _rawin~
Fig. 1 is a block diagram showing an environ-ment in which the router module o this invention may be used;
Fig. 2 is a diagrammatic view showing a type of protocol which may be used with this invention;
Fig. 3 is a block diagram showing how the router module of this invention may be incorporated within the housing of one of the terminals shown in Fig.
l;
Fig. 4 is a schematic bloc~ diagram showing how several router modules may be coupled to a host system; and Fig. 5 is a diagrammatic block diagram showing one embodiment of the hardware used to implement the routing logic shown in Fig. 1.

D _ iled Description o~ the Invention Flg. 1 ls a block diayram showing the router module of this invention which is shown within a dashed rectangle and is designated generally as 20. To illus-trate the invention, the router module 20 is shown in a banking environment although its use may be extended to other environments.
In the banking environment shown, the router module 20 ~Fig. 1) is coupled to a host system 22, which in the embodiment described, could be a central computer system for the associated bank.
The router module 20 (Fig. 1) is also coupled to a plurality of terminals such as terminals 24, 26, and 28, and a printer module 30 via a bus 32. The terminals 24, 26, and 28 are identical and conventional, and are shown only in partial diagrammatic form; each such terminal includes a microprocessor (.~P) 34, a memory system such as a read only memory (RO~I) 36, a display unit such as a cathode ray tube (CRT) 38 and a data entry means such as a keyboard (KB) 40. The print-er module 30 may be conventional and includes a MP 44, aROM ~6, a display such as the light-emitting diode type (LED) 48 and a printer 50 for printing on record media such as ledger cards, passbooks, and the like.
The router module 20 (Fig. 1) is also coupled to a conventional cassette terminal 52 which is used, for example, for data capture, program load, program dump, and re-entry functions.
The router module 20 lFig. 1) includes a Data Link Communications (DLC) low order or primary driver 54 which includes a memory device such as a ROM 56. The primary driver 54 is used to transfer information from the terminals such as 24, 26, 28, etc. to the host system 22 via the high order communications secondary driver 58 and the routing logic 60.
The secondary driver 58 (Fig. 1) essentially provides a handsha~ing function between the host system 22 and the router module 20. The driver 58 may be conventional and can be made in accordance with a number of different protocols, such as International Standards Organization (ISO), binary-synchronous (bi-sync), Data Link Control-Common Carrier (DLC-CC) and Data Link Communication (DLC). The ISO protocol is not complete in itself and is generally modified by the company using it. For example, there may be a Burroughs ISO, an NCR ISO, etc. The ISO and bi-sync protocols are char-acter" protocols. The characters in these character protocols generally utilize the ASCII format. The DLC
protocol is a bit-oriented system in which data is pre-sented in the form of long strings of binary l's and 0's as will be described hereinafter in relation to Fig. 2.
The router module 20 (Fig. 1) also includes a conventional cassette driver and manager 62 which pro-vides the interface between the router module 20 and the cassette terminal 52.

''~~'` 3 ~.~s~
_q _ An important feature of this invention is that the router ~odule 20 (Fig. 1) enables the terminals like 24 and 26, for example, to communicate with each other without the intervention of a complex computer system as earlier explained herein.
Another feature is that the router module 20 tFig. 1) may be mounted on a substrate 21 and incorpor-ated within one of the terminals like 24 as shown in Fig. 3. The terminal 24 is housed within a conven-tional cabinet 64 (shown only in dashed outline in Fig.3), and the router module 20 is housed witnin the cabi-net 64. ~ach of the terminals like 24 and 26 has its own power supply (PS) 66 associated therewith, and conse-quently, the router module 20 is designed to utilize the power supply 66 of the terminal like 24 in which it is housed.
Earlier herein it was stated that DLC protocol used is a bit oriented system. In the embodiment des-cribed, the information which is sent up from the ter-minals like 24 and 26 has the format of the data string66 shown in Fig. 2. The data string 66 is comprised of 8 bit bytes with the entire string 66 being comprised of up to a maximum of 256 such bytes, for example, although this number could be changed to suit different appli-cations.
The first three bytes of the data string 66(Fig. 2) are referred to as the DLC header and are embraced by bracket numbered 68. The header 68 is comprised of an 8 bit flag (F) byte, an 8 bit address (A) byte, and an 8 bit command status (C/S) byte. The DNA header which is embraced by a bracket numbered 70 is comprised of an 8 bit packet format (P/F) byte, an 8 bit packet type (P/T) byte, two 8 bit bytes of a logical origin address (LOA), and two 8 bit bytes of a logical destination address (LDA).
The data string 66 (Fig. 2~ also includes a DLC trailer which is embraced by the bracket 72 and
5~

which is co~prised of two 8 bit bytes of a cyclic re-dundancy check (CRC) and an 8 bit flag byte (F). The CRC provides a cyclical redundancy check for chec~ing any errors of transmission which generally are due to noise occurring during transmission. The check is effected by a ~onventional complex algorithm by a hard-ware integrated circuit associated with the serial interface unit 106 shown in Fig~ 5. The binary data 74 which is to be transmitted in the data string 66 lies between the DNA header 70 and the DLC trailer 72 as shown.
The DLC header 68 and the DLC trailer 72 of the data string 66 (Fig. 2) are used to get data from the terminals such as 24 and 26 (Fig. 1) and the printer module 30 to the DLC communications primary driver 54, to the router module 20, and back to the various ter-minals like 24 and 26 and the printer module 30 in the example being described. For communication with regard to the host system 22, the DLC header 68 and DLC trailer are used to get information from the secondary driver 58 to the host system 22 and vice versa.
As stated earlier herein, the amount of binary data 74 (Fig. 2) within a data string 66 may vary. In the embodiment described, a data string 66 may be up to 25 256 bytes long with up to 244 bytes being provided for binary data 74. The primary driver 54 (Fig. 1) has a buffer (not shown) to receive up to 256 bytes of infor-mation in the embodiment being described. Because the data string 66 may be varied in length, the driver needs some means for determining how long the binary data 74 is in a particular data string 66. This is accomplished by including a conventional circuit in the primary driver 54 which is triggered to start counting by the flag byte (F) in the DLC header 68. A count of 7E (in hex code) for example, can be used in the flag byte (F) to initiate the counting. Because the DLC header 68, the DNA header 70, and the DLC trailer 72 are of a fixed length in a data string 66, when the flag byte F in the DLC trailer 72 is received, it is ~sed to trigger a subtraction in the serial interface unit 106 associated with the primary driver 54 which subtracts a fixed num-ber of bytes from the count which was initiated by theflag byte in the DLC header 68 to arrive at the infor-mation included in bracket 76 in Fig. 2. The DNA header 70 in bracket 76 is used to provide the routing infor-mation to the routing logic 60 in Fig. 1 as will be described hereinafter. The flag byte (F) included in the DC trailer 72 also has a designation of 7E in hex code.
The routing logic 60 (Fig. 1) always uses the DNA header 70 data to ascertain where to send the asso-ciated binary data 74. The routing logic 60 functions as though it were handling a "hot potato", in that upon receiving the information included in bracket 76, the routing logic 60 immediately transfers the information to one of the three drivers 54, 58, or 62 (Fig. 1).
The method by which the information is trans-ferred or routed via the routing logic 60 is handled by the Decision Table shown hereinafter in Table lA and Table lB. Tables lA and lB should be read together with Table lB being placed to the right of Table lA so that ~ines lb through 18b of Table lB are aligned with Lines la through 18a, respectively, of Table lA.

TABLE lA

ORIGIN
OF LOGICAL DESTINATION ADDRESS
RECEIVED
MESSAGE (LDA) OF RECEIVED MESSAGE
.

LOW S3_so Line laORDERS15 through S4 0000 2a ANY " " " 0001 3a " " " " 0010 ~1957~

Table lA Contin~ed 4a " " " " 0011 5a " " " " 0100 6a " " " " 0101 7a " " " " 0110 8a " " " " 0111 9a " " " " 1000 lOa n 1l 1l 1l 1001 lla " " " " 1010 12a " " " " 1011 13a " . ~ n 1l 1100 14a " " " " 1101 15a " " " " 1110 16a " " " " 1111 17a LOW ORDER 0000 0000 0000 0000 18a LOW ORDER ANY OTHER LDA

TABLE lB

DESTINATION TO WHERE ROUTER MODULE

Line lb RM (ACTIVATION ~ESSAGE FOR RM) 2b LOW ORDER INDIVIDUAL LINK ADDRESS 0001 3b ~ n 1l ~ O 01 0 4b " " " " " 0011 5b n ~ n ~ 0100 6b " " " " " 0101 7b " " " " " 0110 8b " " " " " 0111 9b " " " " " 1000 lOb " " " " " 1001 llb " " " " " 1010 12b " " " " " 1011 13b " ~ " " " 1100 14b RESERVED
15b RESERVED
16b DIGITAL CASSETTE DRIYER - MANAGER

~19S7S:~

Table ls Continued 17b LOW ORDER PRIMARY DLC DRIVER (PING PONG
TEST REQUEST) 18b HIGH ORDER LINK

Before discussing the contents of the Decision Table shown in Tables lA and lB, it appears appropriate to discuss the coding involved therein. While Fig. 1 shows only one router module 20 associated with the host system 22, more than one router module may be utilized as shown in Fig. 4.
Fig. 4 is a schematic diagram in block form showing how several router modules like 20, already discussed, may be coupled to the host system 22. The router module 20, also marked as #1 in Fig. 4, is coup-led to the host system 22 by a conventional common bus 78. A second router module marked as #2 and reference numeral 20-2 and a third router module marked as #3 and reference numeral 20-3 are also coupled to the host system 22 via the bus 78 as shown. Router module 20-2 has terminals 80 and 82 and the cassette terminal 84 associated therewith, and these terminals may be iden-tical to terminals 24, 26, and 52 associated with router module 20. Similarly, router module 20-3 has terminals 86 and ~8 and cassette terminal 90 associated therewith.
The router modules 20-2 and 20-3 may also have printer modules (not shown but similar to printer module 30) associated therewith to enable several terminals like 80 and 82 to utilize a printer module in shared relationship as previously described.
In the embodiment described, the identi~ica-tion coding for the modules and terminals shown in Fig.
4 is given in hex coding and is shown within parentheses within the associated block or moduleO For example, router module 20 is identified by the (OOlX) coding shown therein. The "X" in the coding represen~s "don'~
care" bits. The terminals 24 and 26 are identified by the (0011) and (0012) coding shown, and the printer module 30 is identified by the (0013) coding shown. The cassette terminal 52 is identified by (OOlF) in hex form.
To summarize, the identification of the var-ious router modules like 20, is effected by the first three characters (in hex form) within the parenthesis when reading from left to right, and the terminals or the printer modules (like module 30) which are associ-ated with a particular router module like 20 are iden-tified by the right-most character within the paren-thesis (like numeral 3 given in hex form for module 30).
While referring to the Tables lA and lB and Fig. 4, the following discussion will further explain the functioning of the router module 20. A feature of this invention is that the low-order terminals such as terminals 24 and 26 which are "below" the router module 20 perform the decision-making logic with regard to what is to be done to a message which originates at that particular terminal. For example, if terminal 24 (Fig. 1) were to send a message to the printer module 30, the message would have the appearance of the data string 66 shown in Fig. 2 in which two 8 bit bytes for a total of 16 bits are provided for the LDA and a similar amount is provided for the LOA. In this instance, the destination address (LDA) is (0013, in hex orm), repre-senting printer module 30. Loo~ing at line 4a in Table lA, the twelve bits S15-S4 (high order) represent the identification of the router module itself as already explained in relation to module 20 in Fig 4, and the last four binary bits (low order) on line 4a (a binary 3) represent the identification of the printer module 30. The twelve bits S15-S4 are the high order bits and they are strapped or fixed to the router module 20; in other words, data from any low order terminal like 24 or 26 will be forwarded directly to another low order terminal like 28 associated with that router module 20 - ~ o -by the module 20. Line 13a in Table lA indicates that data from any low order terminal like 24 in Fig. 1 will be routed to the low order terminal (OOlC) in hex form or terminal (1100) as written in binary form in Table lA, with this last-named terminal not being shown in the drawings.
From line 16a in Table lA, a LDA of 1111 (in binary form) indicates that a message from any one of the terminals like 24, for e~ample, which terminals are associated with the router module 20, will be routed to the cassette terminal 52 as shown in Fig. 4.
Before discussing how data or information is transferred -to and from the various elements shown in Fig. 1, it seems suitable to discuss generally, the hardware which is associated with the various logical functions or representations shown in Fig. 4.
Fig. 5 is a diagrammatic bloc~ diagram showing one embodiment o~ the hardware used to implement the routing logic 60 of the router module 20 whose logical representation is shown in Fig. 1. The router module 20 includes a processor such as microprocessor (MP) 92, a plurality of random access memories (RAMs) such as RAMs 94-1 and 94-2, and a plurality of read only memory (ROM) units such as 96-1, 96-~, and 96-3, for example, which are conventionally intercoupled by a system bus 98.
Naturally, the number o~ RAM units and ROM units used i5 dependent upon the needs of a particular system. The RAM
units 94-1 and 94-2 are shown only as RAM 94 in Fig. 1, and similarly, ROM units 96-1, 96-2, and 96-3 are shown only as ROM 96 in Fig. 1.
The routing logic 60 (Fig. 5) also includes a timer 100 which is selected to provide a plurality of different predetermined times as needed by the particu-lar routing logic 60 rather than use the MP 92 ~or this function. The routing logic 60 also includes a plural-ity of s~itches such as manually-settable switches 102, with one such switch being provided for each router ~s~

module like 20. In the embodiment described, the switches 102 are used to set the upper twelve bits or S4 through S15 shown in Table lA so as to identify each terminal or module within the system as earlier ex-plained. The terminals, like 24, must provide the full16 bits for identification of the LOA, for example;
however, the highest 12 bits thereof are the same as those of the associated router module. The fu11 16 bits for identification of the LOA or portions thereof may be provided from software or keyboards associated with the terminals.
The router module 20 (Fig. 5) also includes a conventional serial interface unit 104 which is used to interconnect the module 20 with the host system 22, and similarly, the module 20 also includes a conventional serial interface unit 106 which is used to interconnect the module 20 with the terminals such as 24, ~6, ~8, etc. as described in relation to Fig. 1. A conventional parallel interface including unit 108 is used to inter-connect the module 20 with the cassette terminal 52simply to match the type of terminal 5~ employed al-though a serial interface tnot shown) could be used with a matching serial type terminal 52. Conventional line receivers 110 are used to receive signals from the host system 22, and similarly, line receivers 112 are used to receive signals from the terminals 24, 26, and 28. The receivers such as 110 and 112 include transformers to receive signals and to provide line isolation, and also include operational amplifiers to provide proper band pass capability for receiving only the desired signals, for eliminating noise, and for shaping the signals into well-shaped digital signals which are fed into the associated serial interface units 104 and 106 which are digital-type devices. The line drivers 114 and 116 are used to strengthen the signals coming from the associ-ated serial interface units 104 and 106, respectively, to modify the signals into signals which are somewhat more analog in nature so as to provide some line-driving capability, and to provide line isolation (via a trans-former) as is conventionally done. The parallel inter-face unit 108 contains 8 data send lines, 8 data receive lines and several associated control lines (not shown) to strobe data between the router module 20 and the cassette terminal 52. The parallel interface unit 108 may be conventional such as integrated circuit #8255 which, for example, is manufactured by Intel Corporation.
The router module 20 (Fig. 5) also includes a conventional direct memory access (DMA) unit 118 which is utilized to avoid having the MP 92 directly effect the accessing oE memory. This aspect will be discussed hereinafter.
The software associated with the primary driver 54 lies in ROM 56 (Fig. 1), the software associ-ated with the secondary driver 58 lies in a ROM 120, and similarly, the software associated with the cassette driver and manager 62 lies in a ROM 122. The software associated with the drivers 54, 58, and the manager 62 is conventional and is dependent upon the particular system or protocol used; consequently, it will not be discussed in detail herein. The ROMs 56, 120, and 122 are shown as separate items for ease of illustration;
however, they may comprise a portion of the ROMs 96-1, 96-2, and 96-3 shown in Fig. 5.
The software associated with the router module 20 lies in portions of the ROMs 96-1, 96-2, and 96 3 shown in Fig. 5. Basically, there are three major subroutines forming the software for the routing logic 60; they are:
(a) Subroutine 1, which processes all re-sponses from the terminals such as 24, 26, etc.;
(b) Subroutine 2 which services high order output messages going to and coming from the host system 22; and (c) Subroutine 3 which performs the routing logic associated with the Decision Table shown in Tables lA and lB discussed earlier herein. Subroutine 3 is called by Subroutines 1 and 2.
Subroutine 1 is part of the primary driver 54 shown in Fig. 1, and it carries out the main functions thereof. Subroutine 1 performs the usual handshaking and protocol associated with the data link communications (DLC) mentioned earlier herein. For example, if one of the terminals like 24 in Fig. 1 wishes to send a data message to either the host system 22 or one of the other terminals, such as 26, the primary driver 54 checks the data string 66 (Fig. 2) to make sure that a proper format exists. After the usual handshaking procedures, a point is reached in the processing by the primary driver at which it determines, after protocol error checking, that the data string 66 is in the proper format and is correct. At this point, the primary driver 5~ calls the router module 20 to pass that por-tion of the data string 66 shown in bracket 76 in Fig. 2 thereto. The DLC header 68 and the DLC trailer 72 are used for protocol purposes.
Subroutine 2 is part of the secondary driver 58 shown in Fig. 1, and it carries out the main func-tions thereof. Essentially, subroutine 2 is a high order commu~ications driver and it calls upon sub-routines of a smaller nature in order to effect thatfunction. Because this subroutine may be conventional and is dependent upon the particular protocol used as mentioned earlier herein, i~ need not be described in any further detail. Eventually a point will be reached at which the driver 58 will decide that the data coming from the host system 22 is in the proper format and is correct. At this point, the secondary driver 58 calls the router module 20 to pass the data thereto.
Subroutine 3, alluded to earlier herein, is used to perform the routing logic; essentially, it interprets the Decision Table shown in Tables lA and lB.
The routing logic 60 for the router module 20 is shown in Table 2 which is listed hereinafter.

s~

Table 2 Router Module 20 essentially contains the routing logic for messages, based on a logical destination address.
A. Pseudo-Structured Code:
__ _ 1) IF message destination is a low order, (terminal) THEN return LOWRTE=l,HIWRTF=O.
2) IF message destination is a high order, (host system 22) THEN
2a) Increment Nr count of origin via call to UPDTNR.
2b) IF high order buffers are full or high order line is inactive THEN dispose of message.
ELSE set high order buffer full flag to indicate which buffer message is in and return LOWRTF=O,HIWRTF=l.
3) If message is Ping Pong test request, THEN
3a) Increment link Nr via call to UPDTNR.
3b) Run Ping Pong test via call to PPTDX.
4) If message is to be broadcast, THEN
4a) Increment link Nr via call to UPDTNR.
4b) Swap logical origin address and logical destination addresses.
4c) Set up group 1 address field and unnum-bered information control field (Poll bit = O).
4d) Transmit frame via call to DMAOUT.
5) If message is router diagnostic, THEN
5a) Increment link Nr via call to UPDTNR.
5b) Push return address.

5c) Push 2 byte test number.
5d) Generate table entry address and begin execution at given address.
6) If message destination in cassette terminal 52, THEN
6a) Increment link Nr via call to UPDTNR.
6b) Process message via call to DCMESG.

l_ Table 2 Concluded B. Entry _ int and Calling Sequence-CALL Router Module 20 C. Exit _onditions:
No requirements D. _te n~ Defin_d Subroutines:
UPDTNR - increlnent station Nr count.
RETURN - dispose of undeliverable message.
MOVBUF - move block of memory DMAOUT - transmit frame via DMA
CHSTAT - send RNR message.
PPTDX - execute in-link Ping Pong Test.
DCMESG - process digital cassette terminal 52 message.
E. Other Considerations:
In the embodiment described, an 8085 type micro-processor 92 was used in association with the various programs and subroutines mentioned, and in the process, certain registers associated with the microprocessor 92 were destroyed~ The particular registers which were destroyed were the PSW, B, C, D, and E registers; they are listed here simply to facilitate the writing of other routines which may be associated with the router module 20.

The routing logic 60 is shown in pseudo-structured code beginning at A in Table 2. A descrip-tion of each of the various code words used therein is listed at the end of Table 2. The routing logic 60 is presented in a series of, "If", statements followed by, "Then", statements which define what the routing logic 60 will do under given situations or conditions. A
general discussion of Table 2 will follow.
With regard to Table 2, line 1 thereof states that if a message is to be transferred to a low order terminal like 26, for example, two flags are set. The embodiment described sets a low order write flag (LOWR~F~

equal to a binary one and a high order write flag (HIWRTF) equal to a binary zero. The binary one flag indicates to the primary driver 54 that it may use the data which is in a buffer located in the RAM 94-1 (Fig.
5) and the binary zero flag indicates to the secondary driver 58 that it may not use this data. These flags LOWRTF and HIWRTF are not those flags which are asso-ciated with the DLC header 68 and DLC trailer 72 as shown in Fig. 2, but they are flags which are used by the routing logic 60 to indicate whether the router module 20, the primary driver 54, or the secondary driver 58 has control of the message or data. The router module 20, the primary driver 54, and the second-ary driver 58 can all work asynchronously, and can communicate with one another by the use of the flags LOWRTF and HIRWTF.
With regard to Table 2, line 2 thereof states that if a message is to be routed to the host system 22, then certain counters such as Nr counters are incre-mented to take care of certain housekeeping functions;this is efected by a call to a subroutine which is identified as UPDTNR. The Nr counters (not shown) are utili~ed to indicate to the primary driver 54 that a message has been received correctly and has been pro-cessed lrelayed at a later time to the host system 22).For example, the Nr counters are "scratch-pad" counters which are associated with the MP 92 (Fig. 1), and the term "Nr" stands for "number received" count. In the embodiment described, three bits are reserved for this count and they appear in the command status (C/S~ word of the DLC header 68 shown ln Fig. 2.
Before the message can be relayed to the host system 22, it is necessary first to determine whether or not certain high order buffers in RAM 94-1, for example, are available to store the message until the host system 22 requests it. If there are no available buffers, or if the high order line 122 (Fig. 5) is active as indi cated on line 2b), then the message is disposed of and ~17-the terminal which initiated the message must try again at a later time to send the message. If a high order buffer in RAM 94-1, for example, is available, then the message is transferred thereto, and a flag is set in RAM
94-1 to indicate that this buffer is full. The HIWRTF
flag is then set to a binary one indicating that the communication with the high order driver 58 (Fig. 1) is desired.
With regard to Table 2, line 3 thereof indi-cates a check on an incoming message to determine whetheror not it represents a request for a Ping Pong test. As used herein, this test is simply a diagnostic test to check on the hardware shown in Fig. 5 to determine whether or not it is operating properly and to enable a serviceman to repair the router module 20 if it is not.
Line 3a of Table 2 is identical to line 2a thereof already described. Line 3b indicates a call to a sub-routine PPTDX which contains all -the necessary steps to effect the diagnostic test. Because this aspect is not important to this invention, it need not be described in any further detail.
With regard to Table 2, line 4 thereof indi-cates a check to determine whether or not a message is to be broadcast. As used herein, the term broadcast means the ability of the router module 20 to transmit a message simultaneously to all the associated terminals like 24, 26, 28, and 30 shown in Fig. 1.
Messages are broadcasted in the following situations:
1. If a broadcast program load is requested, the appropriate or selected data records from the cas-sette terminal 52 (Fig. 1) will be broadcasted to the terminals like 24 associated with a router module like 20.
2. If a message is received from the host system 22 and its logical destination address (LDA) is not equal to one of the terminals like 24, 26, 28, or 30 associated with a router module like 20, it will be broadcasted to all of the terminals associated with that router module.
3. If a message is received by a router module li~e 20 from an associated low order terminal like 24, 26, for example, and the message has a logical origin address (LOA) which is not equal to the address of any one of these terminals, it will be broadcasted to all the associated terminals.
With regard to the host system 22 broadcasting messages to terminals associated with a particular router module like 20, for example, the following com-ments apply. Each router module like 20, 20-2, and 20-3 shown in Fig. 4 has its own slightly different protocol associated therewith; this feature enables the host system 22 to select the particular router module like 20, 20-2, or 20-3 with which it is to communicate. In other words, when the host system 22 wishes to communi-cate with a particular terminal like 24 associated with a router module like 20, it first selects router module 20 (via the protocol mentioned), and thereafter the data string like 66 in Fig. 2, which has the appropriate LDA
therein, is used by the router module 20 to route the message to the appropriate terminal. If the LDA in the data string 66 is not equal to one of the terminals associated with a router module like 20, then the mes-sage is broadcasted to all the terminals associated with that router module.
The following Table 3 indicates how a message from a terminal like 24 in Fig. 4 is routed in a broad-cast mode to the other terminals like 26 and 30 associ-ated with the router module 20.

LOA LDA
Line 1 0011 0013 Line 2 1111 0011 Line 3 0011 1111 The numbers shown in Table 3 are hexadecimaldesignations. Line 1 in Table 3 represents a selective transference; it indicates that a data message origina-ting at terminal 24, also having an LOA marked (0011) in Fig 4 will be routed to the printer 30, having the LDA
of (0013). Line 1 in Table 3 is similar to the function of Tables lA and lB which handle all messages except the broadcast messages.
Line 2 in Table 3 shows how a terminal like 24 in Fig. 4 can initiate a broadcast message to the other terminals like 26 and 30 associated with the router module 20. When a broadcast message is to be initiated at the terminal 24, its LOA is purposely changed (via a keyboard entry, for example) from the usual (0011) to an LOA of (1111) as seen in line 2 of Table 3. Because this is not the usual LOA designation associated with the terminal 24, the router module 20 recognizes this as a request to broadcast the message, and the router module 20 will then switch the LOA and LDA fields as shown in Line 3 of Table 3. Line 3 of Table 3 effects the broadcasting mode to the other terminals like 26 and 30 associated with router module 20 The address marked A located in the DLC header 68 of the data string 66 is utilized by a router module like 20 to broadcas~ a message to its associated ter-minals, like 24, 26, etc. The address A in the DLC
header 68 is an 8 bit address, in the embodiment des-cribed, and is referred to as the link address in Table lB. The first four bits on a line like 13b in Table 1 represent the upper four bits of the link address. In the particular embodiment described, the lower four bits of the 8 bit address A are all identical; consequently, they are not shown in Table lB. For router module 20 shown as module #l in Fig. 4, the hex designation there-for is (OOlX) as previously described. A terrninal like26 in Fig. 4 having a hex designation of (0012) is represented by line 3b in Table lB.

Continuing with broadcasting a message, line 4a of Table 2 is identical to line 2a already described.
Line ~b describes the function of switching the LDA and LOA fields in the DLC header 68 of the data string 66 so that the message will be in the proper format to be transmitted down the line drivers ~16 associated with the primary driver 54. Line 4(c) describes the DLC
protocol requirements associated with the primary driver 54 to broadcast a message. Line 4(d) refers to calling a subroutine which is part of the primary driver 54;
this subroutine transmits the message down the communi-cations link including the line drivers 116 shown in Fig. 5.
With regard to Table 2, line 5 thereof refers to certain messages which are initiated by the terminals like 24, and are used to activate the router modules like 20 to perform certain test or diagnostic routines.
These certain messages are recognized by the router modules, like 20, by the logical destination address (LDA) shown in Table lA. For example, a user of a terminal like 24 may want to initiate a test routine on its associated router module 20. The L~A of the asso-ciated router module 20 is supplied by the terminal 24, for example, and is located in the DNA header 70 shown in Fig. 2. The upper twelve digits S15-S4 entered are the same as the digits which are strapped to the router module 20; these digits are manually entered upon the switches (shown generically as 102 in Fig. 5) associated with the router module 20. The lower four digits S3-S0 are all zeroes as shown on line la of Table lA. The16 digits mentioned, S15-S0 indicate to the router module 20 that a test or diagnostic routine is requested, and the test routine requested is entered as part o~ the data string 66 (Fig. 2) entered upon the terminal 24 in the example being described.
I~ a diagnostic or test routine is requested as discussed in the prior paragraph with regard to paragraph 5 of Table 2, then steps 5a through 5d will follow as listed in Table 2. Step 5a is identical to step 2a already described. At steps 5b, 5c, and 5d, a subroutine associated with the router module 20 and stored in a ROM like 96-1, for example, is called upon for the execution of the test routine requested. The subroutine mentioned will save the return address (step 5b) and then calculate (step 5c) the address (in a look-up table) as to where the requested test routine is located (step 5c). Thereafter the router module 20 executes (step 5d) the test routine first accessed.
When the test routine is completed, control is returned to the router module for continued processing.
With regard to Table 2, line 6 indicates a check to determine whether or not a message destination is for the cassette terminal 52. As seen from Line 16a of Table lA, when the S3-So digits o~ the LDA are all binary ls, the message destination (from line 16b of Table lB) is the cassette terminal 52. Step 6a is identical to step 2a, already described, and step 6b relates to processing the message by calling a sub-routine DCMESG which provides the necessary steps to effect the transfer of the message to the cassette unit or terminal 52.
Paragraph B of Table 2 simply relates to an entry point for calling the router module 20.
Paragraph C of Table 2 indicates that no special requirements are necessary to exit from the routines discussed in relation to the router module 20.
Paragraph D of Table 2 lists the externally defined subroutines which are used with the router module 20.
Paragraph E of Table 2 states other consider-ations associated with the router module 20; these considerations have been discussed earlier herein in connection with Table 2.
Having described generally some of the routines (Table 2) associated ~lith the routing logic 60, it ;i7~

appears appropriate to discuss, in more detail, how a message such as a data string 66 shown in Fig. 2 is processed by the router module 20 shown in Figs. 1 and 5~
A message like data string 66 which originates at a terminal like 2~ (Fig. 1) will pass through the line receivers 112 (Fig. 5) to the serial interface unit 106. The interface unit 106 recognizes a message like data string 66 by its starting flag F in header 68, and its ending flag F in trailer 72. As the message is received by the interface unit 106, it is transferred into the RAM 94-1 by the DMA unit 118. After the entire data string 66 is received at the interface unit 106, a CRC error check is made of the data within the data string 66 to make sure that errors are detected. After the error check is made, the interface unit 106 will interrupt the MP 92, informing it that the unit 106 has a message which it can dispose of. Thereafter, the MP
92 will enable the primary driver 54 (Fig. 1) to execute an associated program which is a part thereof, and which program establishes communication or transfer protocol.
The message or data string 66 is left in the RAM 94-1 at a particular address therein. The program associated with the primary driver 54 will then call the routing logic 60 which will determine the destination of the message. The program associated with the routing logic 60 is stored in a portion of ROM 96-1, for example, and the MP 92 in conjunction with this program and the Decision Table shown in Tables lA and lB will ascertain ~here the message is to be sent. In the example being described, the LDA of the header 70 (Fig. 2) of the data string 66 may indicate that the message is to go to the printer module 30 (Fig. 1). This means that the primary driver 54 is called, and it is given the starting ad-dress of the data string 66 which was stored in the ROM94-1. The driver 54 then gives 'che appropriate command to the DMA unit 118 to effect the transfer of the data string 66 from the ROM 94-1 to the interface ~nit 106, which in t~rn will transfer the data string 66 to the line drivers 116 which in turn transfer the data string 66 to the printer module 30 in the example being des-cribed. While the message transferred is described as being the entire data string 66, there are many messages which are transerred, Eor example, between the termin-als like 24, 32 and the MP 92 which messages have only the DLC header 68 and the DLC trailer 72 (Fig. 2) form-ing the entire message data string like 66. These shortened messages are simply protocol control messages which may be going on all the time asynchronous to the fact that the MP 92 in association with the routing logic 60 is also concurrently executing the program represented by the routing logic 60.
When a message such as that represented by data string 66 is to be transferred from a terminal, like 24, to the host system 22 (Fig. 1), the following procedure is used. As previously described, the des-tination or LDA of the data string 66 is entered on a terminal like 24 or initiated thereby, and that data string LS routed up the line receivers 112 (Fig. 5) to the interface unit 106. From the interface unit 106, the data string 66 is transferred to the RAM 94-1, for example, by the DMA unit 118 as previously described.
~After error detection and correction have been per-formed with regard to the CRC bytes in the trailer 72 (Fig. 2), the MP 92 will be interrupted and the MP 92 will start execution of the software portion of the primary driver 54 which examines the LDA and C/S fields of the data string 66. After examination, the data string 66 is passed to the routing logic 60 with a software call. This call is referred to in section B of Table 2. The software associated with the routing logic 60 will ascertain from the LDA of the data string 66 that the message is to be transferred to the host system 22. In this regard, the routing logic 60 will call the secondary driver 58 so that the message can be trans-ferred to the host system 22 The address at which the ~5~
~24-message or data string 66 is stored in RAM 94-1 is then passed to the secondary driver 58 which includes a program which is stored in a ROM 120. The secondary driver 58 then waits for a poll or call from the host system 22 to effect the transfer of data thereto. In the embodiment described, the interface unit 104 trans-fers one character at a time to the host system 22, and while this is being done, the MP 92 then pulls the next character from the data string 66 stored in the RAM 94-1 through the accumulator of the MP 92 and transfers it to the interface unit 104. From the interface unit 104, the cllaracters are sent via the line drivers 114 to the host system 22. In the embodiment described, the characters are transmitted serially out of the interface unit 104 at a maximum rate of 4800 Baud. Thus, while the interface unit 104 is transmitting one character at a time, the MP 92 can suspend the secondary driver 58, permitting the MP 92 to process other procedures such as the polling of low order terminals such as 24 and 26 and transmitting other messages throughout the system.
Essentially, transferring characters out of the serial interface unit 104 takes longer than it takes the MP 92 to feed characters thereto rom the RA~I 94-1. The interface unit 104 is conventional and may be a #8251 integrated circuit chip which is manufactured by Intel Corporation, for example. As far as transmission of characters is concerned, the MP 92 selects two eight bit bytes or two characters from the data string 6~ and transfers them to the interface unit 104. ~hile ~he first of these two bytes is being transmitted, the second byte is located at a ready station or a buffer (not shown) included in the interface unit 104. When the first byte or character is sent over the line drivers 114, an interrupt signal is sent to the MP 92 to interrupt it to obtain the third character or byte as the interface unit 104 transfers the second byte or character from its buffer to start the transmission of the second byte over the drivers 114.

When a message such as data string 66 (Fig. ~) is to be transferred from the host system 22 to one of the terminals like 24 or 26 (Fig. 1), for example, the following procedure is used. In this situation, the secondary driver 58 will issue a call to the router module 20; this will cause the MP 92 to execu~te the routing logic 60. The LDA of the data string 66 will indicate (via Tables lA and lB) that the message is to go to terminal 24, in the example being described, and the data string 66 will be stored in the RAM 94-1 (Fig.
5). The routing logic 60 will then call the primary driver 54 (Fig. 1) to effect the transfer. The primary driver 54 will initiate the appropriate input and output (I/O) commands required for the serial interface unit 106 (Fig. 5) to set up the DMA unit 118 previously described. The message will then be sent serially over the line drivers 116 to the terminal 24. The terminal 24 responds by sending a supervisory frame to the router module 20 as part of the protocol associated with the primary driver 58.

Claims (7)

CLAIMS:
1. A combination comprising:
a host system:
a plurality of terminal units including first units, at least said first units having means for entering at least routing data thereon; said routing data including a logical origin address (LOA) which indicates the origin of a string of information to be routed and a logical destination address (LDA) which indicates the intended destination of said string of information;
a router module for receiving a said string of information including said routing data and for routing said string of information to selected ones of said plurality of units or to said host system in accordance with said routing data;
said router module comprising:
first coupling means for coupling said router module with said host system for transferring said string of information to and from said host system;
second coupling means for coupling said router module with said plurality of terminal units for transferring said string of information from one of said terminal units to at least another one of said terminal units; and routing logic including a decision table which utilizes said routing data to route said string of information in accordance with said routing data.

2. The combination as claimed in claim 1 in which said router module further includes means for assigning a said LOA to each of said plurality of ter-minal units for identification thereof, and in which said routing logic includes a portion for examining the LOA of each said string of information and also for routing said string of information in a broadcast mode
2. (concluded) to each of said terminal units when the LOA in a string of information is different from the LOA assigned to that said terminal unit from which the said string of information originated.
3. The combination as claimed in claim 2 in which said routing logic includes a second portion which enables at least said first units to initiate prede-termined test routines, for example, in response to a predetermined said LDA assigned to a said string of information by at least said first units.
4. The combination as claimed in claim 1 further comprising a permanent storage and in which said routing logic further includes a third coupling means for coupling said router module with said permanent storage means for transferring a said string of infor-mation to and from said permanent storage.
5. The combination as claimed in claim 1 in which each said first unit has a source of power sup-plied thereto, and said router module is mounted on a substrate to enable said router module to be mounted in a said first unit to utilize the associated said source of power.
6. The combination as claimed in claim 1 in which said plurality of terminal units includes a per-ipheral device such as a printer module which is shared by at least two of said first units to receive a said string of information therefrom.
7. The combination as claimed in claim 1 in which said routing logic includes a storage device in which said decision table is stored.
CA000411944A 1981-09-28 1982-09-22 Apparatus for routing data between low order terminals and high order communications Expired CA1195751A (en)

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Families Citing this family (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
JPS6255767A (en) * 1985-09-03 1987-03-11 Matsushita Electric Ind Co Ltd Electronic catalog device
US4787027A (en) * 1985-09-20 1988-11-22 Ncr Corporation System using an adapter board to couple a personal computer to a plurality of peripherals in a financial environment
US4942552A (en) * 1986-11-20 1990-07-17 Allen-Bradley Company, Inc. Method and apparatus for saving and performing industrial control commands
US4887076A (en) * 1987-10-16 1989-12-12 Digital Equipment Corporation Computer interconnect coupler for clusters of data processing devices
US4949337A (en) * 1989-01-30 1990-08-14 Honeywell Inc. Token passing communication network including a node which maintains and transmits a list specifying the order in which the token is passed
US5249292A (en) * 1989-03-31 1993-09-28 Chiappa J Noel Data packet switch using a primary processing unit to designate one of a plurality of data stream control circuits to selectively handle the header processing of incoming packets in one data packet stream
JP2504206B2 (en) * 1989-07-27 1996-06-05 三菱電機株式会社 Bus controller
US5163138A (en) * 1989-08-01 1992-11-10 Digital Equipment Corporation Protocol for read write transfers via switching logic by transmitting and retransmitting an address
JP2945757B2 (en) * 1989-09-08 1999-09-06 オースペックス システムズ インコーポレイテッド Multi-device operating system architecture.
US5163131A (en) * 1989-09-08 1992-11-10 Auspex Systems, Inc. Parallel i/o network file server architecture
US5165022A (en) * 1989-10-23 1992-11-17 International Business Machines Corporation Channel and control unit having a first I/O program protocol for communication with a main processor and a second universal I/O program protocol for communication with a plurality of I/O adapters
CA2076366C (en) * 1990-03-02 1998-05-26 Michel J. Remion Telecommunication interface apparatus and method
ATE207679T1 (en) * 1992-04-20 2001-11-15 3Com Corp DEVICE FOR EXPANSION OF NETWORK MEANS TO REMOTE NETWORKS
WO1994001828A1 (en) * 1992-07-02 1994-01-20 Wellfleet Communications Data packet processing method and apparatus
DE69431186T2 (en) * 1993-06-03 2003-05-08 Network Appliance Inc Method and file system for assigning file blocks to storage space in a RAID disk system
DK0702815T3 (en) * 1993-06-03 2000-12-18 Network Appliance Inc Set up a file system for writing at any location
US6604118B2 (en) 1998-07-31 2003-08-05 Network Appliance, Inc. File system image transfer
US7174352B2 (en) 1993-06-03 2007-02-06 Network Appliance, Inc. File system image transfer
US6138126A (en) * 1995-05-31 2000-10-24 Network Appliance, Inc. Method for allocating files in a file system integrated with a raid disk sub-system
DE69434381T2 (en) * 1993-06-04 2006-01-19 Network Appliance, Inc., Sunnyvale A method of parity representation in a RAID subsystem using nonvolatile memory
US5511168A (en) * 1993-07-01 1996-04-23 Digital Equipment Corporation Virtual circuit manager for multicast messaging
US5509006A (en) * 1994-04-18 1996-04-16 Cisco Systems Incorporated Apparatus and method for switching packets using tree memory
US5519704A (en) * 1994-04-21 1996-05-21 Cisco Systems, Inc. Reliable transport protocol for internetwork routing
US5867666A (en) * 1994-12-29 1999-02-02 Cisco Systems, Inc. Virtual interfaces with dynamic binding
US6097718A (en) * 1996-01-02 2000-08-01 Cisco Technology, Inc. Snapshot routing with route aging
US6147996A (en) 1995-08-04 2000-11-14 Cisco Technology, Inc. Pipelined multiple issue packet switch
US6917966B1 (en) 1995-09-29 2005-07-12 Cisco Technology, Inc. Enhanced network services using a subnetwork of communicating processors
US7246148B1 (en) 1995-09-29 2007-07-17 Cisco Technology, Inc. Enhanced network services using a subnetwork of communicating processors
US6182224B1 (en) 1995-09-29 2001-01-30 Cisco Systems, Inc. Enhanced network services using a subnetwork of communicating processors
US6091725A (en) 1995-12-29 2000-07-18 Cisco Systems, Inc. Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network
US6035105A (en) * 1996-01-02 2000-03-07 Cisco Technology, Inc. Multiple VLAN architecture system
US6243667B1 (en) 1996-05-28 2001-06-05 Cisco Systems, Inc. Network flow switching and flow data export
US6308148B1 (en) 1996-05-28 2001-10-23 Cisco Technology, Inc. Network flow data export
US6212182B1 (en) 1996-06-27 2001-04-03 Cisco Technology, Inc. Combined unicast and multicast scheduling
US6434120B1 (en) * 1998-08-25 2002-08-13 Cisco Technology, Inc. Autosensing LMI protocols in frame relay networks
US6304546B1 (en) 1996-12-19 2001-10-16 Cisco Technology, Inc. End-to-end bidirectional keep-alive using virtual circuits
WO1998035489A1 (en) * 1997-02-07 1998-08-13 Samsung Electronics Co. Ltd. Device for transmitting and processing group communications in the e-mail system
US6122272A (en) * 1997-05-23 2000-09-19 Cisco Technology, Inc. Call size feedback on PNNI operation
US6356530B1 (en) 1997-05-23 2002-03-12 Cisco Technology, Inc. Next hop selection in ATM networks
US6862284B1 (en) 1997-06-17 2005-03-01 Cisco Technology, Inc. Format for automatic generation of unique ATM addresses used for PNNI
US6078590A (en) 1997-07-14 2000-06-20 Cisco Technology, Inc. Hierarchical routing knowledge for multicast packet routing
US6212183B1 (en) 1997-08-22 2001-04-03 Cisco Technology, Inc. Multiple parallel packet routing lookup
US6512766B2 (en) 1997-08-22 2003-01-28 Cisco Systems, Inc. Enhanced internet packet routing lookup
US6157641A (en) * 1997-08-22 2000-12-05 Cisco Technology, Inc. Multiprotocol packet recognition and switching
US6343072B1 (en) 1997-10-01 2002-01-29 Cisco Technology, Inc. Single-chip architecture for shared-memory router
US7570583B2 (en) 1997-12-05 2009-08-04 Cisco Technology, Inc. Extending SONET/SDH automatic protection switching
US6424649B1 (en) 1997-12-31 2002-07-23 Cisco Technology, Inc. Synchronous pipelined switch using serial transmission
US6111877A (en) 1997-12-31 2000-08-29 Cisco Technology, Inc. Load sharing across flows
US6457130B2 (en) 1998-03-03 2002-09-24 Network Appliance, Inc. File access control in a multi-protocol file server
US6317844B1 (en) 1998-03-10 2001-11-13 Network Appliance, Inc. File server storage arrangement
US6853638B2 (en) * 1998-04-01 2005-02-08 Cisco Technology, Inc. Route/service processor scalability via flow-based distribution of traffic
US6920112B1 (en) 1998-06-29 2005-07-19 Cisco Technology, Inc. Sampling packets for network monitoring
US6370121B1 (en) 1998-06-29 2002-04-09 Cisco Technology, Inc. Method and system for shortcut trunking of LAN bridges
US6377577B1 (en) 1998-06-30 2002-04-23 Cisco Technology, Inc. Access control list processing in hardware
US6095594A (en) * 1998-07-21 2000-08-01 Chrysler Corporation Exterior body side cladding attachment for a motor vehicle and related method
US6182147B1 (en) 1998-07-31 2001-01-30 Cisco Technology, Inc. Multicast group routing using unidirectional links
US6308219B1 (en) 1998-07-31 2001-10-23 Cisco Technology, Inc. Routing table lookup implemented using M-trie having nodes duplicated in multiple memory banks
US6101115A (en) * 1998-08-07 2000-08-08 Cisco Technology, Inc. CAM match line precharge
US6389506B1 (en) 1998-08-07 2002-05-14 Cisco Technology, Inc. Block mask ternary cam
US6119244A (en) 1998-08-25 2000-09-12 Network Appliance, Inc. Coordinating persistent status information with multiple file servers
US6343984B1 (en) 1998-11-30 2002-02-05 Network Appliance, Inc. Laminar flow duct cooling system
US6581792B1 (en) 1998-12-07 2003-06-24 Tjandra Limanjaya Closure cap
US6771642B1 (en) 1999-01-08 2004-08-03 Cisco Technology, Inc. Method and apparatus for scheduling packets in a packet switch
US7065762B1 (en) 1999-03-22 2006-06-20 Cisco Technology, Inc. Method, apparatus and computer program product for borrowed-virtual-time scheduling
US6757791B1 (en) 1999-03-30 2004-06-29 Cisco Technology, Inc. Method and apparatus for reordering packet data units in storage queues for reading and writing memory
US6603772B1 (en) 1999-03-31 2003-08-05 Cisco Technology, Inc. Multicast routing with multicast virtual output queues and shortest queue first allocation
US6760331B1 (en) 1999-03-31 2004-07-06 Cisco Technology, Inc. Multicast routing with nearest queue first allocation and dynamic and static vector quantization
WO2001028179A2 (en) * 1999-10-14 2001-04-19 Bluearc Uk Limited Apparatus and method for hardware implementation or acceleration of operating system functions
US6876991B1 (en) 1999-11-08 2005-04-05 Collaborative Decision Platforms, Llc. System, method and computer program product for a collaborative decision platform
US8799138B2 (en) * 2000-04-10 2014-08-05 Stikine Technology, Llc Routing control for orders eligible for multiple markets
US7890410B1 (en) 2000-04-10 2011-02-15 Stikine Technology, Llc Automated trial order processing
US8249975B1 (en) 2000-04-10 2012-08-21 Stikine Technology, Llc Automated first look at market events
US8296215B1 (en) * 2000-04-10 2012-10-23 Stikine Technology, Llc Trading system with elfs and umpires
US7813991B1 (en) * 2000-04-10 2010-10-12 Christopher Keith Automated trading negotiation protocols
US7472087B2 (en) * 2000-04-10 2008-12-30 Stikine Technology, Llc Trading program for interacting with market programs on a platform
US7539638B1 (en) 2000-04-10 2009-05-26 Stikine Technology, Llc Representation of order in multiple markets
US7398244B1 (en) 2000-04-10 2008-07-08 Stikine Technology, Llc Automated order book with crowd price improvement
US7882007B2 (en) * 2000-04-10 2011-02-01 Christopher Keith Platform for market programs and trading programs
US7908198B1 (en) 2000-04-10 2011-03-15 Stikine Technology, Llc Automated preferences for market participants
US7496533B1 (en) 2000-04-10 2009-02-24 Stikine Technology, Llc Decision table for order handling
US7383220B1 (en) 2000-04-10 2008-06-03 Stikine Technology, Llc Automated short term option order processing
US7792733B1 (en) 2000-04-10 2010-09-07 Christopher Keith Automated synchronization of orders represented in multiple markets
US7644027B2 (en) * 2000-04-10 2010-01-05 Christopher Keith Market program for interacting with trading programs on a platform
US7774246B1 (en) 2000-04-10 2010-08-10 Christopher Keith Automated price setting for paired orders
US8775294B1 (en) 2000-04-10 2014-07-08 Stikine Technology, Llc Automated linked order processing
US6850980B1 (en) 2000-06-16 2005-02-01 Cisco Technology, Inc. Content routing service protocol
US7111163B1 (en) 2000-07-10 2006-09-19 Alterwan, Inc. Wide area network using internet with quality of service
US7230600B1 (en) * 2000-09-28 2007-06-12 Intel Corporation Repairable memory in display devices
US7095741B1 (en) * 2000-12-20 2006-08-22 Cisco Technology, Inc. Port isolation for restricting traffic flow on layer 2 switches
US7076543B1 (en) 2002-02-13 2006-07-11 Cisco Technology, Inc. Method and apparatus for collecting, aggregating and monitoring network management information
US7603481B2 (en) 2002-10-31 2009-10-13 Novell, Inc. Dynamic routing through a content distribution network
US8041735B1 (en) 2002-11-01 2011-10-18 Bluearc Uk Limited Distributed file system and method
US7457822B1 (en) 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system
US20060122951A1 (en) * 2004-12-03 2006-06-08 Pitney Bowes Incorporated High speed postage metering device and method utilizing a single print head controller with multiple printing modules
US7710959B2 (en) * 2006-08-29 2010-05-04 Cisco Technology, Inc. Private VLAN edge across multiple switch modules
US9998278B2 (en) * 2015-09-07 2018-06-12 Rohde & Schwarz Gmbh & Co. Kg Method and apparatus for synchronization of a decoding unit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544769A (en) * 1967-04-05 1970-12-01 Digital Identification Systems Electronic identification and credit card system
US3632881A (en) * 1970-03-16 1972-01-04 Ibm Data communications method and system
US3680056A (en) * 1970-10-08 1972-07-25 Bell Telephone Labor Inc Use equalization on closed loop message block transmission systems
NL7503539A (en) * 1974-04-05 1975-10-07 Cselt Centro Studi Lab Telecom LOGICAL CHAIN FOR COMPLETING DIGITAL DATA.
US3866175A (en) * 1974-04-24 1975-02-11 Ncr Co Data communication system between a central computer and a plurality of data terminals
US3956615A (en) * 1974-06-25 1976-05-11 Ibm Corporation Transaction execution system with secure data storage and communications
US4246637A (en) * 1978-06-26 1981-01-20 International Business Machines Corporation Data processor input/output controller

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