CA1194146A - Voltage translator - Google Patents

Abstract

ABSTRACT:
"Voltage translator."

A bipolar voltage translator contains a pair of differentially-coupled transistors for converting an input voltage supplied to the base of a first (Q1) of the pair into an output voltage taken between a first resistor (R9) and the collector of the second (Q2) of the pair. A second resistor (R12) is coupled between a VEE supply and a current-source transistor (Q4) which supplies current to the differential pair. The current-source transistor is controlled by a reference voltage which equals VEE + (1 + ?) VBE where ? is in the range 0.2 to 3Ø
The ratio of the first resistor to the second resistor is desirably .beta./? where .beta. VBE is the output voltage swing.
Circuitry such as a Schottky diode (S4) is coupled between the emitters of the differential Pair to prevent the emitter-base junction of the second transistor from break-ing down. Where the transistors are NPN devices and .beta.
equals 1, the output voltage is provided at levels suitable for current tree logic.

Description

~94~4~

This invention relates generally to a voltage translator suitable for a semiconductor integrated cir-cuit and more particularly to an electronic circuit for converting an input voltage into an output voltage at a 5 different level wherein (1) a first bipolar transistor of a given polarity has an emitter, a base for receiving the input voltage, and a collector coupled to a source of a first supply voltage,(2) a second bipolar transistor of the given polarity has an emitter coupled through a first 10 node to the emitter of the first transistor, a base for receiving a first reference voltage, and a collector for supplying the output voltage, (3) a first resistor is coupled between the source of the first supply voltage and the collector of the second transistor, (4) a current-15 source bipolar transistor of the given polarity has an emitter, a base for receiving a second reference voltage, and a collector coupled to the node, and (5~ a second resistor is coupled between a source of a second supply voltage and the emitter of the current-source transistor.
The invention will be described in more detail with reference to Figures 1 to 5, in which:
Fig. 1 is a circuit diagram of a prior art volt-age translator.
Fig. 2 is a circuit diagram of an embodiment of 25 a voltage translator in accordance with the invention.
Fig. 3 is a circuit diagram of a voltage refer-ence circuit alternatively employable in the embodiment of Fig. 2.
Fig. 4 is a layout view of the voltage trans-30 lator of Fig. 2.
Fig. 5 is a cross-sectional side view of a por-tion of the embodiment shown in Fig. 4.
In a conventional type of voltage translator, a ~' ~194~6 pair of bipolar transistors are connected in a differen-tial configuration for converting an input signal into an output signal at a different voltage level. Fig. 1 illus~
trates such a prior art device as employed in the input section of the 8T14 integrated circuit manufactured by Signetics Corporation. In this translator, an input volt-age VIN is applied to the base of an ~PN transistor Ql whose emitter is connected through a node Nl to the emitter of an identical NPN transistor Q2. An output voltage VOUT
is taken between the collector of transistor Q2 and 1,680-ohm resistor Rl connected to a source of a supply voltage Vcc at 5 volts. A PN junction diode Jl between the collec-tor of transistor Ql and the Vcc supply protects it from receiving current from the input. A reference voltage VREFl is supplied to the base of transistor Q2 from an NPN
transistor Q3 which forms part of a voltage divider further consisting of resistors R2, R3 and R4 and a PN junction diode J2 connected as shown between the Vcc supply and a source of another supply voltage VEE at ground reference (0 volt). A hysteresis input VHyS supplied to the base of transistor Q3 callses voltage VREFl to vary about + 0.2 volt from its nominal 1.5 volt operating point.
A substantially constant current is provided to the emitters of transistors Ql and Q2 from a current source consisting of an NPN transistor Q4 which is part of a cur rent mirror that also includes NPN transistors Q5 and Q6, a 1,400-ohm resistor R5l and a 4,000-ohm resistor R6 con-nected as shown. Resistor R5 fixes the current through transistor Q5. This current is then mirrored in transis-tor Q4. More particularly, the current mirror establishesa reference voltage VRE~,2 of about lVBE at the base of transistor Q4 to make it conductive. VBE is the standard base-to-emitter voltage for an NPN transistor when its base-emitter junction is just conductively forward biased.
Resistors R7 and R8 in the emitters of transistors Q4 and Q5, respectively, are small 50-ohm resistors that act to make the current source less sensitive to noise and sub-stantially do not effect voltage VREF2. Such resistors 119~146 are often not included in a current mirror.
In operation, transistor Ql turns on when volt-age VIN is raised to a logical high value above VREFl.
This causes transistor Q2 to turn off, and voltage VOUT
goes to a logical high value near 5 volts. When voltage VIN drops to a logical low value below VREFl, transistor Ql turns off and transistor Q2 turns on to bring voltage VOUT down to a logical low value around 0~8 volt.
While the input impedance of this transistor is high, its resistors are not directly ratioed for VBE
tracking. A separate current mirror must be provided for each such translator used in an integrated circuit. In addition, a VIM excursion above 5-6 volts could degrade the transistor and allow current to flow into the Vcc supply by causing the emitter-base junction of transistor Q2 to break down.
In one aspect of the invention, an electronic circuit for converting an input voltage into an output voltage at a different level contains a pair of bipolar transistors of a given polarity differentially coupled to each other by way of their emitters. A first transistor of the pair receives the input voltage at its base. Its collector is coupled to a source of a first supply voltage (Vcc). The output voltage is supplied from the collector of the second transistor of the pair while its base receives a first reference voltage. A first resistor is coupled between the Vcc source and the collector of the second transistor. A current-source bipolar transistor of the given polarity is coupled by way of its collector through a node to the emitters of the pair of transistors.
A second reference voltage is provided to the base of the current-source transistor. A second resistor is coupled between a source of a second supply voltage (VEE) and the emitter of the current-source transistor. In accordance with the invention the electronic circuit is characterized in that the second reference voltage equals to second sup-ply voltage VEE + (1 +cC)VBE where c~ is in the range 0.2 to 3.0 and VBE is the average base to emitter voltage of the transistor when their base-emitter junctions are just conductively forward biased. By so choosing the second reference voltage, it can be supplied to the current-source transistors of other such voltage translators.
The resistance ratio of the first resistor to the second resistor is preferably ~/oC where ~ VBE is the desired voltage swing in the output voltage. Inasmuch as this resistance ratio is direc-tly related to VBE, the translator thereby provides VBE tracking.
In another aspect of the invention, a voltage translator contains the first and second transistors and the first resistor all arranged as in the first aspect plus a current source which preferably consists of the current-source transistor and the second resistor likewise arranged as in the first aspect. In the second aspect, the voltage translator contains circuitry coupled between the emitters of the first and second transistors for pre-venting the emitter-base junction of the second transistor from breaking down. Desirably, the breakdown prevention circuitry is a diode such as a Schottky diode coupled between the node and the emitter of the second transistor.
The reference voltages are optimally provided by a voltage reference circuit in which a first diode is coupled between the base of the second transistor and an intermediate second diode. A third diode is coupled be-tween the second diode and the VEE source. A pair of resistors is coupled across the second diode and commonly to the base of the current-source transistor. To provide greater current drive capability and to prevent the refer-ence voltages from varying as the current drive varies, aPN junction diode is desirably coupled between the third diode and the V~E source, and a pair of bipolar transistors of the given polarity are base-emitter coupled respectively between the first diode and the resistor pair, on one hand, and the bases of the second and current-source transistors, on the other hand.
In the situation where the transistors are NPN
devices, and ~ is 1, the present translator provides a ~g4~

logical high output signal at Vcc and a logical low output signal at Vcc-VBE. These voltage levels are compatible with current tree logic (CTL) which is similar to emitter-coupled logic but runs with different voltage levels and swings. CTL uses a lVBE swing referenced to the Vcc supply. Accordingly, the present voltage translator is suitable for use as a CTL input device.
Like reference symbols are employed in the draw-ings and in the description of the preferred embodiments to represent the same or very similar item or items.
Referring to the drawings, Fig. 2 illustrates a bipolar voltage translator for converting input voltage VIN applied to the base of NPN transistor Ql into output voltage VOUT taken from the collector of identical NPN
transistor Q2. Voltages VIN and VOUT are measured with respect to the VEE source which is preferably ground reference. Current is supplied to the collectors of transistors Ql and Q2 from the Vcc supply which is pre-ferably 5.0 volts.
On the input side, a Schottky diode Sl connected between the Vcc supply and the collector of transistor Ql serves to prevent VIN surges above 5.6 volts from supply-ing current to the Vcc source. A Schottky diode S2 con-nected between the base of transistor Ql and the VEE
supply clamps voltage VEE. A Schottky diode S3 clamps transistor Ql so as to keep it out of deep saturation and increase the switching speed of the voltage translator.
On the output side, a Schottky diode S4 is con-nected between the emitters of transistors Q1 and Q2. In particular, the cathode of diode S4 is connected through node Nl to the emitter of transistor Ql, and the anode is connected to the emitter of transistor Q2. The normal breakdown voltage for transistor Q2 is about 3.0 volts.
Diode S4 prevents the emitter-base junction of transistor Q2 from hreaking down should voltage VIN rise to a level that exceeds 3.0 volts by lVBE plus the voltage at the base of transistor Q2.

1~94~4~
Pl-IA 10 (~5 27~1-1983 ~n output resistor R9 is connected between the Vcc supply and the collector of transistor Q2. Resistor R9 has a resistance Rg which is preferably 1~800 ohms but may be varied in the manner described below.
Reference voltage VREF1 is provided to the base of transistor Q2 at a preferred value of 2VBE+Vs measured relative to VEE. VBE varies wi-th temperature from o.6 to 1.0 volt for a -typical NPN transistor and is about 0.75 volt at room temperature. VBE is also the PN-junction diode-drop voltage. Vs is the starldard Schottky diode-drop voltage for a Schottky diode when it is just con-ductively forward biased. For a typical Schottky diode, VS varies from 0.4 to 0.~5 volt with tempera-ture and is about 0.55 volt at room temperature.
Voltage VREF1 is provided from a voltage refer-ence circuit 10 through the emitter of an alwa~s-on NPN
transistor Q7 whose collector is coupled to the Vcc supply.
The base of transistor Q7 is coupled through a node N2 -to the VEE source by way of a set of four cathode-to-anode serially coupled diodes S5, J3, J4 and J5. Diode S5 is a Schottky diode while dio~es J3, J~ and J5 are PN junction diodes. Voltage Vcc is suPplied through a resistor R10 to the diode set and to the base of transistor Q7. Re-sistor R10 is 5,000 ohms. A resistor R11 is optionally connected between the emitter of transistor Q7 and the VEE source so as to assure that the emitter of transistor Q7 is always at the desired voltage level and does not float high.
Each of Schott~y diodes S5 and S5 could alter-30 natively be replaced by a PN junction diode. The operationof the voltage translator would no-t be affected exCePt that voltage VREF1 would be 3VBE.
A substantially constant current is provided to transistorS Q1 and Q2 by way of a current source con-taining always-on NPN transistor Q4 whose collector is coupled to their emitters. The current source also includes a resistor R12 connected between the VEE source and the emitter of transistor Q4. Resistor R12 has a resistance PHA 1o65 7 2'7-1-19~3 R12 which is preferably 900 ohms but may be varied in the manner described below.
g RE~2 s provided to the base of transistor Q4 at a preferred value of 1.5 VBE relative to V~E. Voltage VREF2 is supplied from circui-t 10 by way of the emitter of an always-on NPN transistor ~8 whose collector is connected -to the Vcc supply. The base of transistor Q~ is connected through a node N3 to a voltage divider connected across diode J3. The voltage divider consists of a resistor R13 connected to the anode of diode J3 and a resistor R14 comlected to the cathode of diode ~3. Resistors R13 and R14 each have the same resistance which is preferably 6,ooo ohms. ~ resistor Rt5 is optional-ly coupled ~etween the VEE source and the emitter of lS transistor Q8 so as to assure that the emitter of tran-sistor Q~ does not float high.
While VEE+1.5VBE is the preferred value of vol-tage VREF2, it more generally equals VEEI(11o~)VBE, where ~ is in the range of 0.2 to 3Ø In this manner, resistor 20 R12 determines the current I supplied ~rom the current source to transistors Q1 and Q2. In Particular, current I
equals o~VBE/R12.
The switching point for voltage VIN is 2VBE. When voltage VI~ rises to a logical high input value above 25 2VBE, transistor Q1 turns on but does not saturate. Current flows between the Vcc and VEE sources by way of transistors Q1 and Q4. Transistor Q2 is off, and its collector supplies voltage V0uT at a CTL high logical output value equal to Vcc. When voltage VIN drops to a logical low input value 30 below 2VBE, transistor Q1 turns off. Transistor Q2 turns on but does not sa-turate. Current flows between the Vcc and VEE sources by way of transistors Q2 and Q4. In the preferred embodiment in which the resistance ratio R9/R~2 equals 2.0, the collector of transistor Q2 then supplies 35 voltage V0uT at a CTL low logic le-vel equal to Vcc-VBE.
That is, the voltage swing from the logical low output level to the logical high output leve~ optimally equals BE

~941~6 PH~ 1065 8 27-1-1983 More generally~ voltage VOuT equals Vcc- ~ VBE
at the logical low output condition -where ~ is selected to meet desired VOuT conditions. ~ should not be so high as to put transistor Q2 into saturation at the logical low condition. Since transistor Q1 is off at tha-t point, current I then equals ~ VBE/Rg. Accordingly, ratio Rg/~12 equals f~ /~ in the general case. Likewise~ the general g OUT is ~ VBE since voltage V still equals Vcc at the logical high condi-tion.
In the embodiment of` Fig. 2, o~ is varie~ from 0.2 up to nearly 1.0 by appropriately adjusting the resis-tances of resistors R13 and R14. To achieve ~ equals 1.0, resistors R13 and R14 are deleted, and the base of tran-sistor Q8 is connected directly to the anode of diode J3.
To achieve ~ in excess of 1.0, one or more diodes are serially connected between diodes JL~ and J5, and the re-sistances of resistors R13 and R14 are adjusted accordingly.
Turning to Fig. 3, it shows an al-ternative ver-sion of voltage reference circuit 10 in which transistors Q7 and Q8 and di~de J5 have been eliminated. Voltage VREF1 and VREF2 in this alternative are provided directly from nodes N2 and N3, respectively, -to the bases of tran-sistors Q2 and and Q4 at the same levels as be~ore. The deletion of elements Q7 and Q8 and J5 make circuitry 10 of Fig. 3 simpler than circuitry 10 of Fig. 2 but provides less current dirve capability and increases the risk of voltages VREF1 and VREF2 changing with the current drive.
In circuit 10 of Fig. 3, C~ may be varied in the same manner as previously described for circuit 10 of Fig. 2.
Methods of manufacturing the VariOUs elements of the present voltage translator are well known in the semiconduc~Q~ art. Fig. 4 shows a layout view of a pre-ferred embodiment of the voltage translator of Fig. 2 manufactured as a monolithic integrated circuit according -to conventional planar processing techniques using oxide isolation to separate active regions on a semiconductor wafer. In Particular, Fig. 4 shows the P-type and N-type Iegions along the top surface of the wafer below overlying i~94146 PHN lo65 9 27-1-1983 insulating material and metallic electrical con~ections.
The overlying insulating ma-ter:ial is not shown at all.
The area shaded in slanted lines indicates insulating material separating the VariOUs active semiconductor regions from one another. The black rectangles represent the overlying metallic Schottky-diode electrical con-tacts while the small black squares represent -the other electrical contacts. The overlying metallic connections are indicated as thick lines extending from -the various l electrical contacts. ~he areas enclosed by dotted lines indicate buried N+ regions. The unshaded areas that are either unlabeled or are labeled as cathodes for Schottky diodes are N- epitaxial regions.
"A" and "C" followed by a subscript ~hich is the symbol for a diode indicate i-ts anode and cathode, respec-tively. "B", "E" and "C" followed by a subscript which is the symbol for the transistor indicate its base~ emitter and collector, respectively. Diode S2 is not shown in Fig 4.
To further illustrate the construction of the translator, Fig. 5 depic-ts a cross-sectional side view taken through the staircase section 5-5 in Fig. 4. All the elements of the translator not shown in Fig. 5 are preferably fabricated in the rnanner described below. Con-25 ventional masking, etching and cleaning techniques are employed in creating the VariOUs P-type and N-type regions.
To simplify the discussion, references to the masking, etching, cleaning, and other well-known s-teps in the semi-conductor art are omitted from the following fabrication 30 discussion. In many of the diffusion steps, an impurity may be alternatively introduced into a wafer by ion im-planation and vice versa.
With reference to ~ig. 5, the s-tar-ting material is a P-type monocrystalline silicon substrate 12 into 35 whose upper surface an N-type impurity (antimony) is selec-tively diffused to form N+ regions 14, 16~ 18 and 20.
According to conventional techniques~ an N- epitaxial layer 22 is grown over the upper surface of` substra-te -l2, after ~4~4~;

which an oxide-isolation region 24 is formed through epi-taxial layer 22 and partially into substra-te 12 to define active semiconductor regions 26, 28, 30, 32 and 34.
An N-type impurity (phosphorus) is selectively ion implanted to define deep N+ regions 36 and 38 -that eventually extend down to buried regions 16 and 18~res-pectively. A thin electrically insulating layer 40 con-sisting of silicon dioxide and silicon nitride is then formed at the top of the wafer. After selectively etching oxynitride layer 40 to form windows -through it, an N-type impurity (arsenic) is diffused into epitaxial layer 22 through these windows to define shallow N+ regions 42, 44 and EQ4. A P-type impurity (boron) is then s~lectively ion implanted -through layer 40 to form P regions R9, BQ4, lS and R12. The structure is now annealed to cause the Var~L-ous impuritieS to redistribute to -the locations generally shown in Fig. 5.
A pattern of leads indicated by diagonal-line shading in ~ig. 5 is f`ormed according to conventional tech-20 niques on the top of the wafer and extends -through the various contact windows down to the unc~erlying semiconduc-tor regions. Each lead is a sandwich consisting of a thin lower layer of platinum silicide over the underlying silicon, a thin intermediate layer of titanium-tungsten, and an 25 upper layer of aluminum. Lead As4 forms the anode for diode S4 N+ regions 36 and 42 connect collector CQ2 which is the remaining N~type portion of buried region 16 with the upper surface of the wafer. Likewise~ N+ regions 38 and 44 perform the same function for collector CQ4 which 30 is -the remaining N-type portion of buried region 18.
Regions B~4 and EQ4 are the base and ernitter, respectively, for transistor Q4. The remaining N- portion Cs4 of epi-taxial layer 22 in island 30 serves as the cathode for diode S4 and extends down to collector CQ4. The structure 35 is then finished in a conventional manner.
As shown in Figs. 4 and 5, resistors R9 and R12 are laid out in the same direc-tion and have the same width.
This assures that ratio R9/R12 varies less -than lr/~ over the 1~9414~
PH~ 1065 '1'1 27~ 1983 temperature range -55 C to 125 C.
~ hile the invention has been described with reference to the preferred embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the inven-tion claisned below. For example, semiconductor materi.als of opposite conductivity types to those described above mav be employed to accomPlish the same results except that most of the Schottky diodes would be deleted or replaced with appropria-te PN junction diodes; in this case, VBE
is negative in value. Thus, VariOUs modifications, changes, and applications may be made by those skllled in the art without departing from the true scope and spirit of -the invention as defined by the appended claims.

Claims (15)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A voltage translating circuit which has: a first bipolar transistor having an emitter, a base for receiving an input voltage, and a collector coupled to a source of a first supply voltage; a like-polarity second bipolar transistor having an emitter coupled through a first node to the emitter of the first transistor, a base for receiving a first reference voltage, and a collector for supplying an output voltage at a different level from the input voltage; a first resistor coupled between the source of the first supply voltage and the collector of the second transistor; a like-polarity current-source bipolar transistor having an emitter, a base for receiving a second reference voltage, and a collector coupled to the node; a second resistor coupled between a source of a second supply voltage and the emitter of the current-source transistor; and means for providing the reference voltages;
characterized in that:
the means for providing comprises (1) a set of cathode-to-anode serially coupled diodes comprising a first diode coupled through a second node to the base of the second transistor, an intermediate second diode, and a third diode forwardly coupled to the source of the second supply voltage and (2) a pair of resistors coupled across the second diode and commonly through a third node to the base of the current-source transistor; and the second reference voltage equals the second supply voltage plus (1+?)VBE where ? is in the range of 0.2 to 3.0 and VBE is the base-to-emitter voltage of the current-source transistor when its base-emitter junction is just conductively forward biased.

2. A circuit as in Claim 1, characterized in that the resistance ratio of the first resistor to the second resistor is .beta./? where .beta. is the voltage swing divided by VBE.

3. A circuit as in Claim 1, characterized by means coupled between the emitters of the first and second trans-istors for preventing the emitter-base junction of the second transistor from breaking down.

4. A circuit as in Claim 3, characterized in that the means for preventing comprises a diode coupled between the node and the emitter of the second transistor in an opposing configuration with the base-emitter junction of the first transistor.

5. A circuit as in Claim 4, characterized in that the diode is a Schottky diode.

6. A voltage translating circuit wherein: a first bipolar transistor has an emitter, a base for receiving an input voltage, and a collector coupled to a source of a first supply voltage; a like-polarity second bipolar trans-istor has an emitter coupled through a first node to the emitter of the first transistor, a base for receiving a first reference voltage, and a collector for supplying an output voltage at a different level from the input voltage;
a first resistor is coupled between the source of the first supply voltage and the collector of the second transistor;
a like-polarity current-source bipolar transistor of the given polarity has an emitter, a base for receiving a second reference voltage, and a collector coupled to the node; and a second resistor is coupled between a source of a second supply voltage and the emitter of the current source transistor, characterized in that:
the circuit is a monolithic integrated circuit in which the resistors have substantially the same width and are oriented in substantially the same direction; and the second reference voltage equals the second supply voltage plus (1+?)VBE where ? is in the range 0.2 to 3.0 and VBE is the base-to-emitter voltage of the current-source transistor when its base-emitter junction is just conductively forward biased.

7. A circuit as in Claim 6, characterized in that the resistance ratio of the first resistor to the second resistor is .beta. /? where .beta. is the voltage swing divided by VBE.

8. A circuit as in Claim 6, characterized in that the resistance ratio of the resistors varies less than 1 percent over a temperature range of -55°C to 125°C.

9. A circuit as in Claim 1, characterized in that the means for providing further includes (1) a like-polarity bipolar transistor having an emitter coupled to the base of the second transistor, a base coupled to the second node, and a collector coupled to the source of the first supply voltage, (2) a like-polarity bipolar trans-istor having an emitter coupled to the base of the cur-rent-source transistor, a base coupled to the third node, and a collector coupled to the source of the first supply voltage, and (3) a PN junction diode cathode-to-anode coupled between the third diode and the source of the second supply voltage.

10. A circuit as in Claim 9, characterized in that the transistors are NPN transistors.

11. A circuit as in Claim 10, characterized in that the first diode is a Schottky diode and that the second and third diodes are PN junction diodes.

12. A circuit as in Claim 11, characterized in that the first transistor is Schottky clamped.

13. A circuit as in Claim 12, characterized by a Schottky diode forwardly coupled between the source of the first supply voltage and the collector of the first transistor.

14. A circuit as in Claim 1, 9 or 10, characterized in that the resistances of the pair of resistors are sub-stantially the same whereby .alpha. is 0.5.

15. A circuit as in Claim 2 or 7, characterized in that the transistors are NPN transistors and that .beta. is 1.