CA1193000A - Image data masking apparatus - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The target screen of a television camera is divided into a matrix in horizontal and vertical directions to receive image data signals as divided in the matrix for subsequent processing.
A memory circuit having the same number of memory elements as the divisions of the matrix, a circuit for scanning addresses of the memory elements of the memory circuit in synchronization with scanning in the television camera, a circuit for preliminarily memorizing signals, which are used to discriminate which of the image data signals are processed or not, on memory elements of the memory circuit with addresses corresponding to the image data signals respectively and a circuit for generating a control signal based on the memory data signal from the memory circuit to determine which image data signals is used or not in response to scanning of the target screen of the television camera is provided. A circuit for controlling supply of the image data signal from the television camera to the processing apparatus is also provided.

Description

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BACKGROUND OF THE INVENTION
-The present invention relates generally to an image data masking apparatus which employs a television camera to pick Up an obJect or the like, and is directed more particularly to an lmage data masking appdratus by which an electronic masklng is applled to the lmage Or an object that ls picked up by the television camera when the object is picked up by the television camera.

Du,ing recent years, various image processine systems or defect inspection systems utilizin~ television cameras have been proposed and gradually put into practice. Further, not only televlsion cameras uslng a plck-up tube but also television cameras using a solid state lmage sensor are used. Sometimes, with the use of such televislon cameras, some portions of lts pick-up screen, auch as a target screen, need not be image processed, or only the image lnformation from lts desired portion are to be processed and datarized. On suc~l occasions, lr a computer ~CPU) ls used as the processing system, it may be possible through the application of its software or the like, to utilize the data Or only the necessary sections Or the screen.
However, in such case, when the shape Or the section that is desired to be datariaed and then utill2ed or not desired rOr proces31ng rrequently changes, the complicatlon arise3 that requlres changes in the sortware program adaptlng the CPU ror each case.

O~J_C~S AND SUMMA~f OF THE I~VENTION

Accordlngly, it ls a main object of the present lnvention to provide an lmage data masking apparatus for use with an image data proces31ng system which enables the slmple electronlc masklng Or the unnecessary portions Or the target screen, Or a televislon camera ror example.

According to an aspect Or the present lnventlon, there 1 provided An image data ~ssking apparatus ~or use ~ith lDage data processing apparatus comprislng:
n televiaion camera having a target ~creen tormed Or a number ot sensor elements srranged ln a ~atrlx ln hori~ontal and vertlcal dlrections, said sen~ors bclng sdapted to plck up an ob~ect hnd producing an ima~e data slgnal t~f ~ald ob~ect;
8 processor tor processing the lmage data slgnal rrom ~aid televlslon camera;
memory clrcuit baving a plurality memory elements the number Or whlch belng at least equal to the number Or said sensor elements and which are arranged in a matrix slmllar to that or sald sensor elements, ror storing the lmage data trom said televlslon camera;
scannine means rOr scanning addresses Or aaid memory elements ln synchronlzatioD ~lth horlzontal and vertical ~cannlngs ln said televlsion camera 50 as to store lmage tlata trom respective sen30r elcments on corresponding memory e!ements;

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~ eans for memorizlng si~nals, used to determine which Or said loa~e d~ta from s-ld televi5ion camcra are to bc masked, on ~emory ele~ents of said memory circult at correspondlng ~ddresses;
~ eans for generatlng a control slgnal based on the memory daSa read ouS from ~aid memory clrcult ln rcsponse to the scannlng of sald target screen to indicate which image data is processed or not; and ~eans for controlling supply Or the image data rrom the televl~lon camera to said proccs~or ln response to ~ald control sl6nal.

The addltional, and other ob~ect~, features and advantaBes or the present inventlon will become apparent from the rollowlng descriptlon taken ln conjunctlon with the accompanying drawings through which the like references designate the same elements~and parts.

BRIEF DESCRIPTIO~ OF THE DRAWI~GS

Fig. 1 is a block diagram showine a prior art image : data processing apparatus usin~ a televlsion camera;
Fig. 2 ls a block diaBram showing another prior art lmage data processing apparatu~ using a television camera;
Flg. 3 ls a block dlagram showing an example of the lmage data maskin3 apparatus according to the present lnvention which is applied to the prior art apparatus .shown in Flg. 1, by way of example;

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Flg. 4 is a plan view of an example of the lmage pick-up screen of the television camera which is used ln the present lnventlon;
Figs. 5A to SE are respectively wavefo-m diagrams u~ed to explain the operation Or the present invention; and Fig. 6 ~ appearing with Fi~s. 1, 2 and 4, is a block diagram s~wing ~no~;ler e~r~le of the present invention.

~ESCRIPTIO~ OF THE P~EFE~PED EMBODIMENTS

Prior to the explanations of the present inventlon, for the better understandlns the same, 2 examples or the conventional image data processlng apparatus which use a television camera will be explained ln conjunction with Fig. 1 and Fig. 2, respectively.

In ti~e example shown ln Flg. 1, the lma~e lnformation or data slgnal Or an 4b~ect (not shown on the drawlng) from a televislon camera 1 is amplified by an amplirier 2, which output is supplled to a comparator 3, by which binary data signals such as white and black signals are obtained which are then fed to a processor 4 which, for instance, is a computer and wherein the signals are ima~e-processed sultably, as required. On the other hand, ln the prlor art example shown ln Fig. 2, the image data signal from the televlsion camera 1 is passed as in Flg. 1 through an ampllrler 2 to be ampliried. The analog si6nal from the amplirier is digitalized by A/D ~analo~-to-digital) converter 5, and the dlgital signal is supplied So and processed in the processor 4 such as a computer or the like similar to that shown in Fig. 1. With rererence to Fi8. 3, on example of the lmage data mask~ng apparatus accordirg to the present lnvention, is explalned, for the case where it is applied to the image data processing apparatus as shown in Fig. 1 as an example.

Fi~. 4 shows an exsmple in accord with the present lnventlon o~ a photoelectric converslon screen used ln the televlsion camera 1 formlng lts pick-up screen lP. In this case, 64 picture sensor ele0ents are arranged in an 8 x 8 matrix to rorm the target or lmage plck-up screen 1P.

First, the pick-up screen 1P Or televislon camera 1 will be explalned ln reference with Fig. 4. In Fig. 4, the respective lines in the row or horizontal directlon x of the pick-up screen are each rormed Or 8 sensor elements a1 ........ a8, b1 ...... b8, ....... hl ...... h8, while the respectlve llnes in the column or vertlcal directlon y each consists of 8 sensor elements a1 ...... h1, a2 ~... h2, ..... , a8 ..... h8. The target screen 1P ln practical use may contain a large number Or sensor elements such as 300 x 200 as an example, but rOr explanation convenience, ln the example on Fig. 4, the number illustrated is 8 x 8 = 64.

Now turning to Fig. 3, there is provided a television 3~

camera 1, ampllfler 2, comparator 3 and processor 4 same to the case of Fig. 1, but wlth the important difrerence that an lmage lnrormation or data masklng apparatus generally referred to by the numeral MA i3 inserted between the output Or the comparator 3 and the input of the processor 4.

Thls image data masking apparatus MA includes an AND
circuit 6, a memory circuit 7, a manual reverse switch 8, an lnverter 9, horizontal and vertical synchronizing signal separat'on circults 10 and 11, a first binary counter 12, a clock generator 13, a second blnary counter 14, inverters 15, 16, an OR
circuit 17 and a manual control switch 18.

The output of the comparator 3 is supplied to one input terminal Or the AND circuit 6, which output is supplied to processor 4. To the other input terminal of the AND circuit 6, ls connected the data output from the memory circuit 7, which contains memory elements, the number of which corresponds to that of the picture elements al ...... h8. The output from the memory circuit ls supplied directly via the reverse switch 8 or through inverter 9. For this memory circuit 7, read/write memory is used as an example, but when the number of memory elements to memorized data is great, it is convenient to use a RAM Irandam access memory) or the like for the memory circult 7, and therefore in the following explanations we shall assume that a RAM is used. In other words, the output of the memory circuit 7, 3~

dependance on lts memory content constructlon is passed to the AND circuit 6 which ls then operated so that the output signal from comparator 3 is controlled to either be red or not to the processor 4. Therefore, the capacity of memory circult 7, ln other words, the number Or lts memory element3, becomes dlfferent depending upon the number Or dlvisions of the target or picture screen 1P Or the televislon camera 1. In the example of the present lnvention, as shown on Fig. 4, the target screen lP ls rormed Or 8 x 8 - 64 sensor elements arranged in a matr~x form, and accordin~ly the capaclty Or memory circult 7 will be sufriclent wlth 64 bits. However, when the number Or sensor elenents ln the target screen 1P ls greater such as 300 x 200, the memory circults 7 will necessltate a memory capacity over 60 bit.

In the television camera 1, scanning normally takes place rol.lowing the sequence of sensor elements a1 .... a8, bl ..... b8, ..... , hl ...... h8 of the tar8et screen 1P as shown in Fi6. 4. At such case, if image data signals only from a llmited pattern area such as the sections hatched with a single line containing sensor elements c3, c4, d3, d4, e3, e4, e5, e6, r3, f4, f5 and f6 are desired to be processed then the other parts of the target screen 1P are masked out so that any ima_e data Slgnals therefrom are not fed to the processor 4.

Accordlng to the present lnventlon, the above masking ~3~

i3 carrled out mainly by the functior of the memory circuit 7, which will be explained hereunder in conjunction wlth Fig. 3.
The lmage data signal icomposite video signal) from the television camera l normally contains the image signal o~ the entire tar~et screen 1P as well as horizontal and vertical synchronlzing slgnal~. Thus, the image data signal from television camera 1 is ~upplled to the comparator 3 through ampll~ier 2 while at the same time lt is also fed to the horizontal synchronlzlng signal separation circuit tO and vertlcal synchronizing signal separation circuit 11, where the horizontal and vertical ~ynchronizih~ ~ignals HD and VD are respectively separated or extracted from the image data slgnal.

Next, the separated horizontal synchronizing signal HD
ls applled to the clcck lnput terminal of the flrst binary coutner 12 and the output from the blnary counter 12 ls applied to the higher address lnput terMinal among the address lnput terminalls of memory circuit 7. On the other hand, the clock pulse signal that is the output of the clock generator 13 is fed to the clock input terrsinal of the second binary counter 14, and the binary output signal therefrom ls applied to the lower address irput terminal of memory circuit 7.

As the next step, reference is made to the waveform diagram of Flg. 5A to Fi8. 5D. Flgs. 5A and SB respectlvely show the vertlcal 9ynchronizlng signal VD as well as horizontal 1. .

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synchronizlng signal HD from the vertical as well as horizontalsynchronizing signal separation circuit 11 and 10 respectively.
~igs. 5A and 5B is based on the example of a target screen 1P
which is rormed Or a relatively small number of sensor elements such as 8 x 8 - 64 as in Fig. 4, but is correspondin31y lllustrative Or the case where a larger number of sensor elements are used.

Normally, the horizontal synchronizing signal HD is outputted when one horizontal scan of the target screen lP is completed, whereas the vertical synchronizing signal VD is outputted when all scans of one target screen 1P are completed, so that the rollowing explanations will be made under such same concept.

In the illustrative example where the tar~et screen or sensor element matrix llP formed of 8 x 8 = 64 sensor elements 8 horizontal synchronizing signals are outputted during the time period TV betweer. the consecutive vertical synchronizing slgnals VD. ~herefore, when the horizontal synchronizing slgnal HD from the horlzontal synchronizing signal separation circult 10 ls supplied to the blnary counter 12 at its clock input terminal and output binary counter 12 at its clock input terminal and output bina~y signal from the latter is fed to the higher address termlnal of the memory circuit 7, the respectlve addresses in memory clrcult 7 appolnted thereby designate sensor elements a1 _9_ ~ 9;~
..... a8, b1 ...... b8, ..... , hl ...... h3 on the column direction or vertlcal directlon y in the sensor element matrlx 1P shown ln Fie. 4.

As the next step, the lower address of memory circult 7 is determined, which address designates the row direction or horizontal directlon x of sensor elements in the sensor element matrlx 1P Or Flg. 4. The clock generator 13, whlch supplles the clock sigral to the binary counter 14, that appoints the lower addresses of memory circuit 7, has an oscillation period preset so as to Benerate 8 pulses within one period Th Or the horizontal synchronizlng signal HD. (see Figs. 5D and 5E) In order to attain accurate clock generation, it may be proper to use a crystal generator as the generator 13. Otherwise, although not illustrated on the drawings, ir clock signals are outputted rrom the television camera 1, such signals may also be used. ~ow, the vertical synchronizing signal VD is supplied to an inverter 15 to invert the polarity thereof forming a signal ~ as shown on Fig.
5C, which ls then supplied through the OR gate 17 to the enable terminal of the clock generator 13. Accordln~ly, as shown ln Fig. 5C, when the reversed vertical synchronizing slgnal~ rises to posltve, which is the time point t1, the clock generator 13 starts to 8enerate the clock pulse CK as shown in Fig. 5E. Thus, as aforementioned, 8 clock pulses CK are generated during each perlod Th Or the horizontal synchronizlng slgnal HD. It ls noted that whlle the tlme point tl ls the same on Figs. 5A throu~h 5E, ~ ~ 9~

in order to clarify the relation between the respective slgnals, the time ba~e is expanded on Figs. 5C to 5E as compared to that of Flgs. SA and SB. Further, the horizontal synchronizing signal ~, ls, as shown on Fig. SD, polarity-reversed by bein8 fed to the inverter 16 and then supplied to tne other input ter~inal of the OR 8ate 17, so as to form a part of the snable signal to the clock generator. Therefore, the clock generator 13 is also controlled by the horizontal synchronizing signal to thereby generate a clock pulse C~ always and accurately during the period Th Or the horizontal synchronizine signal.

The clock pulse CK is supplied to the clock input tçrminal of the second counter 14, which output binary signal is supplied to the lower address lnput terminal of memory circuit 7 to thereby designate the lower addresses thereor. This means that the addresses or the 8 sensor elements in line direction or horizontal direction x on the sensor element matrlx or target screen lP as shown on Fig. 4, are designated in memory circuit 7.

Thus, in response (synchronism) with the scan of the television camera l, the addresses of the memory element3 in the memory clrcuit 7 are practically canned.

Further, the rirst counter 12 which designates the higher addresses Or memory circuit 7, ia cleared at every scan completion of the entire target screen lP because the inverse .

vertical synchronizing slgnal~~ as provided by the inverter 15 is supplied to its clear lnput terminal. On the other hand, the counter 14 whlch designates the lower addresses Or memory circult 7, ls cleared at every one horizontal scan of the target rcreen lP since the reverse horiaontal synchronizin~ signal ~ provided the inverter 16 ls applled So its cleaqr input terminal.

In the above example of the present invention, the division of target screen 1P in the vertical and horizontal direction i5 set as 8 x B = 64, so that an address bus Or 3 bits for the hlgher addresses as well as 3 bits ~or the lower addresses which total is 6 bits at the memory circuit 7 will sufflce.

Turnin~ to the memory circuit 7, the control switch 18 iFig. 3) i~ a manually operated control switch connected to a source Or current controllins the read and write functions of memory circult 7,. When control switch 18 ls connected to the postive side 18P, it is arranged ~or read mode and when the control switch 18 is connected to the ground side 18G, it is arrangled for write mode, respectively. Let's assume that the control switch 18 is connected to the side 18G which is the read side. As shown in FiB. 3 the binary data signal rrom comparator 3 is supplled to the data input terminal Or memory circult 7, so that the binary slgnals (low or high) from comparator 3 in response to the scan Or the target screen 1P in the television camera 1 are supplied to respective memory elements of the memoryclrcuit 7 and then memorized thereon.

Now, it is assumed that among the 8 x 8 = 64 sensor or plcture elements on the tar6et screen 1P, the plcture elements c3, c4, ..... .f5 and f6 of the small pattern with sin&le hatch lines ln Fi~. 4 are taken as black while the other picture elements as whlte. When this target screen 1P of the television camera 1 ls scanned, comparator 3 outputs such lmage data signals ln which the slgnals from the above mentioned picture elements c3, c4 ...... f5 and r6 ln the hatched portion are low, while the same for the remalning picture elements are high. Thus derived lmage data 31gnals are then supplled to the data inpuk termlnal of the memory clrcuit 7. At this time, as above mentioned, the control lnput terminal 18 of the memory circuit 7 is switched to the write slde 18G of the control switch 18 so that at the respective memory elements of memory circuit 7 with the addresses corresponding to the picture elements on the target screen lP
that is dlvided into 8 x 8 - 64, the high or low data from the comparator 3 are respectively memorized. As the next step, the control switch 18 ls switched to contact 18P so that the manually operated reverse switch 8, which is connected to the data output terminal Or the memory clrcuit 7, is connected to the lnverter 9.
The output signal ~data) from memory clrcult 7 ls thus supplied as a reverse signal to the other lnput terminal of the AND
clrcult 6. Under such condition; if the television camera 1 ~3~

starts its pick up operatlon and the picture elements c3, c4 ~ . rs and f6 of the target scren 1P are scanned, the hlgh signals are supplied to one input terminal of the A~D clrcult 6 from the comparator 3. Thus, only the output slgnals that correspond to the image data of the picture elements c3, c4 .....
fs and f6 ~with the single hatch lines) from the comparator 3 are supplied to the processor 4 via the AND circult 6. In other words, the ima8e data si~nals from the plcture ele~ents of other sections than that of the plcture elements within the hatch line group are masked, which means that such data signals are not transferred to the processor 4.

So long as the above maskins pattern is constructed ln the memory circuit 7 and its control input terminal ls connected wLth the read side 18P Or the control switch 18, even though there are changes (low or high) in each data within the small pattern or picture elements c3, c4 ...... rs and f6, only such data s:Lgnals (data) from the picture elements within the small pattern will be 3upplied to the processor 4.

In contrast to the above case, when only the small pattern sectlon or picture elements c3, c4 ...... r5 and f6 are deslred to be masked, it is sufficient that the reverse switch 8 is connected to the side 8I so that the inverter 9 ls not passed, and the data output from the memory circuit 7 Ls directly supplied to the other lnput terminal of the AND clrcult 6. rhat !

is, slnce the low data are respectively memorized in the memory elements at the addresses Or the memory circuit 7, which correspond to the small pattern or picture elements c3, c4 .....
r5 and f6 ln the tar~et screen lP, the other input Or the AND
circuit 6 ls low when the small pattern of picture elements c3, c4 ...... f5 and f6 on the target screen lP lr television camera 1 are scanned. Thus, the passage of output si~nal from comparator 3 through the A~D circuit 6 to processor 4 ls stopped from perrorolng the masking. Only when the other picture elements are scanned the output signal from the comparator 3 transrerred to the processor 4.

To lnitially set the system for masking, it ls enough that a pattern cr ~hite and black (paper may be used~ be preliminarily plcked up by the television camera 1. By throwing the control switch 18 to the write side 18G the picked up mask patSern ls constructed withln the memory circuit 7 based upon the output from the comparator 3. Further, it may also be possible to make a mask pattern by using the actual objects (products or the like) to be picked up.

As such, according to the present lnvention, lt is very easy to form the desired masking pattern and also to chan~e the same as desired, so that superior effects can be presented.

Further, when the present invuntion 13 applled to the ~~ )V~

case where, lnstead o~ convertlng the ima~e data 5ignal rrom thetelevision camera 1 into the binary data signal by comparator 3 as shown in Fig. 1, the data signal may be datarlzed to the multi value signal by the A/D Converter 5, as shown on Flg. 2, as shown in Fi~. 6. Instead, Or the AND clrcuit 6 in the masking apparatus MA as shown on Fig. 3, a bus buf~er 19 or the like which can control the data passage ~ay be used. or course, in such case, to the data input terminal Or the memory circuit 7 (not shown in Fig. 61, ls as shown ln the drawing supplled with an lnput slgnal from the output amplifier 2 via the comparator 3.
The other constructlon and functions of the example shown in Fig.
6 are exactly the same as those of the example shown on Fig. 3, so that such illustration as well as explanation will be herewith omitted.

~ hen the horizontal and vertical synchronizing signals are outputted rrom the television camera 5eparate from the image signal, the separation circuits used in the above example Or the inventlon may be oMitted. Further, various circuit changes such as changing the memory capacity Or the memory circuit 7 in accordance with the number Or the divided picture elements, instead Or the AN~ circult 6 or bus burrer 19, masking the lmage data slgnal as an analong signal and then supplyln~ the same to the processor by the use of an analog switch and so on may be freely made without departing from the main concepts Or the present invention.

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-It is noted that the above mentioned example of the present lnvention is applied to the case where the tar~et screen lP of the television camera 1 is formed of a plurality of sensor or picture elements arranged in a matrix pattern. Ho~ever, the present invention may be applied to a case where a television camera, uses a normal pick-up tube, for example, a clock generator is used to divide the output lmage data si~nals from the televlsion camera as aforementioned. It will be apparent that the latter case becomes the same as the case where the television camera which has a plurality of picture elements arranged ln a matrix as shown ln Fig. 4, is employed, ~ he above description ls given on preferred embodiments of the present invention, bLt it will be apparent that many modifications and variation~ could ~e effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the lnvention.

Claims (11)

1, An image data masking apparatus for use with image data processing apparatus comprising:
a television camera having a target screen formed of a number Or sensor elements arranged in a matrix in horizontal and vertical directions, said sensors being adapted to pick up an object and producing an image data signal of said object;
a processor for processing the image data signal from said television camera;
a memory circuit having a plurality memory elements the number of which being at least equal to the number of said sensor elements and which are arranged in a matrix similar to that of said sensor elements, for storing the image data from said television camera;
scanning means for scanning addresses of said memory elements in synchronization with horizontal and vertical scannings in said television camera so as to store image data from respective sensor elements on corresponding memory elements;
means for memorizing signals, used to determine which of said image data from said television camera are to be masked, on memory elements of said memory circuit at corresponding addresses;
means for generating a control signal based on the memory data read out from said memory circuit in response to the scanning of said target screen to indicate which image data is processed or not; and means for controlling supply of the image data from the television camera to said processor in response to said control signal.

2. The image data masking apparatus according to claim 1, wherein said scanning means comprises a horizontal synchronizing signal separating circuit for separating a horizontal synchronizing signal from the image data signal applied thereto from said television camera and a first binary counter supplied with the horizontal synchronizing signal thus separated as its clock and producing output signals which are applied to said memory circuit at its higher addresses to designate addresses of said memory elements in the vertical direction.

3. The image data masking apparatus according to claim 2,wherein said scanning means includes a clock generator for producing clock pulses, the number of which is same as the number of said sensor elements in the horizontal direction and a second binary counter supplied with the clock pulses and producing output signals which are applied to said memory circuit at its lower addresses to designate addresses or said memory elements in the horizontal direction.

4. The image data masking apparatus according to claim 1, herein memorizing means comprises switch means for controlling writing and reading of said memory circuit.

5. The image data masking apparatus according to claim 1, wherein said control signal generating means comprises an inverter for inverting the control signal in polarity.

6. The image data masking apparatus according to claim 1, wherein said supply controlling means is a digital switch.

7. The image data masking apparatus according to claim 1, wherein said supply controlling means is an analog switch.

8. The image data masking apparatus according to claim 2,wherein said scanning means includes a vertical synchronizing signal separating circuit for separating a vertical synchronizing signal from said image data signal and a first inverter for inverting the vertical synchronizing signal applied thereto from said vertical synchronizing signal separating circuit in polarity, said inverted vertical synchronizing signal being supplied to said first binary counter at its clear input terminal.

9. The image data masking apparatus according to 3, wherein said scanning means includes a horizontal synchronizing signal separating circuit for separating a horizontal synchronizing signal from said image data signal and a second inverter for inverting the horizontal synchronizing signal applied thereto from said horizontal synchronizing separating circuit in polarity, an inverted horizontal synchronizing signal being applied to said second binary counter at its clear input terminal.

10. The image data masking apparatus according to claim 9, including an OR gate through which the inverted horizontal and vertical synchronizing signals from said second and first inverters are supplied to said clock generator at its enable input terminal.

11. The image data masking apparatus according to claim 1,including a comparator which receives the image data signal from said television camera and converts said image data signal to binary data, said binary data being supplied to said memory circuit.