CA1181480A - Electric motor chopper control apparatus and method - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A programmed microprocessor controller chopper apparatus for an electric motor is responsive to an oper-ating condition of the chopper such as at least one of the commutation capacitor charge voltage and the level of motor current for determining the desired commutation circuit operation for that chopper apparatus in relation to the provision of an OFF control pulse in relation to an ON control pulse every cycle of the microprocessor program operation.

Description

49 ~ ~73 ELECTRIC MOTOR CHOl?P~ CONTROL
APPARAl~S AND P!l:ETH~D
CROSS- REFERENOE TO RELAT~D PATENTS
The pre~ent application is r~lated to a U~.S., Patsnt No. 4,257,092 ls~ued March 17l 1981 to F, JO
Prine~3 et al. aIld U.S. Patent 4,090,115 of JO Ho Fr~z, ~Tr. ~ d Ma~ 16, 1978, which are a~lgned to the same a~signee O

l~e pres~snt i~nven~on rçlate~ to the appllcatlon o:~ thyrlstor chopp~r apparatu~ ~or dete~m:lnlrlg th~ eîec-tric bral~e ~peratioxl oï a ~er:~e~ propul~ n motor an~ more particularly -to control apparat~ls including a micr~pro-ces~or that i3 progralluned for ~he de~lred co~trol o~ such thyx~tor chopper apparatu~
a:rticle entitled "Propul~ion Control for Pas~enger Train~ Provide3 High-S~eed Service" pllbli~hed .~n the Westillghou~e Englneer ~or ~eptem~er~ 1970 ~ page~ 143 to 149 a~d. in an artic:l.e entitled "A:Ltc~na~ive ~ys~em~3 for R~pid Tran~it Propul~ion and Electric Braklng" publîshed in the We~tinghou~e Eng~neer ~or March~ 1~73 at pa~es 34 to 41, th~re i~ de~cribed a thyri~tor chopper control system .~or psopul~ion and ~lectric ~akl3lg oi tra~s:Lt ~ehlcle~. The ~hyris~,or chopper pro~ride~ a propulslon sy~tem that is sup2rior in ~moothnes~ and ea~e OI ma:lLn~
taiT~ng a given æpeed which latter feature provldes ~h~
25 de~ired automat:Lc train oontrol~ In addlt~on, the thy-8~

2 49,373 ristor system makes regenerative braking practical because the response is fas~ enough to continuously match regener-ated voltage to line voltage.
It is known in the prior art as disclosed in U.S. Patent ~,095,153 issued June 13, 1978 of T. C. Matty et al. to use a dynamic braking control chopper apparatus for a vehicle electric motor propulsion system, wlth a regulator turning on the chopper when the motor current goes below a predetermined level for increasing motor current and the regulator turning off the chopper when the motor current goes above a second predetermined level for decreasing the motor current.
It is known as disclosed in U.S. Patent ~l,090,115 to provide a boost pulse to control the dead time around the ON control pulse in relation to the OFF
control pulse of the main chopper for controlling the commutation circuit of the main thyristor. This commuta-tion circuit requires a predetermined ~ime interval to be established to prevent the firing ON of the main thyristor while the commutation circuit is operative relative to the commutation thyristor. The actual time length of the provided control boost pulse is determined by the required length of time or the associated program software to be executed for providing this boost pulse ~unction. A
microprocessor permits changing the execution path in the program to control the start time of the boost pulse, which is the last time an OFF pulse can be ~irecl, and to control the start time of the ON pulse positionecl in relation to the middle of the boost pulse. The trailing edge o~ each boost pulS2 iS the first place the next OFF
pulse can be ~ired to protect against running the OFF
pulse into the next ON pulse and to protect against run-ning the last ON pulse into the next OFF pulse. This avoids any problem with the thyristor memory to assure that the proper thyristor goes ON when desired. I~ -the desired thyristor were not fired ON at the proper time, this could result in an undesired positive feedback oper-~8~

3 ~9,373 ation to lock up the chopper system with the main choppernot functioning as desired.
UMMARY OF THE PRESENT INVENTION
A programmed microprocessor apparatus establish-es a boost signal for controlling the operation of anelectric motor control chopper apparatus, with every cycle of the program operation including an ON control pulse positioned within the boost signal for establishing the desired commutation circuit operation in relation to the main thyristor of the chopper and assuring that the chop-per will function properly. To enable an adequate re-charge of the commutation circuit capacitor during the OFF
pulse cyGle of the chopper operation when the motor cur-rent is low, such as when dynamic brake build-up is desir-ed, the microprocessor senses an operating condition ofthe chopper, such as the motor current, to determine an adaptive extension o~ the OFF control time period by one of modifying the boost pulse after the last OFF pulse and before the next ON pulse or by adjusting the position o the OFF control pulse to increase the time the main thy~
ristor is OFE when desired to increase the available commutation capacitor charge voltage for improving the control of the chopper operation. It is within the scope o this invention to sense at least one of the motor current and the commutation capacitor charge voltage to adjust the provision time of the OFF pulse in relation to the ON pulse to increase the OFF time o~ the chopper when re~uired to build up that commutation capacitor charye volta~e.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a unctional showing of a prior art pr~pulsion motor control apparatus in relation to the typical input signals and the output signals operative with such a control apparatus;
Fig. 2 illustrates the input signal operations and the output signal operations of the prior art control apparatus shown in Fig. 1;

4 49,373 Figs. 3A, 3B and 3C illustrate schematically the provided hardware interface of the prior art control apparatus shown in Fig. 2;
Fig. 4 shows the response of a prior art propul-sion motor control apparatus to a well-known P signal;
Fig. 5 shows the time relationships of the prior art boost pulse, the ON signal within the boost pulse and the clock pulse;
Fig. 6 shows in greater detail the prior art time relationships of the boost pulse and the ON signal within the boost pulse as shown in Fig. 5;
Fig. 7 shows the well-known position relation-ships of the prior art ON control pulse in relation to ~arious OFF control pulses Eor providing respective desir-ed duty cycles for the chopper apparatus;
Fig. 8 shows the provision of an e~tended timeduration boost pulse in relation to sensed motor current in accordance with the present invention;
Fig. 9 shows in greater detail the extended boost pulse of Fig. 8;
Fig. 10 illustrates a modified adaptive adjust-ment of the boost pulse time duration in relation to the sensed motor current;
Fig. 11 shows the charge voltage providecl across the commutation capacitor of the chopper apparatus in relation to the ON and OFF operations of the chopper apparatus;
Fig. 12 (on the same sheet as Fig. 10) shows a suitable circuit arrangement for sensing the charge voltage o~ the commutation capacitor; and Fig. 13 shows a diferent embodiment of the present invention including a ~lodification of the hardware inter~ace shown in Figure 3A to provide a comparison o:E
sensed motor current with the charge voltage of the commu-tation capacitor for determining the chopper OFF time bycontrolling the time occurrence oE -the OFF control pulse in relation to the ON pulse; and 8~
49,373 Figure 1~ (on the same sheet as Fig. 9) shows a further embodiment o~ the present invention to provide a comparison of the commutation capacitor charge voltage with a reference bias voltage for controlling the OFF time of the chopper apparatus.
DESCRIPTION OF A PREFERRED EMBODIMENT
In relation to Figs. 1 through 6, there i.s provided a more detailed description of the illustrated prior art propulsion control apparatus in the dis~losure of U.S. Patent 4,090,115, which is above cross-re~erenced.
In Fig. 1, there is shown a functional illustra-tlon of a prior art chopper control apparatus incl~lding typical input signals and output signals opera-tive there-with in relation to controlling a transit vehicle propul-sion motors. A CPU microprocessor 9~ is operative with aPROM programmable memory 96 and a scratchpad RAM random access memory 98 used for intermediate storage. A suit-a~le application program, such as the program listings included in the Appendix A and Appendix ~, is stored in the programmable memory 96. The microprocessor 9~ can be an Intel 8080, the random access memory 98 can be an Intel 8101 and the programmable memory 96 can be an Intel 1702 programmable read-only memory, which items are currently available in the open marketplace. The illustrated digit-al inpu~ signals are supplied through digital input 100from the transit vehicle associated with the chopper apparatus 101. The illustrated analog input signals are supplied through analog input 102, the illustratecl digital output signals are supplied through digital output 104 and the analog output current request signal I~ is supplied through analog output 106 to the analog phase controller 108 operative to cletermine the control signal ON to fire the main thyristor Tl, the control si.gnal OFF to fire the commutating thyristor T2 and the control signal T5 for the dynamic brake T5 thyristor in the propulsion motor control chopper apparatus 101, as well known to persons skilled in this art and as described in the above r~ferenced March 1973 article. The time period associated with turning the 6 49,373 chopper apparatus ON and OFF is at a constant freguency of 21g hertz that defines the clock time interval for the program cycle and for checking the process operation.
During each of the 218 time intervals per second, the application program cycle operates.
In Fig. 2, there is illustrated the input signal operations and the output signal operations of the prior art chopper control apparatus including the microprocessor 94 operative with its random access memory 98 and its pro-grammable memory 96. The analog input signals are sup~plied through the analog input 102 through the multiplexer 120, the analog to digital converter 122 and the input port 124 of the microprocessor 94 operative with a data bus 126 and an address bus 128. The address bus 128 and the data bus 126 operative through an output port 130 to control the multiplexer 120 and the analog to digital converter 122. The digital input signals are supplied through the digital input lO0 operating through bu~fer 132 with the input port 136 operative with the data bus 126 and the address bus 128. The digital output signals are supplied through the digital output 104 including output ports 140 and 142 and respective isolation circuits 144 and 1~6 with dri~ers 148 and 150 in relation to the data bus 126 and the address bus 128. The analog output 106 is operative through output ports 152 and 154 through a buffer 156 and a digital to analog converter 15~ with the analog phase controller 108. The output port 153 is operative through isolation circuit 194 with the provided test point 190 and is operative with display 192. The manual switches 196 are operative with input port 137 as shown. The analog phase controller 108 supplies, through the respective ampli*iers 109, 111, and 113, the ON COIl-trol pulse T1 for the main thyristor, the OFF control pulse T2 for the commutating thyristor, and the T5 dynamic brake control pulse.
In Figs. 3A, 3B and 3C, there is schematically illustrated the provided hardware interface of the prior 7 ~9,373 art chopper logic control apparatus disclosed in U.S.
Patent 4,090,115. The analog input 102 is shown in Fig.
3A operative through multiplexer 120 and the analog to digital converter 122 with the input port 124 of the microprocessor. The output port 130 is operative with the register 131 to control the multiplexer 120 and the analog to digital converter 122. The output port 152 is shown operative with the digital to analog converter 158 and the analog phase controller 108. The output port 106 is shown operative through buffer amplifiers 156 with the drivers 109, 111 and 113 for controlling the respective thyristors Tl, T2 and T5. The output port 142 is shown operative with the isolation amplifiers 146. The output port 1~0 is shown operative with the isolation amplifiers 144. The output port 153 is shown in Eig. 3B operative with isola-tion amplifiers 194 and test point 190 and operative with display 19~.
The load weighed current re~uest P signal is output by amplifier 1530. Then the buffer 155 leads to the phase controller amplifier 157, which responds to the current request signal from buffer 155 and the motor current signals Il and I2 from lines 159 and 161, and the output of phase controller amplifier 157 is the re~uested OFF pulse position or the phase angle IP. The output of the amplifier 157 is compared by comparator 163 with the timing ramp from amplifier 165 which is reset by the computer each 218 hertz. The comparator 163 establishes when the phase angle signal IP has exceeded the timi.ng ramp, and this would determine at the output of comparator 163 where the OFF pulse is positioned. The logic block 167 determines whether or not the OFF pulse position output of comparator 163 is actuall~ used. For example, if comparator 169 determines there is too much current in the system, the OFF pulse will be ~ired and might inhibit or suppress the ON pulse in logic block 171 which is operative with the Tl ON pulse. The boost pulse comes from the computer and goes into the logic block 167 on 8 49,373 line 173, and will fire an OFF pulse on the leading edge if comparator 169 has not already fired a pulse and sup-press any further action out of the control system. The logic block 167 includes a flip-flop operative such that if an OFF pulse is fired once during a given program cycle, a second OFF pulse is not fired during that same program cycle.
In Fig. 4, there is illustrated tne well-known response of the prior art propulsion motor control appar-atus to the P signal 30. When the P signal 30 is below avalue of about 60 milliamps, ~he control apparatus oper-ates in the brake mode and for a P signal above this value of 60 milliamps, the control apparatus operates in the power mode.
The boost pulse signal .is developed during every cycle of the program operation. The start of the boost ,~ pulse as shown in Fig. 5 is provided in response to the clock pulse~The position of the ON signal within the boost pulse is determined by the control program. The current re~uest is provided at output 152 going to the digital to analog converter 158 and the analog phase controller 108 shown in Fig. 2 and Fig. 3A. The P signal determines the current requast I~ to the analog phase controller for establishing the ratio of ON to OFF operation of the chopper. The end of the boost pulse is determined by the control program.
The boost signal provides a protectlon time band during which an OFF pulse cannot be provided, which pro--tection time band is selected in relation to the known operational speed of the microprocessor such that an OFF
pulse cannot occur within a known time period be~ore the ON pulse and w.ithin a known time period after the ON pulse as il].ustrated in Fig. 6. The guard protection time band is provided to the analog system operation, since the boost is used to release the OFF pulse. The OFF pulse can be defeated during the boost signal interval, and the ON
pulse can be suppressed by the SUPPRESS signal ~rom the 9 49,373 digital output 104 if desired for some reason. An OFF
pulse is allowed only outside of the boost signal, and the position of the boost signal protects the ON pulse in this regard, and thus the main chopper circuit.
The output 154 shown in Figure 2 provides the boost signal to the buffer 156 and the analog phase con-troller 108. The microprocessor operates in a time se-quential manner. The prior art chopper control apparatus provided the boost signal and the ON pulse position rela-tionship generally as shown in Fig. 6.
The analog phase controller 108 can respond to an OFF pulse anywhere between the falling edge of one boost signal and the leading edge of the next succeeding boost signal, and this establishes the OM/OFF ratlo of the chopper since the microprocessor puts out the ON pulse shown as ~0 in Fig. 1 and it puts out the boost pulse.
The phase controller cannot fire the OFE pulse before the falling edge and cannot fire after the leading edge of the boost pulse, so the boost pulse in effect determines a dead band. The boost pulse can be determined to have a known time duration and the time cycle of the boost pulses is determined by the clock puise rate. The analog phase controller can fire the OFF pulse anywhere during the total time cycle other than during the boost pulse. The ON pulse is timed by the microprocessor to be within the boost pulse, as shown in Fig. 6. This time relationship is required to allow the thyristor circuit of the chopper to compl.ete the last received command signal; for example, after an OFF pulse is given to the thyristor T2 then -the provided time period is required before an ON pulse can be given to thyristor T1 to permit the chopper circuitry to reset properly for this operation. If the OFF pulse is not specifically suppressed before the leading edge of the next boost pulse, then an OFF pulse is fired by the phase controller, and after the leading edge of the boost pulse an ON pulse can be fired, i~ allowed. Normally, this ON
pulse is allowed, but the ON pulse can be suppressed 49,373 independently as well as the OFF pulse can be suppressed if desired. But in normal operation, the leading ed~e of the boost would be followed after a provided time period by the ON pulse, and after another provided time period the falling edge of the boost pulse is provided, with the phase controller establishing the desired ON/OFF time ratio by appropriately firing the OFF pulse in accordance with the current request si~nal I+.
The digital output provides the boost pulse to the analog phase controller. The clock initiates each program cycle and at the beginning of each cycle provides the leading edge of the boost as shown in Figure 5, then the microprocessor provides the ON pulse and provides the trailing ed~e of the boost pulse. After the boost inter-va]., the program goes through its desired operationsbefore the next boost pulse.
In Fig. 7, there is shown in general the well-known prior art provision of ON control pulses in relation to the OFF control pulses for providing desired duty cycles for the chopper apparatus. The clock pulse 300 initiates the provision of the boost pulse 302 with the ON
pulse 30~ provided more or less in the center of the boost pulse. If a 10% duty cycle of the chopper apparatus is desired, the OFF pulse 306 is provided. If a 20% duty cycle is desired, the OFF pulse 308 is provided. If a 30%
duty cycle is desired, the OFF pulse 310 is provided. If a 40% duty cycle is desired, the OE'F pulse 312 is provid-ed. If a 50% duty cycle is desired, the OFF pulse 31~ is provided. If a 60% duty cycle is desired, the OFF pulse 316 is provided. If a 70% duty cycle is desired, the OFF
pulse 318 is provided. If an 80% duty cycle is desired, the OFF pulse 320 is provided, a~ld if a 90% duty cycle is desired, the OFF pulse 322 is provided. For a 100% duty cycle of the chopper apparatus, no OFF pulse is provided.
In Fig. 8, there is illustrated the extended time duration boost pulse in accordance with a first embodiment of the present invention where the clock pulse 11 ~9,373 300 initiates the boost pulse 330; however, the ON pulse 332 has been delayed hy extending the portion o~ the boost pulse 330 prior to the occurrence of the ON pulse 332 in relation to the portion of the boost pulse 330 following

5 the ON pulse 332. In Fig. 8, the second clock pulse 340 is shown to initiate a normal boost pulse 342 without such an extended time duration before the ON pulse and with the ON pulse 3~6 positioned as shown in Fig. 7.
In Appendi~ A there is shown a control program listing in accordance with the first embodi~en-t which operates with the microprocessor 94 to sense the averacJe of the motor currents Il and I2 to determine if a normal or an extended boost pulse is provided. If the actual value of the average motor current is above a predeter-r~ined reference value, such as 100 amperes, then a normal boost pulse B as shown in Figure 8 is provided. If the actual value of the average motor current is below this reference value, such as 100 amperes, an extended boost pulse A as shown in Figure 8 is provided. A normal time delay after the beglnning of the boost pulse is about 386 microseconds for an above 100 amperes average motor cur-rent, and the extended time delay is about 539 microse-conds for a below 100 amperes average motor current.
In Fi~. 9, there is shown the extended boost 25 pulse 330 of Fig. 8 with the ON pulse 332 positioned such that the portion of the boost pulse 330 prior to the occurrence of the ON pulse 33~ has appro~imately a 539 microsecond extended time duration while the portion of the boost pulse 330 subsequent to the ON pulse 332 has the normal 386 microsecond time duration provided by the con-trol program of Appendix A.
In Fig. 10, there is shown the adaptive adjust-ment of the boost pulse time duration in accordance wlth a second embodiment of this invention and in relation to the sensed average motor current. The clock pulse 350 ini-tiates a boost pulse having one of a normal time delay after the beginning of the boost pulse, a first time delay 12 49,373 or a second larger time ~elay depending upon the average motor current ~alue. For the illustration of Figure 10, the boost pulse 35~ has the second time delay of about 629 microseconds prior to the occurrence of the ON pulse 35~ and this enahles a longer duration of the OEF cycle of the chopper apparatus for increasing the charge voltage on the commutation capacitor for particularly low motor current conditions of operation. The next clock pulse 356 initiates a boost pulse 35~ which has a first ~ime delay of about 539 microseconds prior to the occurrence of the ON pulse 360. The next clock pulse 362 initiates the boost pulse 364 which has the normal 386 microsecond time duration of the boost pulse prior to the occurrence of the ON pulse 366.
In Appendix B there is shown a control program listing in accordance with this second embodirnent of this invention, and which operates with the microprocessor 94 to sense the actual average motor current to determine of a normal boost pulse, a first time delay boost pulse or a second time delay boost pulse is desired. If the actual average motor current is above a first predetermined reference value, such as 100 amperes, then a normal boost pulse 364 is provided. If the actual average motor cur-rent is less than the first reference value of 100 amperes and above a second predetermined reference value, such as 50 amperes, then the first time delay boost pulse 358 is provided. If the average motor current is less thall the second pr~determined reference value, then the second time delay boost pulse 352 is provided.
In Fig. 11, there is shown the char~e voltage buil.d-up across the commutation capacitor in relation to the ON and OFF operations of the chopper apparatus, with the time duration TDl between the OFF pulse TOFF1 and the next ON pulse TON2 being in accordance with the normal boost pulse 364 and ON pulse 366 relationship shown in Fig. 10 while the time duration TD2 between the OEF pulse 13 49,373 TOFF2 and the subsequent ON pulse TON3 is greater and in accordance with one of the relationships of the boost pulse 358 to the ON pulse 3~0 or the boost pulse 352 with the ON pulse 354. The curve portion 400 is shown to bring the charge voltage across the capacitor to a level 402 whereas the curve portion 404 shows an extended commuta-tion capacitor charge resulting in a higher charge voltage level 406 on the commutation capacitor.
~s showrl in Fig. 11, the commutation capacitor BCC voltage level 405 goes down about 15% when an ON pulse 410 is fired. During the next OFF cycle initiated by the OFF pulse 412, thls charge voltage drops back about 15%
followed by a linear recharge ~00 up to line voltage 402.
~ Iowever, at low motor current, due to the I2R energy losses and at constant current of the motor circuit, this line voltage might not be reached if the ON pulse is fired too soon, such as ON pulse 414 following the OFF pulse 412 with the result that the BCC charge voltage on the com-mutation capacitor over several program cycles can keep getting smaller and smaller with the waveform 405 tele-scoping towards zero. A minimum charge voltage on the commutation capacitor is required to be reasonably certain that the chopper can be turned OFF before allowing the chopper to go ON. Otherwise, fault conditions miyht result. At higher motor currents, it is known that so many volts allows so many amperes, for example, 500 volts charge on a commutation capacitor will comm~ltate 1000 amperes of motor current. As the motor current gets higher, this BCC charge voltage must go higher. On the other hand, at low motor currents, sufficient time is required for the recharge of the commutation capacitor to reach an adequate commutation voltage.
In Fig. 12, there is shown a suitable circuit arrangement for sensing the charge voltage BCC of the commutation capacitor and the currents Il and I2 in the respective motor branches. As described in the above 14 49,373 cross-referenced patent 4,257,092, a direct current chopper apparatus is shown for controlling the average current suppl.ied from a direct current source 10 to a DC
series motor load circuit 12 which motor load circuit includes parallel branches well known to persons skilled in this art and described in the above-re~erenced article published in the Westinghouse Engineer for March, 1973.
A main thyristor switch device Tl repetitively operates in an ON condition and an OFF condition to chop the voltage applied to the motor load 12. The control of this voltage is determined by changing the ON operation time in relation to the OFF operation time of the conduc-tion o~ the main thyristor Tl ~or controlling the speed of the. motors in the motor load circuit 12. To reduce -the speed of the motors, the armature voltage is decreased and to increase the motor speed, the armature voltage is increased. The main thyristor switch Tl is gated ON to become conductive and subsequently commutated OFF to open and block as required to provide an average voltage across the motor load 12 which determines the motor speed. Each time the main thyristor Tl conducts, the voltage across the motor load 12 and the inductor 18 rises to the voltage o~ the power supply 10. Each time the main thyristor Tl blocks, the voltage across the motor load circuit 12 and the inductor 18 falls to zero, the motor load 12 responds to the average motor voltage. The main thyristor switc~
Tl requires a commutation circuit to become blockecl when it i9 desired that the main thyristor switch Tl no longer conduct current to the motor load 12. The commutation circuit includes a parallel connected commutating capacitor 26 and a comm~ltating thyristor switch T2 operative to shunt the motor current and stop conduction of the main thyristor switch Tl. To block the main thyristor switch Tl and stop conduction o~ motor current by the main thy-ristor switch Tl, the commutating thyristor T2 is gzted toconduct and applies a reverse bias voltage ~rom the capa-citor 26 across the main thyristor switch Tl to block the thyristor switch Tl.

49,373 The voltage charge across the commutation capac-itor 26 is shown measured with a well-known differential amplifier 27, and the ON pulse of the chopper apparatus as shown in Fig. lO can be delayed in relation to the sensed value of thls charge voltaye across the commutating capac-itor 26. The motor current Il through the motor circuit branch including the armatures Al, ~2 and the fields F1 and F2 is provided by a current sensing Hall effect trans-ducer 29, and the motor current I2 through the branch circuit including the motor armatures A3 and ~4 and the motor fields F3 and F4 is provided by a current sensing Hall effect transducer 31.
A dynamic brake build-up problem can result from the chopper attempting to stay ON too long during a de-sired brake current build-up operation. The chopper by staying ON too long reduces the voltage charge on the commutation capacitor to a level where an entire ON cycle has to be skipped. Since every ON cycle extracts I2R
losses from the commutation circuit and every OFF cycle includes a recharge period as a function of the current of the motor, if the motor current is high enough, then every OFF cycle of the chopper rechar~es the commutation capa-citor ade~uately to line voltage and proper commutation operation of the main thyristor Tl is enabled. However, when the motor current becomes low, such as when a brake build-up is attempted, the OFF pulse cycle might not fully recharge the capacitor adequately and the ON pulse can occur too soon before an adequate recharge of the commuta-tion capacitor is e~ected. Then the next OFF pulse cycle starts from an even lower voltags level and this OE'F cycle does not make up the voltage charge on the commutation capacitor that is lost by the previous ON cycle. The result of such successive cycles of operation when the motor current is low is the voltage across the capacitor can drop down to a level where further ON cycle operation of the chopper is prevented because the sensed BCC voltage across the commutation capacitor is too low to safely 16 49,373 permlt continued ON cycle operation of the chopper. Since the microprocessor senses the motor current, a predeter~
mined low value of the motor current can be selected such as 100 amperes for a well-known Westinghouse Type 1462 propulsion motor, where the initial portion of the boost pulse can be extended after the last OFF pulse and before the next ON pulse occurs by an amount determined by the sensed motor current value. By extending the front por-tion of the boost pulse as shown in Fig. lO, this in effect delays the next ON pulse to restrict the amount of time the main thyristor is ON and to increase the amount of time the maln thyristor is OFF which enables a longer voltage charge recycle in relation to the commutation capacitor. This increase in OFF time increases the commu-tation capacitor charge voltage to a level such that itwill not stop the desired operation of the chopper. In this way, the control apparatus senses a predetermined low motor current, such as 100 amperes, and extends the front portion of the boost pulse before providing an ON pulse.
It is within the scope of the present invention to sense a predete~^mined function of the motor current rather than to sense one predetermined low level of motor current. The ON and OFF time relationship of the chopper apparatus can be varied to maintain the desired brake motor current which builds during the ON cycle, and maintain the desired commutation capacitor charge voltage that builds during the OFF cycle.
In accordance with the first and second embodi-ments of the present invention, the average motor current is sensed to determine a front extension of the boost pulse, such as illustrated in Fig. 8 and in Fig. 10, to assure an ade~uate BCC charge voltage which may not get back up to line voltage but is sufficient, such as 400 volts, for a predetermined low motor current to control the chopper OFF operation. By sensing the motor current and providing a known exten~ion of the front portion of the boost pulse before the ON pulse occurs for a predeter 17 49,373 mined low motor current, the BCC charge voltage may tele-scope down to a predetermined charge voltage level, for example, 400 vol~s and maintain that 400 volts in response to this predetermined low motor current. The ON pulse is fired on a time base by the computer and the ~ront portion of the boost pulse is extended to increase the time dura-tion between the last OE'F pulse and the firing of the succeeding ON pulse when a predetermined low motor current is sensed and as required to enable an adequate charge of the commutation capacitor.
A third embodiment o the present invention is shown in Figure 13 and responds to a sensed BCC charge voltag0 across the commutation capacitor and a sensed motor current to control the provision of the OFF control pulse in relation to the boost pulse. The sensed BCC
charge voltage on the commutation capacitor is compared with a sensed motor current, such as Il, to establish the time occurrence of the OFF control pulse in relation to the provision of the boost pulse.
In Figure 13 there is shown a modification of the hardware interface apparatus shown in Figure 3A for comparing a sensed actual motor current, such as I1, with the sensed actual BCC voltage. The actual BCC negative voltage is applied to terminal ~50 and a positive offset voltage V~, in accordance with a desired reference value of the BCC voltage, is applied to the terminal 452, such that the actual BCC voltage has to remain more negative than this positive offset reference voltage V* to enable continued ON operation of the chopper. In addition, the timing ramp voltage from amplifier 165, which is reset by the microprocessor each 218 Hertz, is added at junction 454 so in relation to each time the ramp voltage builds up then enough actual BCC negative voltage is re~uired to prevent the provision of an OFF control pulse thereby.
The actual positive motor current Il is applied to termi-nal 456 and made negative by circuit 458 to negate the positive ramp voltage, such that if the actual motor r~
18 49~ 373 current stays greater than a predetermined reference level, such as 100 amperes, this will remove the effect of the ramp voltage from the comparator 46~. If the actual motor current is lower than this reference level, the ramp comes into effect and additional actual BCC negative charge voltage is then needed to overcome the positive ramp voltage and with time as the ramp builds up to avoid an OFF control pulse being fired. Thusly, in operation this OFF pulse control apparatus will determine if the actual motor current is below a predetermined reference level, such as 100 amperes, when the ramp voltage becomes effective to provide the OFF control pulse earlier and move away from the normal boost pulse to give a longer OFF
time period for building up the commutation capacitor charge voltage.
A fourth embodiment of the present invention is shown in Figure 14 and is another modification of the hardware interface apparatus shown in Figure 3~, and responds to sensed actual BCC negative commutation capac-itor charge voltage applied to terminal 470. A samplingswitch 472 is closed each time an ON control pulse is provided and the BCC voltage has stabilized. The summing junction 474 compares the actual BCC voltage with a posi-tive reference voltage applied to terminal 476 and corre ~5 sponding to a desired minimum BCC reference voltage, such as 300 volts. If the sampled ~CC actual voltage is less than this minimum reference voltage, the integrator ~7~3 will start integratin~ negatively. The integrator output is then compared by the comparator 480 with the positive voltage ramp from the amplifier 165, such that as the integrator output voltage drops negatively, it starts to intersect with the positive ramp voltage ancl the OFF pulse is provided in a time relationship more away ~rom the ON
pulse to in effect increase the OFF time period of the chopper apparatus. When the OFF pulse is pulled back in time far enough from the ON pulse for the actual BCC
charge voltage to build up to at least the desired minimum 19 44,373 reference level, such as 300 volts, then the sampling switch 472 would sense this adequate actual BCC voltage charge and the integrator 478 would then hold its output to maintain that desired minimum level of BCC charge voltage.
The application program listings included in the Appendix A and Appendix B are written in the assembly language developed for use with the Intel 8080 micropro~
cessor, such as the central processor 94.

(The following page is A1) APPENDIX A Al OOOOlINT: PUSH B

00005 M~I A,68H :RESET INT #l 00008 OUT 2DH :LOCATION IS INTERUPT
00009 LDA ?R~O
00010 XRI 20H :TOGLE
00011 STA ?RYO

00014 LDA ?ACNT
00015 MO~ C,A

00018 MYI B,14~1 :WAIT 386 USEC
00019 LDA ?IM
00020 CPI 19H :I ~ 100 AMPS ?
00021 JNC NCHG :YES
00022 MYI B,28H :WAIT 539 USEC

00024 JNZ $-1 00026 LDA ?T6FLG :CHECK T6 SUPRESS

00028 JNZ T6SUP :JUMP IF T6 SUPRESSED
00029 LDA ?BCO
00030 ORI 40H :TURN T6 ON

00033T65UP MOY A,C :&ET ?ACNT
00034 ORI ODOH :SET BOOST, ON, T5SUP

00036 ANI OBFH :READY CLEAR ON
00037 MYI B,08H :WAIT 72 USEC

00039 JNZ $-1 00040 OUT 32H :CLEAR ON
00041 LDA ?BCO
00042 ANI OBFH :TURN T6 OFF

00045 CALL DIGIN :GET DIGITAL INPUTS
00046 MYI B,15H :WAIT 272 USEC

00048 JNZ $-1 00049 MO~ A,C
00050 ANI 3FH :CLEAR BOOST, ON

8~

APPENDIX B Bl 00001INT: PUSH B

00005 M~I A,68H :RESET INT #l 00008 OUT 2DH :LOCATION IS INTERUPT
00009 LDA ?R~0 00010 XRI 20H :TOGLE
00011 STA ?RY0 00014 LDA ?ACNT
00015 MO~ C,A

00018 MYI B,14H :WAIT 386 USEC
00019 LDA ?IM
00020 CPI l9H :I ~ 100 AMPS ?
00021 JNC GTHAN :YES
00022 MYI B,28H :WAIT 539 USEC
00023 CPI ODH : ~ 50 AMPS ?
00024 JNC GTHAN :YES
00025 MYI B,3CH :WAIT 629 USEC
00026GTHAN: DCR B
00027 JNZ $-1 00029 LDA ?T6FLG :CHECK T6 SUPRESS

00031 JNZ T6SUP :JUMP IF T6 SUPRESSED
00032 LDA ?BC0 00033 ORI 40H :TURN T6 ON

00036T6SUP: MOY A,C :GET ?ACNT
00037 ORI ODOH :SET BOOST, ON, T5SUP

00039 ANI 0BFH :READY CLEAR ON
00040 M~I B,08H :WAIT 72 IJSEC

00042 JNZ ~-1 00043 OUT 32H :CLEAR ON
00044 LDA ?BC0 00045 ANI OBFH :TURN T6 OFF

00048 CALL DIGIN :GET DIGITAL INPUTS
00049 M~I B,15H :WAIT 272USEC

00051 ~NZ $-1 00052 MO~ A,C
00053 ANI 3FH :CLEAR BOOST, ON

Claims (10)

CLAIMS:

1. In control apparatus for a chopper having an ON operation and an OFF operation, said chopper hav-ing a commutation capacitor with a charge voltage and being operative to control the energization current of an electric motor, the combination of:
means for providing a first pulse signal for determining the ON operation of said chopper, means for providing a second pulse signal for determining the OFF operation of said chopper, means for comparing the actual value of at least one of said charge voltage and said motor current with a predetermined reference value, and controlling the time period relationship between said second pulse signal and said first pulse signal to increase the charge voltage when said actual value is less than said predetermined reference value.

2. The control apparatus of claim 1, with said first pulse signal having a first time period, said con-trol apparatus including, means for providing a third pulse signal having a second time period greater than said first time period and with the first time period being provided within the second time period, and controlling said relationship by increasing the second time period prior to the provision of said first pulse signal.

3. The control apparatus of claim 1, with controlling said relationship to provide an adaptive extension of the OFF operation of said chopper to increase the charge voltage when said actual value is less than said predetermined reference value.

4. The control apparatus of claim 1, with extending said time period relationship to provide an extension of the OFF operation of the chopper by changing the provision of the second pulse signal in relation to the first pulse signal when said actual value is less than said reference value.

5. The control apparatus of claim 1, with said comparing means being responsive to the actual value of motor current for comparison with a first predetermined reference value for providing a first change in said relationship and being responsive to the actual value of motor current for comparison with a second predetermined reference value for providing a second change in said relationship.

6. In a method of controlling a chopper having an ON operation and an OFF operation to regulate the current of an electric motor, said chopper having a commutation circuit with a charge voltage, the steps of sensing an actual operating condition of said chopper comprising one of the motor current and the charge voltage, providing an ON control signal for determining the ON operation of the chopper, providing an OFF control signal for determining the OFF operation of the chopper, comparing said operating condition with a predetermined reference value of said operating condition, and controlling the time duration between said OFF
control signal and said ON control signal to increase the charge voltage when the actual operating condition is less than said reference value.

\

7. The method of claim 6, with the actual operating condition being the motor current, and with said operating condition being compared with a first reference value of said operating condition for providing a first increase in said time duration and being compared with a second reference value of said operating condition for providing a second and greater increase in said time duration.

8. The method of claim 6, including sensing another actual operating condition of said chopper com-prising the other of the motor current and the charge voltage, and controlling said time duration in response to said another actual operating condition.

9. The method of claim 6, with said actual operating condition being the charge voltage, and controlling said time duration such that said charge voltage is made substantially the same as said reference value.

10. The method of claim 6, with the ON control signal having a first time period, and including providing a boost pulse having a second time period greater than the first time period and with the first time period being with the second time period, and controlling an extension of the second time period prior to the first time period in accordance with the difference between the actual operating condition and said reference value.