CA1180107A - Two dimensional interpolation circuit for spatial and shading error correction systems - Google Patents
Two dimensional interpolation circuit for spatial and shading error correction systemsInfo
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- CA1180107A CA1180107A CA000374808A CA374808A CA1180107A CA 1180107 A CA1180107 A CA 1180107A CA 000374808 A CA000374808 A CA 000374808A CA 374808 A CA374808 A CA 374808A CA 1180107 A CA1180107 A CA 1180107A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
Abstract
ABSTRACT OF THE DISCLOSURE
Data for providing spatial and shading correction error signals during the operating mode of a television camera are taken from a two dimensional array of correction points distributed across a television image during the camera set-up mode and are stored as 8 bit words. The error correction signals extend smoothly (linearly) between the correction points. The smoothing is performed by selectively interpolating selected reference points on each video line to provide values which vary smoothly from one row of correction points to the next. A vertical interpolation circuit performs a vertical interpolation on a line-by-line basis, by adding signals produced by a multiplying D/A converter when loaded with the two values to be interpolated and weighted by factors related to the distance from each correction point. The results of the vertical interpolation circuit are fed to a horizontal interpolation circuit which ramps linearly from one reference point to the next, to provide the spatial and shading error correction output signals.
Data for providing spatial and shading correction error signals during the operating mode of a television camera are taken from a two dimensional array of correction points distributed across a television image during the camera set-up mode and are stored as 8 bit words. The error correction signals extend smoothly (linearly) between the correction points. The smoothing is performed by selectively interpolating selected reference points on each video line to provide values which vary smoothly from one row of correction points to the next. A vertical interpolation circuit performs a vertical interpolation on a line-by-line basis, by adding signals produced by a multiplying D/A converter when loaded with the two values to be interpolated and weighted by factors related to the distance from each correction point. The results of the vertical interpolation circuit are fed to a horizontal interpolation circuit which ramps linearly from one reference point to the next, to provide the spatial and shading error correction output signals.
Description
The invention relates to the correction of er ors in a television picture, and particularly to an error correction circuit which performs horizontal and vertical interpolation to provide error correction waveforms in a camera head during the camera operating mode Related material is disclosed in application Serial NoO 371,597, filed February 24, 1981 and in application Serial No. 374,867, filed April 7, 1981.
Both applications are assigned to the assignee of this invention Various systems are available for measuring selected errors in a television picture and for selectively storing the measured errors, during a camera setup mode~
During the subsequent camera operating mode, the error correction waveforms corresponding to the measured errors are applied via an error correcting system located in the camera head, to various control inputs, scan deflectors, etc., to correct the given errors in the picture. Such systems utilize accordingly, an error measurement circuit generally removed from the camera head and which must be coupled, generally via cables, to the camera head to retrieve the stored error data during the camera operating mode.
Predominant among such correction schemes are those employing analog sources such as potentiometers, integrators, capacitors, etc., wherein the measured errors are encoded, multiplexed and decoded, -thereby requiring considerable analog circuitry which in some systems, mg/,~ - 2 -53'~G~7 may ge~erate considerable drift and thus stability problems. ~he analog sources must be read and continually re-adjusted, whereby the camera head, i.e., the correction circuit, is usually continually dependent upon the signals from the measurement circuit.
Recent improvements in error measurement and correction systems have included a remotely-located analog measurement circuit, which automatically generates error measurement signals during the setup mode and supplies the si~nals in digital form to a digltal error eorrection circuit located in the camera head. The "~ measured error data are measured by a differential sample value technique.~h~ are digitally stored in the camera head for subsequent use by the error correction circuit therein independently of the error measurement circuit, during the camera opera-ting mode. During the camera operating mode, the correction circuit digitally reads out the differential data, performs an interpolation from correction point to correction point, converts the differential data to absolute values~'generates analog error voltage waveforms ~lhich are superimposed on the basic deflectlon waveforms to correct, for example, horizontal and vertical spatial errors. Shading error eorreetion signals are retrieved, converted to analog signals, and are fed to the video processing circuit to correct any shading errors.
mg/~b - 3 -)7 Such an error correction circuit has the disadvantage of being generally complex in circuitry and lacking in the degree of accuracy whi.ch is presently desirable in spatial error measurement and corrector circuits.
Typical of the above prior art analog error measurement and digital error correction system is the system described in co-pending applica-tion Serial No.
371,597.
SUMMARY OF THE INVENTION
The invention relates to a circuit for inter-polating between values taken from two spaced rows of data points to define an interpolated output, comprising:
means for providing an upper set of data words corresponding to data points along a row above a line therebetween, and a lower set of data words interleaved in time with the upper set and corresponding to data points along a row below the line; multiplying D/A converter means for alternately multiplying upper and lower data words with respective voltages indicative of the position of the line between the rows to provide a corresponding interleaved sequence of product voltages; summing means for selectively combining the product voltage sequence to provide a final interleaved sequence of vertically interpolated voltages;
and means for horizontally interpolating be-tween the final interleaved sequence of voltages to define the interpolated output.
Thus, the invention overcomes the above-mentioned shortcomings of the prior art, by providing a simplified, highly accurate digital error correction circuit which digitally performs horizontal and vertical interpolation to produce video mg/J~
, correction signals for spatial and shading corrections, To this end, a vertical interpolator portion of the two-dimensional interpolator of description herein, receives two sets of words from a random access memory (RAM), which correspond to the correction data from a correction matrix row above a line presently being corrected, and the correction matrix row that is just below. The words from the two sets of data areinterleaved, i.e., the successive words in the upper and lower rows are selectively mixed in a given order to pro-vide an interleaved stream of data. The stream is fed to a multiplying ~/A converter, along with a voltage waveform which is applied to the multiplying voltage input thereof. The voltage waveform is an interleaved combination of two voltage levels whose value is determined by the position of the line being corrected ~ the present~correction ~ff~. The,two ~0~ s voltages and the two data sets are interleaved in turn with selected phasing. Selected voltages of the resulting sequence are temporarily stored and added with other voltages of the sequence, to generate a vertical output sequence consisting of a weighted sum of the row above, and below, the line being corrected.
The vertical output sequence is fed to a horizontal interpolator portion. At a single summing junction thereof, the sums of the odd and even numbered values in the sequence from the vertical interpolator are added to the negative of the video correction output waveform, plus a DC offset voltage.
The latter offsets the output waveform to provide a range of, for example, from -~2 1/2 to -2 1/2 volts. The resulting voltage at the summing junction represents the difference between where the output waveform is, and where it should be by the end of the next correction. This difference voltage is selectively )7 sampled and fed to an output integrator, which has a time constant corresponding to tlle correction interval. The integrator ramps from its existing voltacJe level, to that voltage plus the difference voltage. The resulting voltage is the video correction signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a block diagram of the invention interpolator circuit.
FIGURE 2 is a plan of a television raster depicting a given array of correction points via which data is taken during the camera setup mode.
FIGURE 3A,B is a schematic diagram depicting implementations of the horizontal and vertical interpolators.
FIGURE 4A,B is a schematic diagram depicting a control/interface circuit for the interpolator circuit of FIGURE 3A,B.
DE5CRIPTION OF T~E PREFERRED EMBODIMENTS
Referring to FIGURE 1, the interpolator circuit 10 consists of a vertical (V) interpolator (portion) 12, and a horizontal (~) interpolator (portion) 14 coupled at its input to the output of the V interpolator 12, wherein the circuit 10 includes a random access memory (RAM) 16 for storing measured error data in the form of 8 bit words.
The measured error data is received for storage from an error measurement circuit and a multiplexing system (not shown) of the camera system, via a microprocessor control system 18 and data and address input buses 20,22 respectively.
An interface circuit 24 provides the required control logic timing/control signals, addresses, etc., between the interpolator circuit 10 and the associated microprocessor control system 18. Examples of error measurement, multi-plexing and microprocessor control systems, and their mg/lc - 6 -relationship to a spatial/shading error corrector (SEC) circuit, are shown and described in the copending application Serial No. 371,597~ The interpolator circuit 10 of description herein defines, in essence, an SEC
circuit portion of the above camera system combination.
The interpolation circuit 10 provides video error correction signals for scan correction, i.e., horizontal and vertical spatia] error correction, and black/white shading correction. The data used to generate the correction signals originates from a 16 X 16 array of correction points, which are distributed evenly in the horizontal and vertical directions across the television image, to provide a 13 by 14 array of correction points actually within the active picture, as depicted in FIGURE 2~ The actual waveform extends very smoothly (linearly) between these points. It is the function of this interpolator circuit 10 to accomplish this smoothing by performing highly accurate horizontal and vertical interpolation between correction points. The error data corresponding to the 182 correction points are provided via an error measurement circuit, of previous mention, which also employs a generally analogous sampling array of, for example, 13 by 14 blocks evenly distributed across the active television picture. Such an error measurement circuit is described, for example, in the copending application Serial No. 374,867, Along with the V and H correction data, pertinent V and H addresses are supplied via the associated interface circuit and particularly via a timing generator/
circuit 30 under the microprocessor 18 control, and are loaded in the RAM 16 via V and ~ address buses 26, 28 respectively, along with the data. The data is supplied rt mg/~
~L8~1()7 via a data latch 31 and El and V channel red (R), green (G) and blue (B) select commands on lines 33. The RA~ is loaded in response to a write enable and RAM strobe on control lines 32 from the interface circuit timing generator/
circuit 30. The V addresses are supplied via an adder 34, in response to an upper/lower row select command on a line 36.
The contents of the RA~I 16 are read out in response to a read ena~le on the control lines 32, and are fed to a multiplying digital-to-analog (D/A) converter 38 via a multiplexed bus 40u The D/A 38 has a write control input thereto on a line 41.
A ramp generator 42 in the interface circuit 24, supplies a horizontal-rate voltage staircase in response to a line clock on a line 44 thereto. The staircase is supplied to a commutating switch 46 as a V-lower voltage, and also as a V upper voltage via an inverter 48 and a summing junction 50. The summing junction 50 receives a given DC
voltage (e.g., 2.5 volts) on input 52. The switch 46 provides for selecting the V lower or V upper thereto in response to a 259 KHZ clock related to the upper/lower row select command on the line 36. Tha output of the switch 46 is fed to a reference, or multiplying, voltage input of the D/A converter 38 via a line 54.
The D/A converter 38 is coupled directly to a sample-and-hold (S/H) circuit 56 and to a resistive summing junction 58, and also is coupled thereto via the negative input of an amplifier 60. The positive input of amplifier 60 is tied to ground. The S/E~ circuit 56 is coupled to the summing junction 58, and is responsive to a sample-l (Sl) pulse (250 KEJZ) via a line 62. The summing junction also receives a V-offset voltage via a line 64. The output of the junction 58 is fed to an operational amplifier 66 which . ~
~f" mg/¦~ - 8 -~8~ 7 is sampled for a short interval (250 nanoseconds) via a sample- (S2) pulse on a line 68. The amplifier 66 feeds an output integrator 70~ whose output corresponds to the interpolation circuit 10 output 72~ i.e~, to the video correction signal which performs the spatial and shading error corrections. The output 72 is fed back as a negative waveform to the summing junction 58 via a line 73 Referring now to FIGURE 3A~ 3B~ the interpolator 10 of FIGURE 1 is shown in schematic, wherein like components are similarly numbered. As may be seen, the block diagram of FIGURE 1 represents twelve similar interpolation circuits, viz, the red, green and blue (R~ G~ B) interpolator circuits or the correction of registration, i.e., spatial errors in the vertical (V) and horizontal (H) dimensions of a television picture, and the RGB interpolator circuits for the correction of black and white shading errors. The interpolator circuit 10 oi FIGURE 1 thus is formed of six identical registration interpolator circuits, viz, RH 74, RV 76, GH 781 GV 80~ BH 82 and BV 841 and also six identical RGB white shading (WS) and black shading (BS) interpolator circuits, viz, RWS 86~ RBS 88~ GWS 90~ GBS 92~ BWS 94 and BBS 96~ as depicting by dashed blocks in FIGURE 3A~ 3Bo Since the twelve circuits are identical for all twelve channels with the only difference being the respective channel input data and output correction signals, only the green (master) horizontal spatial error interpolator circuit 78 is specifically described herein, to simplify the presentation. The composite blanking on line 95 to the shading interpola-tor circuits (FIGURE 3B) provides reference level for the black clamping clrcuitry in later video processing.
mg/~
1~ 7 Thus, during a prior setup mode the spatial and shading errors are measured as in application Serial No.
374,867 of previous mention, using a 16 by 16 matrix of measurement blocks (13 by 14 in the active picture area).
Subsequently, when in the camera operating mode, and referring to FIGURE 3A, 3B, the data bus 20 from the microprocessor control system 18 is fed to the RAM 16 of the green horizontal (G~) channel via the data latch 31, in response to a GH command on the respective line of the lines 33 thereto. The RAM 16 is loaded in response to the write enable and RAM strobe signals, and chip select (CS-l, CS-2) commands, on the respective control lines 32.
The error data is stored as 8 bit words in the respective RAM chips, and corresponds to correction data for one field, for one tube, i.eO, the green tube in the GH
channel circuit 78. Each channel of the twelve channels thus stores 256 bytes of 8 bit words, of registration and shading correction data.
Thus, subsequently, as when in the camera operating mode, the V interpolator portion (12 of FIGURE 1) is provided with two sets of words in the respective RAM 16.
The two sets correspond to the measured error correction data indicative of H spatial errors in the picture, and which corresponds to the stored correction data from a correction matrix row that is above the line presently being corrected, and the correction matrix row that is below the line being corrected. FIGU~E 2 depicts the line and row matrix, wherein there are 17 scan lines between successive rows of correction data points. As may be seen, an array of 16 by 16 correction data points are stored, however only 13 by 14 are within the active video picture, and thus are actually used. The words from the two sets mg/J~ - 10 -, -of data are interleaved whereby the first word of the lower row follows the first word of the upper row, tthen the second word of the upper row follows the first word of the lower row, the second word of the lower row follows the second word of the upper row, the third word of the upper row follows the second word lower row, the third lower follows - the third upper, and so on khrough all upper and lower words along a line of video being scanned. The interleaving process is provided in the interface circuit 24 of FIGURE 4A, 4B, via the -timing generator/circuit 30, i.e., H and V address generatlng counters 98, lO0 respectively, and a latch 102. Thus, the two sets of data are retrieved from the RAM 16 along with the H and V addresses via the multiplexed address bus 26, 28. The V address from the V
counter 100 is fed to the adder 34, which adds a "1" or "0" to the V address~ If adder 34 adds a "0" the V address corresponds to data from an upper row (i.e., the row above the line being scanned), and if it adds a "1" the V address corresponds to data from a lower row (a row below the line).
For example, when scanning a line between rows 5 and 6, if the adder 34 adds a "0'l to the V address, the data output is the data corresponding to row 5. If a "l" is added to the V address, the data output is from row 6.
The adder 34 is clocked at the upper/lower clock rate of 250 KHZ, and thus alternately adds "0" for 2~s, and "1" for
Both applications are assigned to the assignee of this invention Various systems are available for measuring selected errors in a television picture and for selectively storing the measured errors, during a camera setup mode~
During the subsequent camera operating mode, the error correction waveforms corresponding to the measured errors are applied via an error correcting system located in the camera head, to various control inputs, scan deflectors, etc., to correct the given errors in the picture. Such systems utilize accordingly, an error measurement circuit generally removed from the camera head and which must be coupled, generally via cables, to the camera head to retrieve the stored error data during the camera operating mode.
Predominant among such correction schemes are those employing analog sources such as potentiometers, integrators, capacitors, etc., wherein the measured errors are encoded, multiplexed and decoded, -thereby requiring considerable analog circuitry which in some systems, mg/,~ - 2 -53'~G~7 may ge~erate considerable drift and thus stability problems. ~he analog sources must be read and continually re-adjusted, whereby the camera head, i.e., the correction circuit, is usually continually dependent upon the signals from the measurement circuit.
Recent improvements in error measurement and correction systems have included a remotely-located analog measurement circuit, which automatically generates error measurement signals during the setup mode and supplies the si~nals in digital form to a digltal error eorrection circuit located in the camera head. The "~ measured error data are measured by a differential sample value technique.~h~ are digitally stored in the camera head for subsequent use by the error correction circuit therein independently of the error measurement circuit, during the camera opera-ting mode. During the camera operating mode, the correction circuit digitally reads out the differential data, performs an interpolation from correction point to correction point, converts the differential data to absolute values~'generates analog error voltage waveforms ~lhich are superimposed on the basic deflectlon waveforms to correct, for example, horizontal and vertical spatial errors. Shading error eorreetion signals are retrieved, converted to analog signals, and are fed to the video processing circuit to correct any shading errors.
mg/~b - 3 -)7 Such an error correction circuit has the disadvantage of being generally complex in circuitry and lacking in the degree of accuracy whi.ch is presently desirable in spatial error measurement and corrector circuits.
Typical of the above prior art analog error measurement and digital error correction system is the system described in co-pending applica-tion Serial No.
371,597.
SUMMARY OF THE INVENTION
The invention relates to a circuit for inter-polating between values taken from two spaced rows of data points to define an interpolated output, comprising:
means for providing an upper set of data words corresponding to data points along a row above a line therebetween, and a lower set of data words interleaved in time with the upper set and corresponding to data points along a row below the line; multiplying D/A converter means for alternately multiplying upper and lower data words with respective voltages indicative of the position of the line between the rows to provide a corresponding interleaved sequence of product voltages; summing means for selectively combining the product voltage sequence to provide a final interleaved sequence of vertically interpolated voltages;
and means for horizontally interpolating be-tween the final interleaved sequence of voltages to define the interpolated output.
Thus, the invention overcomes the above-mentioned shortcomings of the prior art, by providing a simplified, highly accurate digital error correction circuit which digitally performs horizontal and vertical interpolation to produce video mg/J~
, correction signals for spatial and shading corrections, To this end, a vertical interpolator portion of the two-dimensional interpolator of description herein, receives two sets of words from a random access memory (RAM), which correspond to the correction data from a correction matrix row above a line presently being corrected, and the correction matrix row that is just below. The words from the two sets of data areinterleaved, i.e., the successive words in the upper and lower rows are selectively mixed in a given order to pro-vide an interleaved stream of data. The stream is fed to a multiplying ~/A converter, along with a voltage waveform which is applied to the multiplying voltage input thereof. The voltage waveform is an interleaved combination of two voltage levels whose value is determined by the position of the line being corrected ~ the present~correction ~ff~. The,two ~0~ s voltages and the two data sets are interleaved in turn with selected phasing. Selected voltages of the resulting sequence are temporarily stored and added with other voltages of the sequence, to generate a vertical output sequence consisting of a weighted sum of the row above, and below, the line being corrected.
The vertical output sequence is fed to a horizontal interpolator portion. At a single summing junction thereof, the sums of the odd and even numbered values in the sequence from the vertical interpolator are added to the negative of the video correction output waveform, plus a DC offset voltage.
The latter offsets the output waveform to provide a range of, for example, from -~2 1/2 to -2 1/2 volts. The resulting voltage at the summing junction represents the difference between where the output waveform is, and where it should be by the end of the next correction. This difference voltage is selectively )7 sampled and fed to an output integrator, which has a time constant corresponding to tlle correction interval. The integrator ramps from its existing voltacJe level, to that voltage plus the difference voltage. The resulting voltage is the video correction signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a block diagram of the invention interpolator circuit.
FIGURE 2 is a plan of a television raster depicting a given array of correction points via which data is taken during the camera setup mode.
FIGURE 3A,B is a schematic diagram depicting implementations of the horizontal and vertical interpolators.
FIGURE 4A,B is a schematic diagram depicting a control/interface circuit for the interpolator circuit of FIGURE 3A,B.
DE5CRIPTION OF T~E PREFERRED EMBODIMENTS
Referring to FIGURE 1, the interpolator circuit 10 consists of a vertical (V) interpolator (portion) 12, and a horizontal (~) interpolator (portion) 14 coupled at its input to the output of the V interpolator 12, wherein the circuit 10 includes a random access memory (RAM) 16 for storing measured error data in the form of 8 bit words.
The measured error data is received for storage from an error measurement circuit and a multiplexing system (not shown) of the camera system, via a microprocessor control system 18 and data and address input buses 20,22 respectively.
An interface circuit 24 provides the required control logic timing/control signals, addresses, etc., between the interpolator circuit 10 and the associated microprocessor control system 18. Examples of error measurement, multi-plexing and microprocessor control systems, and their mg/lc - 6 -relationship to a spatial/shading error corrector (SEC) circuit, are shown and described in the copending application Serial No. 371,597~ The interpolator circuit 10 of description herein defines, in essence, an SEC
circuit portion of the above camera system combination.
The interpolation circuit 10 provides video error correction signals for scan correction, i.e., horizontal and vertical spatia] error correction, and black/white shading correction. The data used to generate the correction signals originates from a 16 X 16 array of correction points, which are distributed evenly in the horizontal and vertical directions across the television image, to provide a 13 by 14 array of correction points actually within the active picture, as depicted in FIGURE 2~ The actual waveform extends very smoothly (linearly) between these points. It is the function of this interpolator circuit 10 to accomplish this smoothing by performing highly accurate horizontal and vertical interpolation between correction points. The error data corresponding to the 182 correction points are provided via an error measurement circuit, of previous mention, which also employs a generally analogous sampling array of, for example, 13 by 14 blocks evenly distributed across the active television picture. Such an error measurement circuit is described, for example, in the copending application Serial No. 374,867, Along with the V and H correction data, pertinent V and H addresses are supplied via the associated interface circuit and particularly via a timing generator/
circuit 30 under the microprocessor 18 control, and are loaded in the RAM 16 via V and ~ address buses 26, 28 respectively, along with the data. The data is supplied rt mg/~
~L8~1()7 via a data latch 31 and El and V channel red (R), green (G) and blue (B) select commands on lines 33. The RA~ is loaded in response to a write enable and RAM strobe on control lines 32 from the interface circuit timing generator/
circuit 30. The V addresses are supplied via an adder 34, in response to an upper/lower row select command on a line 36.
The contents of the RA~I 16 are read out in response to a read ena~le on the control lines 32, and are fed to a multiplying digital-to-analog (D/A) converter 38 via a multiplexed bus 40u The D/A 38 has a write control input thereto on a line 41.
A ramp generator 42 in the interface circuit 24, supplies a horizontal-rate voltage staircase in response to a line clock on a line 44 thereto. The staircase is supplied to a commutating switch 46 as a V-lower voltage, and also as a V upper voltage via an inverter 48 and a summing junction 50. The summing junction 50 receives a given DC
voltage (e.g., 2.5 volts) on input 52. The switch 46 provides for selecting the V lower or V upper thereto in response to a 259 KHZ clock related to the upper/lower row select command on the line 36. Tha output of the switch 46 is fed to a reference, or multiplying, voltage input of the D/A converter 38 via a line 54.
The D/A converter 38 is coupled directly to a sample-and-hold (S/H) circuit 56 and to a resistive summing junction 58, and also is coupled thereto via the negative input of an amplifier 60. The positive input of amplifier 60 is tied to ground. The S/E~ circuit 56 is coupled to the summing junction 58, and is responsive to a sample-l (Sl) pulse (250 KEJZ) via a line 62. The summing junction also receives a V-offset voltage via a line 64. The output of the junction 58 is fed to an operational amplifier 66 which . ~
~f" mg/¦~ - 8 -~8~ 7 is sampled for a short interval (250 nanoseconds) via a sample- (S2) pulse on a line 68. The amplifier 66 feeds an output integrator 70~ whose output corresponds to the interpolation circuit 10 output 72~ i.e~, to the video correction signal which performs the spatial and shading error corrections. The output 72 is fed back as a negative waveform to the summing junction 58 via a line 73 Referring now to FIGURE 3A~ 3B~ the interpolator 10 of FIGURE 1 is shown in schematic, wherein like components are similarly numbered. As may be seen, the block diagram of FIGURE 1 represents twelve similar interpolation circuits, viz, the red, green and blue (R~ G~ B) interpolator circuits or the correction of registration, i.e., spatial errors in the vertical (V) and horizontal (H) dimensions of a television picture, and the RGB interpolator circuits for the correction of black and white shading errors. The interpolator circuit 10 oi FIGURE 1 thus is formed of six identical registration interpolator circuits, viz, RH 74, RV 76, GH 781 GV 80~ BH 82 and BV 841 and also six identical RGB white shading (WS) and black shading (BS) interpolator circuits, viz, RWS 86~ RBS 88~ GWS 90~ GBS 92~ BWS 94 and BBS 96~ as depicting by dashed blocks in FIGURE 3A~ 3Bo Since the twelve circuits are identical for all twelve channels with the only difference being the respective channel input data and output correction signals, only the green (master) horizontal spatial error interpolator circuit 78 is specifically described herein, to simplify the presentation. The composite blanking on line 95 to the shading interpola-tor circuits (FIGURE 3B) provides reference level for the black clamping clrcuitry in later video processing.
mg/~
1~ 7 Thus, during a prior setup mode the spatial and shading errors are measured as in application Serial No.
374,867 of previous mention, using a 16 by 16 matrix of measurement blocks (13 by 14 in the active picture area).
Subsequently, when in the camera operating mode, and referring to FIGURE 3A, 3B, the data bus 20 from the microprocessor control system 18 is fed to the RAM 16 of the green horizontal (G~) channel via the data latch 31, in response to a GH command on the respective line of the lines 33 thereto. The RAM 16 is loaded in response to the write enable and RAM strobe signals, and chip select (CS-l, CS-2) commands, on the respective control lines 32.
The error data is stored as 8 bit words in the respective RAM chips, and corresponds to correction data for one field, for one tube, i.eO, the green tube in the GH
channel circuit 78. Each channel of the twelve channels thus stores 256 bytes of 8 bit words, of registration and shading correction data.
Thus, subsequently, as when in the camera operating mode, the V interpolator portion (12 of FIGURE 1) is provided with two sets of words in the respective RAM 16.
The two sets correspond to the measured error correction data indicative of H spatial errors in the picture, and which corresponds to the stored correction data from a correction matrix row that is above the line presently being corrected, and the correction matrix row that is below the line being corrected. FIGU~E 2 depicts the line and row matrix, wherein there are 17 scan lines between successive rows of correction data points. As may be seen, an array of 16 by 16 correction data points are stored, however only 13 by 14 are within the active video picture, and thus are actually used. The words from the two sets mg/J~ - 10 -, -of data are interleaved whereby the first word of the lower row follows the first word of the upper row, tthen the second word of the upper row follows the first word of the lower row, the second word of the lower row follows the second word of the upper row, the third word of the upper row follows the second word lower row, the third lower follows - the third upper, and so on khrough all upper and lower words along a line of video being scanned. The interleaving process is provided in the interface circuit 24 of FIGURE 4A, 4B, via the -timing generator/circuit 30, i.e., H and V address generatlng counters 98, lO0 respectively, and a latch 102. Thus, the two sets of data are retrieved from the RAM 16 along with the H and V addresses via the multiplexed address bus 26, 28. The V address from the V
counter 100 is fed to the adder 34, which adds a "1" or "0" to the V address~ If adder 34 adds a "0" the V address corresponds to data from an upper row (i.e., the row above the line being scanned), and if it adds a "1" the V address corresponds to data from a lower row (a row below the line).
For example, when scanning a line between rows 5 and 6, if the adder 34 adds a "0'l to the V address, the data output is the data corresponding to row 5. If a "l" is added to the V address, the data output is from row 6.
The adder 34 is clocked at the upper/lower clock rate of 250 KHZ, and thus alternately adds "0" for 2~s, and "1" for
2~s, for a total period of 4~s.
The H and V addresses are loaded through an address multiplexer 104 which is dedicated to the address buses 26, 28 as long as the microprocessor control 18 is not reading or writing into the RAM 16. The H and V addresses generated commensurate with the data correction points, are fed via the multiplexed address buses 26, 28 respectively, to the mg/J~
.~
address por-ts of the respective RAM 16 of the twélve (six spatial and six shading) interpolator circuits 74-96. The H address on bus 28 clocks at the H line rate, while the V address on bus 26 clocks at the 17 line rate, i.e., every 17 scan linesO The H and V addresses thus provide twelve different sets of data sequences via respective RAM 16.
The data thus is accessed in the interleaved fashion of previous mention in each RAM 16; i.e., the adder 34 address alternately accesses data from the upper and lower rows of data in the RAMs. The interleaved data is strobed into the D/A converter 38. The data is read out via chip selects CSl and CS2, which simultaneously go low at the 500 KHZ rate at all RAMs 16. Thus every 2~s another word appears at the RAM output, corresponding to every 2~s that the adder 34 alternates from the upper, lower, upper, etc., address. Every 2~s of data is also strobed into the internally latched D/A converter 38.
The converter 38 also receives the V staircase voltage via the line 54 from the ramp generator circuitry 42 of the inte~face circuit 24, performs the D/A conversion and multiplies the resulting analog signal times the V
staircase to provide an analog output signal which is the product of that data word and the staircase~ ~
The staircase voltage waveform consists of an interleaved pair of voltage levels whose value corresponds to the position of the line being corrected relative to the correction rows ahove and below the line. That is, the staircase voltage provides a weight factor corresponding to the line (L) position between the rows, as shown by the following table.
mg/~ - 12 -~.
lines/frame 525(NTSC) 625(PAL) V upper 2.5r(17-L)/17] 2.5[(20~L)/20 V lower 2.5(L/17) 2.5(L/20) lines/row 17 20 Note that the voltages (weights) of V upper plus V lower sum to 2.5 volts exactly. Thus the pair of analog weights change in value in inverse relation, as the lines are scanned from zero line to sixteen lines between two rows of correction points. To exemplify, given rows 3 and 4, the weight that corresponds to "upper" row 3, starts at 2.5 volts when scanning the first scan line below row 3, and decreases to zero volts in the course of scanning through the 17 lines below row 3. The weight corresponding to "lower" row 4, starts at zero volts with the first scan line below row 3 and increases to 2.5 volts in the course of scanning through the 17 scan lines. Thus, for example, the weight of upper row 3 is slightly less, and the weight of lower row 4 is slightly more, when scan line 3 below row 3 is scanned, than when scan line 2 below row 3 is scanned. In effect, the multiplication and subsequent addition, performs an interpolation between the data at rows 3 and 4O
The voltage staircase is generated as 17 voltage steps with one step per television line. Therefore, the raster scan in the vertical direction is discrete and the product output is also stepped through 17 levels. The staircase is generated via the ramp generator 42, which in FIGURE 4B includes a counter 106 and a D/A converter 108.
The latter feeds the inverter 48 and the summing junction S0, where the offset voltage of 2.5 volts is added via the line 52 to the junction 50. The resulting V-upper weight is fed to the commutating switch 46. The output of the D/A
'~u mg/~ - 13 -. . .
3L~ 7 converter 108 also is coupled directly to -the switch ~6 as the V lower weight. Since the D/A 108 writes at the line rate the weights thus are constant for an entire line, and step to the next respective lower and higher voltage of the staircase at the beginning of the next line. The switch ~6 also toggles at the same rate as does the adder 34, l.e., at 250 KHZ. Therefore, when the upper row data are presented to the D/A converter 38, the V upper staircase weight is also presented to the multiplying D/A 38, and are multiplied thereby. Likewise, the lower row data are presented to the D/A 38 with the V lower staircase weight, and are multiplied. Thus the output of the D/A converter 38 also is an interleaved sequence of voltages corresponding to the product of the commutated voltage waveform, and the prior interleaved sequence of data as illustrated by the following sequence. (V upper) X (word 1 upper), (V lower) X (word 1 lower), (V upper) X (word 2 upper), (V lower) X
(word 2 lower), etc.,. The sequence appears at the D/A 38 output, i.e., the output of the amplifier 60.
Next, the V upper and V lower terms of the sequence are added together at the summing junction 58. To this end, the sample/hold 56 successively tracks and halds the V upper terms in the sequence, such that when the respective V lower terms arrive at the summing junction 58, the terms are added together. Thus, the V upper terms are stripped, delayed 2~s, and the addition is performed every ~s to provide the following sequence. (V upper) X (word 1 upper) +
(V lower) X (word 1 lower), (V upper) X (word 2 upper) +
(V lower) X (word 2 lower), etc.,.
This sequence consists of the weighted sum of the correction row above, and the correction row below, the line being scanned and corrected. The values of the weights mg/)~
(corresponding to the upper and lower voltages) are deter-mined by the position of the line being corrected between the upper and lower correction rows. The rules by which the values of these weights are produced, insure that the sequence between the correction rows vary linearly from one correction row to the next. This final sequence is presented from the section 14, in each of the twelve interpolator circuits 74-96.
At the instant that the summing is done at junction 58, the state of sample-2 on line 68 goes high to provide emitter current to the operational amplifier 66. The latter is a very fast sample-and-hoLd operational amplifier, ~Ihich acquires the signal at its input in less than 250 nanoseconds (ns), which is the width of the pulse S2, and holds it for the required 4~s to provide the input signal to the output integrator 70. The integrator 70 has a precise time constant equal to the correction interval, i.e., 4~s, and integrates the incoming signal to provide the video correction signal at the interpolator circuit output 72.
The correction signal is fed back to the summing junction 58, to provide a feedback signal.
Thus the summing junction 58 output is the difference between where the signal level should be after 4~s, and where it is at presentO It is this difference signal that is applied to the integrator 70. It is sampled a-t operational amplifier 66, is integrated via integrator 70, and moves the output at 72 to the value it should be after 4~s.
Various resistors in the circuit should be matched;
i.e., resistors 110 and 112 should be matched to 0.1% to prevent a sawtooth component from being added to the output correction signal.
mg/Jc - 15 -~8~7 The timing generator/circuit 30 is provided with the various sync, reset, etc., clocks from the carnera system labeled SEC write, 1 MHZ, 15.62 KHZ, 2 MHZ, SEC
clock and V drive on lines 114 and 116 of FIGURE 4A, 4B, whereby the various component controls are provided and the SEC addresses are generated in sync with the camera raster scan. The circuit 30 thus provides a read/write low on the lines 32, which is normally high, when a RAM
performs the write function. The output DAC write on line 41 is the signal that latches the data input to the latching D/A converter 38, whereby changing data at the RAM output is ignored by the D/A 38 until latching is desired as, for example, when the data stahilize. RAM strobe on lines 32 is required in the RAM used, to determine the duty cycle.
S2 on line 6B is the sample signal for the first order sample-and-hold 66, i.e., the horizontal interpolator. Sl on line 62 is the sample signal that samples the V upper terms from the D/A converter 38 output sequence. The wait signal on a line 118 is a signal fed to the microprocessor control 18. The RAMs in the interpolator circuit may be written into, or read from, directly by the microprocessor control 18, at ~iven times. ~ut the microprocessor runs a 2 MHZ signal which can be out of phase. Thus the wait signal on line 118 provides direct memory access in the proper phase.
The chip select, CS, slgnals are provided on the control lines 32 via NOR gates 120, and provide means for selecting a specific RAM of the twelve channels, which is to be accessed by the microprocessor control 18. A signal on the second inputs to the NOR gates 120 -termed "500 KHZ
delayed by 1 MHZ" also is provided on a line 122 which, in its high state, provides a low on all chip selects, which turns all twelve of the RAMs on to read all into the '-~, mg/~ - 16 -~8~ '7 respective vertical interpolator sections A decoder 124 provides the inputs from the microprocessor control 18 to the gates 120.
A series of AND gates 126 provide means ~or controlling respective data bus latches 31 in each of the twelve interpolator circuits 74-96, via the lines 33 thereto. The latches 31 are coupled in pairs and allow the read or write function via a respective control line, when the logic state from the AND gates 126 go high. The decoder 124 again decodes the address of -the memories in keeping with the chip select signals on lines 32 mg/~ - 17 -~ .
The H and V addresses are loaded through an address multiplexer 104 which is dedicated to the address buses 26, 28 as long as the microprocessor control 18 is not reading or writing into the RAM 16. The H and V addresses generated commensurate with the data correction points, are fed via the multiplexed address buses 26, 28 respectively, to the mg/J~
.~
address por-ts of the respective RAM 16 of the twélve (six spatial and six shading) interpolator circuits 74-96. The H address on bus 28 clocks at the H line rate, while the V address on bus 26 clocks at the 17 line rate, i.e., every 17 scan linesO The H and V addresses thus provide twelve different sets of data sequences via respective RAM 16.
The data thus is accessed in the interleaved fashion of previous mention in each RAM 16; i.e., the adder 34 address alternately accesses data from the upper and lower rows of data in the RAMs. The interleaved data is strobed into the D/A converter 38. The data is read out via chip selects CSl and CS2, which simultaneously go low at the 500 KHZ rate at all RAMs 16. Thus every 2~s another word appears at the RAM output, corresponding to every 2~s that the adder 34 alternates from the upper, lower, upper, etc., address. Every 2~s of data is also strobed into the internally latched D/A converter 38.
The converter 38 also receives the V staircase voltage via the line 54 from the ramp generator circuitry 42 of the inte~face circuit 24, performs the D/A conversion and multiplies the resulting analog signal times the V
staircase to provide an analog output signal which is the product of that data word and the staircase~ ~
The staircase voltage waveform consists of an interleaved pair of voltage levels whose value corresponds to the position of the line being corrected relative to the correction rows ahove and below the line. That is, the staircase voltage provides a weight factor corresponding to the line (L) position between the rows, as shown by the following table.
mg/~ - 12 -~.
lines/frame 525(NTSC) 625(PAL) V upper 2.5r(17-L)/17] 2.5[(20~L)/20 V lower 2.5(L/17) 2.5(L/20) lines/row 17 20 Note that the voltages (weights) of V upper plus V lower sum to 2.5 volts exactly. Thus the pair of analog weights change in value in inverse relation, as the lines are scanned from zero line to sixteen lines between two rows of correction points. To exemplify, given rows 3 and 4, the weight that corresponds to "upper" row 3, starts at 2.5 volts when scanning the first scan line below row 3, and decreases to zero volts in the course of scanning through the 17 lines below row 3. The weight corresponding to "lower" row 4, starts at zero volts with the first scan line below row 3 and increases to 2.5 volts in the course of scanning through the 17 scan lines. Thus, for example, the weight of upper row 3 is slightly less, and the weight of lower row 4 is slightly more, when scan line 3 below row 3 is scanned, than when scan line 2 below row 3 is scanned. In effect, the multiplication and subsequent addition, performs an interpolation between the data at rows 3 and 4O
The voltage staircase is generated as 17 voltage steps with one step per television line. Therefore, the raster scan in the vertical direction is discrete and the product output is also stepped through 17 levels. The staircase is generated via the ramp generator 42, which in FIGURE 4B includes a counter 106 and a D/A converter 108.
The latter feeds the inverter 48 and the summing junction S0, where the offset voltage of 2.5 volts is added via the line 52 to the junction 50. The resulting V-upper weight is fed to the commutating switch 46. The output of the D/A
'~u mg/~ - 13 -. . .
3L~ 7 converter 108 also is coupled directly to -the switch ~6 as the V lower weight. Since the D/A 108 writes at the line rate the weights thus are constant for an entire line, and step to the next respective lower and higher voltage of the staircase at the beginning of the next line. The switch ~6 also toggles at the same rate as does the adder 34, l.e., at 250 KHZ. Therefore, when the upper row data are presented to the D/A converter 38, the V upper staircase weight is also presented to the multiplying D/A 38, and are multiplied thereby. Likewise, the lower row data are presented to the D/A 38 with the V lower staircase weight, and are multiplied. Thus the output of the D/A converter 38 also is an interleaved sequence of voltages corresponding to the product of the commutated voltage waveform, and the prior interleaved sequence of data as illustrated by the following sequence. (V upper) X (word 1 upper), (V lower) X (word 1 lower), (V upper) X (word 2 upper), (V lower) X
(word 2 lower), etc.,. The sequence appears at the D/A 38 output, i.e., the output of the amplifier 60.
Next, the V upper and V lower terms of the sequence are added together at the summing junction 58. To this end, the sample/hold 56 successively tracks and halds the V upper terms in the sequence, such that when the respective V lower terms arrive at the summing junction 58, the terms are added together. Thus, the V upper terms are stripped, delayed 2~s, and the addition is performed every ~s to provide the following sequence. (V upper) X (word 1 upper) +
(V lower) X (word 1 lower), (V upper) X (word 2 upper) +
(V lower) X (word 2 lower), etc.,.
This sequence consists of the weighted sum of the correction row above, and the correction row below, the line being scanned and corrected. The values of the weights mg/)~
(corresponding to the upper and lower voltages) are deter-mined by the position of the line being corrected between the upper and lower correction rows. The rules by which the values of these weights are produced, insure that the sequence between the correction rows vary linearly from one correction row to the next. This final sequence is presented from the section 14, in each of the twelve interpolator circuits 74-96.
At the instant that the summing is done at junction 58, the state of sample-2 on line 68 goes high to provide emitter current to the operational amplifier 66. The latter is a very fast sample-and-hoLd operational amplifier, ~Ihich acquires the signal at its input in less than 250 nanoseconds (ns), which is the width of the pulse S2, and holds it for the required 4~s to provide the input signal to the output integrator 70. The integrator 70 has a precise time constant equal to the correction interval, i.e., 4~s, and integrates the incoming signal to provide the video correction signal at the interpolator circuit output 72.
The correction signal is fed back to the summing junction 58, to provide a feedback signal.
Thus the summing junction 58 output is the difference between where the signal level should be after 4~s, and where it is at presentO It is this difference signal that is applied to the integrator 70. It is sampled a-t operational amplifier 66, is integrated via integrator 70, and moves the output at 72 to the value it should be after 4~s.
Various resistors in the circuit should be matched;
i.e., resistors 110 and 112 should be matched to 0.1% to prevent a sawtooth component from being added to the output correction signal.
mg/Jc - 15 -~8~7 The timing generator/circuit 30 is provided with the various sync, reset, etc., clocks from the carnera system labeled SEC write, 1 MHZ, 15.62 KHZ, 2 MHZ, SEC
clock and V drive on lines 114 and 116 of FIGURE 4A, 4B, whereby the various component controls are provided and the SEC addresses are generated in sync with the camera raster scan. The circuit 30 thus provides a read/write low on the lines 32, which is normally high, when a RAM
performs the write function. The output DAC write on line 41 is the signal that latches the data input to the latching D/A converter 38, whereby changing data at the RAM output is ignored by the D/A 38 until latching is desired as, for example, when the data stahilize. RAM strobe on lines 32 is required in the RAM used, to determine the duty cycle.
S2 on line 6B is the sample signal for the first order sample-and-hold 66, i.e., the horizontal interpolator. Sl on line 62 is the sample signal that samples the V upper terms from the D/A converter 38 output sequence. The wait signal on a line 118 is a signal fed to the microprocessor control 18. The RAMs in the interpolator circuit may be written into, or read from, directly by the microprocessor control 18, at ~iven times. ~ut the microprocessor runs a 2 MHZ signal which can be out of phase. Thus the wait signal on line 118 provides direct memory access in the proper phase.
The chip select, CS, slgnals are provided on the control lines 32 via NOR gates 120, and provide means for selecting a specific RAM of the twelve channels, which is to be accessed by the microprocessor control 18. A signal on the second inputs to the NOR gates 120 -termed "500 KHZ
delayed by 1 MHZ" also is provided on a line 122 which, in its high state, provides a low on all chip selects, which turns all twelve of the RAMs on to read all into the '-~, mg/~ - 16 -~8~ '7 respective vertical interpolator sections A decoder 124 provides the inputs from the microprocessor control 18 to the gates 120.
A series of AND gates 126 provide means ~or controlling respective data bus latches 31 in each of the twelve interpolator circuits 74-96, via the lines 33 thereto. The latches 31 are coupled in pairs and allow the read or write function via a respective control line, when the logic state from the AND gates 126 go high. The decoder 124 again decodes the address of -the memories in keeping with the chip select signals on lines 32 mg/~ - 17 -~ .
Claims (23)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A circuit for interpolating between values taken from two spaced rows of data points to define an interpolated output, comprising:
means for providing a selected stream of two sets of upper and lower data words corresponding to data from respective upper and lower rows of points disposed above and below a line therebetween;
multiplying means including a D/A converter for generating a selected sequence of product voltages by multiplying a selected data word of a row with a voltage indicative of the position of the line between the rows, wherein the sequence of product voltages define an inter-leaved sequence of the upper and lower data words and two voltage levels;
summing means for adding given voltages in the product voltage sequence to provide a final sequence of vertically interpolated voltages;
said summing means including a sample/hold circuit coupled to the multiplying means to delay selected ones of the product voltages, a junction for receiving the undelayed and delayed sequence of product voltages, a negative waveform of the interpolated output, and a DC offset voltage;
said summing means generating a difference voltage indicative of what the instantaneous value of the interpolated output should be; and means for horizontally interpolating between the final sequence of voltages to define the interpolated output.
means for providing a selected stream of two sets of upper and lower data words corresponding to data from respective upper and lower rows of points disposed above and below a line therebetween;
multiplying means including a D/A converter for generating a selected sequence of product voltages by multiplying a selected data word of a row with a voltage indicative of the position of the line between the rows, wherein the sequence of product voltages define an inter-leaved sequence of the upper and lower data words and two voltage levels;
summing means for adding given voltages in the product voltage sequence to provide a final sequence of vertically interpolated voltages;
said summing means including a sample/hold circuit coupled to the multiplying means to delay selected ones of the product voltages, a junction for receiving the undelayed and delayed sequence of product voltages, a negative waveform of the interpolated output, and a DC offset voltage;
said summing means generating a difference voltage indicative of what the instantaneous value of the interpolated output should be; and means for horizontally interpolating between the final sequence of voltages to define the interpolated output.
2. A circuit for interpolating between values taken from two spaced rows of data points to define an interpolated output, comprising:
means for providing an upper set of data words corresponding to data points along a row above a line therebetween, and a lower set of data words interleaved in time with the upper set and corresponding to data points along a row below the line;
multiplying D/A converter means for alternately multiplying upper and lower data words with respective voltages indicative of the position of the line between the rows to provide a corresponding interleaved sequence of product voltages;
summing means for selectively combining the product voltage sequence to provide a final interleaved sequence of vertically interpolated voltages; and means for horizontally interpolating between the final interleaved sequence of voltages to define the interpolated output.
means for providing an upper set of data words corresponding to data points along a row above a line therebetween, and a lower set of data words interleaved in time with the upper set and corresponding to data points along a row below the line;
multiplying D/A converter means for alternately multiplying upper and lower data words with respective voltages indicative of the position of the line between the rows to provide a corresponding interleaved sequence of product voltages;
summing means for selectively combining the product voltage sequence to provide a final interleaved sequence of vertically interpolated voltages; and means for horizontally interpolating between the final interleaved sequence of voltages to define the interpolated output.
3. The circuit of claim 2 further including:
means for generating the respective voltages indicative of position as an alternately interleaved sequence of two voltage levels in sync with respective upper and lower data words; and the multiplying D/A converter means includes a single multiplying D/A converter for generating the selected interleaved sequence of the product voltages formed of the upper and lower data words and the two voltage levels.
means for generating the respective voltages indicative of position as an alternately interleaved sequence of two voltage levels in sync with respective upper and lower data words; and the multiplying D/A converter means includes a single multiplying D/A converter for generating the selected interleaved sequence of the product voltages formed of the upper and lower data words and the two voltage levels.
4. The circuit of claim 3 wherein:
the summing means includes a sample/hold circuit coupled to the single multiplying D/A converter to delay product voltages corresponding to one row relative to those of the other row prior to the combining thereof.
the summing means includes a sample/hold circuit coupled to the single multiplying D/A converter to delay product voltages corresponding to one row relative to those of the other row prior to the combining thereof.
5. The circuit of claim 4 wherein:
the summing means includes a junction for receiving the undelayed and delayed sequence of product voltages, a negative waveform of the interpolated output, and a D.C.
offset voltage;
said summing junction generating a difference voltage indicative of what the instantaneous value of the interpolated output should be.
the summing means includes a junction for receiving the undelayed and delayed sequence of product voltages, a negative waveform of the interpolated output, and a D.C.
offset voltage;
said summing junction generating a difference voltage indicative of what the instantaneous value of the interpolated output should be.
6. The circuit of claim 1 further including:
integrating means operatively coupled to the summing junction and having a precise time constant equal to the time between data points in the rows.
integrating means operatively coupled to the summing junction and having a precise time constant equal to the time between data points in the rows.
7. The circuit of claim 6 further including:
memory means for selectively storing the data words;
said multiplying D/A converter being coupled to the memory means to selectively retrieve the stream of data words.
memory means for selectively storing the data words;
said multiplying D/A converter being coupled to the memory means to selectively retrieve the stream of data words.
8. The circuit of claim 7 further including:
address means associated with the memory means for selectively addressing the data word stream as alternate upper and lower rows of data points, respectively.
address means associated with the memory means for selectively addressing the data word stream as alternate upper and lower rows of data points, respectively.
9. The circuit of claim 8 wherein:
the output of the multiplying D/A converter is represented by the sequence, (V upper)X(word 2 upper), (V lower)X(word 2 lower), etc, where V represents the voltages indicative of the line position.
the output of the multiplying D/A converter is represented by the sequence, (V upper)X(word 2 upper), (V lower)X(word 2 lower), etc, where V represents the voltages indicative of the line position.
10. The circuit of claim 9 wherein:
at the summing junction the final sequence is represented by, (V upper)X(word 1 upper)+(V lower)X(word 1 lower), (V upper)X(word 2 upper)+(V lower)X(word 2 lower), etc.
at the summing junction the final sequence is represented by, (V upper)X(word 1 upper)+(V lower)X(word 1 lower), (V upper)X(word 2 upper)+(V lower)X(word 2 lower), etc.
11. The circuit of claim 4 further including:
interface means, which include the means for generating the position voltages, for supplying timing and clocking signals commensurate with the respective inter-leaving sequences to the means for providing and to the D/A converter means.
interface means, which include the means for generating the position voltages, for supplying timing and clocking signals commensurate with the respective inter-leaving sequences to the means for providing and to the D/A converter means.
12. The circuit of claim 11 wherein the means for generating the position voltage include:
a ramp generator for generating descending and ascending voltage ramps; and switch means coupled to the ramp generator to alternately supply to the multiplying D/A converter descending and ascending position voltages corresponding to the occurrence of the upper and lower data words.
a ramp generator for generating descending and ascending voltage ramps; and switch means coupled to the ramp generator to alternately supply to the multiplying D/A converter descending and ascending position voltages corresponding to the occurrence of the upper and lower data words.
13. The circuit of claim 11 wherein the means for providing the upper and lower set of data words include a single random access memory responsive to the interface means.
14. The circuit of claim 4 wherein the summing means further include:
capacitor means for storing the values of the delayed product voltages; and a summing junction coupled to the multiplying D/A
converter and to the capacitor means for adding the undelayed product voltages to the delayed product voltages of the corresponding upper and lower data points.
capacitor means for storing the values of the delayed product voltages; and a summing junction coupled to the multiplying D/A
converter and to the capacitor means for adding the undelayed product voltages to the delayed product voltages of the corresponding upper and lower data points.
15. The circuit of claim 14 wherein the means for horizontally interpolating include:
means coupled to the summing junction for sampling and holding the vertically interpolated voltages therefrom for a time interval corresponding to the occurrence of a data point; and integrating means coupled to the prior means and having a time constant equal to said time interval.
means coupled to the summing junction for sampling and holding the vertically interpolated voltages therefrom for a time interval corresponding to the occurrence of a data point; and integrating means coupled to the prior means and having a time constant equal to said time interval.
16. A circuit for generating an interpolation output by horizontally and vertically interpolating along a line between rows of data points of a two-dimensional array, comprising:
memory means for providing in response to respective addresses a selected stream of data words commensurate with the rows of data points;
address means for selectively addressing the memory means to generate the stream of data words;
ramp generating means for supplying weighted voltages in sync with the stream of data words which are indicative of the position between the rows of the line along which interpolation is performed;
multiplier means including a multiplying D/A
converter for receiving the data words and the weighted voltages, for latching a data word and multiplying same by the respective weighted voltage to define a sequence of analog product voltages;
summing means coupled to the D/A converter for adding selected product voltages to define a final sequence of weighted voltages;
said summing means including a sample/hold circuit for delaying selected product voltages, a summing junction coupled to the sample/hold circuit for receiving the delayed and undelayed product voltages and for providing a difference voltage indicative of what the value of the interpolated output should be, a negative waveform of the interpolated output, and a selected DC offset voltage; and means coupled to the summing means for ramping the weighted voltages from the value that they are to a value they should be, to define the interpolated output.
memory means for providing in response to respective addresses a selected stream of data words commensurate with the rows of data points;
address means for selectively addressing the memory means to generate the stream of data words;
ramp generating means for supplying weighted voltages in sync with the stream of data words which are indicative of the position between the rows of the line along which interpolation is performed;
multiplier means including a multiplying D/A
converter for receiving the data words and the weighted voltages, for latching a data word and multiplying same by the respective weighted voltage to define a sequence of analog product voltages;
summing means coupled to the D/A converter for adding selected product voltages to define a final sequence of weighted voltages;
said summing means including a sample/hold circuit for delaying selected product voltages, a summing junction coupled to the sample/hold circuit for receiving the delayed and undelayed product voltages and for providing a difference voltage indicative of what the value of the interpolated output should be, a negative waveform of the interpolated output, and a selected DC offset voltage; and means coupled to the summing means for ramping the weighted voltages from the value that they are to a value they should be, to define the interpolated output.
17. A circuit for generating an interpolation output by horizontally and vertically interpolating along a line between rows of data points of a two dimensional array, comprising:
a single random access memory for providing in response to respective addresses a selected stream of interleaved data words representing alternate data values from upper and lower rows of data points;
ramp generating means for supplying alternately interleaved weighted voltages indicative of the position between two rows of the line along which interpolation is taking place;
a single multiplying D/A converter coupled to the single random access memory for receiving the stream of interleaved data words and the weighted voltages and for generating an interleaved sequence of analog product voltages;
summing means coupled to the multiplying D/A
converter for adding a pair of alternate product voltages to define a final sequence of weighted voltages; and means coupled to the summing means for ramping the weighted voltages from a value where they are to a value where they should be, to define the interpolated output.
a single random access memory for providing in response to respective addresses a selected stream of interleaved data words representing alternate data values from upper and lower rows of data points;
ramp generating means for supplying alternately interleaved weighted voltages indicative of the position between two rows of the line along which interpolation is taking place;
a single multiplying D/A converter coupled to the single random access memory for receiving the stream of interleaved data words and the weighted voltages and for generating an interleaved sequence of analog product voltages;
summing means coupled to the multiplying D/A
converter for adding a pair of alternate product voltages to define a final sequence of weighted voltages; and means coupled to the summing means for ramping the weighted voltages from a value where they are to a value where they should be, to define the interpolated output.
18. The circuit of claim 17 as employed in an error correction system for correcting spatial and shading errors in the tubes of a multi-channel camera, the system further including:
a plurality of interpolation circuits respectively disposed in the channels one for each error to be corrected;
and control means coupled to the interpolation circuits of each channel to select the tube and the circuit corresponding to the error being corrected, and for supplying the correction interpolated output to the respective tube.
a plurality of interpolation circuits respectively disposed in the channels one for each error to be corrected;
and control means coupled to the interpolation circuits of each channel to select the tube and the circuit corresponding to the error being corrected, and for supplying the correction interpolated output to the respective tube.
19. The circuit of claim 17 further including:
address means for selectively addressing the single random access memory to retrieve therefrom alternate data words of the interleaved data words during a selected time interval; and wherein the weighted voltages corresponding to upper and lower rows are supplied in sync with the stream of respective upper and lower data words.
address means for selectively addressing the single random access memory to retrieve therefrom alternate data words of the interleaved data words during a selected time interval; and wherein the weighted voltages corresponding to upper and lower rows are supplied in sync with the stream of respective upper and lower data words.
20. The circuit of claim 19 wherein:
the single multiplying D/A converter latches each successive data word and multiplies same by the respective upper and lower weighted voltage to supply an interleaved sequence of analog product voltages.
the single multiplying D/A converter latches each successive data word and multiplies same by the respective upper and lower weighted voltage to supply an interleaved sequence of analog product voltages.
21. The circuit of claim 20 wherein the summing means includes:
a sample/hold circuit for delaying selected ones of the product voltages;
a summing junction coupled to the sample/hold circuit for receiving the delayed and undelayed sequences of product voltages, a negative waveform of the interpolated output, and a selected DC offset voltage; and said summing junction providing a difference voltage indicative of what the value of the interpolated output should be.
a sample/hold circuit for delaying selected ones of the product voltages;
a summing junction coupled to the sample/hold circuit for receiving the delayed and undelayed sequences of product voltages, a negative waveform of the interpolated output, and a selected DC offset voltage; and said summing junction providing a difference voltage indicative of what the value of the interpolated output should be.
22. The circuit of claim 16 wherein the means for ramping coupled to the summing means includes, a sampling means, and an integrating means coupled to the sampling means for ramping the interpolated output to a value corresponding to the difference voltage applied thereto.
23. The circuit of claim 22 further including:
an interface circuit which includes the generating means, and which further includes:
timing generator/circuit means for generating selected timing and clocking signals for the circuit components; and adder/multiplexer means integral with the address means for generating addresses which distinguish the upper and lower data words of the rows of data points.
an interface circuit which includes the generating means, and which further includes:
timing generator/circuit means for generating selected timing and clocking signals for the circuit components; and adder/multiplexer means integral with the address means for generating addresses which distinguish the upper and lower data words of the rows of data points.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US139,512 | 1980-04-11 | ||
| US06/139,512 US4354243A (en) | 1980-04-11 | 1980-04-11 | Two dimensional interpolation circuit for spatial and shading error corrector systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1180107A true CA1180107A (en) | 1984-12-27 |
Family
ID=22487021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000374808A Expired CA1180107A (en) | 1980-04-11 | 1981-04-07 | Two dimensional interpolation circuit for spatial and shading error correction systems |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4354243A (en) |
| JP (1) | JPS5713865A (en) |
| BE (1) | BE888385A (en) |
| CA (1) | CA1180107A (en) |
| DE (1) | DE3114922C2 (en) |
| FR (1) | FR2480544A1 (en) |
| GB (1) | GB2073996B (en) |
| IT (1) | IT1170884B (en) |
| NL (1) | NL8101775A (en) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4309723A (en) * | 1980-04-14 | 1982-01-05 | Ampex Corporation | Apparatus and method for registration and shading of color television cameras |
| DE3028066A1 (en) | 1980-07-24 | 1982-02-18 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | CIRCUIT ARRANGEMENT FOR CORRECTING DISTURBED SAMPLE VALUES IN A PCM TRANSMISSION DEVICE, IN PARTICULAR A DIGITAL TONE PLATE |
| US4484230A (en) * | 1981-02-04 | 1984-11-20 | Crosfield Electronics Limited | Image reproduction method and apparatus |
| US4414573A (en) * | 1981-04-08 | 1983-11-08 | Ampex Corporation | Pattern recognition circuit for reliably distinguishing between different portions of a diascope pattern during video camera setup |
| JPS57206171A (en) * | 1981-06-15 | 1982-12-17 | Ricoh Co Ltd | Shading compensating device |
| JPS57208765A (en) * | 1981-06-18 | 1982-12-21 | Dainippon Screen Mfg Co Ltd | Signal interpolating method for memory device |
| US4524388A (en) * | 1981-08-11 | 1985-06-18 | Konishiroku Photo Industry Co., Ltd. | Shading correction device |
| NL8200234A (en) * | 1982-01-22 | 1983-08-16 | Philips Nv | ADJUSTMENT SYSTEM FOR A TELEVISION CAMERA. |
| US4500916A (en) * | 1982-04-05 | 1985-02-19 | Panavision, Inc. | Automatic on-air registration system and method for color TV camera |
| JPS58223984A (en) * | 1982-06-23 | 1983-12-26 | Hitachi Ltd | Color television camera |
| US4422019A (en) * | 1982-07-12 | 1983-12-20 | Tektronix, Inc. | Apparatus for providing vertical as well as horizontal smoothing of convergence correction signals in a digital convergence system |
| GB2126827B (en) * | 1982-09-09 | 1986-04-30 | Link Electronics Ltd | Electro-optical tube registration |
| GB2132057B (en) * | 1982-09-09 | 1986-04-23 | Link Electronics Ltd | Electro-optical image correction |
| GB2126855B (en) * | 1982-09-09 | 1986-04-23 | Link Electronics Ltd | Focus correction |
| FR2548851B1 (en) * | 1983-07-07 | 1986-11-14 | Electricite De France | METHOD AND APPARATUS FOR ANALYZING AND RESTORING SIGNAL WITH SAMPLE AND INTERPOLATION |
| JPS60218181A (en) * | 1984-04-13 | 1985-10-31 | Fujitsu Ltd | Picture processor |
| US4649482A (en) * | 1984-08-31 | 1987-03-10 | Bio-Logic Systems Corp. | Brain electrical activity topographical mapping |
| US4744029A (en) * | 1984-08-31 | 1988-05-10 | Bio-Logic Systems Corporation | Brain electrical activity analysis and mapping |
| JPS61168078A (en) * | 1985-01-15 | 1986-07-29 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Image processing |
| US4648119A (en) * | 1985-03-18 | 1987-03-03 | Tektronix, Inc. | Method and apparatus for forming 3×3 pixel arrays and for performing programmable pattern contingent modifications of those arrays |
| DE3512631A1 (en) * | 1985-04-06 | 1986-10-09 | Robert Bosch Gmbh, 7000 Stuttgart | METHOD FOR GENERATING CORRECTION SIGNALS FOR GRID AND / OR IMAGE SHADING CORRECTION |
| SE452386B (en) * | 1985-10-07 | 1987-11-23 | Hasselblad Ab Victor | DEVICE FOR APPLIANCES FOR ASTAD COMMANDING OF AN ELECTRIC SIGNAL REPRESENTING A PICTURE |
| US5001651A (en) * | 1986-11-10 | 1991-03-19 | Auto-Trol Technology Corporation | Method and apparatus for interpolating groups of pixels on a scan line |
| US4754334A (en) * | 1987-01-08 | 1988-06-28 | Management Graphics, Inc. | Image recorder having automatic alignment method and apparatus |
| US4816913A (en) * | 1987-11-16 | 1989-03-28 | Technology, Inc., 64 | Pixel interpolation circuitry as for a video signal processor |
| AU622879B2 (en) * | 1987-11-16 | 1992-04-30 | Intel Corporation | Pixel interpolation circuitry as for a video signal processor |
| JP2618951B2 (en) * | 1988-02-16 | 1997-06-11 | 株式会社東芝 | 3D graphics processor |
| US5197108A (en) * | 1988-03-31 | 1993-03-23 | Ricoh Company, Ltd. | Smoothing method and apparatus for smoothing contour of character |
| JP2737877B2 (en) * | 1988-03-31 | 1998-04-08 | 株式会社リコー | Dot character pattern smoothing method |
| US4864386A (en) * | 1988-09-12 | 1989-09-05 | Tektronix, Inc. | Double display mode for differential gain |
| US5134496A (en) * | 1989-05-26 | 1992-07-28 | Technicolor Videocassette Of Michigan Inc. | Bilateral anti-copying device for video systems |
| US5060172A (en) * | 1989-07-06 | 1991-10-22 | Digital Equipment Corporation | Method and apparatus for displaying smooth-shaded objects |
| FR2652695B1 (en) * | 1989-10-03 | 1993-04-16 | Thomson Csf | METHOD AND DEVICE FOR VISUALIZING IMAGES, WITH AUTOMATIC CORRECTION OF DEFECTS BY FEEDBACK. |
| US5157497A (en) * | 1991-02-25 | 1992-10-20 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for detecting and compensating for white shading errors in a digitized video signal |
| US5677967A (en) * | 1993-03-10 | 1997-10-14 | R. R. Donnelley & Sons Company | Method of and apparatus for converting between a color appearance space and a colorant space |
| US5739870A (en) * | 1996-03-11 | 1998-04-14 | Display Laboratories, Inc. | Math engine for generating font gradients |
| JP3351704B2 (en) * | 1997-04-09 | 2002-12-03 | ペンタックス株式会社 | Image signal correction device |
| CN1322749C (en) * | 2001-11-01 | 2007-06-20 | 皇家飞利浦电子股份有限公司 | Edge oriented interpolation of video data |
| US7969224B2 (en) * | 2007-03-20 | 2011-06-28 | Honeywell International, Inc. | Circuit to reduce duty cycle distortion |
| US20080231335A1 (en) * | 2007-03-20 | 2008-09-25 | Honeywell International Inc. | Circuit to reduce duty cycle distortion |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3902011A (en) * | 1969-11-12 | 1975-08-26 | Meldreth Electronics Limited | Image analysing |
| US3678258A (en) * | 1970-09-29 | 1972-07-18 | Electronic Associates | Digitally controlled electronic function generator utilizing a breakpoint interpolation technique |
| US3919473A (en) * | 1974-01-02 | 1975-11-11 | Corning Glass Works | Signal correction system |
| FR2284238A1 (en) * | 1974-09-03 | 1976-04-02 | Bausch & Lomb | Correction of shadow effect on video pictures - involves stores which are used to hold data generated as function of reference video signals |
| US4170024A (en) * | 1977-05-24 | 1979-10-02 | Rca Corporation | Television control system |
| GB1602618A (en) * | 1977-05-30 | 1981-11-11 | Rca Corp | Automatic setup system for television camera |
| US4234890A (en) * | 1978-03-06 | 1980-11-18 | Rca Corporation | Automatic setup system for television cameras |
| US4285004A (en) * | 1980-02-25 | 1981-08-18 | Ampex Corporation | Total raster error correction apparatus and method for the automatic set up of television cameras and the like |
-
1980
- 1980-04-11 US US06/139,512 patent/US4354243A/en not_active Expired - Lifetime
-
1981
- 1981-04-07 CA CA000374808A patent/CA1180107A/en not_active Expired
- 1981-04-10 NL NL8101775A patent/NL8101775A/en not_active Application Discontinuation
- 1981-04-10 FR FR8107218A patent/FR2480544A1/en active Granted
- 1981-04-10 IT IT48255/81A patent/IT1170884B/en active
- 1981-04-11 JP JP5495081A patent/JPS5713865A/en active Granted
- 1981-04-13 BE BE0/204456A patent/BE888385A/en not_active IP Right Cessation
- 1981-04-13 DE DE3114922A patent/DE3114922C2/en not_active Expired
- 1981-04-13 GB GB8111666A patent/GB2073996B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2073996A (en) | 1981-10-21 |
| BE888385A (en) | 1981-07-31 |
| NL8101775A (en) | 1981-11-02 |
| GB2073996B (en) | 1983-11-23 |
| JPH0311149B2 (en) | 1991-02-15 |
| DE3114922C2 (en) | 1986-03-13 |
| FR2480544B1 (en) | 1984-12-28 |
| DE3114922A1 (en) | 1982-05-06 |
| IT8148255A0 (en) | 1981-04-10 |
| US4354243A (en) | 1982-10-12 |
| FR2480544A1 (en) | 1981-10-16 |
| IT1170884B (en) | 1987-06-03 |
| JPS5713865A (en) | 1982-01-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20011227 |