CA1168364A - Soft error rewrite control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Refresh and initialize counter circuits included within a dynamic memory system are supplemented with addi-tional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corre-sponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.

Description

BACKGROUND OF THE INVENTION
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Field of Use _.

This invention xelates to dynamic memory systems and more particularly to improving the reliability of ~uch Systems.

Prior Art Recently, manufacturers of dynamic random access mem-ory chips have noted that high density memory chips lack immunity to soft errors resulting from ionizing alpha particles. To overcome this problem, some manufacturers have improved the structures of the chips so as to proviæe a high degree of immunit~ to soft errors. While this approach reduces the likeliness of such soft errors, such errors still can occur which can give rise to uncorrectahle error conditions.

Other manufacturers have proposed certain systems design alternatives. These include error correction, rewriting the corrected word to prevent error accumula-tion, periodic memory purging and systems redundancy. The soft error problems and the design alternatives are set forth in the publication "~emory System Design Se~inar" by Intel Corporation, Copyright 1979.

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~ 1~83~4 It will be appreciated that while the above àlternatives have been suggested, there appears to be no memory systems which have the ability to protect against soft errors.

S Accordingly, it is a primary object of the present invention to provide a memory system with the capability of protecting against soft errors.

It is a further object of the present invention to provide a soft error protection capability by adding a minimum of additional apparatus to the memory system.

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S ~ K~:5 ~ 7r ru~ u~ o~

The above ohjects are achieved in a preferred embodiment of the present invention by including addition-al apparatus in a dynamic memory system which in conjunc-tion with the refresh initialization circuits and errordetection and correction (~DAC) circuits of the dynamic memory system initiates rewrite cycles of operation at a predetermined rate for writing corrected versions of the information read out from each location. The additional apparatus includes counter control circuits which are synchronized from the same timing source which synchronizes the operation of the refresh and initialize address counter circuits. The counter control circuits count with a modulus one less than a maximum count 1~ ~enerated by such circuits enahle the generation of a sequence of counts which select different combinations of row and column addresses for rewriting all of the locations with error free information during a correspond-ing number of cycles of operation at the predetermined - 20 rate.

The predetermined rate is selected to be much slower than the refresh rate so as to minimize interference with normal memory operations. By utilizing the existing 3~

refresh and ini.tialize circuits and data paths, the amount of additional circuits is kept to a minimum.
In accordance with the present invention, there is provided a semiconductor memory system comprising: a dynamic memory including a number of addressable arrays of memory cells arranged in a number of rows and columns and said arrays being organized into a number of storage locations; error detection and correction means coupled to said memory for detecting and correct-ing single bit errors in the contents of the cells read out from said memory during a memory cycle of operat.ion; timing means for providing sequenees of timing signals for performing said memory cycle of operation; refresh and write control means eoupled to said timing means and to said memory, said refresh control means periodically generating refresh command signals in response to signals from said timing means, and including row and column address counter means; and, rewrite eontrol means eoupled to said refresh and write eontrol means and to said timing means, said rewrite control means including counter means operative after eaeh occurrence of a predetermined number of refresh command signals to condition said timing means to generate a sequence of signals during a rewrite cycle of operation for performing read and write cycles of operations upon the cells within the rows and columns of one of said number of storage locations specified by said row and column address eounter means for enabling the detection and eorrection of said single bit errors within said memory by said : error deteetion and eorrection means at a predetermined rate thereby rendering said memory system less susceptible to soft errors.

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In accordance with another aspect of the invention, there is provided a dynamic semiconductor memory system comprising: a number of addressable arrays of memory cells whose contents must be refreshed within a predetermined ti:me interval, each array beiny divided into a number of rows and columns and organized into a number of storage locations; error detection and correction circuit means coupled to said arrays for detecti.ng and correcting single bit errors in th.e contents of -the cells read out during a memory cycle of operation; addressing means for applying addresses to said number of arrays during said memory cycle of operation; timing control means for providing predetermined sequences of timing signals for performing said memory cycle of operation upon selected ones of said number of arrays; refresh control means for periodic ally generating a refresh command signal for refreshing the memory cells of a different one of each of the rows within sai.d number of arrays within one of a plurality of refresh time intervals evenly distributed throughout said predetermined time interval, said refresh control means being coupled to said addressing means and to said timing and control means, said refresh control means including refresh address counter means for sequentially counting through all of the row addresses required to refresh said number of addressable arrays; write address counter means coupled in series with said refresh address counter means and to said addressing means, said write address counter means being operative in response to said refresh command signal to generate column address signals; and, soft error rewrite control means coupled to said refresh command control means, said timing and control means and said addressing means, said so.ft error rewrite control means including counter - 4a -. , ~

36q means operative in response to s.aid refresh.command signal to generate a sequence oE counts Eor conditioning said timing and control means to initiate a rewrite cycle of operation after each occurrence of a predetermined number of refresh command signals by generating signals during said rewrite cycle of operation for performing read and write operations upon said cells within the rows and columns of one of said number of storage locations specified by the contents of said refresh address counter means and said write address counter means respectively applied to said addressing means for detection and correction of said single bit errors in the contents of all of said cells of said arrays by said error detection and correction means at a predetermined rate thereby rendering said memory system less susceptible to soft errors.
In accordance with a further aspect of the invention, there is provided a dynamic semiconductor memory system comprising:
at least a pair of memory module units, each unit including a plurality of rows of MOS memory chips, each chip including a number of arrays of memory cells organized into a plurality of storage locations including a number of rows and columns; error detection and correction circuit means coupled to said pair of memory module units for detecting and correcting single bit errors in the contents of the cells read out from said memory module units during a memory cycle of operation; addressing means for applying addresses to said plurality of rows of chips during said memory cycle of operation; timing control means for providing sequences of timing signals for performing said memory cycle of operation;
refresh control means for generating a refresh command signal for - 4~ -~ ~LB~36~

refreshing the memory cells within a row of said arrays o~ said plurality of rows of chips of each.of said memory module units during each one of a plurality of evenly distributed refresh cycles of operation, said refresh control means being coupled to said addressing means and to said timing control means, said refresh control means including a refresh address counter for sequentially counting through all of the row addresses required to refresh all of said cells of said memory module units; a write address counter connected in series with sai.d refresh address counter and to said addressing means, said write address counter for sequentially counting through all of the column addresses requ.ired to write data into all of said cells of said memory module units; and, rewrite control means coupled to said refresh control means, said addressing means and to said timing control means, said rewrite control means including a counter having a predetermined number of stages for generating a predetermined maximum count, said counter being operative upon generating a count corresponding to a predetermined number of refresh command signals to condition said timing control means to i.nitiate a rewrite cycle of operation during which said timing control means generates a sequence of signals for performing read and write cycles of operations upon said cells in a row of chips of each of said memory module units within the rows and columns of one of said plurality of storage locations specified by said refresh address counter and write address counter respectively for enabling the detection and correction of said single bit errors within said pair of memory module units by said error detection and correction means at a predetermined rate which is less than the rate for refresh.ing said . .

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~ ~68~4 cells and is sufficient to render said sy~tem less susceptible to soft errors.
The novel features which are beli.eved to be character-istic of the invention both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying drawings. It is to be expressly understood, however, that each of the drawings are given for the purpose of illustration and description only and are not intended as a definition of the limits of the pr~sent invention.

- 4d -Ç36 4 BRIEF DESCRIPTION OF TH~: DRAWINGS

Figure 1 is a block diagram of a dynamic memory sys-tem which incorporates the apparatus of the present inver,-tion.

Figure 2 discloses in greater detail the circuits of block 207 of Figure 1.

Figure 3 discloses in greater detail the timing circuits of block 204 of Figure 1.

Figure 4 discloses in greater detail the circuits of block 214 of the present invention.

Figure 5 discloses in greater detail the read/write control cir~uits of block 208.

Figure 6 discloses in greater detail the circuits of block 212.

Figure 7 discloses in greater detail the chips of blocks 210-20 and 210-40.

Figures 8a through 8c are timing diagrams used to explain the operation of the present invention.

Figure 9 illustrates the format of the memory addresses applied to controller 200 as part of each memory read or write request.

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I lB8~4 MEMORY SUBSYSTEM INTERFACE

Before describing the controller of Figure 1, it is seen that there are a number of lines which constitute the interface between the control:ler and a bus. As shown, the interface lines include a number of address lines (BSAD00-23, BSAP00), two sets of data lines (BSDT00-15, BSDP00, BSDP08) and (BSDT16-31, BSDP16, BSDP24), a number of control lines (BSMREF-BSMCLR), a number of timing lines (BSREQT-BSNAKR), and a number of tie breaking network lines (BSAUOK-BSIUOK, BSMYOK).

The description of the above interface lines are giv-en in greater detail in the section to follow.

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~EMORY S~BSYSTFM_INTERFACE LINES
Desi~nation Description Address Lines BSAD00-BSAD23 The bus address lines constitute a twenty-four bit wide path used in con-junction with the bus memory reference line BS~REF to transfer a 24-hit address to controller 200 or a 16-bit identifier from controller 200 to the bus (for receipt hy a slave unit).
When used for memory addressing, ~he signals applied to lines BSAD00-BSAD03 select a particular 512K word module, the signals applied to lines BSAD04-OBBS~D22 select one of the 512K
words in the module while the signal applied to line BSAD23 selects one of the bytes within the selected word (i.e., BSAD23=1=right byte;
2Q BSAD23=0=left byte).

When used for identification, lines BSAD00-BSAD07 are not used. The lines BSAD08-BSAD23 carry the identification of the receiving unit as transmitted ,, ) ~fi83'64 MEMORY SUBSYSTEM INTERFACE LINES
Designation De ~

to controller 200 during the previous memory read request.

5 BSAP00 The bus address parity line is a hidirectional line which provides an odd parity signal for the address signals applied to lines BSAD00-BSAD07.

Data Lines BSDT00-BSDT15, The sets of bus data lines constitute BSDT16-BSDT31 32-bit or two wo~d wide bidirec-tional path for transferring data or identification information between controller 200 and the bus as a function of the cycle of operation being performed.

During a write cycle of operation, the bus data lines transfer information to be written into memory at the location specified hy the address signals applied to lines BSAD00-BSAD23.
During the first half of a read cycle ~ ~8~$~

MEMORY S~BSYSTEM INTERFACE LINES

of operation, the data lines BSDT00-BSDT15 transfer identification information (channel number) to the controller 200. During the second half of the read cycle, the data lin~s transfer the information read from memory.

BSDP00, BSDP08, The bus data parit~ lines are two BSDP16, BSDP24 sets of bidirectional lines which provide odd parity signals coded as ; follows:
.
BSDP00=odd parity for signals applied to lines BSDT00-BSDT07 (left byte);

BSDP08=odd parity for signals applied to lines BSDT08-BSDT15 (right byte);

BSDP16=odd parity for signals applied : to lines BSDT16-BSDT23; and BSDP24=odd parity signals applied to lines BSDT24-BSDT31.

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MEMORY SUBSYSTEM INTERFACE LINES
De cription Control Llnes BSMREF The bus memory reference lines extends from the bus to the memory controller 200. When set to a true state, this line signals the controller 200 that the lines BSAD00-BSAD23 contain a com-plete memory controller address and that it is performing a write or read operation upon the specified location.

When reset to a false state, the line signals controller 200 that the lines BSAD00-BSAD23 contain information directed to another unit and not con-troller 200.

BSWRIT The bus write line extends from the bus to the memory controller 200.
: This line when set to a true state~ in conjunction with line BSMREF being true, signals controller 200 to per-form a write cycle of operation. When reset to a false ~tate, thls line, in conjunction with line BSMREF being 3~

MEMORY SUBSYSTEM INTERFACE LINES
Desi~nation _scri2tion true, signals controller 200 to per-form a read c~cle of operation.

5 BSBYTE The bus byte line extends from the bus to controller 200. This line, when set to a true state, signals control-ler 200 that it i5 to perform a byte operation rather than a word operation.

BSLOCK The bus lock line extends from the bus to controller 200. When set to a true state, this line signals controller 200 of a request to perform a test or change the status of a memor~ lock flip-flop included within the control-ler 200.

BSSHBC The bus second half bus cycle line is used to signal a unit that the current information applied to the bus by con-troller 200 is the information requested b~ a previous read request.
In this case, both controller 200 and the unit receiving the information are 1 ~ 683B ~

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bus~ to all units from the start of the initiation cycle until controller 200 completes the transfer.

This line is used in conjunction with the BSLOCK line to set or reset its memory lock flip-flop. When a unit is requesting to read or write and line BSLOCK is true, the line BSS~BC, when true, signals controller 200 to reset its lock flip-flop. When in a false state, lt signals controller 200 to test and set its lock flip-flop.
., 15 BSMCLR The bus master clear line extends from the bus to controller 200. When this line is set to a true state, it causes .::
the controller 200 to clear to zeros certain bus circuits within controller 2Q 200.
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BSYELO The hus yellow line is a bidirectional ; line which designates a soft error condition. When set to a true s~ate during the second half of a bus cycle .
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1 ~83~

MEMORY SUBSYSTEM INTERFACE LINES
escription in response to a read command, it indicates that the accompanied transferred information has heen suc-cessfully corrected.
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When set to a true state during a mem-ory read request, this line indicates that the read request is to be interpreted as a diagnostic command.

, Bus Handshake/Timing Lines BSREQT The bus request line is a bidirec-tional line which extends between the bus and controller 200. When set to a true state, it signals the controller 200 that another unit is requesting a bus cycle. When reset to a false state, it signals controller 200 that there is no bus pending bus request.
This line is forced to a true state by controller 2U0 to request a read second half bus cycle.

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MEMORY SVBSYSTEM INTERFACE LINES
Description BSDCNN The data cycle line is a bidirectional line which extends between the bus and controller 200. When forced to a true state, the line signals the controller 200 that a unit was grant~d a request-ed bus cycle and placed information on the bus for another unit.

The controller 200 forces the line to a true state to signal that it is transmitting requested data back to a unit. Prior to this, controller 200 `- had requested and been granted a bus cycle.

BSACKR The bus acknowledge line is a bidirec-tional line which extends between the bus and controller 200. When set to a binary ONE hy controller 200, the line signals that it is accepting a bus trans-fer during a read first half bus cycle or write cycle During a read second half bus cycle, this line when set to a binary ONE by the unit which .

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-15~
MEMORY SUBSYSTEM INTERFACE LINES
. . _ .. . _ . ~
ation Description .
originated the request signals the ~` controller 200 of its acceptance of a transfer.

BSWAIT The bus wait line is a hidirectional line which extends between the bus and .
controller 200. When set to a true or binary ONE state by controller 200, it signals a requesting unit that the controller cannot accept a transfer at this time. Thereafter, the unit will `~ initiate successive retries until the controller 200 acknowledges the trans-fer. The controller 200 sets the BSWAIT line true under the following conditions:

1. It is busy performing an internal read or write cycle of operation.

2. It is requesting a read second half bus cycle.

3. It is anticipating a refresh operation.

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~EMORY SUBSYSTEM INTEREACE LINES
Desi~nation Description

4. It is performing a refresh operation.
:

5. It is bus~ when placed in an initialize mode.

6. It is busy performing a soft error rewrite cycle.

When the BSWAIT line is set to a true or binary ONE state by a unit, this signals the controller 200 that the data is not being accepted by the - requesting unit and to terminate its ;~ present bus cycle of operation.
' 15 BSNAKR Ths bus negative acknowledge line is a bidirectional line which extends ~; between the bus and controller 200.
When this line is set to a true or binary ONE state b~ controller 200, it 2Q signals that is is refusing a specified transfer. The controller 200 sets line BSNAKR to a true state as follows:

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~g;!~lil~S
Designation Description 1. Memory lock flip-flop i5 set to a binary ONE, and 2. The request is to test and set the - lock flip-flop (BSLOCK true and BSSE[BC false).
... .
In all other cases, when the memory lock flip-flop is set, controller 200 generates a response via the BSACKR
line or the BSWAIT line or generates no response.

When the BSNAKR line is forced true by a unit, this signals controller 200 that the data is not accepted by the unit and to ~erminate its cycle of operation.

Tie Break~ Control Lines BSAUOK~BSIUOK The tie breaking network lines extend from the bus to controller 200. ~hese lines signal controller 200 whether units of higher prio~ity have made bus requests. When all the signals on ~ ~83~

MEMORY SUBSYSTEM INTERFACE LINES
51~ Descri~tion -` these lines are binary ONES, this --~ signals controller 200 that it has been granted a hus cycle at which time it is able to force the BSDCNN line to a binary ONE. When any one of the signals on the lines is a binary ZERO, this signals controller 200 that it ~ 10 has not been granted a bus cycle and .~ is inhibited from forcing line BSDCNN
to a binary ONE.

BSMYOK The tie breaking network line extends - from controller 200 to the bus. Con-~: 15 troller 200 forces this line to a false or binary 2ERO state to signal other units of lower priorit~ of a bus - request.

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Gene_al Descri~tion of the S~s_em of_Fi~ure 1 Figure 1 shows a preferred embodiment of a memory controller 200 which is constructed usirlg ~he principles of the present invention. Referring to Figure 1, it is seen that the controller 200 controls the two 256K word memory module units 210-2 and ~10-4 of memory section 210.
The module units of blocks 210-2 and 210-4 include high speed MOS random access memory integrated circuits corre-sponding to blocks 210-20 and 210-40, and address buffer circui~s corresponding to blocks 210-22 through 210-26 and 210-42 through 210-46. Each 256K memory unit is constructed from 64K word by 1-bit dynamic MOS RAM chips illustrated in greater detail in Figure 7. More specifi-cally, referring to Figure 7, it is seen that each 256K by 22-bit memory module includes 88, 65,534 ~64K) word by 1-bit chips. Within each chip there are a number of storage arrays organized in a matrix of 256 rows by 256 columns of storage cells.

The controller 200 includes those circuits required to generate memory timing signals, perform refresh operations, rewrite control operations, data transfer operations, address distribution and decoding operations and bus interface operations. Such circuits are included as part of the different sections of Figure 1.

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' 68~64 The sections include a timing section 204, a refresh control section 205, a soft error rewrite control section 214, a data control section 206, an address section 207, a read/write control section 208, a data in section 209, a bus control circuit section 211, a memory initialize cir-cuit section 212, and bus driver/receiver circuit section 213.

The hus control section 211 includes the logic circuits which generate signals for generating and accepting bus cycle requests for single and double word operations. As seen from Figure 1, these circuits as well as the circuits of the other sections are connected to a bus via the driver/receiver circuits of section 213 which were conventional in design. The section 211 includes the tie breaking network circuits which resolve requests pri-ority on the basis of a unit's physical position on the bus. The memory controller, located at the left most or bottom position of the bus, is assigned the highest prior-ity while a central processing unit (CPU), located at the highest most or top position of the bus is assigned the lowest priority. For further information regarding bus operation, reference may be made to U.S. Patent No.
4,000,485 which issued December 28, 1976.

3~1 The timing section 204, shown in detail in Figure 3, includes circuits which generate the required sequence of timing signals from memory read and write cycles of operation. As seen from Figure 1, this section transmits and receives signals to and from sections 205, 206, 207, 208, 211 and 214.

The address section 207, shown in greater detail in Figures 2a through 2c, includes circuits which decode, generate and distribute address signals required for refresh operations, initialization and read/write selec-tion. The section 207 receives address signals from lines BSAD08-BSAD23 and address lines BSAD00-BSAD07 and BSAP00 in addition to the memory reference control signal from the BSMREF line. Additionally, section 207 receives con-trol and timing signals from sections 204, 212 and 205.

The memory initialization sectlon 212 includes circuits, conventional in design, for clearing the memory subsystem circuits to initial or predetermined state.

The read/write control section 208 includes register and control logic circuits, conventional in design. The register circuits receive and store signals corresponding to the states of the BSWRIT, BSBYTE and the address line BSAD23. The control circuits decode the signals from the register circuits and generate signals which are applied 316~

to sections 204, 207 and 210 for establishing whether-the subsystem is to perform the read, write or read followed by a write cycle of operation (i.e., for a byte command).

The refresh section 205 includes the circuits for periodically refreshing the contents of the memory. Sec-tion 205 receives timing and control signals from section 204 and provides refresh command control signals to sections 204, 207, 208 and 212. For further details, ref-erence may be made to ~.S. Patent No. 4,1~5,323 which discloses circuits for generating refresh command (REFCOM) signals.

The data in section 209 circuits of block 209-4 include a pair of multiplexer circuits and an address reg-ister which is connected ~o receive signals from section 206.

The multiplexer circuits, conventional in design, receive data words from the two sets of bus lines BSDT00 15 and BSDT16-31 and apply the appropriate words via the sets of output line$ MDIE000-015 and MDIO000-015 to the correct memory modules during a write cycle of operation. That is, multiplexer circuits are selectively enabled by signal MOWTES000 generated by an AND gate 209-10 when initialize signal INITTM310 from 212 is a binary ZERO (i.e., not in an initialize mode). The AND

~ ~83G4 gate 209-10 generates signal MOWTES000 as a function of bus address bit 22 (i.e., signal BS~D22) and whether the C ~
~ tem i9 doing a write operation (i.e., signal BSWRIT). During a write operation, signal MOWTES000 5 selects the correct data word (i.e., the word applied to bus lines BSDT00-15 or BSDT16-31) to be applie~ to the correct memory unit. This enables a write operation to start on any word boundary.

During a read operation, the multiplexer circuits are 10 conditioned to apply the module identification information received from the bus lines BSDT00-15 back to the address bus lines BSAD08-23. This is done by loading the signals applied to lines BSDT00-15 into the even data registers 206-8 of section 206. This, in turn, causes the address 15 register latches of block 209-4 to be with the module identification information transmitted via the bus lines BSDT00-15. Since this i5 not pertinent to an understand-ing of the present invention, it will not be further discussed herein.

The data control section 206 includes three tristate operated data registers 206-8 and 206-10 and multiplexer circuits 206-16 and 206-18 with associated control circuits which enable data to be written into and/or read from the even and odd memory units 210-20 and 210-40 of .

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section 210. For example, during a douhle wide read cycle operation, operand or instruction signals are read out from the units 210-20 and 210-40 into the even and odd output registers 206-8 and 206-10. During a write cycle of operation, the byte operand signals are loaded into the leftmost section of the pair of registers 206-8 and 206-10 from the bus via section 209-4 and written into the odd or even unit of section 210.

The controller 200 includes error detection and cor-rection (EDAC) apparatus wherein aach word contains 16data bits and 6 check bits used to detect and correct single bit errors in the data words and detect and signal without correction, double bit errors in the data word.
The EDAC apparatus includes two sets of EDAC
encoder/decoder circuits 206-12 and 206-14. These circuits ma~ take the form of those circuits disclosed in U.S. Patent No. 4,072,853 which issued ~ebruary 7, 1978.
Additionall~, the section 206 enables a return of identi-fication information received from the data lines ~ BSDT00-15 and stored in register 209-4 via the address lines BSAD08-23.

In accordance with the teachings of the present invention, the soft error rewrite control section 214 includes circuits for periodically accessing each of ~he 6~

locations within the memor~ section 210 for reading out and rewriting back into these locations corrected informa-tion so as to render the memory 21~ less susceptible to soft errors produced by alpha particles or other system disturbances. ~s shown from Figure 1, section 214 receives control si~nals from sections 205, 212 and 213.
The section provides control signals to sections 204, 206 and 207, as shown.

Pertinent portions of the above sections will be now discussed in greater detail with reference to Figures 2a through 7.

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DETAILED DESCRIPTION OF CONTROLLER SECTIONS

Only those sections which are believed necessary to an understanding of the present invention are described herein. For further information regarding the remaining sections, reference may be made to the related patent applications or to U.S. Patent: No. 4,185,323.

Section 204 and Section 206 Figure 3 illustrates in greater detail, the timing circuits of section 204. The circuits receive input 10 timing pulse signals TTAP01010 and T~AP02010 from delay line timing generator circuits, not shown, conventional in design. Such circuits may take the form of the timing generator circuits shown in U.S. Patent No. 4,185,323.
The timing generator circuits generate a series of timing pulses via a pair of series connected 200 nanosecond delay lines in response to the signal MYACKR10 being switched to a binary ONE. These pulses in conjunction with the circuits of block 204 establish the timing for the remain-ing sections during a memory cycle of operation.

Additionally, the circuits of block 204 receive a boundary signal MYBNDY010, address signals LSAD22200 and LSAD22210 from section 207 and soft error rewrite control signal ALPCNT010 from sectio!l 214. Also, section 212 1 ~B~36~

applies an initialize signal INITMM100 to section 204.
The signals MYBNDY010 and ALPCNT010 are applied to a NOR
gate 204-5 each of which force signal RASINH010 to a bina-ry ZERO when forced to a binary ONE. The series connected AND gate 204-7 logically combines initialize signal INITMM100, refresh command signal REFCOM100 generated by circuits within section ~4~, not shown, to produce signal RASINH000. A NAND gate 204-8 combines signals RASINH000 and address signal LSAD22210 to produce an even row strobe inhibit signal ERASIH000. The signal is applied to an AND
gate 204-10 for combining with a timiny signal MRASTT010 derived from signal TTAP01010 via an AND gate 204-1. The result output signal MRASTE010 is applied to the RAS
timing input of the even stack units 210-20.

A NAND gate 204-14 comhines signals RASINH010 and LSAD22200 to produce an odd row inhibit signal ORASIH000.
This signal is combined in an AND gate 204-17 with timing signal MRASTT010 to generate row timing signal MRAST0010.

This signal is applied to the RAS timing input of the odd stack units 210-40.

As seen from Figure 3, an AND gate 204-11 applies a timing signal MDECT0010 to a G input terminal of the mid-dle section of even data register 206-8 in the absence of a refresh command (i.e., signal REFCOM000=1). Similarly, .~ ', 1 ~6~364 ~28-an AND gate 204-15 applies a timing signal MDOCT0010 to a G input terminal of the middle section of odd data regis-ter 206-10. The delay network 204-19 which connects in series with AND gates 204-3, 204-18 and 204-20 generate timing signal MCASTS010. The signal MCASTS010 is applied to the CAS timing inp~t of the even and odd stack units 210-20 and 210-~0.

The even and odd data registers 206-8 and 206-10 are tristate operated. More specifically, the registers are constructed from D type transparent latch circuits such as those designated SN74S373 manufactured by Texas Instruments Incorporated. The regis~er circuits are transparent meaning that while the signal applied to the G
input terminal is a binary ONE, the signals at the Q out-put terminals follow the signals applied to the D input terminals. That is, where the signal applied to the G
input terminal goes low, the signal at Q output terminal latches.

The output terminals of registers 206-8 and 206-10 are connected in common in a wired OR arrangement for enabling the multiplexing of the pair of data word signals. Such multiplexing is accomplished by controlling the states of the signals MDOTSC000l MDOTSC010 and MDRELB000 applied to the output control (OC) input 1 16~

terminals of the dlfferent sections of registers 206-8 and 206-10 shown in Figure 1. This operation is independent of the latching action of the register flip-flops which takes place in response to t:he signals applied to the G
input terminals.

The series connected group of gates 204-22 through 204-28 control the states of signals MDOTSC100 and MDOTSC010. The AND gate 204-22 receives timing signals DLYINN010 and DLY020100 at the beginning of a read or write cycle for enabling the storage of identification information from the bus. Since this is not pertinent to an understanding of the present invention, signal PULS20210 can be considered to be at a hinary ZERO state.
During a read operation, read command signal R~ADCM000 is forced to a binary ZERO which causes AND gate 204-26 to force signal MDOTSC100 to a binary ZERO and NAND gate 204-28 to force signal MDOTSC010 to a binary ONE.

The signal MDOTSC100, when a binary ZERO, enables the middle sections of registers 206-8 and 206-10 to apply their contents to their output terminals. The signal MDOTSC010 when a binary ONE, inhibits the right most sections of registers 206-8 and 206-10 from applying their contents to their output terminals. During a write cycle, when read command signal READCM000 is forced to a binary ~ 1~83~

ONE, AND gate 204-26 forces signal MDOTSC100 to a binary ONE while NAND gate 204 28 forces signal MDOTSC010 to a binary ZERO when signal ALPCNT000 ls a binary ONE. This produces ~he opposite result to that described. That is, signal MDOTSC100 inhibits the middle sections of registers 206-8 and 206-10 from applying their contents to their output terminals. At the same time, signal MDOTSC010 enables the right most sect:ion of registers 206-8 and 206-10 to apply their contents to their output terminals.
If signal ALPCNT000 is a binary ZERO, this inhibits NAND

gate 204-28 from forcing signal MDOTSC010 to a binary ZERO
in response to signal READCM000. Accordingly, the right most sections of registers 206-8 and 206-10 are also inhibited from appl~ing their contents to their output terminals.

Lastly, the section 204 further includes an AND gate 204-30. This AND gate in response to the timing signals DLY400010 and DLY220010 generated by the delay line timing circuits provides a reset signal RESET010 which is used to reset the soft error rewrite control circuits of section 214.

1 ~.6~36~

Section 207 _ Figure 2 illustrates the different sections of address section 207. As shown, section 207 includes an input address section 207-1, an address decode section 207-2, an address register section 207-4 and a refresh and initialize address register input sectiorl 207-6.

Sections 207-1 and 207-2 The input address section 207-1 includes a set of manually selectable switches of block 207-10 which receive bus address signals BSAD04110 and BSAD06110. These switches select the high order bus address bit which selects the upper/lower 256K of memory when the system includes the full complement of 128K memory modules. When the memory modules are constructed using 64K chips, the top switch is placed in the clos-ed position. This selects address bit 4 (signal BSAD04110) as the high order bus address bit. For 16K chips, the other switch is placed in the closed position which selects address bit 6.

Since it is assumed that the memory modules use 64K
chips, the top switch is closed while the other switch is opened. The resulting high order bit signal BSADX6010 in addition to its complement along with the least signifi-cant bus address bits 22 and 21 are stored in a register , 3~

207-12. The three signals are loaded into a register 207-12 when address strobe signal ADDSTR000 is forced to a binary ZERO. This occurs when the memory becomes busy (i.e., accepts a bus cycle/a memory request).

The outputs of register 207-12 are applied as inputs to a 2 to 1 MUX SN74S157), conventional in design. As shown, si~nal APLCNT000 from section 214 is inverted via inverter circuit 207-16 and applied as signal ALPCNT010 to the select input terminal (G0/Gl) of circuit 207~14. When signal ALPCNT010 is a binary ZERO, signals BSAD22210 ,~ through BSADX6210' register 207-12 are selected to be applied at the Y output terminals of circuit 207-14. When signal ALPCNT010 is a binary ONE, signals ARAD21010 and ARADX6010 from section 207-6 are selected to be applied to the Y2 and Y3 output terminals while Yl output terminal is forced to a binary ZERO.

As shown, the least significant address bit signals LSAD22210 and LSAD21210 are applied to the input terminals of a binary decoder circuit 207-20. The least significant bit address signal LSAD22210 and its complement signal LSAD22200 generated by an inverter circuit 207-22 are applied to sections 204 and 206. The high order bit sig-nal LSADX6210 i5 applied to the enable/ gate input termi-nal of decoder circuit 207-20. The complement signal ! lB~3~

LSADX6200 generated b~ an inverter circuit 207-15 is applied to the enable/gate input of decoder circuit 207-31, together with address signals LSAD22210 and LSAD21210. When high order address signal LSADX6210 is a binary ZERO, decoder circuit 207-20 is enabled for operation. Similarly, when signal LSADX6210 is a binary ONE, decoder circuit 207-31 is enabled for operation.

Each of the four decode outputs DECOD0000 through DECOD3000 connects to a different pair o~ the NAND gates 207-24 through 207-30. It will be noted that the zero decode signal DECOD0000 connects to the inputs of NAND
gates 207-24 and 207-26 which generate the 0 and 1 row address strobe signals. Similarly, the 1 decode signal DECOD1000 connects to the inputs of NAND gates 207-26 and 207-28 which generate the 1 and 2 row address strobe signals. The next sequential decode signal DECOD2000 connects to the two NA~D gates which generate the next pair of sequential xow address strobe signals. Lastly, the last decode signal DECOD3000 connects to NAND gates 207-30 and 207-24 which generate the 3 and 0 row address strobe signals. In a similar fashion, each of the four decode outputs DECOD4000 through DECOD7000 connects to a different pair of the NAND gates 207-32 through 207-38.

3~

As seen from Figure 2, all of the NAND gates 207-24 through 207-30 and 207-32 through 207-38 receive a further ~ D
A input signal OVRDEC000 generated by~ ~*~ gate 207-39.
When either initialize signal INITMM100 or refresh command 5 signal REFCOM100 is forced to a binary ZERO by the circuits of section 212 or section 204~ AND gate 207-39 forces signal OVRDEC000 to a binary ZERO. This turns on all the decode signals (i.e., signals DRAST0010 through DRAST7010 are forced to binary ONES) enabling eight memor~
10 locations to be written simultaneously during an initialize mode of operation, or "refreshed" during a refresh mode. As shown, the even row address strobe signals DRAST0010 and DRAST2010 are applied to the RAM
chips of the even stack units 210-20. The odd row address strobe signals DRAST1010 and DRAST3010 are applied to the RAM chips of the odd stack units 210-40.

~ ~6~33~4 Section 207-4 The address register section 207-4 as shown in Figure 2 receives the bus address signals BSAD05210 through BSAD20210 applied via the bus receiver circuits of block 213 of Figure 1 as inputs to different stages of a row address register 207-40 and a column address register 207-41. ~lso, as seen from Figure 2, this section receives inputs from the circuits of block 207-6 which are applied to different stages of a refresh address register 207-42 and a column address register 207-43. The enabling gate input terminals of registers 207-40 and 207-41 are connected to receive a memory busy signal MEMBUZ010 from section 204. The enabling gate input terminals ~f registers 207-42 and 207-43 are connected to a +5 volts source. The OC input terminal of row address register 207-40 i5 connected to receive a timing signal MRASCT000 generated by AND gate 207-44, inverter circuit 207-46 and NAND gate 207-47 in response to signals INITMM000, REFCOM000 and MCRSTT010. The OC input terminal of column address register 207-41 is connected to receive a timing signal MC~SCT000 generated by NAND gate 207-48 and NAND
gate 207-50 in response to signals INTREF000 and MCASTT010. The signal INTREF000 is generated by series connected AND gates 207-44 and 207-48 which receive signals INITMM000, REFCOM000 and ALPCNT000. The OC input 36~

terminal of refresh address register 207-42 is connected to receive a control signal MREFCT000 generated by NAND
gate 207-49, NAND gate 207-51 and inverter circuit 207-45, in response to signals INTREF000, MCASTT010, MCASTTO10 and IN ITALl 10 .

Each of the address registers 207-40 through 207-43 are constructed from D type transparent latch circuits such as those designated as SN74S373 previously discussed.
As seen from Figure 2, the different address output terminals of the registers of each set are connected in common in a wired OR arrangement for enabling the multiplexing of these address signals. As previously described, such multiplexing is accomplished by controlling the state of the signals applied to the output control (OC) input terminals of the registers 207-40 through 207-43.

More specifically, the output control (OC) terminals enable so-called tristate operation which are controlled by the circuits 207-44 through 207-51. When each of the signals MRASCTOOO, MCASCT000, MREFCT000 and MWRTCT000 is in a binary ONE state, this inhibits any address signals from being applied at the Q output terminals of that reg-ister. As mentioned, this operation is independent of the latching action of the register flip-flops.

~ ~83~

Additionally, section 207-4 includes a 4-bit binary full adder circuit 207-54, conventional in design. The adder circuit 207-54 is connected to increment by one, the low order address bits 20 through 17. In greater detail, the input terminal Al-A8 receive signals MADD00010 through MADD03010. Binary ZERO signals are applied to input terminals Bl-B8. An AND gate 207-56 generates a carry in signal MADDUC010 as a function of the states of the least significant address signals LSAD22210 and LSAD21210, sig-nal INTREF000 and timing signal DLY060010.

The incremented output signals MADD00111 through MADD03111 appearing at adder sum terminals Sl-S8 are applied via address buffer circuits 210-26 to the even stack RAM chips of Figure 7. The same is true of signals MADD0410 through MADD07010. The odd stack RAM chips of Figure 7 are connected to receive the address signals MADD0010 through MADD07010 via address buffer circuits 210-46.

! ~#38~

Section 207-6 The refresh and initialize address register input section 207-6 includes the refresh cour,ter and write address counter circuits which generate the address values applied to the refresh and write address registers of sec-tion 207-4. As shown, the refresh counter circuits include two series connected binary counters 207-60 and 207-61, each constructed from 74LS393 type circuit chips.
Counter 207-60 is connected to receive a clocking signal 10 RADDUC000 which is generated by an inverter circuit 207-67, NOR gate 207-66 and AND gates 207-65 and 207-68 in response to signals ALPHUC010, INITMM100, REFCOM000 and MCASTT010. ~oth counters receive a clearing signal MYCLRR010 from section 212.

The write counter circuits also include two series connected binary counters 207-62 and 207-63 which are driven by signal REFAD8010 from the refresh counter circuits. Both counters receive a clearing signal MYCLRR110 generated by a NAND gate 207-69 in response to signals MYCLRR000 and PWONLL010, The circuits further include a D-t~pe flip-flop 207-71 which serves as an extra stage of counter 207-63.
The flip-flop 207-71 is connected to receive the comple-ment signal WRITA7100 of most significant write address ~ 16~36~

bit signal WRITA7010 from an inverter circuit 207-72.
Initially, when signal WRITA7010 is a binary ZERO, signal WRITA7100 is a binary ONE. Upon power-up, the D-type flip-flop 207-71 is cleared by signal MYCLRR100. When signal WRITA7010 switches to a binary ONE at the end of a first pass, signal WRITA7100 .switches from a binary ONE to a binar~ ZERO which has no effect on the state of flip-flop 207-71. Upon completion of a second pass, signal WRITA7010 switches back to a binary ZERO which causes sig-nal WRITA7100 to switch flip-flop 207-71 from a binary ZERO to a binar~ ONE. At this time, signal MADROL000 switches from a binary ONE to a hinary ZERO. The signal MADROL000 is applied to section 212 and is used to signal the completion of the initialization operation. The flip-flop 207-71 is enabled for operation by signal PWONLL010 and a +5 volt signal which are applied to the preset and D
input terminals, respectively. Also, an NAND gate 207-70 applies a signal MYCLRR100 to the clear input terminal which is generated in response to signal PWONLL300 and PWONLL010 from section 212.

As seen from Figure 2, section 207-6 includes a further binary counter 207-64. This counter also receives signal WRITA7010 from write address counter ~07-63. It receives clearing signal MYCLRR110 from NAND gate 207-69.

As explained herein, this counter supplements the existing 83~

--~o--refresh and initialization circuits and forms a part of the soft error rewrite control circuits of the present invention as explained herein.

; . . .

~ .~B836~

Read/Write Control Section 208 A portion of the circuits of section 208 is shown in greater detail in Figure 5. As mentioned, the section 208 includes a register 208-10 and circuits 208-12 through 208 45. The register 208-10 is a two-stage D-type flip-flop register for storing signal BSWRIT110 which is repre-sentative of a read/write command and signal BSYELO110 which is representative of a bus single bit error condi-tion. These signals are latched when signal MYACKR010 from section 211 switches to a binary ONE. When any one of the signals REFCOM000, INITMM00 or BSMCLR000 switches to a binary ZERO, an AND ga~e 208-12 forces signal CLRMOD000 to a binary ONE which clears register 208-10 to a binary ZERO state.

The write mode signal LSWRI~010 and error condition signal LSYEL0010 are applied to section 211. The read mode signal READMM010 is applied to an AND gate 208-14 which also receives an initialize signal INITAL000 from section 214.

The AND gate 208-14 in response to a read command (i~e., signal READMM010 is a binary ONE) when the system is not being initialized or is carrying out a-soft error rewrite cycle operation (i.e., signal INITAL000 is a bina-ry ONE) forces signal READMI010 to a binary ONE. When 3 ~ ~

signal READMI010 is a binary ONE, this causes a NOR gate 208-40 to force a read command signal READCM000 to a bina-ry ZERO. An AND gate 208-42 in response to signal READCM000 forces signal READCM100 to a binary ZERO. A
pair of AND gates 208-23 and 208-25 force signals MEREAD010 and MOREAD010 to binary ZEROS. These signals are applied to the read/write control lines of the even and odd stack units 210-20 and 210-40. However, the signals are inverted by circuits included with units 210-20 and 210-40 as shown in Figure 7 before being applied to the chips which comprise such units.

Another one of the input~ signals to NOR gate 208-40 is partial write signal PARTWT010. As discussed in U.S.
Patent No. 4,185,323, there are certain types of memory operations such as byte write and initialize operations which require two cycles of operation. The same is true for rewrite cycIes of opexation. As mentioned, the case of an initialize or a rewrite operation, signal INITAL000 is forced to a binary ZERO. This is effective to override the command applied to the bus. The read/write command signals MEREAD010 and MOREAD010 applied to the stack units 210-20 and 210-40 are generated as a function of signal PARTWT010. Signal PARTWT010 when forced to a binary ONE
remains a binary ONE until the end of the first cycle and 25 initiates a second cycle operation during which another 1 ~ ~83~

set of timing signals identical to the first are generated b~ the circuits of section 204. During the first cycle, the read/write command signals are forced to binary ZEROS
and during the second cycle, the signals are forced to binary ONES. The signal E'ARTWT010 is generated by a D-type flip-flop 208-16 with associated input circuits 208-17 through 208-26. The flip-flop 208 16 is enabled for switching when signal PWTSET000 applied to preset input terminal is forced to a binary ZERO by AND gates 208-17, 208-26, 208-27 and 208-28, in addition to NAND

gates 208-18, 208-19 and 208-20 in response to refresh command signal REFCO~110, initialize signal INITMM010, timing signal MPUhSE010, byte write signals BYWRIT100 and BYWRIT200 and rewrite phase 2 signal ALPHA2000. This enables flip-flop 208-16 to switch to a binary ONE. The flip-flop 208-16 switches to a binary ZERO state in response to signal DLYW02000 being applied to the clock input terminal via an inverter circuit 208-21. The +5 volts signal applied to the clear input terminal of flip-flop 206-18 inhibits resetting. In the same manner, as described above, partial write signal PARTWT010 when forced to a binary ONE initiates a read cycle of operation prior to initiating the write cycle of operation req~ired for the execution of the above mentioned operations in addition to each soft error rewrite control operation of 1 1~836~

the present invention as explained herein. As seen from Figure l, partial write signal PARTWT010 is applied to the G input terminals of the right most sections of registers 206~8 and 206-10. Signal PARTWT010 when a binary ONE
enables the storage of the output signals from EDAC
circuits 206-12 and 206-14.

The other signalc MEMBUZ000 and REFCOMl10 applied to NOR gate 208-40 are forced to binary ONES prior to the start of a memory cycle of operation and during a refresh cycle respectively. It will be noted from Figure 5 that during a write cycle of operation when signal WRITCT000 is forced to a binary ZERO by the circuits of section 204, signal WRITCTl10 generated by an inverter circuit 208-15 causes AND gate 208-42 to switch signal READCMl00 to a binary ONE. This in turn causes AND gates 208-23 and 208-24 to force signals 1~EREAD010 and MOREAD01~ to binary ONES indicating that the stack units 210-20 and 210-40 are to perform a write cycle of operation. At this time, a power on signal PW5ASD000 from section 212 is normally a 20 binary ONE while abort write signals EWRITA000 and OWRITA000 in the absence of error conditions are binary ONES.

As seen from Figure 5, the signals EWRITA000 and OWRITA000 are received from flip-flops 208-44 and 208-45.

~ l B836~

These flip-flops receive as inputs signals MDIEWE010 and MDIOWE010 from EDAC circuits 206-12 and 206-14. The states of these sisnals are stored in the flip-flops 208-44 and 208-45 when signal PARTWT010 switches from a binary ONE to a binary ZERO. The flip-flops 208-44 and 208-45 are cleared to ZEROS via a N3R gate 208-46 when the memory is not busy (i.e., signal MEMBUZ000 is a binary ONE) or is cleared (i.e., signal BSMCLR210 is a binary ONE).

1 16836~

Memory Uni-ts 210-20 and 210-40 - Figure 7 As previously discussed, the even word and odd word stacks of blocks 210-20 and 210-40 are shown in greater detail in Figure

7. These stacks include four rows of 22 64K X l-bit R~ chips as shown. Each 64K chip includes two 32,768 bit storage arrays.
Each array is organized into a 128 row by 256 column matrix and connects to a set of 256 sense amplifiers. It will be appreciated that other 64K chip organizations may also be utilized. The chips and associated gating circuits are mounted on a daughter board.
Each daughter board includes 2 inverters (e.g. 210-203, 210-207) which are connected to receive a corresponding one of the read/
write command signals from section 208 and four, 2 input NAND
gates (e.g. 210-200 through 210-206 and 210-400 through 210-406) which are connected to receive the row and column timing signals from section 204 and the row decode signals from section 207.
Only those chip terminals pertinent to an understanding of the present invention are shown. The remaining terminals, not shown, are connected in a conventional manner. For further information, reference may be made to United States Patent No. 4,296,467, issued on October 20, 1981, entitled "Rotating Chip Selection Technique and Apparatus", invented by Chester M. Nibby, Jr. and William Panepinto, Jr. and assigned to the same assignee as named herein.

~ ~B3S~

Figure 6 shows in greater detail, the initialize log-ic circuits of section 212. As shown, the circuits include a power on flip-flop 212-1, a power on register flip-flop 212-12, an initialize mode flip-flop 212-1~ and a clear flip-flop 212-16. All of the flip-flops are D-type flip-flops. The power on flip-flop 212-1 receives a bus power on signal BSPWON010 at its clock input termi-nal via a series connected resistor 212 2. A +5 volt sig-nal PWONRC010 is applied to clear input terminals of the flip-flops 212-1 and 212-12 via a series connected resis-tor 212-4 when power is applied. A resistor-capacitor filter network including resistor 212-6 and capacitor 212-8 connect in parallel to the clear input terminal.

The binary ONE output signal PWONLL010 is applied to the input of a delay circuit 212-10 constructed of 6 series connected inverter circuits. The output signal PWONLL610 generated by delay circuit 212-10 is applied to the D input terminal of flip-flop 212-12. When signal PWONLL610 is forced to a binary ONE following the switching of signal PWONLL010 to a binary ONE, flip-flop 212-12 switches to a binary ONE state on the positive going edge of signal REFCOM210. The clear flip flop 212-16 switches signal MYCLRR010 to a binary ONE in 1 ~836~
'~
.~9 ~

response to signals MYPWON010 and REFCOM210. The binary ONE output signal MYPWON010 of flip-flop 212-12 is applied to the clock input terminals of initialize mode flip-flop 212-14 and clear flip-flop 212-16. The change in state in signal MYPWON010 switches fl ip-flops 212-14 and 212-16 to binary ONE states. REFCOM210 resets flip-flop 212-16 to a binary ZERO.

The binary ONE and binary ZERO outputs from these flip-flops are applied to the circuits of sections 205, 207 and 209 via inverter circuits 212-18, 212-20 and 212-22 together with signal PWONLL300 generated by delay circuit 212-10. The initialiæe mode flip-flop 212-16 switches to a binary ZERO when the circuits of section 207 force signal MADROL000 ~o a binary ZERO.

3 ~ ~

SOFT ERROR REWRITE CONTROL SECTIO~ 214 Figure 4 shows in greater detail, the soft error rewrite control circuits of the preferred embodiment of the present invention. The section 214 includes a counter section 214-1 and a cycle phase control circuit section 214-2. The section 214-1 establishes the cycle timing for performing a soft error rewrite cycle operation enabling every location in memory to be addressed. Section 214-2 generates the re~uired control signals which define the different phases of operation.

In greater detail, section 214-1 includes three series connected binary counters 214-10 through 214-14, a NAND gate 214-16 and an inverter circuit 214-18. The counters 214-10 through 214-14 constructed from type 74LS393 chips are incremented by one at the end of each refresh cycle in response to signal REFCOM100. This synchronizes the counter operations with the refresh counter circuits. The 11 outputs from the counter stages are applied to NAND gate 214-16. This gate monitors the counts generated by the counters and forces a command sig-nal ALPCOM000 to a binary ZERO each time the counters reach a predetermined count. This predetermi~ed count is selected to have a value which clears out soft errors from memory at a rate which provides a minimum of interference 36~

with normal memory operations. The rate is such that after every 2,047 refresh cycles or counts, a rewrite cycle is performed. Therefore, the 512 thousand memory locations can be cleared from the effects of alpha parti-cle contamination or other noise signal disturbances within a two-hour period.

As seen from Figure 4, the inverter circuit 214-18 inverts the command signal ALPCOM000 to generate a set signal ALPSET110. This signal is applied to the clear input terminals of binary counters 214-10 through 214-14 and to an input NAND gate 214-21 of section 214-2. When signal ALPSET110 is forced to a binary ONE, it clears counters 214-10 through 214-14 to ZEROS for starting a new count.

As seen from Figure 4, section 214-2 includes three phase control D-type flip-flops 214-24 through 214-26 which connect in series, a stop cycle D-t~pe flip-flop 214-27 and associated input and output gate and inverter circuits 214-30 through 214-36 connected as shown. Each of the flip-flops 214-24 through 214-26 are cleared to binary ZEROS in response to a power on signal PWONLL010 generated by the circuits of section 212 (i.e., when sig-nal PWONLL010 is a binary ZERO). The stop cycle flip-flop 3~4 214-27 is reset to a binary ZERO state when a hus clear signal BSMCLR200 is forced to a binary ZERO.

When an initialize operation is not being performed (i.e., signal INITMM100 is a binary ONE), NAND gate 214-21 in response to signal ALPSET:L10 being forced to a binary ONE, switches the phase 1 flip-flop 214-24 to a binary ONE. The flip-flop 214-24 when in a binary ONE state defines the refresh portion of the rewrite cycle. The binary ZERO output signal ALPHA1000 is applied to the pre-set terminal of stop cycle flip-flop 214-27. This switches flip-flop 214-27 to a binary ONE state.

The memory busy signal MEMBUZ000 is switched to a binary ZERO in response to a refresh command ~i.e., when signal RE~COM110 switches to a binary ONE). At the end of the refresh cycle when the memory busy signal switches from a binary ZERO to a binary ONE, signal ALPHA1010 causes the phase 2 flip-flop 214-25 to switch to a binary ONE. This forces signal ALPHA2000 to switch to a binary ZERO which in turn resets the phase 1 flip-flop 214-24 to 2a a binary ZERO state via AND gate 214-30. The flip-flop 214-25 when in a binary ONE state defines the read portio~
of the rewrite cycle sequence.

The binary ONE output signal ALPHA2010 is applied to the D input terminal of the phase ~ flip-flop 214-26.

3 ~ ~

When the RRESET010 pulse signal is generated by the circuits of section 204 at the end of the read cycle of operation, the trailing edge of the pulse signal switches flip-flop 214-26 to a binary ONE state. The binary ZERO
output signal ALPHA3000 upon being switched to a binary ZERO resets phase 2 flip-flop 214-25 to a binary ZERO via AND gate 214-31. The binary ONE state of the phase 3 flip-flop 214-26 defines the write portion of the rewrite cycle. At the end of the write cycle of operation, RRSET010 pulse signal switches the phase 3 flip-flop 214-26 to a binary ZERO state since the signal ALPHA2010 is a binar~ ZERO at this time.

When either the phase 2 flip-flop 214-25 or phase 3 flip-flop 214-26 is a binary ONE, the signal ALPHA2000 or signal ALPHA3000 applied to AND gate 214-32 forces signal ALPCNT000 to a binary ZERO. The signal ALPCNT000 when forced to a binary ZERO conditions the circuits of section 207 to select the address signals from the rewrite counter circuit for decoding during these portions of the rewrite cycle sequence. Additionally, signal ALPCNT000 causes AND
gate 214-33 to force signal INITAL000 to a binary ZERO
which conditions the circuits of section 208 so as ~o override bus commands during the read and write portions of a rewrite cycle.

~ ~6~3 ,j"~

Additionally, signals INITMM100 and R~ADCM000 when binary ONES cause an AND gate 210-38 to force signal INITOR000 to a binary ONE. This signal together with the complement signal ALPCNT010 generated by an inverter cir-cuit 214-35 when forced to binary ONES, condition a NAND
gate 214-39 to force signal MDRELB000 to a binary ZERO.
As seen from Figure 1, signal MDRELB000 is applied to the OC terminals of the right sections of registers 206-8 and 206-10. When a binary ZERO, signal MDRELB000 enables the contents of these registers to be applied to their output terminals.

It will also be noted that when the phase 3 flip-flop 214-26 is reset to a binary ZERO, the switching of signal ALPHA3000 from a binary ZERO to a binar~T ONE resets the stop cycle flip-flop 214-27 to a binary ZERO. This causes a change in state of up count signal ALPHUC010 generated by OR gate 214-34 which in turn increments by one the counter circuits of section 207. OR gate 214-34 also generates an increment signal at the end of a refresh cycle in response to signal REFCOM110.

:

~ 1~836~

~ES _IPTION OF OPERATION

With reference to Figures 1-7, the operation of the preferred embodiment of the present invention will now be described with particular reference to the timi~g diagrams of Figures 8a through 8c. To appreciate the operation of the present invention, it is helpful to describe how the refresh and initialize circuits carry out refresh and initialize operations.

Before discussing an example of operation, reference is first made to Figure 9. Figure 9 illustrates the for-mat of the memory addresses applied to the memory subsystem as part of each memory read or write request.
The high orderjmost significant bit positions are coded to identify the memory module/controller to process the request. Address bit 4 is used to select which 256K half (i.e., upper or lower half~ of controller memory is being accessed. These address bits are processed by the circuits of controller 200 and are not provided to the RAM
chips.

Address bits 5-20 specify the address of the 22-bit storage location within the RAM chips being addressed. As explained in greater detail herein, these 16 address bits are multiplexed into 8 address inputs and applied via the address buffer circuits of blocks 210-26 and 210-46 to the 3~

address inp~t terminals A0-A7 of the RAM chips of Figure 7.

The least significant address bits 21-22 are coded to select which row of RAM chips are being addressed. As discussed herein, these bits are decoded and used to gen-erate a pair of row address strobe (RAS) signals which latch the 8-bit row addresses into the desired row of RAM
chips within each memory stack.

Figure 8a illustrates diagramatically the different timing signals involved during the execution of a refresh cycle of operation by the refresh circuits of section 205 of Figure 1. As previously discussed, these circuits take the form of the circuits disclosed in ~.S. Patent No.
4,185,323. The circuits 205 provide a means of substituting a refresh cycle of operation. This occurs when the controller 200 is not in the process of executing a memory cycle, not anticipating any memory cycle or not requesting a cycle. It will be appreciated that refresh cycles are distributed over a four millisecond interval specified for refreshing the total numbex of rows/columns of the memory system. In the case of a 64K MOS chip, 256 cycles are required to refresh all of the cells of the entire chip. In the present system, a refresh cycle of operation is started every 15 microseconds hy the 30 nano-~ ~6836~

" ~
,.~

second width pulse signal CORREF000. This signal, in turn, causes the generation of a 150 nanosecond fine refresh timing pulse signal FINREF000. The signal FINREF000 causes the switching of a refresh co~mand flip-flop to a binary ONE. As seen from ~igure 8a, thi.sresults in signal REFCOM010 being forced to a binary ONE.
Thus, the complement of the refresh command signal REFCOM000 switches to a binary ZERO.

Referring to Figure 2, it is seen that signal REFCOM000 causes NAND gate 207-49 to force refresh signal MREFCT000 to a binary ZERO. When the binary ZERO signal is applied to the output control (OC) terminal of refresh address register 207-42, this causes the register 207-42 to apply the refresh address contents to the odd and even stack units 210-20 and 210-40 of Figure 7. Sim~ltaneous-ly, refresh command signal REFCOM100 conditions the timing cir~uits 204 of Figure 3 for generating row address timing signals MRASTE010 and MRAST0010. At this time, signal REFCOM100 effectively overrides the state of least signif-icant address bit LSAD22 Also, from Figure 2, it is seen tha~ signal REFCOM100 while a binary ZERO causes AND gate 207-39 to force signal OVRDEC000 to a binary ZERO. This overrides all of the decoded row strobe signals so that all of the row address strobe signals DRAST0010 through DRAST7010 are forced to binary ONES. This loads the 1 1~836Q

~58--refresh address contents into each of the rows of RAM
chips of Figure 7.

The result is that a row within each row of RAM chips included within the units 210-20 and 210-40 of Figure 7 are refreshed as a consequence of a read operation being performed on the addressed 8 rows of RAM chip locations.
That is, the signals MEREAD010 and MOREAD010 from section 208 are hinary 2EROS which causes the RAM chips of Figure 7 to perform a read cycle of operation. That is, refresh command signal REFCOM110 caused the circuits of Figure 5 to maintain signals MEREAD010 and MOR~AD010 at hinary ZEROS. Prior to that, signal MEMBUZ000 was a binary ONE
which forced signals MEREAD010 and MOREAD010 to binary ZEROS.

It will also be noted from Figure 3 that refresh com-mand signal REFCOM100 inhibits the generation of the CAS
timing signal and signals MDOECT000 and MDOOCT000. This prevents information to be written into locations within the stack units 210-20 and 210-40 as well as the read out of information to the output registers 206-8 and 206-10 of Figure 1.

The end of the refresh cycle of operation is signalled by the leading e~ge of pulse signal REFRES000 which resets the refresh command flip-~lop to a binary ~6836 .~

ZERO. This, in turn, forces signal REFCOM010 to a binary ZERO. At the trailing edge of signal REFCOM010, the AND
gate 207-68 of Figure 2 forces signal RADDUC000 from a binary ZERO to a binary ONE which, in turn, increments by one, the address contents of refresh counter 207-60. This address change is transferred to refresh address register 207-42 as shown in Figure 8a by the change in signal MADDXX.

The 8-bit counter 207-62 is added to refresh counter 207-60 which enables controller 200 to operate in an initialize mode. The counter 207-62 furnishes the CAS
addresses required for writing ZEROS into the addressed storage locations when the controller 200 is in an initialize mode of operation (i.e., signal INITMM010 is a binary ONE).

Figure 8b illustrates the different signals involved during the execution of an initialize cycle of operation b~ the circuits of section 212 and write address counter circuits of Figure 2. As shown, when power is turned on, this produces a bus power on transition which resul~s in signal BSPWON010 switching to a binary ONE. From Figure 6, it is seen that this change of state is latched in flip-flop 212-1. That is, flip-flop 212-1 switches signal PWONLL010 to a binary ONE. The signal PWONLL010 is . ~.

J 18~3 j"~

delayed b~ circuit 212-10 and then switches flip-flop 212-10 to a binary ONE. As seen from Figure 8b, the initialize mode flip-flop 212-14 switches to a binary ONE
in response to refresh command signal REFCOM110. Prior to 5that, signal MADROL000 from flip-flop 207-71 of Figure 2 was switched to a binary ONE by signal P~ONLL300. This cleared the initialize mode flip-flop 212-1~ to a binary ZERO state.

The refresh command signal REFCOM110 is generated in the manner previously described. It will also be noted that the circuits of section 208 of Figure 5 switch par-tial write signal PARTWT010 to a binary ONE. That is, AND
gate 208-18 is conditioned by signals REFCOM110 and INITMM010 to force signal PWTSET200 to a binary ONE. This 15enables flip-flop 208-16 to switch to a binary ONE upon the occurrence of timing signal DLY~02000.

Signal PARTWT010 when a binary ONE causes AND gate 208-42 to hold signals MEREAD010 and MOREAD010 at binary ZEROS enabling a refresh operation to be performe~ upon the eight rows of storage locations during the first (1) Of two cycles shown in Figure 8b generated by the timing generator circuits (not shown) of section 204. That is, refresh command signal REFCOM110 when switched to a binary ONE causes the timing generator circuits to initiate a 1 ~683~

series of timing pulses of a first cycle. This results in signal DLYINN0010 being switched to a hinary ONE. Signal PARTWT010 remains a binary ONE and at the end of the first cycle, signal DLYINN010 is switched to a binary ONE. This causes another set of timing signals identical to the first to be generated. Prior to the switching of signal PARTWT010 to a hinary ONE, the signals MEREAD010 and MOREAD010 were at binary ZEROS as a consequence of signals MEMBUZ000 and REFCOM010 being forced to binary ONES.

As described above, during the refresh cycle of operation, the refresh command signal causes the refresh address register 207-42 to apply the refresh address contents to the odd and even stack units 210-20 and 210-40, the timing circuits 204 to generate row address timing signals MRASTE010 and MRAST0010 and force all of the decoded row strobe signals to binary ONES. The result, as mentioned above, causes the refreshing of eight rows of storage locations within the RAM chips of Figure 7.

Since the controller 200 is in an initialize mode, signal ~NITMM100 inhibits AND gate 207-68 of Figure 2 from forcing re~resh increment signal RADDUC000 to a binary ONE
at the end of the refresh cycle. Accordingly, the I ~6~36~
(;/

contents of the refresh address counter 207-60 and 207-61 remain unchanged.

As seen from Figure 8b, a next cycle is entered during which both RAS and CAS timing signals are generated which enables binary ZERO information to be written into a storaye location within each of the eight rows of the RAM
chips of Figure 7. That is, from Figure 3, it is seen that when initialize signal INITMMl00 is forced to a bina-ry ZERO, this enables the generation of timing signals MRASTE010 and MRAST0010. As seen from Figure~ 8b and 3, the timing circuits 204 follow this with the generation of signal MCASTS010 sinçe at this time signal REFCOM100 is a binary ONE. In the manner previously described, the refresh address contents of refresh address register 42 are applied to the odd and even stack units 210-20 and 210-40 as a consequence of signal INITMM000 forcing signal MREFCT000 to a binary ZERO state. The row address signals are stored in each of the rows of RAM chips of Figure 7 in response to signals MRASTE010 and MRAST0010.

From Figure 2, it is seen that the power on signal PWONLL010 was forced to a binary ONE, this caused the clearing of the write counter 207-62 and 207-63 to binary ZEROS. The contents of the write counter are, in turn, loaded into the write address register 207-43. The NAND

" ! 1683~

-6~

gate 207-51 of Figure 2, in response to signals MCASTT010 and INITAL110, forces signal MWRTCT000 to a binary ZERO.
This causes the write address register 207-43 to apply its column address contents to the stack units 210-20 and 210-g0. Since signal INTREF0¢0 was forced to a binary ZERO by signal INITMM000, the adder 207-54 applies the column address contents without modification to even stack unit 210-20.

It is seen from Figure 8b that when partial write signal PARTWT010 switches to a binary ZERO, this, in turn, switches the read command signal READCM000 to a binary ONE. As seen from Figure 5, the flip-flop 208-16 switches to a binary ZERO in response to timing signal DLY400010 following the switching of read command signal REFCOMM110 to a binary ZERO. The signal READCM000 conditions AND
gate 208-~2 to force signal READCM100 to a binary ZERO in response ~o write timing signal WRITCT000 from the timing generator circuits 204. This, in turn, causes AND gates 208-23 and 208-25 to force signals MEREAD010 and MOREAD010 to binary ZEROS. Accordingly, the RAM chips of Figure 7 are conditioned to perform a write cycle of operation upon the eight simultaneously selected chip locations during which binary ZEXOS, loaded into the even and odd data registers 206-8 and 206-10, are written therein. That is, 25 the initialize slgnal INITMM310 from section 212, when ~ ~6~3S~

~4~

forced to a binary ONE upon the setting of th~ initialize mode flip-flop 212-14 of Figure 6, inhibits the enabling of data-in MUXs 209-4. The result is that binary ZEROS
loaded into the leftmost sections of registers 206-8 and 206-10 are applied as inputs to stack units 210-20 and 210-~0 in response to signal MDOTSC010. At this time, signals MDOTSC000 and MDRELB000 are binary ONES which inhibit the middle and rightmost sections of registers 206-8 and 206-10 from applying signals to their output terminals.

At the end of the write cycle, as shown in Figure 8b, signal MCASTT010 switches to a binary ZERO. This causes AND gate 207-68 of Figure 2 to force signal WTCAST010 to.a binary ZERO which, in turn, forces signal RADD~C000 from a binary ONE to a binary ZERO. This causes the serles connected refresh and write counter circuits 207-Ç0 through 207-63 to be incremented by a count of one. At the beginning of the next 15 microsecond interval signalled by pulse CORREF000, the sequence of operations illustrated in Figure 8b is repeated using the next address signals specified by the contents of the refresh and write counter circuits of Figure 2.

By repeating the above operationsr every decoded location of the units 210-20 and 210-40 is initialized to ~ ~6~3~

--6~

ZEROS. Since the decodes are overridden, binary ZEROS are written into an addressed location in each of the eight rows of 64K R~M chips simu:Ltaneousl}~ which reduces the amount of time required for initializing the memory subsystem.

The completion of the ini.tialize operation is signalled by the switching of flip-flop 207-71 of Figure 2 to a binary ONE. This forces signal MADROL000 to a binary ZERO which, in turn, clears initialize mode flip-flop 212-14 to a binary ZERO state. As seen from Figure 2, the flip-flop 207-71 switches to a binary ONE when the write address bit signal WRITAT100 switches from a binary ZERO
to a binar~T ONE state (i.e., positive going transition).
This occurs when bit signal WRITA7010 switches from a binar~ ONE to a binary ZERO indicating that the last address location has been written.

From the above, it is seen how ever}T decoded location is addressed and initialized to ZEROS. In order to be able to address every location, instead of overriding the 2Q decode signals derived from the address signals applied thereto, counter 207-64 is connected in series with the refresh and write address counters 207-60 through 207-63 of Figure 2. This counter generates the address bits LSAD21 and LSADX6 which are used to address the same loca-J ~3~

-6~

tion within both units 210-20 and 210-40, in accordance with the principles of the present invention as explained herein.

Figure 8c is used to explain the operation of the present invention in carrying out a soft error rewrite cycle of operation. This operation is provided by extending the refresh and in:itialize cycles of operation so a to minimize the amount of logic circuits added to the controller 200.

10Where, as the initialize mode occurs only during powering up the controller, a soft error rewrite cycle occurs in synchronism with a refresh cycle of operation.
The frequency of occurrence of the cycle is established by signal ALPCOM000. When this signal is forced to a binary 15ZERO by an all ONES input from counters 214-10, 214-12 and 214-14, two things occur. One is that the counters 214-10, 214-12 and 214-14 are reset to start counting from ZERO by signal ALPSET110 heing forced to a binary ONE.
The other is that the phase 1 flip-flop 214-24 i9 set to a binary ONE.

As seen from Figure 8c, the setting of the phase 1 flip-flop 214-24 to a binary ONE causes the stop cycle flip-flop 214-27 to switch to a binary ONE. For the purposes of the present invention, this signal indicates ~ .

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the occurrence of a soft error rewrite cycle and its dura-tion.

The phase 1 flip-flop 214 24 defines the period or interval d~ring which a normal refresh cycle takes place.
This cycle is carried out in the manner discussed with reference to Figure 8a. tlpon the completion of the refresh cycle, the memory busy signal MEMBUZ000 is forced to a binary ONE. This switches the phase 2 flip-flop 214-25 to a binary ONE. This causes signal ALPHA2000 to reset phase 1 flip-flop 214-24 to a hinary ZERO.
Normally, as seen from Figure 8c, the refresh and write counter circuits are incremented at the end of a refresh cycle. However, since a soft error rewrite cycle is being performed at this time, the setting of the stop cycle flip-flop 214-27 forces up count signal ALPHUC010 to a binary ONE. This, in turn, causes the A~D gate 207-65 of Figure 2 to force signal INITUC000 to a binary ONE causing signal RADDUC000 to be forced to a binary ONE. This prevents the incrementing of the refresh and write counters at this time.

As seen from Figure 8c, the setting of phase 2 flip-flop 214-24 causes partial write flip-flop 208-16 of Fig ure 5 to switch to a binary ONE. That is, signal ALPHA2000, when switched to a binary ZERO, forces signal ~ ~6~3~4 C"/~

BYWRIT010 to a binary ONE. NAND gate 208-19 forces signal PWTSET100 to a binary ZERO upon the occurrence of signal MPULSE010. This forces signal PWTSET000 to a binary ZERO
which enables flip-flop 208-16 to switch to a binary ONE
state. The setting of the partial write flip-flop 208-16 signifies that the timing generator circ~its 204 will gen-erate two sequences of timing signals, one for a read cycle followed by a write cycle. When the flip-flop 208-16 switches to a binary ONE, it causes read command signals MEREAD010 and MOREAD010 to be forced to binary ZEROS.

.~s seen from Figure 4, signal ALP~NT000 is switched to a binary ZERO when the phase 2 flip-flop 214-25 switched to a binary ONE. This signal causes the multiplexer circuit 207-14 of Figure 2 to select as a source of address signals, the signals ARAD21010 and ARADX6010 from the counter 207-64. As seen from Figure 2, least significant address bit LSAD22 is forced to a binary ZERO. This effectively eliminates bit LSAD22 causing a double word operation beginning with the even stack units 210-20 so as to take advantage of the address decode arrangement of Figure 2. Bits 21 and X6 spe~cify the contents of which word locations in stack units 210-20 and 210-40 are to be read out to data registers 206-8 and 206-10. These bits together with bit 22 are decoded by 3 6 ~

decoder circuits 207-20 and 207-31 which force the appro-priate decode row address strobe signals to binary ONES.

Also, signal ALPCNT010 is switched to a binary ONE
when phase 2 flip-~lop 214-25 is switched to a binary ONE.
This signal conditions the timing circuits 204 of Figure 3 so as to enahle the generation of timing signals for cycling both stack units 210-20 and 210-4Q during a read cycle of operation. That is, signal ALPCNT010 forces sig-nal RASINH010 tO a binary ZERO. This, in turn, causes 10 NAND gates 204-8 and 204-14 to force signals ERASIH000 and ORASIH000 to binary ONES which enables timing signals MRASTE010 and MRAST0010 to be applied to the even and odd stack units 210-20 and 210-40. Also, the AND gates 204-11 and 204-15 are conditioned to apply subsequently timing 15 signals MDOECT010 and MDOOCT010 to the even and odd registers 206-8 and 206-10.

The read operation is performed upon the pair of locations specified by the refresh and write address counters, in addition to counter 207-64. That is, in the manner previously described, the address contents of the refresh and write address counters 207-60 through 207-63 are fed into the refresh address and wri~e address registers 207-42 and 207-43, respectively.

1 1683~
G i As seen from Figure 2, signal ALPCNT000 enables the storage of the row address signals by causing AND gate 207-48 to force signal INTREF200 to a binary ZERO. This, in turn, causes NAND gate 207-49 to force signal MREFCT000 to a binary ZERO which enables the address contents of refresh address register 207-42 to be 2ppl ied to the odd and even stack units 210-20 and 210-40. The row address signals are stored in the RAM chips of Figure 7 in the pair of rows specified by the outputs from decoder circuits 207-20 and 207-31. As described previously, the address signals are stored in response to even and odd row address strobe signals MRASTE010 and MRASTO010 generated in response to row address timing signal MRASTT010.

In a similar fashion, the column address signals which correspond to the address contents of the write address register 207-43 are stored in all of the RAM
chips. More specifically, signal MCASTT010 from timing generator 204 and signal INITALllO cause NAND gate 207-51 of Figure 2 to force signal MWRTCT000 to a binar~ ZERO.
Th s conditions the write addxess register 207 43 to apply its address contents to the stack units 210-20 and 210-40.
These signals are stored in the RAM chips of Figure 7 in response to column address signal MCASTS010.

7~

The switching of phase 2 flip-flop 214-25 causes the switching of the partial write flip-flop 208-16 to a bina-ry ONE state. This defines the read operation of the cycle by forcing the signal READCM000 to a binary ZERO.
Signal READCM000 is a binary ZERO at this time which, in turn, causes signals MEREAD010 and MOREAD010 to be binary ZEROS. Therefore, the RAM chips of the selected pair of rows are conditioned to perform a read operation wherein their contents are read out into the even and odd data registers 206-8 and 206-10 which have been enabled hy signals MDOECT0010 and MDOOCT0010, respectively. At this time, read command signal READCM000 holds signal MDRELB000 at a binary ONE. This inhibits the contents of the right most section of registers 206-8 and 206-10 from being applied at the outputs thereof. Also, read command signal READCM000 causes the circuits 204 to force signal MDOTSC100 to a binary ZERO and signal MDOTSC010 to a bina-ry ONE. This inhibits the contents of the left most sections of registers 206-8 and 206-10 from being applied to the inputs thereof. At the same time, the read out word contents, stored in the middle sections of registers 206-8 and 206-10, are applied to EDAC circuits 206-12 and 206-14.

During the read cycle of operation, the words read out from the pair of locations are checked for errors by ~6836 ~/

the error detection circuits included within the ED~C
circuits 210-12 and 210-14. Any single bit errors located within the words are corrected by the error correction circuits included with the EDAC circuits 210-12 and 210-14. Since signal PARTWT010 is a binary ONE, the corrected words are loaded into the rightmost sections of registers and rewritten back into stack units 210-20 and 210-40 during the interval defined by the next occurrence of signal MCASTT010 of Figure 8c.

Where more than one error is detected to have occurred within a word, this causes one of the EDAC
circuits 206-12 and 206-14 to force signal MDIEWE010 or signal MDIOWE010 to a binary ONE state. This, in turn, sets the even abort write flip-flop 208-44 or odd abort write flip~flop 208-45 of Figure 5 to a binary ONE state - when partial write signal switches from a binary ZERO to a binary ONE state. As explained herein, this aborts the write operation thereby preserving the error status of the original information.

When the timing generator 204 generates signal RESET010, the phase 3 flip-flop 214-26 is conditioned by the binary ONE state of signal ALPHA2010 to switch to a binary ONE. As seen from Figure 8c, the phase 2 flip-flop 214-25 is reset to a binary ~ERO by AND gate 214-31 of 1 ~683~

Figure 4. The switching of the phase 3 flip-flop 214-26 initiates a second sequence of timing signals required for performing a write cycle of operation. Since signal ALPUC010 is still a binary ONE (i.e., the stop cycle flip-flop 214-27 is still a binary ONE, this inhibited the incrementing of the refresh, write and decode address counters 207-60 through 207-64 by signal RADDVC000.
Hence, the write operation is performed upon the same pair of locations within the stack units 210-20 and 210-40. In the manner just described, the same row and column address signals are caused to be stored in the RAM chips of the - two rows specified by the address bit signals ARAD21010 and ARADX6010.

Briefly, as seen from Figure 4, the states of signals ALPCNT000 and ALPCNT010 remain the same as a consequence of the phase 3 flip-flop 214-26 heing switched to a binary ONE. Accordingly, the row address contents of the xefresh address register 207-42 are applied to the stack units 210-20 and 210-40 and stored in the RAM chips of the same two rows addressed during the prior read cycle of operation in response to signal MRASTT010.

3B~

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In a similar fashion, the column address contents of write address register 207-43 are applied to the stack units 210-20 and 210-40 and stored in the RAM chips of Figure 7, in response to signal MCASTT010.

As seen from Figure 8c, during the write cycle, the timing generator circuits 204 repeat the generation of the same sequence of timing signals which cause the contents of the addressed pair of storage locations to be read out into registers 206-8 and 206-10. At this time, partial write signal PARTWT010 is a binary ZERO. That is, the partial write flip-flop 208-16 is reset to a binary ZERO
in response to timing signal DLYW0200 since at that time signal ALPHA2000 is a binary ONE.

Since read co~mand signal READCM000 and signal ALPCNT010 are binary ONES, this causes NAND gate 214-39 of Figure 4 to force signal MDRELB000 to a binary ZERO. This enables the right most sections of registers 206-8 and 206-10 containing the corrected word pair to apply its contents to the outputs thereof. At the same time, signals REA~CM000 and ALPCNT000 force signals MDOTSC100 and MDOTSC010 to binary ONES. This inhibits the left most and middle sections of registers 206-8 and 206-10 from applying signals at the outputs thereof during this inter-val.

.

! 1~83~l ~4 Accordingly, the contents of the pair of addressed storage locations previously read out into the right most sections of registers 206-8 and 206-10 are written into the addressed storage locations.

Accordingly, any single bit errors occurring within either one or both of the words read out will have been corrected utilizing the error detection and error correc-tion circuits included within the system. Thu~, any soft errors are eliminated from the pair of words accessed which, in turn, prevents such errors from turning into douhle errors which are not correctable.

However, when a double error condition is detected, the occurrence of the condition is stored and causes the write operation to be aborted. That is, in such lS instances, either signal EWRITA000 or signal OWRITA000 or both are forced to a binary ZERO. This, in turn, causes AND gate 208-23 or AND gate 208-25 to force a correspond-ing one of the signals MEREAD010 or MOREAD010 to a binary ZERO. This, in turn, inhibits the writing of the uncorrectable words into the corresponding one of the addressed pair of locations. As mentioned, this preserves the error condition within the uncorrectable word.

As seen from Figure 8c, the resetting of the phase 3 flip-flop 214-26 to a binary ZERO state causes the stop 1 ~.6B36~

~.~

cycle flip-flop 214-27 to reset to a binary ZERO. This signifies the end of the soft error rewrite cycle of operation. As previously discussed, the phase 3 flip-flop 214-26 is reset to a binary ZERO in response to signal RRESET010 from the timing circuits 204.

~hen the stop cycle flip-flop 214-27 resets, this causes OR gate 214-34 to switch the up count signal ALPHUC010 from a binary ONE to a binary ZERO. As seen from Figure 8c, this causes the read address and write address counters 207-60 through 207-63 in addition to the decode address counter 207-64 to be incremented by one.
That is, signal ALPHUC010 causes increment signal RADDUC000 to switch from a binary ONE to a binary ZERO.
This results in updating the counters at the end of the soft error rewrite cycle In accordance with the teachings of the present invention, the counters 214-10, 214-12 and 21~-14 continue to operate in synchronism with refresh cycles. Following the occurrence of another 2047 refresh cycles, NAND gate 214-16 again forces rewrite command signal ALPCOM000 to a binary ZERO signalling the start another soft error rewrite cycle. By synchronizing the counters on an odd count, which is one less than the maximum count of 2048 (i.e., 21 -1), this selects a sequence of address values 1 ~6836J4 ~G
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stored i~ the refresh, write and decode address counters 207-60 through 207-64 which select every location within stack units 210-20 and 210-40.

The above can be seen by considering an arrangement in which a 4-bit binary counter is used in place of counters 214-10, 214-12 and 214-14. In this arrangemellt, rewrite command signal is forced to a binary ZERO, every 15 counts (2L\-l) rather than 16 which is the maximum count ~2~).

By way of example, it is assumed that the word size of the memory is 32 and all counters are set to ZERO. To provide a 32 binary addressing capability, the refresh address counter is a 5-bit binary counter. It would gen-erate the following sequence of address values:

0,1,2,........ 12,13,14,........... 28,29,30,31, 0,1,2,..10,11,12,13,14,..25,26,27,28,29,...etc.

The count sequence defining the addresses of the locations defined by the 4-bit binary counter at which soft error rewrite cycles are initiated is as follows:

0,15,30,13,28,11,2~,9,24,7,22,5,20,3,18, 1,16,31,14,29,12,27,8,23,6,21,4,19,2,17,0.

~83~;
~i' From the above, it is seen that during a first pass of refresh counter addresses, a soft error rewrite cycle takes place at the location having address value 15. In a second pass (i.e., after the next 15 counts), a soft error rewrite cycle takes place at the location having address value 30. This continues as shown. By letting the counters free run and detecting each occurrence of a count of 15, a soft error rewrite cycle will be performed on every location in a non-sequential fashion.

In accordance with the teachings of the present invention, the present size for the rewrite counters 214-10, 214-12 and 214-14 was selected in order to mini-mize the interference with normal memory operations and still provide the necessary error protection.

From the above, it has been shown how the arrangement of the invention protects the memory system against alpha particle contamination and other system disturbances.
This is accomplished with a minimum amount of additional circuits.

It will be appreciated that man~ modification may be made to the apparatus of the present invention without departing from its teachings. For example, the number of stages of the rewrite control section counter may be expanded or reduced as required to minimize interference 1~836~1 /~
-7~-with normal memory opexations. If desired, the counter may be connected to receive programmed counts via the bus 10. That is, the counter could be loaded with a predetermined count which is decremented by one in response to each refresh command signal until a count is reached at which time a rewrite cycle is initiated and the counter is reset to the predetermined count.

Other changes may also be made to the rewrite control section s~ch as omittin~ the performance of a refresh cycle during each rewrite cycle. However, ~or ease of simplicity, the refresh cycle was included. Also, it will be obvious to those skilled in the art that the apparatus of the present invention may be used with different types of memory organiæations and MOS chips as well as different types of refresh circuits and error detection and correc-tion circuits.

While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the spirit of the invention as set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a correspondin~ use of other features.

What is claimed is:

Claims (40)

THE EMBODIMENT OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A semiconductor memory system comprising: a dynamic mem-ory including a number of addressable arrays of memory cells ar-ranged in a number of rows and columns and said arrays being organized into a number of storage locations; error detection and correction means coupled to said memory for detecting and correct-ing single bit errors in the contents of the cells read out from said memory during a memory cycle of operation; timing means for providing sequences of timing signals for performing said memory cycle of operation; refresh and write control means coupled to said timing means and to said memory, said refresh control means periodically generating refresh command signals in response to signals from said timing means, and including row and column ad-dress counter means; and, rewrite control means coupled to said refresh and write control means and to said timing means, said re-write control means including counter means operative after each occurrence of a predetermined number of refresh command signals to condition said timing means to generate a sequence of signals during a rewrite cycle of operation for performing read and write cycles of operations upon the cells within the rows and columns of one of said number of storage locations specified by said row and column address counter means for enabling the detection and correction of said single bit errors within said memory by said error detection and correction means at a predetermined rate there-by rendering said memory system less susceptible to soft errors.

2. The system according to claim 1 wherein said rewrite con-trol means includes decode circuit means coupled to said counter means, said decode circuit means being operative in response to signals from said counting means indicating said occurrence of said predetermined number of refresh command signals to generate a rewrite command signal for resetting said counter means and for initiating said rewrite cycle of operation.

3. The system of claim 2 wherein said decode circuit means is connected to said counting means to cause the generation of said rewrite command signal in accordance with a modulus which is one less than the maximum count value generated by said counter means.

4. The system of claim 3 wherein said counter means includes a number of stages and said modulus equals 2n -1 wherein n corres-ponds to said number of stages.

5. The system of claim 4 wherein n is selected to have a value for detecting and correcting any single bit errors within all of said cells of all of said number of storage locations in said memory and said predetermined rate is selected to minimize interference with normal memory operations.

6. The system of claim 5 wherein n equals 11, said modulus equals 2047 and said predetermined rate equals .03 seconds.

7. The system of claim 3 wherein said modulus is selected for generating said rewrite command signal when said refresh address counter means and said write counter means stores a different row address and column address respectively enabling all possible combinations of said row and column addresses to be generated.

8. The system of claim 7 wherein said all combinations of said row and column addresses are generated in a predetermined order.

9. The system of claim 8 wherein said predetermined order is non-consecutive.

10. The system of claim 2 wherein said rewrite control means further includes cycle phase control means for generating signals defining the different cycles of said rewrite cycle of operation and wherein said memory system further includes read/write command control means coupled to said timing means, said refresh and write control means, and to said memory, said cycle phase control means including a plurality of series connected bistable means for gen-erating said signals in a predetermined sequence for conditioning said timing means and said read/write command control means to perform in sequence read and write cycles of operation upon said cells within said rows and columns of said one of said number of storage locations specified by said refresh and write control means.

11. The system of claim 10 wherein said read and write cycles of operation include a refresh cycle of operation.

12. The system of claim 10 wherein said read/write command control means further includes write abort control means coupled to said error detection and correction means, said abort control means being conditioned by a signal from said error detection and correction means indicative of an uncorrectable error to inhibit the per-formance of said write cycle of operation preventing the writing of uncorrectable errors into the cells within said rows and columns specified by said refresh and write con-trol means thereby preserving original uncorrectable error conditions within said cells.

13. The system of claim 10 wherein said system further includes addressing means, said number of arrays being organized into at least a pair of memory module units, each including a plurality of word storage locations, said refresh and write control means including a pair of series connected bistable means coupled to said addressing means, said pair of series connected bistable means generating signals for conditioning said addressing means to access all of said memory cells of a pair of storage locations within said pair of memory module units during each said rewrite cycle of operation.

14. The system of claim 10 wherein said system further includes initialize control means coupled to said timing and control means, said refresh counter means, said addressing means and said write address counter means, said initialize control means being operative in response to a signal indicative of power being applied to said mem-ory to condition said timing means in response to each refresh command signal to generate signals for applying to said number of arrays to perform a refresh cycle followed by a write cycle upon said cells having the row and column addresses specified by said refresh and write control means until all of said cells of all of said number of arrays have predetermined data written therein.

15. A dynamic semiconductor memory system comprising: a number of addressable arrays of memory cells whose contents must be refreshed within a predetermined time interval, each array being divided into a number of rows and columns and organized into a number of storage locations; error detection and correction circuit means coupled to said arrays for detecting and correcting single bit errors in the contents of the cells read out during a memory cycle of operation; addressing means for applying addresses to said number of arrays during said memory cycle of operation;
timing control means for providing predetermined sequences of timing signals for performing said memory cycle of operation upon selected ones of said number of arrays; refresh control means for periodically generating a refresh command signal for refreshing the memory cells of a different one of each of the rows within said number of arrays within one of a plurality of refresh time intervals evenly distributed throughout said predetermined time interval, said refresh control means being coupled to said address-ing means and to said timing and control means, said refresh con-trol means including refresh address counter means for sequentially counting through all of the row addresses required to refresh said number of addressable arrays; write address counter means coupled in series with said refresh address counter means and to said addressing means, said write address counter means being operative in response to said refresh command signal to generate column address signals; and, soft error rewrite control means coupled to said refresh command control means, said timing and control means and said addressing means, said soft error rewrite control means including counter means operative in response to said refresh command signal to generate a sequence of counts for conditioning said timing and control means to initiate a rewrite cycle of oper-ation after each occurrence of a predetermined number of refresh command signals by generating signals during said rewrite cycle of operation for performing read and write operations upon said cells within the rows and columns of one of said number of storage locations specified by the contents of said refresh address counter means and said write address counter means respectively applied to said addressing means for detection and correction of said single bit errors in the contents of all of said cells of said arrays by said error detection and correction means at a predeter-mined rate thereby rendering said memory system less susceptible to soft errors.

16. The system according to claim 15 wherein said rewrite control means includes gating means connected to receive signals from said counter means representative of said sequence of counts, said gating means being operative in response to signals representative of a predetermined count corresponding to said occurrence of a predetermined number of refresh time intervals to generate an output rewrite command signal for resetting said counter means and initiating said rewrite cycle of operation.

17. The system of claim 16 wherein said gating means is connected to said counting means to cause the genera-tion of said output rewrite command signal in accordance with a modulus which is one minus the maximum count generated by said counter means.

18. The system of claim 16 wherein said counter means includes a number of stages and said modulus equals 2n -1 wherein n corresponds to said number of stages.

19. The system of claim 17 wherein n is selected to have a value for detecting and correcting any single bit errors within all of said cells of said number of arrays and said predetermined rate is selected to minimize inter-ference with normal memory operations.

20. The system of claim 18 wherein n equals 11, said modulus equals 2047 and said predetermined rate equals .03 seconds.

21. The system of claim 16 wherein said counter means modulus is selected to cause said generation of each said rewrite command signal when a different row address and column address are stored in said refresh address counter means and said write address counter means respectively enabling all possible combinations of said row and column addresses to be generated.

22. The system of claim 21 wherein said all combinations of said row and column addresses are generated in a predetermined order.

23. The system of claim 22 wherein said predetermined order is non-consecutive.

24. The system of claim 16 wherein said rewrite con-trol means further includes cycle phase control means for generating signals defining the different cycles of said rewrite cycle of operation and wherein said memory system includes read/write command control means coupled to said timing and control means, said refresh control means, said rewrite control means and to said number of arrays, said cycle phase control means including a plurality of series connected bistable means for generating said signals in a predetermined sequence for conditioning said timing and control means and said read/write command control means to perform in sequence read and write cycles of operation upon said different one of said cells within said rows and columns specified by said contents of said refresh address counter means and said write address counter means respec-tively.

25. The system of claim 24 wherein said read and write cycles of operation include a refresh cycle of operation.

26. The system of claim 24 wherein said read/write command control means further includes write abort control means coupled to said error detection and correction means, said abort control means being conditioned by a signal from said error detection and correction means indicative of an uncorrectable error to inhibit the gener-ation of signals during said write cycle preventing the writing of uncorrectable errors into the cells within said rows and columns specified by said refresh and write address counter means thereby preserving original uncorrectable error conditions within said cells.

27. The system of claim 24 wherein said number of arrays is organized into at least a pair of memory module units, each including a plurality of word storage locations, said write address counter means including a pair of series connected bistable means coupled to said addressing means, said pair of series connected bistable means generating signals for conditioning said addressing means to access all of said memory cells of a pair of storage locations within said pair of memory module units during each said rewrite cycle of operation.

28. The system of claim 24 wherein said system further includes initialize control means coupled to said timing and control means, said refresh counter means, said addressing means and said write address counter means, said initialize control means being operative in response to a signal indicative of power being applied to said mem-ory system to condition said timing and control means in response to each refresh command signal to generate signals for applying to said number of arrays to perform a refresh cycle followed by a write cycle upon said cells having the row and column addresses specified by the contents of said refresh counter means and said write address counter means respectively until all of said cells of said number of arrays have predetermined data written therein.

29. A dynamic semiconductor memory system comprising: at least a pair of memory module units, each unit including a plur-ality of rows of MOS memory chips, each chip including a number of arrays of memory cells organized into a plurality of storage locations including a number of rows and columns; error detection and correction circuit means coupled to said pair of memory module units for detecting and correcting single bit errors in the con-tents of the cells read out from said memory module units during a memory cycle of operation; addressing means for applying addresses to said plurality of rows of chips during said memory cycle of operation; timing control means for providing sequences of timing signals for performing said memory cycle of operation;
refresh control means for generating a refresh command signal for refreshing the memory cells within a row of said arrays of said plurality of rows of chips of each of said memory module units during each one of a plurality of evenly distributed refresh cycles of operations, said refresh control means being coupled to said addressing means and to said timing control means, said re-fresh control means including a refresh address counter for sequentially counting through all of the row addresses required to refresh all of said cells of said memory module units;
a write address counter connected in series with said refresh address counter and to said addressing means, said write address counter for sequenti-ally counting through all of the column addresses required to write data into all of said cells of said memory module units; and, rewrite control means coupled to said refresh control means, said addressing means and to said timing control means, said rewrite control means in-cluding a counter having a predetermined number of stages for generating a pre-determined maximum count, said counter being operative upon generating a count corresponding to a predetermined number of refresh command signals to condition said timing control means to initiate a rewrite cycle of operation during which said timing control means generates a sequence of signals for performing read and write cycles of operations upon said cells in a row of chips of each of said memory module units within the rows and columns of one of said plurality of stor-age locations specified by said refresh address counter and write address counter respectively for enabling the detection and correction of said single bit errors within said pair of memory module units by said error detection and correction means at a predetermined rate which is less than the rate for refresh ing said cells and is sufficient to render said system less susceptible to soft errors.

30. The system according to claim 29 wherein said rewrite control means includes decode circuit means coupled to said counter means, said decode circuit means being operative in response to signals from said counter indicating said occurrence of said predetermined number of refresh command signals to generate a rewrite command sig-nal for resetting said counter and for initiating said rewrite cycle of operation.

31. The system of claim 30 wherein said decode cir-cuit means is connected to said counter to cause the gen-eration of said rewrite command signal in accordance with a modulus which is one less than the maximum count value generated by said counter.

32. The system of claim 31 wherein said counter includes a number of stages and said modulus equal 2n -1 wherein n corresponds to said number of stages.

33. The system of claim 32 wherein n is selected to have a value for detecting and correcting any single bit errors within all of said cells of said memory module units and said predetermined rate is selected to minimize interference with normal memory operations.

34. The system of claim 33 wherein n equals 11, said modulus equals 2047 and said predetermined rate equals .03 seconds.

35. The system of claim 31 wherein said modulus is selected for generating said rewrite command signal when said refresh address counter and said write counter store a different row address and column address respectively enabling all possible combinations of said row and column addresses to be generated.

36. The system of claim 35 wherein said all combinations of said row and column addresses are generated in a predetermined non-consecutive order.

37. The system of claim 30 wherein said rewrite control means further includes cycle phase control means for generating signals defining the different cycles of said rewrite cycle of operation and wherein said memory system further includes read/write com-mand control means coupled to said timing control means, said re-fresh control means, said rewrite control means and to said pair of memory module units, said cycle phase control means including a plurality of series connected bistable means for generating said signals in a predetermined sequence for conditioning said timing control means and said read/write command control means to perform in sequence read and write cycles of operation upon said different one of said cells within said rows and columns of said one of said number of storage locations specified by said contents of said re-fresh address counter and said write address counter respectively.

38. The system of claim 37 wherein said read and write cycles of operation include a refresh cycle of operation.

39. The system of claim 37 wherein said read/write command control means further includes write abort control means coupled to said error detection and correction means, said abort control means being conditioned by signals from said error detection and correction means indicative of an uncorrectable error in the contents read out from said memory module units during said read cycle of operation to inhibit said write cycle preventing the writing of uncorrectable errors into the cells within said rows and columns specified by said refresh and write address counters thereby preserving original uncorrectable error conditions within said memory module units.

40. The system of claim 37 wherein said system further includes initialize control means coupled to said timing control means, said refresh counter, said address means and said write address counter, said initialize con-trol means being operative in response to a signal indica-tive of power being applied to said memory system to con-dition said timing control means in response to each refresh command signal to generate signals for applying to said plurality of rows of chips to perform a refresh cycle followed by a write cycle upon said cells within said plu-rality of rows of chips having the row and column addresses specified by the contents of said refresh count-er and said write address counter respectively until all of said cells of all of said number of arrays have predetermined data written therein.