CA1155932A - Arrangement for synchronizing the phase of a local clock signal with an input signal - Google Patents
Arrangement for synchronizing the phase of a local clock signal with an input signalInfo
- Publication number
- CA1155932A CA1155932A CA000369102A CA369102A CA1155932A CA 1155932 A CA1155932 A CA 1155932A CA 000369102 A CA000369102 A CA 000369102A CA 369102 A CA369102 A CA 369102A CA 1155932 A CA1155932 A CA 1155932A
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- CA
- Canada
- Prior art keywords
- input
- output
- clock signal
- phase
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
Abstract
11 PHN. 9677 Synchronizing the phase of a locally generated clock signal with the phase of an input signal is usually effected by using a phase-locked loop, but this has a drawback that a certain run-in time is necessary to be sure that the phase of the clock signal is stable. The present arrangement comprises a delay line having taps, the delay line being driven by a crystal oscillator. Clock signal versions Cl(0), Cl(90), Cl(180) and Cl(270) which are phase shifted relative to one another through 90.degree. are available at the successive taps. A coincidence detection circuit comprising trigger circuits and a combining network detects the version of the clock signal whose ascending edge, for example, is located nearest to an ascending edge of the data signal, and this version is supplied as the clock signal at an output by the selective control of switches by control signals from the outputs of the network.
Description
~s~g~2 PHN9677 l 13-9-1980 "Arrangement for synchronizing the phase of a local clock signal with an input signal."
The in~ention relates to an arrangement of a kind suitable for synchronizing the phase of a locally generated clook signal with the phase of an input signal, comprising a clock signal generator and a delay line an input of which is comlected to the generator, the delay line having a plu-rality of taps which are distributed along the delay line.
Such an arrangement is disclosed in the United ~ States Patent No. 3,509,471. In this known arrangement, the `i phase of the locally generated~clock signal is compared with ~; lO the phase of the input signal.~The phase difference between these t~o signals is applied to a control element which, using the tapped delay line, causes the phase of the clock signal to be shifted step-b~-step until the clock signal is in synchronism with the input signal.
~ Such an arrangement has the drawback~that a cer-, . . .
tain run-in~period is required before the phase of the re-generated clock has been ob-tained and is stable. In this period no reliable data transport can take place.
It~ is an object o~ the invention to provide~ an 20 arrangement o~ the abo~e kind by means of which it~is pos-~sible to ac~quire very rapidly~ more speci~ically~within the duration of one cycle of the clock signal~ acquisition of ~` the phase and~to maintain it thereafter.
According -to the in~ention an arrangement of the~
25 abo~e kind is characterized in that each tap of~the~ delay ` ` line is connected to an outpu-t of the arrangemen-t by a res-pecti~e controllable switch; that the arrangement further comprises a coincidence detection circuit ha~ing inputs and outputs, each input being connected to a respective tap of 30 the delay line and each output being connected to a control input of a respective one of the switches, and the coinci-dence detection circuit further being connected -to an input terminal -to which -the input si~nal is to be applied and being operable for generatingj when $here occurs coincidence '1 9 ~ ~
PHN 9677 2 12.9.1980 of the input signal, following an edge thereof~ with an edge of the clock signal version at one of the taps of the delay line~ a control signal at one of the outputs of the coinci-dence circuit for closing the particular switch connecting 5 a selected tap to sald output of the arrangement.
An advantage of the arrangernent according to the invention i8 that, because of the absence of counters and ; dividers, the arrangement can rapidly synchronize a clock signal up to a bit frequency which is equal to the maximum ~clock frequency of the logic used. ~hen, for examp~e, the ; logic is realised in LOCMOS, which has now a maximum clock frequency of 20 ~Iz~ thcn the clock signal can be rege-nerated up to a bit rate of 20 Mbit/sec.
A preferred embodiment of an arrangement according 15to the invention for synchronizing the phase of a localIy generated clock signal with~the~phase of an input signal is characterized in that the coincidence detection circuit comprises a plurality of bistable trigger circuits, each having~a trigger input, a data input, a set and a reset 0input and an output that each of the trigger inputs is , . ~:
connected to a respective input of the coincidence detec-tion circuit, that all the data inputs are connected to said input terminal~ that the coincidence detection circui-t ; ~ further comprises a combining network having inputs and - ~ 25outputs~ that the inputs of the combining network are so connected to the trigger circuit outputs as to select the ~trigger circuit which is~triggered first, and that the outputs of the combining network are connected respectively : ~
to the outputs of the coincidence detection circuit.
` 30 The invantion and its advantages will now be further explained, by way of exa~ple, with reference to the accompanying drawings~ of which:-Figure 1 shows a preferred embodiment of a syn-chronizing arrangement according to the invention; and Figure 2 shows some time diagrams to illus-trate the operation of the synchronizing arrangement shown in Figure 1.
In th0 preferred embodiment of the synchronizing . .
~15~9~2 .
~ PHN ~677 3 12.9.1980 ;~ arrangement shown in Figure 1 an oscillator 1, for examplea crystal oscillator~ is connected to a delay line 2, which has a number o~ sections. This delay line 2 has tapping points 3-0, 3-1, 3-2 and 3-3, denoted taps, which are distributed along it D Each section produces the same time delay, which has been so chosen in this example that clock ; signal versions Cl(0), Cl(90), Cl(180) and Cl(270) whose phase is shifted 90 ralative to one another o~ the clock signal generated by the;~crystal oscillator 1 are present at the tape 3-0, 3-l~ 3-2, 3-3~ such that the clock signal version at tap 3-0 has a phase~o* 0, that a-t tap 3-1 has a phase of 90, that at tap 3-2 has a phase of 180 and *hat at tap 3-3 has a phase of 270 , with respect to the original clock signal.
The delay line 2 may~be, ~or example, a cable having taps, a cascade arrangement o~ LC-networks or, as shown in Figure 1, a cascade arrangement o:~ sections com-; prise~ o~ a respective resisto 4-1, 4-2 or 4-3 and a respective inverter~5-1, 5-2 or 5 3. The taps 3-0,~ 3 `~ ~ 20 3-29 3-3 are connected to the sections via respective in-verters 6-o, 6-1, 6_2 and 6-3. The time delay o~ a~section is compo~ed of the propagation time o~ its inverter~(~5 ~and the time constant formed~by its ras~stor (4~ and the input capacitance of its inverter (5).~Each one o* the : 25 taps 3-0~ 3-1~ 3-2 and 3-3~of~th~e delay line 2 is~connected to an output 8 o~ the arrangement by means of an associated~
controlled switch 7-0, 7-1, 7-2 and 7-3. When~ ~or example, switch 7-0 is closed and the other switches (7-1, 7~2 and 7-3) are open, the undelayed clock signal (which has a 0 phase o~ 0) derived *rom oscillator 1 is then available at output 8. By closing one o~ the other ~witches, ~or example switch 7~2, and opening the remainin~ switches (7-0, 7-1 and 7-3)~ the clock signal is available at out-put 8 with a phase which is shifted through 180. In this 35 ~manner it iq possible to have a clock signal available at output 8 with, optionally, one o~ the phase~ 0, 90, 180 and 270. The phase which i9 the ~ptimum phase as regards the detection of the,'data signal will be chosen. The op-115~932 timum phase occurs when the leading edge of a clock signal is in the centre of a data signal bit to be detected. The signal then available at output 8 is the desired, regene-rated clock signal, whose phase will correspond wi-thin ~ 45 with the optimum phase required for detection of the data signal. It will be clear that a smaller phase devia-tion can be obtained by providing the delay line wi-th more taps than the 4 taps shown in Figure 1 and by reducing the time delay of each section in proportion therewith.
The arrangement includes a coincidence detection circuit 22 by means of which the switches (7) are operated.
The coincidence detection circuit 22 comprises a number o:~
trigger circuits 9-0, 9-1, 9-2 and g-3 of the D-type and a combinating network 10. The input data signal is applied to l5 an input 11 of the arrangement The data inputs D of the trigger circuits 9 are all con~ected to this input 11~and the trigger inputs T are connected to the inputs 23-0~ 23-1, 23-2and 23-39 respectively, of the coincidence circuit 22.
The taps 3-0, 3-1, 3-2 and 3~3 are also connected to these 20 inputs. The ~-output o~ each trigger circuit (9) is con-~ nected to a corresponding input (12) of the network 10; ~
`~ that is, the Q-output o~ the trigger circuit 9-0 is connec-ted to input 12-0, the Q-outpu-t of the trigger circuit 9~
to input 12-1, the Q-outpu-t of the trigger circuit 9-2~to 25 input 12-2 and the Q-output of -the trigger circuit 9-3 to~
inpu-t 12~3. Outputs (13) of the~netwo~k 10, which ~also ~orm the outputs of the coincidence circuit 22, are connected to respective control lnputs (14) of the ~switches (7).
; For simplicity9 the connection between the out-30 puts (13) and the control inputs (14) are not further shown in Figure 1. Outpu-t 13-0 of -the network 10 is connected to controI input 14-2~ output 13-1 is connected to control input 14-3, output 13-2 is connected to control input 14-0 and output 13-3 is connected to control input 14-1.
The network 10 may be implemented witht for exam-ple, a so-called FPLA (Field Programmable Logic Array) or as shown in Figure 1, by means of separate logic modules.
The network 10 as shown in Figure 1 comprises a number of 1 15~932 AND-gates (15), a number of trigger circuîts (16) of the SR-type and an OR-gate 17. One input of the A~-gate 15-0 is connected to input 12-0 and the other input is connected to the Q-output of trigger circuit 9-3; one input of the AND gate 15-1 is connected to input 12-1 and the other in-put is connected to the Q-output of trigger circuit 9-0;
one input of the AND-gate 15-2 is connected to input 12-2 and the other input is connected to the Q-output of trigg~r circuit 9-1; and one inp~lt of the AND-gate 1~-3 is connected to input 12-3 and the other input is connected to the Q-output of trigger circuit 9-2.~The output of each of the AND-gates 15 is connected to the set input S of the associ-ated trigger circuit (16). The`Q-outputs of these triggeI
circuits 16 are comlected to respective outputs (13) of the network 10 and to respe ctive inputs o:E the OR-gate 170 The output 18 of OR-gate 17 is connected to the set inputs S of the trigger circuits (9)0 The reset inputs R o:E the trigger circuits (9) and (16) are connected in common to a reset input terminal 190 20~ The arrangement shown in Figure 1 for synchr~onlz-~ing the phase of a locally generated clock signal with the phas;e o~ an input signal operates as follows. ~ ~
The arrangement shown in Figure 1 is adjusted to the zero-state by a~reset signal RST~ shown in~Flgure 2b~
25 which is applied -to the reset input terminal 19. The input data signal IN applied to input -termlnal 11, is shown i n Figure 2aO The clock signals generated by oscillator 1 have a shape as shown in Figure 2c. Figure 2c also shows the clock signal version C1(0) which is applied to tap 3-00 Each 30 Of the other clock signal versions C1(90), C1(180) and C1 (270) which are shifted successively through 90 , as applied to the taps 3-1, 3-2 and 3-3, are shown in Figures 2d, 2e and 2f, respectivelyO The input data signal IN is applied in parallel to the data input D of the trigger circuits 9-o, 35 9-i, 9-2 and 9-3, each of these circuits being-triggered by a different phase version of the clock signal applied to - their trigger input T. After the first leading (rising) edge occurs in the input data signal IN, so that this signcLl ~L~55~2 is "high", the p~rticular one of the trigger circuits (9) which is connectt~d to receive the clock signal version whose leading (rising) edge follows with the shortest delay after the input data signal IN becomes high~ will be triggered first with the other trigger currents (9) being successive-ly triggered thereafter. ~igures 2g9 2h~ 2i9 2J show the Q~-output signals resulting from this action. The Q-output of trigger circuit 9-1 will be switched first, followed by tha-t of trigger circuit 9-2~ then that of 9-3 and finally that of 9-0 By means of the network 10 it is now determined~in the follo1~ing manner which of the trigger circuits (16) ~ill be switched first. To this end the Q-output of each trigger circuit 9 is connected~ together with the Q-output of the preceding trigger~circuit 9~ t~o AND~-ga~es (15)~ as mentioned 15 previously. In the embodiment of Figure 2,~the AND-gate 15-1 will, consequently, be opened, that is, by the Q-output `~ ~ signal of trigger circuit 9-1 and the Q-ou-tput signal of trigger circuit 9-0~ and will se-t the trigger circuit ~16-1, ` which has its set input S connected to the output of t~his 0~AND-gate 15-1. The ~ther AND-gates 15W2~ 15-3 and 15-0 will not be opened beoause b~the time each receives the Q-output signal from the associated trigger circuit (9)~ the prece-dlng trigger circuit (9) has ~lready~bee~ -triggered~ so~tha-t there is;no~Q-output signal a-t the gate. Thus~ in no cir~
~ 25 cumsta-nces will more than one trigger~circuit (16) be set.~
- After one of the trigger~circuits~(l6) has been set~ OR-gate 17 will produce~ an~output signal ST (Figure 2k), causing the trigger circuits (9~ -to be set and to remain in the set state untiI a reset slgnal RST is next applied to input 19. At 5 30 the moment it is switched, the Q-ou-tput of trigger circuit ;~ 16-1 will apply a signal to the control input 14-3 co~nec-~
ted to it. This causes switch 7-3 to be closed so that the clock signal version at the dela~ line tap 3-3 is available at the output 8 (signal OUT~ Figure 21) as the synchronised~
35 locally geIlerated clock signal.
An advantage of the present arra~gement is that, in contrast to other clock regenera-tion circuits which function by synchronizing the cycle of a counter or a . . .
1~5~
PHN 9677 7 12.9.1980 shift register, the clock signal can be rapidly regenera-ted up to a bit rate of the input data signal which is equal to the maximum clock *requency of the logic used. If, for example, LOCMOS-logic is used with a ma~imum clock frequency of 20 MHz, then a bit rate of 20 Mbit/sec. can be processed.
In addition, the input data signal can be detec ted by means of the locally generated clock signal. To this end, Figure 1 shows, for example, a further ~rigger circuit lO 20, the data input D of which is connected to r0cei~e the input data signal IN and the trigger input T of which is connected to receive the locally generated clock signal.
Output 21 supplies the detected data signal.
In the example chosen in Figure 2, the trigger 15 circuit 9-1 was triggered first, namely by the clock ; signal version Cl(90) whlch is shi~ted through 90 . '~he fact that ultimately switch 7-3 was closed and that as a consequence the clock signal version Cl(270), which is shi~ted through 270, was applied to output 8 as the looal-20 ly generated clock signal is caused by the fact that the clock signal version which is used is the one whose leading (rising) edge is located in the~centre o~ the bit o~ th~
data signal to be detected. This is achieved by intro-ducing an extra delay o~ hal~ a clock period (or 180).
~25 Alternatively, JK-trigger circuits can be used instead of tha D-type trigger circuits (9) shown in Figure 1, and alternatively D-type or JK-type trigger circuits may~
be used instead of the SR-type trigger circuits (16) shown in Fig~re 1.
The arrangement according to the in~ention for synchroni~ing the phase of a locally generated clock signal with the phase of an input signal i9 particularly suitable when the input data signal consists of data packets. In -~ this case - provided the packet length is not too long -35 -the phase of the incoming sequence will not deviate sig~
nificantly from the phase of the clock of the receiver:
this certainly holds i* a crystal-controlled oscillator is included in the data transmitter and the da~a receiver.
1 1559~2 PHN 9677 8 12.9.1980 There~ore, a non-recurrent synchronisation as described above is sufficient. However, the invention is not limited to this. When a continuous data stream is applied, then the usually slow drift o~ the phase o~ the crystal oscil-lator can be readjusted in known ~anner.
In practice the controllable single-pole switches are implemented as MOSEET transistors, which are controlled via their gates.
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~ 15 ' , : :
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The in~ention relates to an arrangement of a kind suitable for synchronizing the phase of a locally generated clook signal with the phase of an input signal, comprising a clock signal generator and a delay line an input of which is comlected to the generator, the delay line having a plu-rality of taps which are distributed along the delay line.
Such an arrangement is disclosed in the United ~ States Patent No. 3,509,471. In this known arrangement, the `i phase of the locally generated~clock signal is compared with ~; lO the phase of the input signal.~The phase difference between these t~o signals is applied to a control element which, using the tapped delay line, causes the phase of the clock signal to be shifted step-b~-step until the clock signal is in synchronism with the input signal.
~ Such an arrangement has the drawback~that a cer-, . . .
tain run-in~period is required before the phase of the re-generated clock has been ob-tained and is stable. In this period no reliable data transport can take place.
It~ is an object o~ the invention to provide~ an 20 arrangement o~ the abo~e kind by means of which it~is pos-~sible to ac~quire very rapidly~ more speci~ically~within the duration of one cycle of the clock signal~ acquisition of ~` the phase and~to maintain it thereafter.
According -to the in~ention an arrangement of the~
25 abo~e kind is characterized in that each tap of~the~ delay ` ` line is connected to an outpu-t of the arrangemen-t by a res-pecti~e controllable switch; that the arrangement further comprises a coincidence detection circuit ha~ing inputs and outputs, each input being connected to a respective tap of 30 the delay line and each output being connected to a control input of a respective one of the switches, and the coinci-dence detection circuit further being connected -to an input terminal -to which -the input si~nal is to be applied and being operable for generatingj when $here occurs coincidence '1 9 ~ ~
PHN 9677 2 12.9.1980 of the input signal, following an edge thereof~ with an edge of the clock signal version at one of the taps of the delay line~ a control signal at one of the outputs of the coinci-dence circuit for closing the particular switch connecting 5 a selected tap to sald output of the arrangement.
An advantage of the arrangernent according to the invention i8 that, because of the absence of counters and ; dividers, the arrangement can rapidly synchronize a clock signal up to a bit frequency which is equal to the maximum ~clock frequency of the logic used. ~hen, for examp~e, the ; logic is realised in LOCMOS, which has now a maximum clock frequency of 20 ~Iz~ thcn the clock signal can be rege-nerated up to a bit rate of 20 Mbit/sec.
A preferred embodiment of an arrangement according 15to the invention for synchronizing the phase of a localIy generated clock signal with~the~phase of an input signal is characterized in that the coincidence detection circuit comprises a plurality of bistable trigger circuits, each having~a trigger input, a data input, a set and a reset 0input and an output that each of the trigger inputs is , . ~:
connected to a respective input of the coincidence detec-tion circuit, that all the data inputs are connected to said input terminal~ that the coincidence detection circui-t ; ~ further comprises a combining network having inputs and - ~ 25outputs~ that the inputs of the combining network are so connected to the trigger circuit outputs as to select the ~trigger circuit which is~triggered first, and that the outputs of the combining network are connected respectively : ~
to the outputs of the coincidence detection circuit.
` 30 The invantion and its advantages will now be further explained, by way of exa~ple, with reference to the accompanying drawings~ of which:-Figure 1 shows a preferred embodiment of a syn-chronizing arrangement according to the invention; and Figure 2 shows some time diagrams to illus-trate the operation of the synchronizing arrangement shown in Figure 1.
In th0 preferred embodiment of the synchronizing . .
~15~9~2 .
~ PHN ~677 3 12.9.1980 ;~ arrangement shown in Figure 1 an oscillator 1, for examplea crystal oscillator~ is connected to a delay line 2, which has a number o~ sections. This delay line 2 has tapping points 3-0, 3-1, 3-2 and 3-3, denoted taps, which are distributed along it D Each section produces the same time delay, which has been so chosen in this example that clock ; signal versions Cl(0), Cl(90), Cl(180) and Cl(270) whose phase is shifted 90 ralative to one another o~ the clock signal generated by the;~crystal oscillator 1 are present at the tape 3-0, 3-l~ 3-2, 3-3~ such that the clock signal version at tap 3-0 has a phase~o* 0, that a-t tap 3-1 has a phase of 90, that at tap 3-2 has a phase of 180 and *hat at tap 3-3 has a phase of 270 , with respect to the original clock signal.
The delay line 2 may~be, ~or example, a cable having taps, a cascade arrangement o~ LC-networks or, as shown in Figure 1, a cascade arrangement o:~ sections com-; prise~ o~ a respective resisto 4-1, 4-2 or 4-3 and a respective inverter~5-1, 5-2 or 5 3. The taps 3-0,~ 3 `~ ~ 20 3-29 3-3 are connected to the sections via respective in-verters 6-o, 6-1, 6_2 and 6-3. The time delay o~ a~section is compo~ed of the propagation time o~ its inverter~(~5 ~and the time constant formed~by its ras~stor (4~ and the input capacitance of its inverter (5).~Each one o* the : 25 taps 3-0~ 3-1~ 3-2 and 3-3~of~th~e delay line 2 is~connected to an output 8 o~ the arrangement by means of an associated~
controlled switch 7-0, 7-1, 7-2 and 7-3. When~ ~or example, switch 7-0 is closed and the other switches (7-1, 7~2 and 7-3) are open, the undelayed clock signal (which has a 0 phase o~ 0) derived *rom oscillator 1 is then available at output 8. By closing one o~ the other ~witches, ~or example switch 7~2, and opening the remainin~ switches (7-0, 7-1 and 7-3)~ the clock signal is available at out-put 8 with a phase which is shifted through 180. In this 35 ~manner it iq possible to have a clock signal available at output 8 with, optionally, one o~ the phase~ 0, 90, 180 and 270. The phase which i9 the ~ptimum phase as regards the detection of the,'data signal will be chosen. The op-115~932 timum phase occurs when the leading edge of a clock signal is in the centre of a data signal bit to be detected. The signal then available at output 8 is the desired, regene-rated clock signal, whose phase will correspond wi-thin ~ 45 with the optimum phase required for detection of the data signal. It will be clear that a smaller phase devia-tion can be obtained by providing the delay line wi-th more taps than the 4 taps shown in Figure 1 and by reducing the time delay of each section in proportion therewith.
The arrangement includes a coincidence detection circuit 22 by means of which the switches (7) are operated.
The coincidence detection circuit 22 comprises a number o:~
trigger circuits 9-0, 9-1, 9-2 and g-3 of the D-type and a combinating network 10. The input data signal is applied to l5 an input 11 of the arrangement The data inputs D of the trigger circuits 9 are all con~ected to this input 11~and the trigger inputs T are connected to the inputs 23-0~ 23-1, 23-2and 23-39 respectively, of the coincidence circuit 22.
The taps 3-0, 3-1, 3-2 and 3~3 are also connected to these 20 inputs. The ~-output o~ each trigger circuit (9) is con-~ nected to a corresponding input (12) of the network 10; ~
`~ that is, the Q-output o~ the trigger circuit 9-0 is connec-ted to input 12-0, the Q-outpu-t of the trigger circuit 9~
to input 12-1, the Q-outpu-t of the trigger circuit 9-2~to 25 input 12-2 and the Q-output of -the trigger circuit 9-3 to~
inpu-t 12~3. Outputs (13) of the~netwo~k 10, which ~also ~orm the outputs of the coincidence circuit 22, are connected to respective control lnputs (14) of the ~switches (7).
; For simplicity9 the connection between the out-30 puts (13) and the control inputs (14) are not further shown in Figure 1. Outpu-t 13-0 of -the network 10 is connected to controI input 14-2~ output 13-1 is connected to control input 14-3, output 13-2 is connected to control input 14-0 and output 13-3 is connected to control input 14-1.
The network 10 may be implemented witht for exam-ple, a so-called FPLA (Field Programmable Logic Array) or as shown in Figure 1, by means of separate logic modules.
The network 10 as shown in Figure 1 comprises a number of 1 15~932 AND-gates (15), a number of trigger circuîts (16) of the SR-type and an OR-gate 17. One input of the A~-gate 15-0 is connected to input 12-0 and the other input is connected to the Q-output of trigger circuit 9-3; one input of the AND gate 15-1 is connected to input 12-1 and the other in-put is connected to the Q-output of trigger circuit 9-0;
one input of the AND-gate 15-2 is connected to input 12-2 and the other input is connected to the Q-output of trigg~r circuit 9-1; and one inp~lt of the AND-gate 1~-3 is connected to input 12-3 and the other input is connected to the Q-output of trigger circuit 9-2.~The output of each of the AND-gates 15 is connected to the set input S of the associ-ated trigger circuit (16). The`Q-outputs of these triggeI
circuits 16 are comlected to respective outputs (13) of the network 10 and to respe ctive inputs o:E the OR-gate 170 The output 18 of OR-gate 17 is connected to the set inputs S of the trigger circuits (9)0 The reset inputs R o:E the trigger circuits (9) and (16) are connected in common to a reset input terminal 190 20~ The arrangement shown in Figure 1 for synchr~onlz-~ing the phase of a locally generated clock signal with the phas;e o~ an input signal operates as follows. ~ ~
The arrangement shown in Figure 1 is adjusted to the zero-state by a~reset signal RST~ shown in~Flgure 2b~
25 which is applied -to the reset input terminal 19. The input data signal IN applied to input -termlnal 11, is shown i n Figure 2aO The clock signals generated by oscillator 1 have a shape as shown in Figure 2c. Figure 2c also shows the clock signal version C1(0) which is applied to tap 3-00 Each 30 Of the other clock signal versions C1(90), C1(180) and C1 (270) which are shifted successively through 90 , as applied to the taps 3-1, 3-2 and 3-3, are shown in Figures 2d, 2e and 2f, respectivelyO The input data signal IN is applied in parallel to the data input D of the trigger circuits 9-o, 35 9-i, 9-2 and 9-3, each of these circuits being-triggered by a different phase version of the clock signal applied to - their trigger input T. After the first leading (rising) edge occurs in the input data signal IN, so that this signcLl ~L~55~2 is "high", the p~rticular one of the trigger circuits (9) which is connectt~d to receive the clock signal version whose leading (rising) edge follows with the shortest delay after the input data signal IN becomes high~ will be triggered first with the other trigger currents (9) being successive-ly triggered thereafter. ~igures 2g9 2h~ 2i9 2J show the Q~-output signals resulting from this action. The Q-output of trigger circuit 9-1 will be switched first, followed by tha-t of trigger circuit 9-2~ then that of 9-3 and finally that of 9-0 By means of the network 10 it is now determined~in the follo1~ing manner which of the trigger circuits (16) ~ill be switched first. To this end the Q-output of each trigger circuit 9 is connected~ together with the Q-output of the preceding trigger~circuit 9~ t~o AND~-ga~es (15)~ as mentioned 15 previously. In the embodiment of Figure 2,~the AND-gate 15-1 will, consequently, be opened, that is, by the Q-output `~ ~ signal of trigger circuit 9-1 and the Q-ou-tput signal of trigger circuit 9-0~ and will se-t the trigger circuit ~16-1, ` which has its set input S connected to the output of t~his 0~AND-gate 15-1. The ~ther AND-gates 15W2~ 15-3 and 15-0 will not be opened beoause b~the time each receives the Q-output signal from the associated trigger circuit (9)~ the prece-dlng trigger circuit (9) has ~lready~bee~ -triggered~ so~tha-t there is;no~Q-output signal a-t the gate. Thus~ in no cir~
~ 25 cumsta-nces will more than one trigger~circuit (16) be set.~
- After one of the trigger~circuits~(l6) has been set~ OR-gate 17 will produce~ an~output signal ST (Figure 2k), causing the trigger circuits (9~ -to be set and to remain in the set state untiI a reset slgnal RST is next applied to input 19. At 5 30 the moment it is switched, the Q-ou-tput of trigger circuit ;~ 16-1 will apply a signal to the control input 14-3 co~nec-~
ted to it. This causes switch 7-3 to be closed so that the clock signal version at the dela~ line tap 3-3 is available at the output 8 (signal OUT~ Figure 21) as the synchronised~
35 locally geIlerated clock signal.
An advantage of the present arra~gement is that, in contrast to other clock regenera-tion circuits which function by synchronizing the cycle of a counter or a . . .
1~5~
PHN 9677 7 12.9.1980 shift register, the clock signal can be rapidly regenera-ted up to a bit rate of the input data signal which is equal to the maximum clock *requency of the logic used. If, for example, LOCMOS-logic is used with a ma~imum clock frequency of 20 MHz, then a bit rate of 20 Mbit/sec. can be processed.
In addition, the input data signal can be detec ted by means of the locally generated clock signal. To this end, Figure 1 shows, for example, a further ~rigger circuit lO 20, the data input D of which is connected to r0cei~e the input data signal IN and the trigger input T of which is connected to receive the locally generated clock signal.
Output 21 supplies the detected data signal.
In the example chosen in Figure 2, the trigger 15 circuit 9-1 was triggered first, namely by the clock ; signal version Cl(90) whlch is shi~ted through 90 . '~he fact that ultimately switch 7-3 was closed and that as a consequence the clock signal version Cl(270), which is shi~ted through 270, was applied to output 8 as the looal-20 ly generated clock signal is caused by the fact that the clock signal version which is used is the one whose leading (rising) edge is located in the~centre o~ the bit o~ th~
data signal to be detected. This is achieved by intro-ducing an extra delay o~ hal~ a clock period (or 180).
~25 Alternatively, JK-trigger circuits can be used instead of tha D-type trigger circuits (9) shown in Figure 1, and alternatively D-type or JK-type trigger circuits may~
be used instead of the SR-type trigger circuits (16) shown in Fig~re 1.
The arrangement according to the in~ention for synchroni~ing the phase of a locally generated clock signal with the phase of an input signal i9 particularly suitable when the input data signal consists of data packets. In -~ this case - provided the packet length is not too long -35 -the phase of the incoming sequence will not deviate sig~
nificantly from the phase of the clock of the receiver:
this certainly holds i* a crystal-controlled oscillator is included in the data transmitter and the da~a receiver.
1 1559~2 PHN 9677 8 12.9.1980 There~ore, a non-recurrent synchronisation as described above is sufficient. However, the invention is not limited to this. When a continuous data stream is applied, then the usually slow drift o~ the phase o~ the crystal oscil-lator can be readjusted in known ~anner.
In practice the controllable single-pole switches are implemented as MOSEET transistors, which are controlled via their gates.
'~ :
~ 15 ' , : :
: ~
~ 30 :`
.', .
: .
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An arrangement for synchronizing the phase of a locally generated clock signal with the phase of an input signal, comprising a clock signal generator and a delay line an input of which is connected to the generator, the delay line having a plurality of taps which are distri-buted along the delay line, characterized in that each tap of the delay line is connected to an output of the arrange-ment by a respective controllable switch, that the arrange-ment further comprises a coincidence detection circuit having inputs and outputs, each input being connected to a respective tap of the delay line and each output being connected to a control input of a respective one of the switches, and the coincidence detection circuit further being connected to an input terminal to which the input signal is to be applied and being operable for generating, when there occurs coincidence of the input signal, following an edge thereof, with an edge of the clock signal version at one of the taps of the delay line, a control signal at one of the outputs of the coincidence circuit for closing the particular switch connecting a selected tap to said output of the arrangement.
2. An arrangement as claimed in Claim 1, charac-terized in that the coincidence detection circuit comprises a plurality of bistable trigger circuits, each having a trigger input, a data input, a set and a reset input and an output that each of the trigger inputs is connected to a respective input of the coincidence detection circuit, that all the data inputs are connected to said input ter-minal, that the coincidence detection circuit further comprises a combining network having inputs and outputs, that the inputs of the combining network are so connected to the trigger circuit outputs as to select the trigger circuit which is triggered first, and that the outputs of PHN. 9677 10 the combining network are connected respectively to the outputs of the coincidence detection circuit.
3. An arrangement as claimed in Claim 2, charac-terized in that the combining network has a number of AND-gates and a number of further trigger circuits, that each of the AND-gates has a first and a second input and an output, the first inputs being connected to a non-inverting output of a respective one of said bistable trigger circuits and the second input of each AND-gate being connected to an inverting output of the bistable trigger circuit preceding that to the non-inverting out-put of which the first input is connected, and that the output of each AND-gate is connected to a set input of a respective one of the further trigger circuits, the out-puts of which are connected to respective outputs of the combining network and to inputs of an OR-gate an output of which is connected in common to the set inputs of the bistable trigger circuits, the reset inputs of the further trigger circuits and the reset inputs of the trigger cir-cuits being interconnected and connected to a reset input terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NLAANVRAGE8000606,A NL183214C (en) | 1980-01-31 | 1980-01-31 | Apparatus for synchronizing the phase of a locally generated clock signal with the phase of an input signal. |
| NL8000606 | 1980-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1155932A true CA1155932A (en) | 1983-10-25 |
Family
ID=19834765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000369102A Expired CA1155932A (en) | 1980-01-31 | 1981-01-22 | Arrangement for synchronizing the phase of a local clock signal with an input signal |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4386323A (en) |
| JP (1) | JPS56120227A (en) |
| BE (1) | BE887296A (en) |
| CA (1) | CA1155932A (en) |
| DE (1) | DE3102447A1 (en) |
| FR (1) | FR2475318A1 (en) |
| GB (1) | GB2069263B (en) |
| NL (1) | NL183214C (en) |
| SE (2) | SE449941B (en) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0048896B1 (en) * | 1980-09-25 | 1985-12-27 | Kabushiki Kaisha Toshiba | Clock synchronization signal generating circuit |
| US4525674A (en) * | 1982-07-28 | 1985-06-25 | Reliance Electric Company | Circuit for synchronizing a switching power supply to a load clock |
| JPS5986385A (en) * | 1982-11-09 | 1984-05-18 | Toshiba Corp | Sampling pulse producing circuit |
| US4617679A (en) * | 1983-09-20 | 1986-10-14 | Nec Electronics U.S.A., Inc. | Digital phase lock loop circuit |
| JPS60143017A (en) * | 1983-12-29 | 1985-07-29 | Advantest Corp | Clock synchronizing logical device |
| US4575860A (en) * | 1984-03-12 | 1986-03-11 | At&T Bell Laboratories | Data clock recovery circuit |
| JPS60204121A (en) * | 1984-03-29 | 1985-10-15 | Fujitsu Ltd | Phase synchronization circuit |
| EP0185779B1 (en) * | 1984-12-21 | 1990-02-28 | International Business Machines Corporation | Digital phase locked loop |
| US4604582A (en) * | 1985-01-04 | 1986-08-05 | Lockheed Electronics Company, Inc. | Digital phase correlator |
| US4635249A (en) * | 1985-05-03 | 1987-01-06 | At&T Information Systems Inc. | Glitchless clock signal control circuit for a duplicated system |
| US4675612A (en) * | 1985-06-21 | 1987-06-23 | Advanced Micro Devices, Inc. | Apparatus for synchronization of a first signal with a second signal |
| US4654599A (en) * | 1985-07-05 | 1987-03-31 | Sperry Corporation | Four phase clock signal generator |
| US4787095A (en) * | 1987-03-03 | 1988-11-22 | Advanced Micro Devices, Inc. | Preamble search and synchronizer circuit |
| US4791488A (en) * | 1987-08-12 | 1988-12-13 | Rca Licensing Corporation | Line-locked clock signal generation system |
| US4757264A (en) * | 1987-10-08 | 1988-07-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Sample clock signal generator circuit |
| JPH0795731B2 (en) * | 1987-10-30 | 1995-10-11 | 株式会社ケンウッド | Optimal clock forming device for data receiving device |
| US4868514A (en) * | 1987-11-17 | 1989-09-19 | International Business Machines Corporation | Apparatus and method for digital compensation of oscillator drift |
| JPH01149516A (en) * | 1987-12-04 | 1989-06-12 | Mitsubishi Electric Corp | Clock generating circuit |
| US5022057A (en) * | 1988-03-11 | 1991-06-04 | Hitachi, Ltd. | Bit synchronization circuit |
| ATE76706T1 (en) * | 1988-03-22 | 1992-06-15 | Siemens Ag | METHOD AND ARRANGEMENT FOR CONTINUOUSLY ADAPTING THE PHASE OF A BINARY DATA SIGNAL TO A CLOCK. |
| ES2037902T3 (en) * | 1988-04-29 | 1993-07-01 | Siemens Aktiengesellschaft | PROCEDURE AND DEVICE FOR THE RECOVERY OF THE CLOCK IMPULSE OF A DATA SIGNAL BY CONTINUOUS ADAPTATION OF A LOCALLY GENERATED CLOCK IMPULSE TO A DATA SIGNAL. |
| US5034967A (en) * | 1988-11-14 | 1991-07-23 | Datapoint Corporation | Metastable-free digital synchronizer with low phase error |
| US5050189A (en) * | 1988-11-14 | 1991-09-17 | Datapoint Corporation | Multibit amplitude and phase modulation transceiver for LAN |
| US5008879B1 (en) * | 1988-11-14 | 2000-05-30 | Datapoint Corp | Lan with interoperative multiple operational capabilities |
| US5048014A (en) * | 1988-12-30 | 1991-09-10 | Datapoint Corporation | Dynamic network reconfiguration technique for directed-token expanded-address LAN |
| US4908842A (en) * | 1989-02-14 | 1990-03-13 | Galen Collins | Flash synchronized gated sample clock generator |
| DE58908236D1 (en) * | 1989-02-23 | 1994-09-29 | Siemens Ag | Method and arrangement for adapting a clock to a plesiochronous data signal and for clocking it with the adapted clock. |
| JP2664249B2 (en) * | 1989-03-13 | 1997-10-15 | 株式会社日立製作所 | Timing extraction circuit, communication system using the same, timing extraction method, and communication device |
| US5267267A (en) * | 1989-03-13 | 1993-11-30 | Hitachi, Ltd. | Timing extraction method and communication system |
| US5424882A (en) * | 1989-03-13 | 1995-06-13 | Hitachi, Ltd. | Signal processor for discriminating recording data |
| JP2536929B2 (en) * | 1989-07-21 | 1996-09-25 | 富士通株式会社 | Phase matching circuit |
| DE3931259A1 (en) * | 1989-09-19 | 1991-03-28 | Siemens Ag | Continual matching of digital signal to clock - using output of second tapped delay line to control selection of tap on first line |
| US4998264A (en) * | 1989-09-20 | 1991-03-05 | Data Broadcasting Corporation | Method and apparatus for recovering data, such as teletext data encoded into television signals |
| DE3936901A1 (en) * | 1989-11-06 | 1991-05-23 | Ant Nachrichtentech | Semiconductor chip with several shift registers - has number of series-connected bistable flip=flops, with digital signal writing |
| US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
| US5212716A (en) * | 1991-02-05 | 1993-05-18 | International Business Machines Corporation | Data edge phase sorting circuits |
| JPH0778774B2 (en) * | 1991-02-22 | 1995-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Short latency data recovery device and message data synchronization method |
| US5255292A (en) * | 1992-03-27 | 1993-10-19 | Motorola, Inc. | Method and apparatus for modifying a decision-directed clock recovery system |
| EP0608578B1 (en) * | 1993-01-28 | 1998-08-26 | Alcatel | Synchronizing circuit |
| US5412698A (en) * | 1993-03-16 | 1995-05-02 | Apple Computer, Inc. | Adaptive data separator |
| DE69332333T2 (en) * | 1993-10-12 | 2003-05-15 | Alcatel Sa | synchronization circuit |
| JPH08111675A (en) * | 1994-10-07 | 1996-04-30 | Mitsubishi Denki Eng Kk | Synchronizing circuit |
| US6239627B1 (en) * | 1995-01-03 | 2001-05-29 | Via-Cyrix, Inc. | Clock multiplier using nonoverlapping clock pulses for waveform generation |
| US5646568A (en) * | 1995-02-28 | 1997-07-08 | Ando Electric Co., Ltd. | Delay circuit |
| US6064707A (en) * | 1995-12-22 | 2000-05-16 | Zilog, Inc. | Apparatus and method for data synchronizing and tracking |
| KR100197563B1 (en) * | 1995-12-27 | 1999-06-15 | 윤종용 | Digital delay synchronous loop circuit using synchronous delay line |
| WO1998004043A1 (en) * | 1996-07-23 | 1998-01-29 | Honeywell Inc. | High resolution digital synchronization circuit |
| US6043694A (en) * | 1998-06-24 | 2000-03-28 | Siemens Aktiengesellschaft | Lock arrangement for a calibrated DLL in DDR SDRAM applications |
| JP3394013B2 (en) * | 1999-12-24 | 2003-04-07 | 松下電器産業株式会社 | Data extraction circuit and data extraction system |
| US7253671B2 (en) * | 2004-06-28 | 2007-08-07 | Intelliserv, Inc. | Apparatus and method for compensating for clock drift in downhole drilling components |
| US9582449B2 (en) | 2005-04-21 | 2017-02-28 | Violin Memory, Inc. | Interconnection system |
| US9384818B2 (en) | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
| US8112655B2 (en) * | 2005-04-21 | 2012-02-07 | Violin Memory, Inc. | Mesosynchronous data bus apparatus and method of data transmission |
| KR101331569B1 (en) * | 2005-04-21 | 2013-11-21 | 바이올린 메모리 인코포레이티드 | Interconnection System |
| US8452929B2 (en) * | 2005-04-21 | 2013-05-28 | Violin Memory Inc. | Method and system for storage of data in non-volatile media |
| US9286198B2 (en) | 2005-04-21 | 2016-03-15 | Violin Memory | Method and system for storage of data in non-volatile media |
| US8028186B2 (en) | 2006-10-23 | 2011-09-27 | Violin Memory, Inc. | Skew management in an interconnection system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3029389A (en) * | 1960-04-20 | 1962-04-10 | Ibm | Frequency shifting self-synchronizing clock |
| FR1422959A (en) * | 1964-11-13 | 1966-01-03 | Thomson Houston Comp Francaise | Improvements to phase control devices |
| US3509471A (en) * | 1966-11-16 | 1970-04-28 | Communications Satellite Corp | Digital phase lock loop for bit timing recovery |
| US4169995A (en) * | 1970-01-21 | 1979-10-02 | The United States Of America As Represented By The Secretary Of The Air Force | Pulse repetition frequency tracker |
| US3763317A (en) * | 1970-04-01 | 1973-10-02 | Ampex | System for correcting time-base errors in a repetitive signal |
| FR2283592A1 (en) * | 1974-08-27 | 1976-03-26 | Thomson Csf | SYNCHRONIZATION EXTRACTOR AND INFORMATION TRANSMISSION SYSTEM INCLUDING SUCH A DEVICE |
| JPS5563123A (en) * | 1978-11-04 | 1980-05-13 | Sony Corp | Phase control circuit |
-
1980
- 1980-01-31 NL NLAANVRAGE8000606,A patent/NL183214C/en not_active IP Right Cessation
-
1981
- 1981-01-22 CA CA000369102A patent/CA1155932A/en not_active Expired
- 1981-01-23 US US06/227,892 patent/US4386323A/en not_active Expired - Fee Related
- 1981-01-26 DE DE19813102447 patent/DE3102447A1/en active Granted
- 1981-01-26 FR FR8101381A patent/FR2475318A1/en active Granted
- 1981-01-28 JP JP1032681A patent/JPS56120227A/en active Pending
- 1981-01-28 GB GB8102580A patent/GB2069263B/en not_active Expired
- 1981-01-28 SE SE8100527A patent/SE449941B/en not_active IP Right Cessation
- 1981-01-28 SE SE8100527D patent/SE8100527L/en not_active Application Discontinuation
- 1981-01-29 BE BE0/203645A patent/BE887296A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| FR2475318A1 (en) | 1981-08-07 |
| US4386323A (en) | 1983-05-31 |
| DE3102447A1 (en) | 1981-11-19 |
| NL8000606A (en) | 1981-09-01 |
| SE8100527L (en) | 1981-08-01 |
| BE887296A (en) | 1981-07-29 |
| DE3102447C2 (en) | 1989-05-11 |
| NL183214B (en) | 1988-03-16 |
| GB2069263A (en) | 1981-08-19 |
| NL183214C (en) | 1988-08-16 |
| JPS56120227A (en) | 1981-09-21 |
| GB2069263B (en) | 1983-11-30 |
| FR2475318B1 (en) | 1984-05-11 |
| SE449941B (en) | 1987-05-25 |
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