CA1139002A - Microprogrammed programmable controller - Google Patents

Abstract

Abstract of the Disclosure A programmable controller includes a processor formed around a pair of four-bit bipolar microprocessors. A con-trol program formed by selected macroinstructions is stored in a random access memory and it is executed by sequentially mapping each macroinstruction operation codes into a corres-ponding microroutine which is stored in a read-only memory.
Some macroinstructions include operand addresses of a line in an I/O image and data table portion of the random access memory and one macroinstruction (ADX) expands this operand address to enable the I/O image and data table to be expanded in size. A timer macroinstruction is executed in part by reading the state of a counter which is driven by a real time clock, and arithmetic functions are performed more effectively with the use of a decimal adjust accumulator.

Description

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MICROPROGRaD:MED PROGRAMM~LE CONTROLLER

The field of the invention is programmable controllers such as those disclosed in U.S. Patent Nos. 3,942,158 and 3,810,118.
S Programmable controllers are typically connected to industrial equipment such as assembly lines and machine tools to sequentially operate the equipment in accordance with a stored control program. In programmable controllers such as those disclosed in the above cited patents, for example, the control program is stored in a memory and in-cludes instructions which are read out in rapid se~uence to examine the condition of selected sensing devices on the controlled equipment and instructions which energize or de-energiæe selected operating d2vices on the controlled equip-ment contingent upon the status of one or more of the examined sensing devices. The processor in a programmable controller is designed to rapidl~ execute programmable controller type instructions which call ~or the manipulation of single-bit input data and the control of singlé-bit output data.
The length of the control program, and hence the com-plexity of the system to be controlled, must be limited to insure that the entire control program can be executed, or scanned, within a set tima. Such time limits are required to insure that the programmable controller will provide virtually instantaneous response to any change in the status of sensing devices on the controlled system. Therefore, the speed with which a controller processor can execute program-mable controller instructions has a direct bearing on the size of the machine or process which it can efectively control.

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~lthough the vast majority of programmable control--lPrs presently in use are comprised of discrete components, a number of small programmable controllers have been intro-duced in recent years which employ a microprocessor. Here-tofore, such microprocessor based programmable controllers have been limited in size by the speed with which the micro-processor can execute programmable controller type expressions, and hence, the speed with which it can scan the control pro-gram. To assist the microprocessor in carrying out the numerous single-bit calculations necessary to execute a control program, hardware such as data selectors and addres-sable latches have been employed to "convert" the word-oriented microprocessor to a single-bit processor. Or, as disclosed in U. S. patent No. 4,165,534 hardwired "Boolean processors"
have been employed to assist the microprocessor in performing single-bit calculations.
Not only should a programmable controller processor be able to execute Boolean expressions rapidly, but it also should be able to execute programmable controller type in-structions. Such instructions have become quite standardized in the industry in terms of the functions they perform. They may be directly associated with elements of a ladder diagram and are, there:Eore, easily understood by control engineers who use programmable controllers. Program panels such as those disclosed in U. S. Patent Nos. 3,798,612, 3,813,643 and 4,070,702 have also been developed to assist the user in developing and editing a control program comprised of pro-grammable controller type instructions. Such program panels account to a great extent for the rapidly increasing populari ty of programmable controllers and any new controller processor should be compatible with them. In other words, the con-troller processor should be capable of directly executing programmable controller type instructions.
The present invention relates to a programmable con-troller which employs a micropxogrammed processor and specialpurpose hardware to execute programmable controller type macroins~ructions, one of which (ADX) operates the system to expand the addressing capability o~ the macroinstructions in the control program.
Accordingly, the present invention will enable one to provide a programmable controller which will accommodate a large I/~ image and data table that is addressable by pro-grammable controller instructions. This is accomplished by the use of the special address expansion macroinstruction (ADX) which may be inserted just prior to any controller macroinstruction that is to address a memory location outside the range o~ its own address code. A selected microprogram is executed when the address expansion macroinstruction (ADX) is rea~ ~rom the con~rol program memory and this microprogram presets the most significant address bus leads in the pro-grammable controller to a value which brings the desired memory location within the range of the address code in the programmable controller macroinstruction that follows.
The practical result of this invention is that the I/O image ~5 table, data table and timers and counters which are stoxed in the controller memory can be expanded in size far beyond that possible in prior programmable controllers.
In drawings which illus~rate the embodiments of the invention, Fig. 1 is an electrical block diagram of a programmable controller which employs the present invention~
Figs. 2A and 2B are an electrical block diagram of the controller processor which forms part of the controller of Fig. 1, Fig. 3 is an electrical sche~atic diagram of the central processor unit which forms part of the controller processor of Fig. 2B, Fig. 4 is an electrical schematic diagram of the real time clock circuit which forms part of the controller processor of Fig. 2A, Figs. 5A and 5B are schematic representations of the microinstruction field assignments, Fig. 6 is an electrical schematic diagram o~ the decoder circuit which forms part of the controller processor of Fig. 2B, Fig. 7 is a flow chart which illustrates the general operation of the programmable controller of Fig. 1, Figs. 8A and 8B are a flow chart which illustrates the manner in which the pro~rammable controller o Fig. 1 executes the TON.01 macroinstruction, and ~ig. 9 is a schematic illustration of the contents of four memory lines which are dedicated to function as part of a ten millisecond counter.
Referring to Fig. 1, the programmable controller is structured around an eight-bit bidirectional data bus 1 and includes a controller processor 2 which directs the flow of data thereon by means of control lines and a sixteen-bit address bus 3. A randon access memory (RAM) 4 connects to both the data bus 1 and the address bus 3 and an eight-bit data word may be written into an addressed line or read ~L~39~

out of an addressed line of the memory 4 in response to control signals applied to a WRITE control line 28 and a READ control line 16. The RAM 4 may include anywhere from lK to 16K lines of memory depending on the size of the con-trol program to be stored. The first 96 to 512 lines con-sist of working registers 7, an I/O image table 8 and a timers and counters storage 9, although, as will be described hereinafter, this can be expanded by using the ADX macro-instruction of the present invention. The remainder of the RAM 4 stores the control program 10 which is comprised of a large nl~ er of programmable controller type instructions.
The control program lO is loaded into the memory 4 and edited by means of a program panel 11 which couples to the data bus 1 through a universal asynchronous receiver/trans-mitter (UAR/T) 12 and two sets o data gates which areindicated collectively at 13~ When data is received ~rom the program panel 11 serially through a cable 17 an interrupt request is generated on an INT REQ line 80. The controller processor executes an interrupt service microroutine in response to this interrupt request and the received eight~
bit word is gated onto the data bus l. The UAR/T 12 is enabled through a control line 39 and a DBIN control linP 35.
A byte of data is written into the UAR/T 12 when a WRITE
control line 28 is at a logic low voltage and a byte o~
data is read from the UAR/T 12 when the READ line 16 is low.
Data i5 gated from the data bus l to the UAR/T 12 when a logic high voltage is applied to the UAR/T data gates 13 through a control line 15 and da~a is coupled to the data bus l from the UAR/T 12 when the gates 13 are enabled through a control line 29.

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The programmable controller i5 connected to the machine, or system being controlled, through I/O interface racks 20-23~ Each interface rack 20-23 includes an I/O adapter card 24 and up to sixteen four-bit input or output cards (not shown in the drawings) that are received in eight slots 0-7.
That is, each slot 0-7 may include two four-bit I/O msdules, or cards. Each input card contains four input circuits for receiving digital signals that indicate the status of sensing devlces such as limit switches on the machine being controlled, and each output card contains four output circuits for con-trolling operating devices on the machine such as motor starters and solenoids. Input and output circuits such as those disclosed in respective U.S. Patent Nos. 3,643,115 and 3,745,546 may be employed for this purpose although numerous circuits are available to interface with the many types of sensing devices and operating devices which may be encountered in industrial applications.
Data is coupled to or rom a particular card in one o~
the I/O interface racks 20-23 by addressing it khrough a five-bit I/O address bus 25. Two bits select the appropriate I/O interface rack 20-23 and the remaining three bits identify the slot being addressed. The I/O adapter card 24 on each I/O interface rac~ 20-23 includes means for recogni~ing when its rack is being addressed (not shown in the drawings) for enabling the appropriate slot and caxd. Reference is made to U.S. Patent No. 4,118,792 whichissued on October 3, 1978 and which is entitled "Malfunction Dstection Syctem rox a Microprocessor Based Programmable Controller," for a more detailed description of the I/O adaptex cards 24.
As will be explained in detail hereinafter~ the I/O

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address is generated on the address bus 3 (AB0-AB4) by ~he controller processor 2. It is coupled to the I/O address bus 25 by a set of I/O address gates 26 which are enabled when a logic high voltage i5 generated on an "I~O RDWR"
control line 27. In addition to the I/O address, the gates 26 couple the WRITE control line 28 and READ control line 16 to each of the interface racks 20-23 through an I/O
read line 30 and an I/O write line 31. A strobe line 27' also connects to each rack 20-23 to indicate when an input or output function is to be performed.
Data is coupled between the controller processor 2 and the I/O interface racks 20-23 through an eight-bit I/O
data bus 32 and a set of eight I/O data gates 33. When a logic high voltage is generated on the I/O read line 30, eight bits of data are gated onto the I/O data bus 32 by the addressed I/O card and this byte of data is coupled to the data bus 1 by the I/O data gates 33. Conversely, when a logic high is generated on the I/O write control line 31, an eight-bit output data word is coupled from the controller processor 2, through the I/O data gates 33 and to an addressed output card in one of the I/O interface racks 20-23. The I/O data gates 33 a~e controlled by a "BE" control line 34 which is driven to a logic high voltage when data is to be outputted to the I/O interface racks 20-23, and the I/O RDWR
control line 38 which is driven low to enable the gates 33.
A 5 mHz "OSC" control line 36 synchronizes the operation of the I/O data gates 33 with that of the contxoller processor 2.
As will be explained in more detail hereinafter, the control program stored in the RAM 4 is repeatedly exeruted, ~L3~

or scanned, by the controller processor Z when in the "run"
mode. Each scan through the control program requires typically rom five to twenty milliseconds (the exact time depends on the length of the control program 10 and the types of instructions contained therein) and after each such scan, an I/O scan routine is executed to couple data between the I/O interface racks 20-23 and the I/O imaye table 8 in the RAM 4. The I/O image table 8 stores an input status data word and an output status data word fox each I/O card in the interface racks 20-23. Each data word in the I/O
image table 8 is thus associated with a specific card in one of the I/O interface racks 20-23. Each input status word is an image of the state of eight sensing devices connected to its associated I/O card and each output status word is an image of the desired state of any operating de-vices connected to its associated I/O card. If a particular I/O slot contains an input card, the output status word in the I/O image table 8 which corresponds to that slot is blank or can be used for other purposes.
The I/O scan is made after each scan, or execution, of the control program 10. The I/O scan is a programmed sequence in which output status words are sequentially coupled from the I/O image table 8 to their associated I/O cards and input status words are sequentially coupled from the I/O
cards to their associated memory locations in the I/O
image table 8. The I/O scan is performed frequently and thus the I/O image table 8 is kept up to date with changing conditions on the machine or process being controlled. As will become apparent from the discussion to follow, the controller processor ~ operates on data in the I/O image table 8 rather than data received directly from the I/O
interface xacks 20-23. This allows the processor to opexate at maximum speed to execute the control program 10 in a minimum amoun~ of time while at the same time minimizing the data rates in the I/O data bus 32 and the I/O address bus 25. The latter consideration is impoxtant since lower data rates allow the use of more effective noise immunity circuits which are so necessary in an industrial environment.
The overall ~unction of the programmable controller is governed by the programmable con~roller type instruations stored in the control program portion lO of the RA~I 4.~ As will become apparent from the description to follow, these programmable control~er type instructions are treated as "macroinstructions" in the invented controller in that each is mapped into a set of rl~croinstructions which are executed by the controller processor 2 to carry out the function indicated by the macroinstruction. Beore describing the manner in which the controller elements function to execute the programmable controller type instructions, however, a brief discussion o~ the programmable controller instruction se~ is in order~ The macroinstruction set includes all of the controller instructions described in the above cited U.S. Patent No. 3,942,158 entitled "Programmable Logic Controller'l which includes three general types: bit instruc-tions; word instruc~ions; and control instructions. Bitinstructions and word instructions are stored on two memory lines, the first line storing an operand address and the second line storing an operation code. The control instruc-tions are comprised solely of a two~line operation code. Th~
bit instructions include the following:

TABLE I
__ . ... .. .. .. . ~ ~
EXECUTION
~NEMONIC BIT POINTER OPERATION CODE TIME
~___ .. . . . . ~_ XIO/XOD X X X 1 1 0 1 1 3.0 usec.
_ ~

OTL X X X 0 0 1 1 1 4.0 usec.

. , , " .......... _, , . .
INSTRUCTION

.. ~ , ,, The operations performed by these bit instructions are briefly defined as follows:
XIC - Examine status bit closed or, is the status bit in a logic 1 state?
XOE - Same as XIC, but refers to a status bit in the output image table.
XIO - Fxamine status bit open or, is the status bit in a logic 0 state?
XOD - Same as XIO, but refers to a status bit in the output image table.
OTU - If conditions are true kurn status bit off, or to a logic 0 state, and if false do nothing.
OTL - If conditions axe true turn status bit on, or to a logic 1 state, and if false do nothing.
OTE - If conditions are true turn status bit on and if conditions are false turn status bit off.

The 8-bit operand address which is associated with each of the above operation codes identifies the memory address of the word containin~ the desired status bit whereas the bit pointer associated with the operation code identifies the location o~ the status bit in the addressed memory word.

The operand address ~ypically identiies a line in the I/O
image table 8 or the timers and counters portion 9 o~ ~he memory 4. Because the range of the 8-bit operand address is only 256 a~dresses, these portions of the memoxy 4 have heretofore been limited in size.
The control instructions include the following:

TABLE II

__ . .................... . . _ ..
MN3MONIC O'ERATION _3DE IXECUTION

BST 0 0 0 1 0 0 1 1 2.2 u~ec.

______________ ________~____ ______________ ___~____________ END 0 0 1 0 0 1 0 0 <1.000 usec.

~ ..... _ , ~ , . ~
INSTRUCTION

_ ~
Note: X Signifies "don't care"

The operations performed by these control instructions are briefly defined as follows:

NOP - No operation BND - Branch end~ termination of a Boolean subbranch BST - Branch start. opens or begins a Boolaan subbranch END - End of the control program MCR - Master Control register 5 ADX - Expand the operand address in the macroinstruction which follows.

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The word ~ype programmable controller instructions in-clude the following:

TABLE III

EXECUTION
~EMONIC OPER~TIO~ CODE TIME

TOF .01 sec. X 1 0 0 0 0 0 0 TOF Q.l sec. X O 0 1 O 0 0 0 TOF 1.0 sec. X 1 O 1 0 O 0 0 TON .01 sec. X O 1 0 0 0 0 O lS usec.
TON O~l sec. X 0 1 1 0 0 0 0 TON 1.0 sec. X 1 1 1 0 0 0 0 RTO 0.1 sec. X 0 0 0 1 0 0 0 RTO 1. 0 sec. X 1 0 0 1 0 0 0 . ________________ _____________________________ _______________ RTR X 1 0 0 0 1 0 0 15 usec.

. ____________.___ _________________________ ___ _______________ PUT X 1 0 1 1 0 0 0 4.8 OE T X 0 0 1 1 0 0 0 4.4 usec.
EQU X 0 1 1 1 0 0 0 S. 6 LES X 1 1 1 1 0 0 0 5.6 INSTRUCTION

. ........ ; ~
X is no~ part of operation code/ but is an additional operand address bit.
25ThP operations per~ormed by these word-type instructions are briefly defined as follows:
TOF - I conditions are true turn output on, otherwise, wait until time is out then turn output off.
TON - If conditions are true wait until time is out then 30turn output on, otherwis~, turn output o~f.
RTO - If conditions are true wait until time is out then turn output on, otherwise, stop timer.

CTD - If the conditions are true reduce the count by one.
CTU - If the conditions are true increase khe count by one.

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PUT - If conditions are true write the number in the micro-processor accumulator in the selected memory line, otherwise, do nothing.
RTR - If the conditions are true reset the timer.
CTR - If the conditions are true reset the cou~ter.
GET - Fetch the word on the selected memory line and store in the microprccessor accumulator.
EQU - Is the value stored in the microprocessor accumu-lator equal to the value stored on ~he selected memory line?
LES - Is the value stored in the microprocessor accumulator less than the value stored on the selected memory line?

The operand address which is associated with each of these word-type operation codes is a l~wer eight-bit byte of a 16-bit address of a line in the RAM 4.
Referring to Figs. 2A and 2B, the controller processor

2 is organized around a central processor unit 40 which re-c~ives data from an eight-lead B-bus 41 and generates data on an eight-lead D~bus 42. The central processor 40 is shown in Fig. 3 and it includes a pair o~ four-bit bipolar microp~ocessors 43 and 44 which each connect to four leads in the data buses 41 and 42. The microprocessors 43 and 44 are high-speed cascadable elements manufactured and sold commercially by Advanced Micro Devices, Inc. as the ~m2901A.
A complete description of this microprocessor as well as many of the supporting circuits discussed herein is provided in the publication entikled "Advanced Micro Devices - The Am2900 Family Data Book" published in 1978 by Advanced M~cro Devices, Inc.
Referring again to Fig. 2A, the controller data bus 1 is coupled to the processor B data bus 41 by a set of eight data-in gates 45. An enable terminal on each of these gates 45 is commonly connected to a DATA IN control line 46, and when this control line 46 is driven low, an eight-bit byte - ~iL3~

of data is read onto the B data bus 41.
An eight-bit data-out latch 47 couples the processor D
data bus 42 to the controller data bus 1. When a logic high voltage is applied to a DATA DEST control line 48 an eight-bit byte of data on the D data bus 42 is stored in the latch47, and when a logic low voltage is genera~ed on a DATA OUT
Gontrol line 49, this eight-bit byte of data is generated o~
the controller data bus 1. The processor B and D data buses 41 and 42 are thus coupled to the controller data bus 1.
The processor D data bus 42 is also coupled to the con-troller address bus 3. More speci~ically, it connects to the inputs of an eight-bit address high latch 50 and to the inputs of an eight-bit address low latch 51. Data is stored in khe latch 50 when a logic hlgh voltage is applied to a HI ADDR
control line 52, data is storsd in the latch 51 when a logic high voltage is applied to a LO ADDR control line 53, and a sixteen-bit address is generated on the controller address bus 3.
Referring particularly to Figs. 1 and 2A, each con-troller instruction stored in the control program portion 10of the RAM 4 includes an operation code which indica~es a function to be performed by the controller processor 2. These operation codes are applied to eight input terminals on a mapping PROM 55 which converts them to a starting address of a microroutine that is stored in a microprogram PROM 56.
The mapping PROM 55 is a 256x12-bit programmable read-only memory having its twelve data output terminals connected to the twelve leads in a rnicro-address bus 57. The mapping PROM 55 is "programmed" to converk each eight-bit operation code applied to its eighk address terminals into a twPlve-0~

bit micro-address. This micro--address is generated on ~he micro-address bus 57 when a pair o chip enable terminals on the mapping PROM 55 are driven low by a MAP control line 58 and a MICRO 5 control line 59.
The microprogram starting address generated by the mapping PROM 55 is coupled to the microprogram PROM 56 through a microprogram controller 60. The controller 60 is a commercially available integrated circuit manufactured and sold by Advanced Micro Devices, Inc. as Serial No. Am2910.
It operates as an address sequencer for controlling the sequence of execution of micxoinstructions stored in the microprogram PROM 56~ A complete description o~ this device is provided in the above cited publication. It is controlled by a set of five lines (MICRO 0-4) which connect to a 32-bit microinstruction register 61. The controller 60 also receives a signal through a CC control line 62 and it is synchronized with the other elements in the system by an OSC clock line 63~ The microprogram controller 60 drives the MAP control line 58, and hence, it controls the mapping PROM 55.
rwelve outputs 6A on the controller 60 connect to the address terminals on the microprogram PROM 56. The micro-program PROM 56 is comprised of eight lK by eight~bit pro-grammable read-only memories which are interconne~ted to store 2K 32-bit microinstructions. One of these 32-bit micro-instructions is addressed by the microprogram controller 60 and the addressed microinstruction is generated on a bu~ 65 to the microinstruction register 61. The micro instruction regist~r 61 is comprised of four hex latches and two quad latches which are clocked in synchronism with the microprogram controller 60 through the OSC clock lina 63. The microinstruction addressed by the controller 60 is thus read out of the PROM 56 and stored in the microinstruction register 61.
The thirty-two output terminals (MICRO 0-31~ on the microinstruction register 61 are connected to various ele-ments in the controller processor to read data from an indicated source, perform indicated functions on the data and to write data into an indicated destination. The con-troller 60 and microinstruction register 61 are clocked every 200 nanoseconds by the 5 mHz OSC line 63 and a sequence of microinstructions is thus rapidly read out of the microprogram PRQM 56 and executed to control the operation of the controller processor 2.
A detailed description of many of the microprograms stored in the PROM 56 is provided hereinafter and a chart of the microfield assignments for "register to register" and "~ranch" type microinstructions is provided in Figs. 5A and 5B. A "register immediate" type microinstruction is also employed and its microfleld assignments are the same as the register to register microinstruction except that bits 20-27 (i.e., MICRO 20-27) contain an eight-bit byte of data.
Referring particularly to Fig. 2A, when a branch micro-instruction is read out of the microprogram PROM 56 and the tested condition is true, the twelve bit target address (MICRO 20-31) is gated through a set of twelve micro-jump gates 67 and applied to the inputs of the microprogram controller 60. The controller 60 is thus preset to read out the microinstruction stored at the target address in the microprogram PROM 56. The micro-jump gates 67 are enabled when the micro clock line (MICRO 5) is at a logic -- ~.3911~Z

low voltage. Similarly, when a reyister immediate micro-instruc~ion is executed, an eight-bit byte of data in the microinstruction (MICRO 20-27) is coupled through a set of eight immediate gates 68 to the B data bus 41. The immediate gates are enabled by a logic low voltage on an IMM control line 69.
The microprogram counter 60 includes a register/counter ~not shown in the drawings) which can be preloaded with a number generated on the ~ data bus 42. Eight loop gates 7G
connect the leads (D0-D7) in the D data bus to the eight least significant digit leads in the micro-address bus 57 and four other gates connect the remaining four leads to a logic low voltage source. Enable terminals on the loop gates 70 are commonly connected to the output o~ a NOR gate 71 and when neither the micro clock (MICRO 5) nor the MAP
line 58 are at a logic low voltage, the gates 70 are enabled.
This occurs, for example, when a multiply or divide is to be performed and the register/counter within the micro-program controller 60 is preset to the value of the multi-plicand or the divisor.
Referring particulaxly to Fig. 3, the central processor unit 40 performs the logical and arithmetic functions indi cated by the microinstructions. Each four-bit microprocessor slice 43 and 44 connects to outputs on the microinstruction register 61 (MICRO 8-13, 16-18, 24-31) to receive codes that indicate the ~unction which it is to perform. The "carr~ in" terminal ~CN) on the microprocessor slice 44 connects to the "carry out" terminal (CN+4) on the micro-processor slice 43 and the "carry in" terminal (CN~ on the microprocessor slice 43 connects to the output o~ an OR

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gate 75. The OR gate 75 is connected to the MICRO 14 line and to the output of an AND gata 76. A "carry out"
terminal (CN+4~ on the microprocessor slice 44 connects to an OR gate 77, and clock terminals (CP) on both micro-processor slices 43 and 44 connect to a clock line (CL LO).As shown in Fig. 2A, the signal on the clock line (CL LO) is derived from a NAND gate 78 which is driven by the 5 mHz OSC line 63 and the micro clock ~MICRO 5~..
The microprocessor slices 43 and 44 have three ad-ditional "status" oriented outputs F3, F=0 and OVR. The F3output is the most signi~icant (sign) bit, the F=0 output goes high when all bits are zero and the OVR output goes high when an arithmetic operation exceeds the available two's complement number range. The F=0 outputs on both microprocessor slices 43 and 44 are connected to a D2 input on a 6-bit status latch 79. The F3 output and the OVR output on the microprocessor slice 44 connect to the D3 and D4 inputs on the status latch 79 and its CN input connects to the D6 status latch input. The output of OR gate 77 connects to the D5 input on status latch 79 and the status latch Dl input is driven by the INT REQ line 80 through an inverter 81. The status latch 79 is clocked in synchronism with the microprocessor slices 43 and 44 by the CL LO clock line, and after each micxoinstruction is executed, the status of the microprocessor is stored and generated at a set of status latch output terminals Ql--Q6.
Referring particularly to Figs. 2A and 3, five Gf the six status latch outputs connect to inputs D0-D7 on an 8~
bit status selector 82. The output of the status selector 82 drives the CC control line 62 that connects to the micro-~9~

program controller 60. The three data select terminals on the selector 82 are driven by microinstruction register outputs (MICRO 8, 9 and 10). During a branch micxoinstruction for example, one of the eight status selector inputs is generated on the CC control line 62, and if the condition of that status bit is true, a branch in the microprogram is to occur. In such case, a target address in the same branch microinstruction is loaded into the microprogram controller 60 through the micro-jump gates 67 to execute the branch operation.
Referring particularly to Figs. 2B and 3, to assis~
the central processor unit 40 in executing programmable controller macroinstructions, a decimal adjust accumulator 85 and a bit pointer circuit 86 are coupled to it through the B-bus 41 and the D-bus 42~ The decimal adjust accumulator is a 512 by 8-bit PROM which has its address input terminals A0, Al, A2, A4, A5, A6 and A7 connected to respective D-bus leads Dl-D7 and which has its eight data output terminals connected to leads B0-B7 in the B-bus 41. Address terminals A3 and A8 on the decimal adjust accumulator 85 connect to respective control lines E~ F CAR 87 and FULL CAR 88. ~ALF
CAR line 87 connects to the Q6 output on the status latch 79 and the FULL CAR line 88 connects to the Q5 output.
The FULL CAR line 88 is also coupled through gates 76 and 75 back to the "carry in" terminal CN on the microprocessor slice 43 and it is coupled through an AND gate 89 and OR
gate 77 to the D5 input on the status latch 79. A carry generated by the decimal adjust accumulator is thus OR'd with any carry generated by the binary arithmetic operation~
The decimal adjust accumulator 85 is enabled during arithmetic calculations by a DAA EN control line 90. The DAA EN control line 90 also connects through an inverter 91 to a second input on the ~ND gate 89. The arithmetic data operated upon by the central processor unit 40 is in binary coded decimal, whereas the microprocessor slices 43 and 44 only add and subtract binary nu~bers. It is the function of the decimal adjust accumulator 85 to adjust the eight-bit result of an arithmetic operation which appears on the D-bus 42 along with the carry bits which appear on lines 87 and 88, to generate the proper arithmetic result as two BCD digits on the ~-bus 41. More specifically, the decimal adjust accumulator generates 00, 06 r 60 or 66 (Hexadecimal) which is addea to the 8-bit binary number that results from an arithmetic function to convert it to a two-digit BCD number. The contents of the decimal adjust accumulator are listed in Appendix A.
The bit pointer circuit ~6 is a 32x8-bit PROM which has its eight data output terminals connected to the leads ., B0-B7 in the B-bus 41. Four o~ its address input terminal~
(A0-A3) are connected to the respective outputs on a bit pointer code latch 95 and its fifth address input (A4) is connected to a logic low voltage. The four inputs on the latch 95 are connected to the leads B0-B3 in the B-bus 41 and when the latch 95 is clocked by a gate 96, a bit pointer code from a controller instruction is stored therein. This bit pointer code is converted to a mask by the bit pointer circuit 86 in which all but one of eight bits are at a logic low voltage. This mask is generated on the B-bus 41 when the bit pointer circuit 86 is enabled ~hrough a MASK
control line 97. The mask generated by the bit poin~er --2~-~3~

circuit 86 is employed to carry out single-bit calculations which consume a considerable proportion of the calculating time. The bit pointer circuit 86 thus serves to speed up the rate at which the central processor unit 40 can execute S the bit instructions described above.
Re~errlng particularly to Figs. 2A and 4, to enable the controller processor to execute timer instructions, a real time clock circuit 100 is coupled to the data bus 1.
The real time clock circuit 100 includes three series con-nected divide by ten circuits 101-103 which reduce an applied 100 kHz signal to a 100 hertz clock signal. The 100 hertz clock signal is applied to the A input 104 on a four-bit binary counter 105 and the four outputs (QA-QD) on this counter 105 connect to the four inputs (Dl-D4) on an 8-bit latch 106. The counter 105 counts ten milli-second time intervals and when the latch 106 is clocked through a control line 107, the contents of the counter 105 is stored in the latch 106.
The QD outpu~ on the counter 105 also connects to the C input of a D-type flip-flop 108. At the Q output of the flip~flop 108 is a clock signal which changes state once every 0.1 seconds and this is applied both to the D8 input o~ the 8-bit latch 106 and to the input of a divide by ten circuit 109. The output of the divide by ten 109 changes state once every one second and it is connected to the D7 input on the 8-bit latch 106. When a logic low voltage is appliad to the latch lG6 through a TIMER con-trol line 110, the contents of the latch 106 is output to the data bus 1.
As will be explained in more detail hereinafter, each ~L3~Z

time a timer macroinstruction is executed, ~i.e., ~OF, TON, RTO) the state of the real time clock is checked to deter-mine if a time interval has elapsed since the same timer instruction was last executed. When 1.0 and 0.1 time incre-ments are involved, the state of a single~bit (Q7 or Q8on the latch 106) is examined to determine i~ it has changed.
However, this cann~t be done when ten millisecond timer instructions are employed because the timer instruction may not be executed within every 10 millisecond time increment.
Therefore, when a ten millisecond timer macroinstruction is executed, the four-bit binary count (Ql-Q4 on the latch 106) is examined and this count is compared with a previous count to determine how many 10 millisecond time increments have elapsed since the previous scan through the control program.
This will be described in more detail hereinafter in connec-tion with the TON .01 microroutine.
Re~erring to Figs. 2B and 6, the control lines which operate the various elements o~ the programmable controller eminaté from a decoder circuit 115. The signals on the control lines which operate the controller processor ele-ments are derived directly from the microinstruction in the microinstruction register 61. On the other hand, the remaining elements in the programmable controller are "memory mapped" and hence the signals on their control lines are derived in part from the address code on the address bus 3.
Numerous decoding techniques are known in the art and the detailed decoding employed in the pre~erred embodiment described herein is illustrated in Fig. 6.
Referring to Fig. 7, the programmable controller sequentially executes microinstructions stored in the .

-22~

~3~

microprogram PROM 56 to carry out its functions. After power-up, microinstructions are executed ko initialize the system as indicated by process block 116 and then the status latch 79 is examlned to determine if an interrupt request is present as indicated by decision block 117.
A mode switch (not shown in the drawings) is then examined as indicated by decision block 118 to determine if the system is in the "program" mode. If it is, the system re-mains in a loop in which repeated interrupts are generated I0 by the UAR/T 12 and data is entered into the read/write memory 4 by the user and edits are made to this data.
When the system is switched to the "run" mode, it branches to a fetch microroutine which reads tha operation code in the first control program macroinstruction out of the lS memory 4, as indicated by process block 120. This operation code is applied to the mapping PROM 55 which presets the microprogram controller 60 to address the microroutlne which corresponds to that operation code. The microroutine is then executed to carry out the function indicated by the macroinstruction as illustrated by process block 121. The system then loops back to fetch the next macxoinstruction operation code in the control program 10. The sys~em re-mains in the loop until the entire control program 10 has been executed.
The last macroinstruction in the control program 10 is an "END" macroinstruction which is mapped into a micro-routine that performs an I/O scan. As shown in Fig. 7, when this microroutine is executed the system branches at decision block 122 and the first line in the output portion of the I/O image table 8 is output to the first I/O slot as ~z indicated by process block 123. A check i5 then made for an interrupt request as indicated by decision block 124 and data is ~hen inpu~ from the sam~ I/O slot and written in~o a line in the input portion of the I/O image table 8 as indicated by process block 125. A check is again made for an interrupt request as indicated by decision block 126 and then the system loops at decision block 127 to continue the I/O scan. When completed, the system branches back to decision block 117 to completely repeat control program 10 again. It typically takes from 5 to 20 milliseconds to execute the entire control program and perform the I/O scan and this loop is continuously executed while the programmable controller is in the run mode.
The microprocessor slices 43 and 44 include sixteen internal registers S0-S15 which are employed ~or very specific functions during the execution of the control program 10. These functions are listed in Table A.

TABLE A
S0 and Sl Sixteen-bit address of next control in-struction (i.e., macroprogram counter).
S2 and S3 Storage or high and low bytes of operand address.
S6 and S7 Sixteen-bit accumulator I.
S8 and S9 Sixteen-bit accumulator II.
Sll Rung condition register. All ones equal true, zeros equal false.
S12 First branch flag, or rung condition save register.

S13 Rung condition, branch or accumulator.
-~0 S14 Master control relay - when zero all results ~3~0~

forced false, when all ones is inactive.
S15 General register.

As indicated generally above, the macroinstruction operation codes are read out of the control program portion 10 of the memory 4 by the FETCH microroutine which is stored in the microprogram PROM 56. This microroutine is listed in Table B and as will become more apparent hereinafter, this microroutine can be entered at a number of locations which are separately labeled.

TABLE B
FETCH MICROROUTINE
Label Instruction Comment NEWFET Sll=OFF Set Runy Condition register to all ones, or "true"
condition.

NFET+l S12-080 Set first branch flag to indicate that no branch has occurred up to this point in the run diagram.

FET-l S2=160 Preset the high byte of the control instruction operand addxess.

FETCH ADDL Al-Sl-l Set the addxess lines to the ADDH A0=S0-C READ current operation code and initiate memory read. Set registers S0 and Sl to thP
operand address.

Q-3 Set address lines to the operand ADDL Al-Sl~Q IN address and increment Sl and S0 ADDH A0=S0+C IN registers to point the next opera-N=DAT~ MAP IN tion code. Enable mapping PROM
to receive operation code and pre-set microprogram controller 60 to start of corresponding microroutine.

The microinstructions in the FETCH microroutine and the other microroutines stored in the PROM 56 are executed at the rate of one every 200 ~anoseconds. On the other hand, ~25-13~

a "READ" :~rom the memo~y 4 may require a full microsecond, and as a result, after a memory READ is initiated, the data will not app~ar until the ~i~th microinstruction thereafter. During the interim other processing can take place or no-operation microinstructions (CONT) can be executed to mark time.
The FETCH microroutine reads the operation code in a controller macroinstruc~ion and employs it to map to the corresponding n~croroutine which will carry out the required functions. The microroutines or a number o~ representative programmable controller operation codes are listed in Table C. Where the controller macroinstruction includes an operand address, this 8-bit byte of data is then read from the memory 4 and is employed to form a 16-bit address which identi~ies the memory location of the operand. The mlcroroutine per-forms its function, and when it is completed, it branches back to the FETCH microroutine to read out the operation code of the next programmable controller macroinstruction.

TABLE C

Label In9truction Comment BST S12aSl~ IF FIRST BRAMC~ FIA~l, B BST01 MI~S JU~? TO BST0~
S13=S13 OR Sll ELSE UPDATE OR ACCIJM~ATOR
Sll=NOT S13 A~D SET S~ R~G CONDITION
B FET-l BRANCH TO ~ETCH ~IC~OROUTINE
BS T0 1 Q=S l l S12=OF AND Q SAVE R~G CO~TDITION AL~JD C1EAR
FIRST B~ALNCR FI~G
S13~NOT Sll INITIALI2E OR ACCU~LATOR
B FET-l BP~MC~ TO FET~ MICROROUTIN~

~l39 ~'~

TABLE C Continued . . . .
Label Instruction Comment . _ _ BND Q=512 LOOK AT SAVE R GISTE~
Q=0OF AND Q l~ASK OUT lST BST FLAG
B BND0l ZERO JT~MP IF RUNG WAS FALSE
Q-Sll OR Sl3 ELSE LOO~ AT LAST B~ANCH OR ACC~
BND0l Sll=Q SET RUNG COMDITION
Sl2=080 5ET lST BST FLAG
B FET-l BRANCX TO FETC'~ MICROROUTINE

XIC Sll-Sll READ IS ~UMG A~EADY FALSE?
B FET-l Z~RO JUMP IF ALREADY FALSE
ADD~ N=S2 IN S2 HAS HIGH BYTE OF OPERAND ADDRESS
CONT IN
ADDL N-~ATA IN SET ADDL TO LOW BYTE OF ADDRESS
Ç=MASR READ ~EAD MASK S~T UP BY BIT POI~TER
S2=150 PRESET S2 TO ~IGR BYT~ OF I/O
CONT IN I~AGE TABLE STARTING ADDRESS FOR
COMT IN NEXT I~STRUCTION (TO CLEAR EFFECT OF
AN ADX) ~DATA ~TD Q IN R~AD A~TD ~ASK THE BIT DESIR~D
B FETCH NZER JU~ IF BI~ IS "lll Sll-0 ELSE SET R~G CONDITION FALSE
~ FETC~ B ~NCH TO FETCH MICROROUTI~E

XIO Sll-Sll READ IS RUNG ALP~EADY FALSE?
B FET-l ZEXO JUMP IF ALRE~3Y FALSE
ADDH N=S2 I~ I~UT OPE~AND ADD~ESS AND
' CONT IN
ADDL N=DATA IN SET ADDRESS LINES TO POINT TO
02ERA*1D
Q=~ASK ~EAD READ MASK SET UP BY BIT POINTER
S2~l60 PRESET S2 TO HIGH BYTE OF I/O
COMT IN I~GE TABLE STARTIMG ADDRESS
CONT IN
N-DATA SZC Q IN INVERT DATA, THEN MASK DESIRED BIT
B FETCH NZER JUMP IF BIT IS O~P (O) Sll~0 ELSE, SET RUN~ CO~DITION FALSE
B FETC~ BR~CH TO FETCH MICROROUTINE

OTE NaSll .~ND 514 READ RU~G TRUE .3~D MCR INACTIVE?
B OTU0l ZERO JU2~ IF FALSE ( TUR~I OUTPUT OFF) B OTL0l IN JU~ IF TRU~ (TURN O~TPUT ON) -27- .

1~3~

TABL~E C Con~inued....

Label Instruction Co~nent OT~ N--Sll AND S14 READ RU~G TRUl~ AND 2~C~ ACTIVE?
B N~FET ZERO LEAVE OUTP UT ALONE I~ RUNG FALSE
CONT IN
OTI.01 Sll=OFF IN SET RUNG COMDITION TXUE
ADDI, N=DAT~ IN SET ADDRESS LINES TO OPERAND
AI~DH N--S2 RE~ D IN~ EXISTI2~G DATA
Q-~ASR BIT POINT~3R MASK
S12=080 IN SET lST BST FLAG FOR ~IEXT RUNG
S2=160 I~ P~ESET S2 TO HIGH BYT OF I~O
DAT~ Q=DATA OR Q IN IMAGE TABhE STARTING ADDRESS
CONT RE~D WRITE NE~ DATA BACR
CONT WRIT
B FETC~ WRIT BRANCH TO FETCH kIICROROtJTINE

OTUL N=Sll AND S14 READ R~TG TRUE A~tD MCR INACTIVE
B NEWFET ZERO LE~VE OUTPUT AL~t.~G IF RlJ~tG F.~LS}:
OT~01 CONT IN
Sll=0PF I~ SET R~G CONDITION TRUE .
A~DL N=DATA IN SET A~DRESS LINES TO OPERAND
ADD~ N~S2 READ
Q=NOT ~ASX BIT POI~ER L~ASK
S12=080 IN SET lST BST FLAG FOR NEXT R~G
S2-160 I~T PRESET S2 TO ~IGH BYTE OF I/O
DAT~ N=DATA AND Q I~ I~GE TABhE STARTING ADDRESS CONT ~EAD WRITE NE~ DATA BAC~
CONT WRIT
, B FETCH WRIT BRANC~ TO F~TCH MICROROUTINE

Referring particularly to Fig. 1, the 8-bit operand address which accompanies many of the controller instruc-tion operation codes identi~ies a line in the I/O image table 8 or the timers and counters portion 9 of the memory 4. The B-bit operand address is loaded into the S3 register and it serves to select one of 256 lines in a "page" of the memory 4. The pa.rticular page is selected by the 8-bit high addxess byte which is loaded into the S2 register. In prior programmable controllers ~his high address bytP is prese' to a selected value which is the address of the first line in the I/O image table 8 and it cannot be changed by the control program instructions. As a result, the I/O image table 8 and timers and counters portion 9 have in the past been limited in size to 256 lines - that is, the addressing range of the 8-bit operand address in the controller in-structions.
As indicated in the above listed microroutines, the high address byte is present to a "base page" address of 160 (decimal) in the preferred embodiment. Unlike prior programmable controllers, however, this value can be altered by the execution of an ADX macroinstruction. The ADX micro-routine which is e~ecuted each time the ADX operation code is fetched ~rom the memory 4 is listed in Table D.

TABLE D
Label Instruction Comment ~DX CONT READ Read operand of ADX in-CONT struction which is high ,t CONT IN address byte or next controller instruction.

S2=080 IN Set register S2 to high address S2=DATA OR S2 IN byte indicated by ADX operand B FETC~ and branch to FETCH microroutine.

By employing the ADX macroinstruction in the control program 10, the range of the operand address in the con-trol instructions can be increased from 256 lines (8-bit operand address) to 65K lines (16-bit operand address).
The net result of this enh'anced addressing capability is that the I/O image table 8 and the timers and counters portion 9 can be expanded to meet the requirements of any programmable controller application.

~31L39~

It should be noted that whenever the ADX macroinstruction is not present, the high address byte (stored in register S2) is automatically preset to the base page prior to reading the operand. This is accomplished in a number of ways.
Referring to the above microroutine listings, for example, it may ~e accomplished by branching to the label "FET-l" in the FETCH microroutine aftex the execution of the macro instruction interpreter microroutine (see BST and BND). On the other hand, the register S2 may be preset by a specific microinstruction within the macroinstruction interpreter microroutine being executed (see OTL and OTU). When the ADX macroinstruction is not employed, therefore, the S2 register is preset by default to the base page address.
The ADX macroinstruction may be employed before any programmable controller instruction to increase the addressing range of its operand address. It accomplishes this result by loading its own operand address into the register S2 and bypassing any microinstructions which would otherwise preset register S2 to the base page address. The regis~er S2 remains set to this modified address until the operand for the following controller macroinstruction i5 read from the memory 4, after which it is again preset to the base page address. Because the ADX macroinstruction modifies or expands, only the operand address of the controller macroinstruction which follows it, the ADX macroinstruction must be used before each controller macroinstruc~ion which operates on data outside the 256 line base page. In the preferred embodiment the ADX macxoinstruction is auto-matically inserted in the control program 10 by the program panel ll and its use is thus "transparent" to the user.

- ~39~

The manner in which the real time clock circuit 100 and the decimal adjust accumulator 85 operate in the pro-grammable controller can be demonstrated by explaining the mannex in which the programmable controller executes the S TON.01 macroinstruction. As indicated above, each time the TON.01 instruction is executed, a test is made to determi,ne if the "rung" of which it is a part is true. I
it is, a preset time interval is measured and then a selected bit is set high to indicate that the timer has timed out. The TON.01 macroinstruction measures 10 millisecond time increments and it includes an 8-bit operand address which points to an accumulated time and preset value stored in the timers and counters poxtion 9 of the memory 4.
Of course, it is one of the advantag~s of the present inven-tion that this 8-bit operand address can be expanded to ,, 16-bits by the use of the ADX macroinstruction as described above, and hence, the accumulated time and preset value associated with a timer can be stored anywhere in the memory 4.
Referring to E'ig. 9, the operand ~or each TON~01 macroinstruction includes a two byte preset value and a two byte accumulated time. The accumulated time includes three BCD digits which indicate the number of 10 milli-second time increments that have elapsed since timing began and the preset value includes three BCD digits which indicate the number o~ 10 millisecond time incre-ments which must be accumulated before the timer "times out." The three BCD digit preset value is loaded into the memory 4 by the user when the control program 10 is developed using the program panel 11.
Associated with the high byte of the accumulated ~39~;2 time are four status bits which indicate the state of the timer. More specifically, bit seven provides an indication of whe~her the timer has started timing, and bit five indicates whether or not lt has timed out.
Also, associa~ed with the high byte of the preset value is a 4-bit storage location which stores the value o~ the 10 millisecond counter output of the real time clock circuit 100.
There may be one or more TON.01 macroinstructions in the control program 10, and during each scan ~hxough the control program 10 each of these are executed. A listing of the TON.01 microroutine is provided in Table E and a flow chart of this microroutine is illustrated in Figs.
8A and 8B. Re~erring ~irst to this flow chart, the opera-tion code for the TON.01 macroinstruction is mapped intoits corresponding microroutine which is entered at 130.
Microinstructions indicated by process block 131 are then executed to input data from the real time clock ciruit 100 and the preset value high byte is read ~rom the memory 4 and stored in the microprocessor as indicated by process block 132. The new real time clock value is then written into the preset value high byte for use when the timer macro-instruction is executed next as indicated by prQcess block 132'. The status of the ladder diagram rung of which the timer is a part is then examined as indicated by decision block 133. The rung status is stored in the register Sll, and if conditions are not proper for the timer to operate, the register Sll is zero and the system branches at decision block 133. In such case, zeros are wxitten into the accumulated time low byte and high byte as indicated by process blocks 134 and 135 and the system branches back to the FETCH micro-routine as indicated by process block 136.
When conditions are proper for the timer to start or continue timing, as determined at decision block 133, the high byte of the accumulated time is read out of the memory 4 as indicated at process block 137. Bit 5 of this high byte is checked to see if the timer has timed out, as indicated by decision block L38, and if it has, the micro-routine branches. Otherwise, the accumulated time low byte is read from the memory 4 as indicated by process block 139. The previous value of the ten millisecond counter, which forms part of the preset value high byte, is then compared with current value of the ten milli-second counter. If no change has occurred (i.e., the control program scan time is less than ten milliseconds) the microroutine branches at decision block 140. Otherwise, the preset value low byte is read from the memory 4, as indicated by process block 141, and the change in the ten millisecond real time clock is then added to the three digit accumulated time number as indicated by process block 142.
The accumulated time low byte is then written back into the memory 4 as indicated by process block 143 and the three digit accumulated time number is then compared with the three digit preset value numberO As indicated by decision block 144; if the accumulated time has reached or exceeded the present value, the "timed out" bit tbit 5~ in the accumulated time high byte is set to "one" as indicated by process block 145. In either case, the accumulated time high byte is written back into the memory 4 as indicated by process block 146 and the system then branches to the FETCH microroutine to read the next macroinstruction from the control program.

t.3~

- 'rABLE E

Label Instruction Co~mnent TON0 1 BL TIMER READ CALL TIME~ SUBROUTINE AND
ST~RT OPERAr~D ADDRESS READ
S6=0 N=Sll A~D S14 CHECK IF RUNG IS T~U:E AND
L~CR I S IN~CTIVE
B CLE~CC ZE~O JU2~ IF EITHER IS F~LSE
TON00 S3=S3-1 SET S3 TO PRESET VALUE LOW
BYTE ADDRESS
ADDL S 3aS 3--1 READ SET ADDL--$ 3 = ACC ~I BYTE
ADDRESS
S3=S3-1 SET S3 TO ACC LOW BYTE ADDRESS
52=020 IN MASX FOR TI.~ED OUT BIT
ADDL A3=S3+1 IN SET ADDL= ACC LOW, S3 = ACC HI ADD
Q--DP.TA IN STORE ACCUMULATED TI.~ IG~ BYTE
IN Q REGISTE~
S 3--S 3+1 READ SET S 3 TO PRESET VAI,UE LOW BYTE
Al)DRESS
S6=02F ~ND Q SAVE ACC HI BYTE ~ITH TIMED OUT
BIT
N~S2 AND Q IN LOOK AT TI~ED OUT BIT
B SETTON NZER IN JUMP IF PREVIOUSLY TI~:D OUT
S 7=DATP. IN STQRE ACCUMULATED TIL~E LOr~ BYTE

Q=SlS - S9 SU:BTRACT Ol,D CLOCK BITS PROM

B SETTON ZERO JU~ TO SETTON IF NO CHANGE I~J
10 MSÆC CLOCK
B NOINC CARR ~UMP TO NOINC IF RESUL~ IS POSITIVE
Q=OA0~Q OTHE~WlSE, ADD 10 TO MARE IT POSI-TIVE

SET, S 3-- ACC TI'ME HIG~ BYTE
ADDRESS
R15=~ STORE C~TGE IN 10 MSEC CLOCR IN
~15 R15=S15 IN S~IFT lû MSEC C~OCX BITS
Rl 5=S l; IN
S9=DATA IN LCAD PRESET VALUE I,06~ BYTE INTO 59 Rl 5=SlS

T~BLE E Corltinued....

Label Instruc_ion C~r~ent 57--S7~S15 ADD C:~ANGE IN 10 MSEC CLOCK TO
ACCUMVI.ATED TI.~: I.OW B'L'TE
A7=DAA+S7 ADJUST TO B~D USING DECIM~
ADJUST ACCUMUIATOR
S 6=S 6+C ADD CARF.Y OUT TO ACC~MULATED
TIME HIGH BYTE
A6=DA~S 6 ADJUCT TO ~CD - .
~DL 5 3=S 3-1 ~EAD ADDL = S 3 = ACC TIME LOW BYTE
ADD~:S5 DATA ~ 7=S 7 WRXT WRITE ACCUMULATED TIME LOW BYT~
BACX INTO ME~qOP~Y
--S6-S 8 WRIT CO~IPARE ACC TO PÆSET
B ST17 NCAR JU~ IF ACC ~ PRESET
}3 TOU~ NZER JU~? I.F ACC ~ PRE:SE:T
N=S7-S9 E~SE CHEC'~ LOW BYTES
B ST17 NCAR JU~P IF ACC c PRE$13 TOUT S6=S6 OR S2 SET TIMED OUT BIT I~T ACCUMUL~T33D
TIME HI GE E~YTE
S~'17 S12a080 SET lST BST FLAG
ADDI~ 5 3--S 3~1 READ ADDRESS ACCUMULATED TIME ~IIGT~
BY~E MEMORY LOCATIOM
DATA N=S6 OR S12 WRIT WRITE ACCUMULATED TIME HIÇ~
BYTE I~JTO ~ ~qORY
B FET-1 WRIT JU~P TO FETC~ ~q~ CROROUTI~JE
SETTON S3=S3-1 SET S3 TO ACC EIIGH BYTE ADDRESS
S3=S3-1 SET S3 TO ACC hOW BYTE ADDRESS
B STl 7 CL~ACC ADDL S3-S3-Q READ SET ADDL TO ACC LOW (Q = 3) - DATA N=0 WRIT 2:ERO IT
511 Sll-Sll-l WRIT INITIALIZE RUNG COND TE~ FF~
S2=160 DEFAULT OPERAMD E~IGH ADDP~F.SS
S12-080 SE'r lST BST FI~G
DATA NaS6 WRIT WRIT~ ~ERO INTO ACC HIGH
B FETCH WRIT JUMP TO FETCH MICRO:ROUTINE

TI~IER S 7=#P~TC I.OAD REAL TIME CLOC~ P~DDP~ESS
S 6- ~IO IN l NTO S 7 AND S 6 S 3=OFC IN
S 3=DATA A~D S 3 I~ ~qASK 2 LSB OFF OF OPERAND ADDRESS
ADDEI S6=S6 SET ADDRESS I~I2`lES TO REAI) ADDL N=S7 READ REAL TIME CLOC~ AND STORE
S15=DATA I~ REAh TINE CLOCX DATA IM S15 ADDH S 2=S 2 ADDL S 3=S 3+Q ~AD ~AD PRESET ~UE HIGsI BYTE
S9~OFO
S15 S15 A~D S9 IN MASK ALL Bt~T 10 MSEC CLOC~ DATA
S 8=OF IN MAS~ FOR PRESET VALUE
S 7=DATA I~ STO~ PPESET ~rALuE HIGH BYTE
I~;T S 7 S8=S8 ANI) S7 READ STO~E M5B OF PR:ESET VALUE IN S8 DATA N--S8 OR Sl~ WRIT OR P~SET WITH NEW 10 klSEC CLOCX

S9-S9 ~a~D S7 RT STOPE OLD C~C)CT.~ ~ITS I~ S9 and WRIT RETURN

The decimal adjust accumulator is employed in the TON.01 microroutine to add the change in the ten milli-second real time clock counter to khe accumulated time number. The accumulated time number is comprised of thre~ BCD digits (LSBCD, MBCD, MSBCD) and the micro-processor slices 43 and 44 only add binary numbers. Con-sequently, after each addition the result is applied to the decimal adjust accumulator 85 through the D-bus 42 and the number which is generated by the decimal adjust accumulator 85 on the B-bus 41 is added to the result to convert it to BCD. This is represented in the TON.01 microroutine by the microinstructions A7=D~A+S7 and A6=DAA+S6. It should be apparent, therefore, that the decimal adjust accumulator enables the adjustment to be made with a single 200 nanosecond microinstruction.
Although this saving in execution time is not substantial in the TON.01 microroutine, it does become significant when axithmetic functions are performed such as ADD, SUB-TRACT, MULTIPL~ and DIVIDE.
A microprogrammed pxogrammable controller has been described which provides a number of advantages over prior programmable controllers. It should be apparent to those skilled in the art, however, that the address expansion provided by the ADX macroinstruction and the ten milli-second timer provided by the TON.01 macroinstruction could be embodied in other well known progxammable con-troller structures. Consequently, reference is made to the following claims for a definition of the scope of the inventionO

~ ~L39a~0;Z

COMPONENT APPEMDI~

Reference Manu~acturer &
~o. 3~ be- ~

Memory 4 Harxis Semiconduc- lK by 1 or 4X ~y 1 tor H~-6508 CMOS RAM's U~R/T 1~ ~dvanced M~cro- Programmable Communications devices AM9551DC Inter~ace (US.~RT) UAR/T Data Texas Instxuments Octal Buffers/Line Drivers/
Gates 1~ S~74LS244N Line Receivers I/O Address Texas Ins~rumen~s Dual Peri~heral Positive-Ga~s 26 SN75452B Nand Drivers I/O Data Advanced Micro- Quad Bus Transceiver Gates 33 devices A~2907PC
Micro- Advanced Micro- 4-Bit ~ipolar Microprocessor processor devices AM2901APC Slice Slices 43 and 44 Data In Texas Instrume~ts Octal Burrers~Line Dri~ters/
Gates 45 SN74LS244N Line Receivers Data Out Texa~ Instruments Octal D-Type Latches ~a~ch 47 S?l74S373N
Address Texas Instruments Octal D-Type Latches ~igh Latch S~T74S373N

Address Texas Instruments Octal ~-Type Latch~s Low Latch SN74S373N

Mappin~ Texas Instruments P~OM 55 SN74S471N 256x8 PROM
$~74S287N 256x4 1024 Bit ~ROM
Micro- Sign~tics l~x8 Bipolar PROM
program ~82S181N

Micro- Advanced Micro- ~icroprogram Controller program de~ices AM2910DC
Controller ~0 '~Iicro- Texas Instruments instruction SN74LS174N ~ex D-Type Flip-Flo~s Register 61 SN74LS175N ~ua~ D-~ype Flip-Flops ~icro-~ump Texas Ins~ruments Hex Bus Dri~ers Gates 67 SW74LS367N

0~2 COMPO~NT APPEMDIX Continued...

Reference r~anufacturer &
No. Serial Number Description Im~edi~ts Texas Instruments Octal Bu~ers/Line Drivers/
Gates 68 SN74LS244N Lir.e Receivers Loop Gates T~xas Instruments Hex Bus Drivers Status Texas Instruments Hex ~-Type Flip-Flop Latch 79 S~T74LS174N
8-Bit Status Texas I~s~ruments 1 of 8 Data Selectors/
5el~ctor 82 SN74LSl51N Multiplexers Decimal Texas Instruments 512x8 PROM
A~just SN74S472N
Accumu-lator 85 Bit Poin~er Te~as Instruments 32x8 256 Bit P~OM
Circuit 86 SN74S288N
Bit Pointer Texas Instruments Quad D-Type Flip-Flops Code Latch SN74LS175N

Counter 105 Texas Instr~ments Dual Decade Counters S~74LS390N
8-8it La~ch Texas Instrumen~s Octal D-Type Flip-Flops - ~3~ 2 APPENDIX A

~le2a~
Dec~nal Add:ress Conter.ts . .

0020 00 ao oo oo oo 06 06 06 06 G6 06 06 06 06 06 06 0030 00 00 00 00 00 06 06 Q6 06 06 06 06 û6 06 06 06 0~50 00 00 00 00 00 06 06 06 06 06 06 06 06 06 06 06 0060 00 00 00 00 00 06 ~6 06 06 06 06 06 06 06 06 06 0070 00 00 00 00 00 06 06 06 06 ~6 06 06 06 06 06 06 0080 00 00 00 00 00 ~6 06 06 06 06 06 06 06 06 06 06 OOCO 60 60 6~) 60 60 6~ 66 66 66 66 66 66 66 66 66 66 OOW 60 60 60 60 60 66 66 66 66 66 ~6 66 66 56 ~6 66 0100 60 60 60 60 ~0 66 66 66 66 66 66 66 66 66 ~ ~6 0120 ~ 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 0140 60 6û 60 60 60 66 66 66 66 66 66 66 66 66 66 66 0150 60 60 60 60 60 66 66 66 ~6 66 66 66 66 66 ~6 66 01~0 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 OlAO 60 60 ~0 60 60 66 66 66 66 66 66 66 66 66 66 66 01~30 60 60 60 60 60 66 66 66 66. 66 66 66 66 66 ~6 66 OlC0 60 60 60 60 60 66 66 66 66 66 66 66 66 56 66 66 OlD0 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 OlE0 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 OlP0 60 60 60 ~0 ~0 66 66 66 66 66 66 ~6 66 66 66 66

Claims (5)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A programmable controller which comprises:
a random access memory having n+m address input terminals and a set of data terminals, said random access memory storing an I/O image and data table comprised of a base page portion stored on selectable memory lines and an ex-tended portion stored on other selectable memory lines;
control program storage means for storing control in-structions having an operation code that indicates a function to be performed and an n-bit operand address that indicates a selected line in said random access memory;
an address bus having n+m leads connected to respec-tive ones of said n+m address input terminals on said random access memory, a data bus having leads connected to said set of data terminals on said random access memory; and a controller processor which includes:
(a) address low storage means having outputs coupled to the n leads in said address bus;
(b) address high storage means having outputs coupled to the m leads in said address bus;
(c) means coupled to said control program storage means for sequentially reading the control instructions therefrom;
preset means coupled to said address high storage means for storing therein an m-bit base page address number;
means responsive to the operation code in a control instruction read from said control program storage means for storing its associated n-bit operand address in said address low storage means and reading a line of data from said I/O image and data table which is selected by the n+m bit address stored in said address high and address low storage means; and means responsive to a selected one operation code (ADX) in a control instruction read from said control program storage means for storing its associated n-bit operand address in said address high storage means and decoupling said preset means from said address high storage means;
wherein control instructions preceeded by a control instruction containing said selected one operation code (ADX) may read data from the extended portion of said I/O image and data table and control instructions which are not pre-ceeded by a control instruction containing said selected one operation code (ADX) may read data from the base page portion of said I/O image and data table.

2. The programmable controller as recited in claim 1 in which n equals eight and m equals eight.

3. The programmable controller as recited in claim 1 in which said control program storage means forms part of said random access memory.

4. The programmable controller as recited in claim 1 in which said controller processor is a microprocessor which executes instructions stored in a read-only memory o carry out its functions.

5. The programmable controller as recited in claim 1 in which said data bus is coupled to a plurality of sets of I/O circuits that connect to a controlled machine and said address bus is coupled to each of said sets of I/O circuits, and in which data is periodically coupled through said data bus from selected lines of said I/O
image and data table to each set of I/O circuits.