CA1133133A - Non-volatile memory devices fabricated from graded or stepped energy band gap insulator mim or mis structures - Google Patents

Non-volatile memory devices fabricated from graded or stepped energy band gap insulator mim or mis structures

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Publication number
CA1133133A
CA1133133A CA335,224A CA335224A CA1133133A CA 1133133 A CA1133133 A CA 1133133A CA 335224 A CA335224 A CA 335224A CA 1133133 A CA1133133 A CA 1133133A
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Prior art keywords
layer
insulator
silicon
band gap
metal
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CA335,224A
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French (fr)
Inventor
Roger F. Dekeersmaecker
Donelli J. Dimaria
Donald R. Young
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Abstract

NON-VOLATILE MEMORY DEVICES FABRICATED FROM
GRADED OR STEPPED ENERGY BAND GAP
INSULATOR MIM OR MIS STRUCTURES

Abstract of the Invention New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.

Description

~33~3 NON-VOLATILE MEMORY DEVICES FABRICATED FROM
GRADED OR STEPPED ENERGY BAND GAP
INSULATOR ~i~ OR MIS STRUCTURES

Background of the Invention The present invention generally relates to improved semiconductor devices which use a graded band gap structure to promote the injection of holes or electrons at one interface of an insulator, while, simultaneously, electron or hole injection from the opposite interface is blocked and which use a trapping layer to capture holes or electrons with 100~ efficiency. More particularly, the present invention, in a preferred embodiment, relates to a graded oxide metal-silicon dioxide-silicon (GO~OS) semiconduc.tor structure which is useful in forming a more efficient memory function.

~` FET memory devices are known in the art. One such device employs a M1112S str~cture wherein 1l and 12 denote first and second insulator layers. The 11I2 interface may include a metallic impurity which provides a well-defined electron trapping region. The presence or absence of ~rapped e!ectrons in this region is used to define a memory function either by different values of capacitance of the structure or by monitoring the value of source-drain current as affected by the Yog78-oo7 "~

~133~3~
trapped electron charges in the ~resence of suitable applied gate voltages. Metallic impurities are not always requ;red at the 11I2 interface as the same effect can be realized by using two different kinds of insulatars.
For example, one such known device employs an MNOS structure where a thin oxide film is first formed on a silicon substrate, and over this thin oxide film is laid a much thicker silicon nitride film. In this structure, electrons or holes are trapped in the silicon nitride layer. There is a disadvantage associated wiLIl this particular structure, however, and that relates to the thin oxide layer. This oxide layer must be quite thin, on the order of about 20 R thick, in order to allow tunneling of the electrons or holes from the Si substrate.
Reliability problems have been encountered with memory devices with this thin tunnel oxide layer because of the - high fields across it during operation.

U. S. Patent No. 4,104,675 and assigned to a common assignee discloses a device which uses a graded band gap structure to make a charge storage device wherein - iniection of holes or electrons from one contact is possible without simultaneous injection of electrons or holes from the other contact. The patent shows a structure ~ employing the band gap reduction in an GOMOS FET which `~ 25 performs a memory function. The GOMOS structure employs hole trapping near the Si-SiOz interface with the structure in an FET configuration. The "write" step involves hole injection from the gate electrode under moderate positive voltage bias and transport to the Si-SiO2 interface where some of the pos;tively-charged holes are trapped in a very stable manner. The "erase" step Yog78-007 3 ~.~33~3~

1 involves electron injection from the gate electrode under moderate negative voltage bias and transport to the Si-SiO2 interface where the electrons would annihilate trapped holes very readily. The "read" operation uses the conductance of the silicon surface to sense the charge state o-f the oxide region near the Si-SiO2 interface and uses low gate voltages to prevent further charging of this region.

The band gap graded structure may be fabricated by forming several pyrolytic or CVD SiO2 layers over a relatively thick thermal SiO2 layer with the pyrolytic SiO2 layers having se-quentially increasing excess Si content. The structure may also be fabricated by controlled Si ion implantation in the thermal SiO2 layer. The structure can also be fabricated using Plasma deposited layers of SiO2 graded with Si. Other insulating layers which give an enhanced carrier injection from the gate electrode due to actual band gap reduction or effective band gap reduction (for instance, by trap-assisted tunneling) are also possible.
The devices having the structure shown in U.S. Patent 4,10~,675 have the disadvantages of having the charge trapping region being process dependent, suffer from surface state build-up àt the Si-SiO2 interface due to the passage of holes, are sensitive to "hot" carrier injection from the Si substrate due to the presence of the trapped holes, and require hole injection and trapping to be the first operation since these traps do not capture electrons without the presence of the holes first.

Y09-7~-007 ''~,D
~,~

4 ~33~L33 1 Summary of the Invention The present invention uses an improved graded band aap structure to make a charge storage device wherein injection of holes or electrons from one contact is possible without compensating injection of electrons or holes from the other contact. The improvement is the inclusion of a charge trapping layer in the thick insulator region adjacent to the silicon semicon-ducting body. The trapping layer is situated at a distance of approximately 50A or more from the Si-insulator interface to prevent trapped carriers from tunneling from this layer to the Si substrate.
:, .:
This trapping layer captures and stores either electrons (write operation) or holes (erase operation) with as close to 100%
,, ; efficiency as possible, unlike the prior art device of U.S.
Patent No. 4,104,675 which is capable of trapping holes only.
Electrons will annihilate these trapped holes, but they are not captured when the hole traps are empty and in a neutral charge state. In the present invention, the write and erase ` 20 operations can be interchanged if holes are injected ~irst to write and the electrons are used to erase.

The band gap structure may be fabricated by the method dis-closed in the above-mentioned U.S. Patent No. 4,104,675. The structure is fabricated by forming several pyrolytic or CVD
SiO2 layers over a relatively thick thermal SiO2 with the pyrolytic SiO2 layers havinq se~uentially increasina excess Si content. The trapping layer may be formed by controlled impurity ion-implantation, by diffusion of the impurity into the relatively thick thermal SiO2 layer, or by deposit-ion of the impurity on thermal .,, ,.,~

~33~L33 SiO2 with stoichiometric CVD SiO2 isolating it from the injector region consisting of the Si rich CVD
SiO2 layers.

: Brief Description of the Drawings :~

FIG. l(a-c) are zero field energy band diagrams for ; prior art MIS structures, stepped insulator MIS (SIMIS) -~ structures, and graded insulator MIS (GIMIS) structures, :~
respectively.

FIG. 2(a-c) are energy band diagrams for nega~ive gate ~-bias electron injection from the gate electrodes for the structures represented by FIG. 1.

-~ FIG. 3 is an energy band diagram for negative gate bias for a GIMIS structure showing electron injection and ~ subsequent capture in a purposely introduced charge :; 15 trapping layer in the wide band g~p insulator near the insulator-silicon interface.

FIG. 4 is a diagram depicting the high frequency capacitance as a function of the gate voltage for a SIMIS structure (a) an as fabricated virgin SlMiS, (b) after electron 20 ;n)ection and trapping, and (c) after hole injection ~:
and trapping.

FIG. 5 is a cross-sectional view of a SIMIS FET
structure according to the invention.

FIG. 6 is a cross-sectional view of a GIMIS FET
25 structure according to the invention.

Description of the Preferred Embodiment A novel type of semiconductor device ~hich can be used for electrically-alterable-read-only-memory (EAROM) is Yog7a-0o7 6 ~33~33 described. This device is formed by stepping or grading the energy band gap near the metal gate electrode of a metal-insulator-semiconductor (MIS) structure as shown in FIG. Ia.

FlGs. Ib and Ic are il1ustrative of the structures of the present invention. With these types of s.ructures electrons or holes can be injected from the gate electrode more easily into the insulating layer with less applied voltage. The stepped or graded regions - 10 in this drawing are kept thin compared to the thermal oxide region to minimize the effects of trapped space charge in the graded or stepped regions on the electric fields at the interfaces which control carrier injection and charge sensing.
. ,.
FIG. 2 is illustrative of the ease oF injection. It shows the effect of negative gate voltage bias (electron injection) where the average electric field in the bulk of the wide band gap insulator is the same for FlGs. 2a, b and c.
Clearly, the GIMIS FIG. 2c structure is a better injector than the MIS (FIG. 2a) or SIMIS (FIG. 2b) due to the smaller energy barrier at this interface and therefore shorter tunneling distance. The band distortion in the stepped or graded region is t~pical fr~r real istic materials which all have hiqh~r di~lectric consta~ts than ci~2.

Elec;ron or hole injection from the semiconductGr substrate will not simultaneously occur due to the larger energy band gap (see FIG. 1) that those carriers "see"
fo! the same average electric fields that produce injection (via tunneling) from the top gate contact.

Using the graded or stepped energy band gap insulator-~lS
system, a non-volatile semiconductor structure can be fabricated which uses the substrate Si-insulator Y~g78-oo7 ~33~L33 interface strictly for sensing storagc charge ("read:' operation) in a purposely introduced charge trapping layer in the wide energy band gap insulator (as shown in FIG. 3). Ion implanted As and P, deposited W less than a monolayer thick, and deposited polycrystalline - silicon can be usPd for this trapplng layer which will capture either injected electrons or holes. The "write"
("erase") operation is achieved by electron (hole) injection or vice versa at low to moderate average electric fields (2-5 MV/cm are typical) from the gate electrode for negative (positive) voltage bias, and the subsequent ~; capture of preferably all injected electrons (holes) in the trapping region. This separation of sensing and charging operations makes this structure unique compared to other types of non-vola~ile memory structures, or their variations, such as floating-gate-avalanche-injection-metal-silicon dioxide-semiconductor (FAMOS) or metal-silicon nitride-silicon dioxide-semiconductor (MNOS) structures. GIMIS and SI~IS
devices also potentially have other advantages over these EA~OM structures. Some of these are the following:

1. Low voltage is required. Local fields at the - substate Si-insulator interface are low, interface state generation should be minimized, and this interface should not deteriorate. MNOS structures are believed to deteriorate with cycling due to high electric fields at the Si-tunnel SiO2 interface. Low power is also required for the GIMIS or SIMIS structures since large Si currents are not required as in EARO~s which use avalanche injection from the Si to charge traps such as FA~OS structures.
2. Interface state generation or trapped charge build-up at the 5i-SiO2 interface due to "hot" carrier injection from the Si substrate will no~ occur. FAMOS

Yog7a-0o7 ~33~33 structures or their variations have these problems which limit the number of cycles they can be put through.
3. GIMIS or SI~IS structures can be electrically "erased" in place in short times with the same type of charge retention as FA~OS devices. FAMOS-like structures are difficult to erase and require ultra-violet light and long times (minutes to hours) to photodetrap electrons on the floating gate embedded in the SiO2 layer.

In one embodiment of the invention a structure is fabricated to demonstrate GIMIS or SlMiS type operation. The structure fabricated is a variation of an ~NOS device.
However, unlike the ~NOS structures which have a thick Si3N4 trapping layer to store charge~and a thin tunnel oxide of ~20-30 R thickness grown on the Si substrate, the SII~IS devices have thick oxide and thin nitride layers. The thin 5i3N4 layer (5.2 eV band gap, 7.5 low frequency dielectric constant) is used as the electron or hole injecting layer and not a charge storage layer as in a standard MNOS structure. The energy band diagram for the type of SIMIS structure is similar to that shown in FIGS. lb and 2b. The thermal SiQ2 layers (9 eV band gap, 3.9 low freque~cy ;~
dielectric constant~ in these 5IMIS str~lctures were grown on <100> 2 Qcm p-type Si substrates at 1000C in 2 to thicknesses between 400-1300R. The Si3N4 layers are chemically vapor deposited (CVD) to thicknesses between 25-600A at 810C with a NH3/SiH4 ratio of 150/1 on top of the SiO2 layer.

The charge trapping region is formed in the thick SiO2 layer by using ion implanted As prior to the Si3N4 deposition. After implantation a 1000C
anneal in N2 for 30 min. is performed to remove radiation damage followed by a 500C fomning og78-007 ~33~.3~

gas anneal for 30 min. to reduce surface states at the Si-SiO2 interface. Then the SiO2 surface is cleaned of metals and hydrocarbons. Finally, an Al metal gate electrode is deposited on top of the Si3NL~layer.

FIG. 4 shows the "write" and "erase" operation of one of these SIMIS structures. This structure was formed from a 1334A SiO2 layer and a 298R Si3~4 layer. An As implant at a fluence of 1 x 1016 ions/cm2 at an energy of 40 keV was used to form the trapping region for electrons and holes. This heavy fluence was used to insure 100~ trapping of injected carriers. Lighter fluences, which were also studied, were not as effective.
Negative (positive) gate voltages, producing a moderate average field in the SiO2, were used to inject electrons (holes) which were trapped on As-related sites. This rmoved the high frequency (1 MHz) capacitance-voltage curves to morc positive (negative) voltages due to the change in the internal electric fields as sensed by the Si substrate.
Without the trapping region, no significant charge storage effects were seen under the conditions listed in FIG. 4. The Si3N4 layer was kept as thin as possible relative to the oxide layer to minimize trapped space charge effects in this layer which would limit injection efficlencies.

Scaled down s~ructures similar to that in FIG. 4 with an oxide thickness of 550R and a nitride thickness of 50R were also fabricated. The trapping layer for these was formed using a 10 keV implant to prevent n-type doping 30 of the p-type Si substrate with As. Thinner oxide layers were not possible due to this doping effect, and lower energy irnplants at fluences of I x 1016 ions/cm2 were also difficult due to the implantation times involved.
Other structures with oxide and nitride thicknesses and ion energies between this and those in FIG. 4 were Yo978-Co7 also fabricated. All structures behaved in a fashion similar to that in FIG. L~ for comparable conditions with applied voltage renuirements decreasing with insulator thickness.

The SIMIS structures described (see FiG. 5) here having ion implanted oxide layers and an injecting layer of smaller energy band gap Si3N4 can be cycled reproducibly between the "written" and 'ierased"
states after the first Few cycles. Once written, "read perturb" effects at room temperature were fairly low with only a small percentage of trapped electrons being lost or compensated at the low average fields requ;red for actual read operations in a field effect transistor (FET) structure.

Some preliminary FET struçtures were fabricated using a floating polycrystalline Si charge storage layer, on thermal SiO2 with thin CVD
SiO2 and Si3N4 layers between it and a top gate -electrode also o~ poly-57. These structures switched as would be expected for SIMIS operation at voltages as low as 15V with Minimal "read perturb" at voltages ~6V.

It should be noted that in these floating gate type structures there may be injection regions, separate and apart from the gate region.

As seen in FIG. 2, a GI~IS structure is a more eFficient carrier injector than a SIMIS structure.
A graded band gap is pictured as a stepped band gap with an infinite number of steps.

Another type of injector using a CVD or plasma deposited SiO2 layer with increasing Si content and therefore decreasing energy band gap and resistivity can also be fabricated. CVD structures were ~' 3~33 shown to be extremely efficient electron injectors and fairly good hole injectors. In these structures, 3 IC6 times the electron current and ~10 times the hole current were observed for the same 3 5average thermal SiO2 electric fields as compared to s~ructures without the Si rich CVD SiO2 injecting layer.

Other materials to srade the SiO2 layer to a metal or poly-Si gate electrode contact with low frequency 10dielectric constants equal to or less than that of thermal SiO2 which has a value of 3.9 are desirable.

The best possible GIMIS structure would require complete grading of SiO2 to a top gate electrode of polycrystalline Si. This can be accomplished 5using low temperature plasma deposition techniques as opposed to GVD deposition techniques in which only 10% Si at most can be incorporated into the SiO2 film.

GIMIS devices can be fabricated according to the method disclosed in U. S. Patent No. 4,104,675 commonly a,si~ne~i. T~ricallv, the fahrication is as follo~s:

Starting with a single crystal silicon subs;rate, a relatively thick thermal SiO2 insulator laycr is grown.
Over this thermal oxide insulator layer are deposited successive pyrolytic or chemical vapor depos tion (CVD) SiO2 layers. In FIG. 6, three such layers are shown, but any number of layers may be used. Each pyrolytic oxide layer is relatively thin compared to the overall thermal oxide insulator layer; and each successive pyrolytic oxide layer has an increasing amount of excess silicon. It is known that pyrolytic oxide layers can be formed with excess silicon as described, for example, in U. S. Patent ~o. 3,649,884. Ihe Yog78-007 ~3~33 number of pyrolytic layers, the thickness of each layer, and the amount of excess silicon in each successive layer is a matter of design choice.

The thick oxide layer is ion implanted to form a trapping layer as described above for the SIMIS
type structure. A trapping layer can also be formed by diffusing or depositing an impurity such as W prior to CVD SiO2 deposition. This impurity would be isolated from the graded injector region with a stoichiometric CVD SiO2 layer.

While the invention has been described in terms of preferred embodiments, those skilled in the art will understand that various modifications can be made in the practice of the invention wi~hout departing from the SCOI)e Or LhC appcndcd claims. For ~XanlPIe, ;1l~l10U9l1 i the preferred embodiment of the invention has been described in terms of MNOS and MOS structures, the teachings of the invention are equally applicable to ;~
metal-insulator-metal (MIM) or MIS structures. Moreover, while the gate structure of the preferred embodiment has been described as comprising an aluminum contact, those skilled in the art will recognize that other metals or semiconductors could be used. Specifically, polycrystalline silicon could be deposited over the pyrolytic oxide layers to form the gate electrode contact.

`~og78-007

Claims (18)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A metal-insulator-metal or metal-insulator-semiconductor structure including:
a first portion of an insulator layer having a reduced band gap at a first interface with a first metal layer so as to pro-vide an injection region for either holes or electrons as deter-mined by a voltage bias applied to said structure so as to enable holes or electrons to be injected into said insulator layer from a contact at said first interface under low to moderate field conditions, a second portion of said insulator layer having a large band gap near a second interface with a second metal or a semiconductor layer to thereby block electron or hole injection from said insu-lator layer's second interface, said second portion of said insulator layer including a charge trapping layer embedded within said insulator layer near said second interface, said trapping layer capturing and storing in-jected electrons or holes with high efficiency.
2. The structure of claim 1 further including a silicon sub-strate for supporting said insulating layer at said second inter-face, said insulating layer having a first relatively thick in-sulator portion which has embedded therein a layer of impurity atoms proximate to said insulator layers second interface at said substrate, and said thick insulator having a decreasing band gap in the vicinity of said first interface, said decreasing band gap being produced by ion implantation.
3. The structure of claim 1 further including a silicon substrate for supporting said insulating layer, said insulator layer including a first relatively thick oxide insulator having embedded therein a layer of impurity atoms proximate to said second interface, said insulator layer further including a relatively thin layer of Si3N4 deposited over said thick oxide insulator; and said metal or semi-conductor layer being a metal or semiconductor contact on said Si3N4 layer.
4. The structure of claim 1 further including a silicon substrate and wherein said second portion of said insulator layer comprises a relatively thick oxide insulator formed on said substrate and has a layer of impurity atoms proximate to said second interface embedded in said second portion, said first portion comprising a plurality of relatively thin pyrolytic or plasma oxide layers, deposited on said second portion, each successively deposited pyrolytic or plasma oxide layer containing silicon in an increas-ing excess, and a metal or semiconductor contact on the last py-rolytic or plasma deposited oxide layer.
5. A stepped insulator-metal-silicon dioxide-silicon SIMOS
FET structure including an injection region comprising a thin stepped band gap in-sulator adjacent to a gate electrode of said FET structure, and a relatively thick silicon dioxide insulator layer having a layer of impurity atoms embedded therein, said injection region being formed adjacent to a surface of said silicon dioxide insulator layer remote from said embedded layer of impurity atoms.
6. A stepped insulator metal-silicon dioxide-silicon SIMOS
FET structure of claim 5 wherein said electrode relatively thick dioxide layer is formed on a silicon substrate and said injection region consists of a relatively thin layer of Si3N4 formed over said dioxide layer.
7. An improved graded oxide metal-silicone dioxide-silicon GIMOS FET structure comprising a silicon substrate, an oxide layer formed on said silicon substrate, said oxide layer having a layer of impurity atoms embedded therein adjacent to said silicon substrate, an injection region comprising a thin graded band gap formed-on said oxide layer, and a gate electrode adjacent to said injection region.
8. An improved GIMOS FET structure as in claim 7 wherein said oxide layer comprises a relatively thick oxide and said injection region comprises a plurality of relatively thin pyrolytic or plasma deposited oxide layers formed over said relatively thick oxide layer, each successive pyrolytic or plasma deposited oxide layer containing silicon in an increasing excess.
9. In a MOSFET device for performing a memory function wherein said device comprises a silicon substrate, source and drain regions formed within said substrate, and an insulated gate structure formed between said source and drain regions, said insulated gate structure including an injection region having a reduced band gap near an electrical contact-gate structure inter-face thereby enabling holes or electrons depending on the voltage bias, to be injected into said insulated gate structure under low to moderate electric field conditions from said gate electrical contact, and means for blocking electron or hole injection into said in-sulated gate structure from said substrate over a gate structure substrate interface, said blocking means including a layer of im-purity atoms embedded in said insulated gate structure at said gate structure-substrate interface to thereby capture and store injected electrons or holes with high efficiency.
10. The MOS FET device of claim 9 wherein said insulated gate structure includes a first oxide layer having deposited thereon a thin layer of Si3N4, said layer of Si3N4 providing said reduced band gap in the vicinity of the electrical contact-gate structure interface.
11. The MOS FET device of claim 9 wherein said insulated gate structure includes an oxide layer having a decreasing band gap in the vicinity of said electrical contact-gate structure inter-face, said decreasing band gap being produced by ion implantation.
12. The MOSFET device of claim 9 wherein said insulated gate structure includes a first relatively thick oxide layer deposited on said substrate and a plurality of relatively thin pyrolytic or plasma oxide layers, deposited on said thick oxide layer, each successively deposited pyrolytic or plasma oxide layer containing an increasing silicon content.
13. A MOS FET device according to claim 9 wherein said layer of impurity atoms is replaced by a floating polycrystalline silicon charge storage layer.
14. A metal-insulator-metal or metal-insulator-semiconductor structure as defined in claim 1 wherein said charge trapping layer is a floating polycrystalline silicon charge storage layer.
15. A stepped insulator metal-silicon dioxide-silicon SIMOS
FET structure including a gate electrode, an injection region adjacent said gate electrode, said in-jection region comprising a thin stepped band gap insulator, and a relatively thick silicon dioxide insulator layer having a floating polycrystalline silicon charge storage layer formed therein, said injection region being formed adjacent to said silicon dioxide insulator layer.
16. A stepped insulator metal-silicon dioxide-silicon SIMOS
FET structure of claim 15 wherein said injection region is separate from said gate electrode.
17. A graded oxide metal-silicon dioxide-silicon GIMOS FET struc-ture including a silicon substrate, an oxide layer adjacent said substrate, said oxide layer in-cluding a floating polycrystalline silicon charge storage layer, an injection region comprising a thin graded band gap in-sulator formed on said oxide layer, and a gate electrode adjacent said injection region.
18. An improved graded oxide metal silicon dioxide silicon GIMOS
FET structure of claim 17 wherein said injection region is separate from said gate region.
CA335,224A 1979-02-15 1979-09-05 Non-volatile memory devices fabricated from graded or stepped energy band gap insulator mim or mis structures Expired CA1133133A (en)

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US4217601A (en) 1980-08-12

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