CA1124887A - Variable capacity data buffer system - Google Patents
Variable capacity data buffer systemInfo
- Publication number
- CA1124887A CA1124887A CA338,894A CA338894A CA1124887A CA 1124887 A CA1124887 A CA 1124887A CA 338894 A CA338894 A CA 338894A CA 1124887 A CA1124887 A CA 1124887A
- Authority
- CA
- Canada
- Prior art keywords
- data
- data storage
- processor
- storage means
- capacity value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
- G06F2205/063—Dynamically variable buffer size
Abstract
VARIABLE CAPACITY DATA BUFFER SYSTEM
Abstract A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value.
The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simulta-neously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device. Circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storage capacity value while the data storage device receives data from the processor and outputs data to the I/O device.
Abstract A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value.
The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simulta-neously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device. Circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storage capacity value while the data storage device receives data from the processor and outputs data to the I/O device.
Description
VARIABLE CAPACITY DATA BUFFER SYSTEM
Description Technical Field This invention relates to computer systems, and more particularly to a data buffer having a variable capacity for controlling the transfer of data between a central processing unit and input/output (I/O) devices.
'I A A A
48~7 Background Art Digital processing or computing systems in which input/output devices are utilized for entering data into the processing system and for retrieving data generated by the processing system typically utilize data buffers for data being supplied to or received from the I/O device. In those processing systems in which the I/O device is a magnetic tape device, it is necessary for the buffer to supply data at a data transfer rate compatible with that of the recording rate of the magnetic tape device. Because there are various other I/O devices requesting data from the processor and because the data transfer rate of the processor is greater than the drive rate of the magnetic tape device, buffering of the data is necessary.
Previously developed I/O device buffering schemes have utilized fixed length buffer storage devices, such as first-in first-out (FIFO) buffer storage and dual FI~O storage buffers referred to as a "Ping-Pong"
- buffer. A further buffering scheme is described in U.S. Patent No. 4,125,870 issued to Suzuki et al on November 14, 1978 and entitled "Information Transfer Control System". These previously developed approaches using fixed length FIFO buffer storage introduce a fixed time delay in the data stream being transferred from the processor to the I/O device.
An additional problem observed with previously developed data buffering devices is that such buffers must be initially full prior to a write command to the I/O device. This condition is necessary to insure that the I/O device will not exhaust the amount of data being transferred after beginning the write - ~ 1124887 operation. The amount of data needed to be held in a data buffer at the start of the write operation varies with the application of the processing system.
However, for fixed buffer arrangements it is typically necessary to fill the entire buffer even though the I/O device may not require this amount of data to beyin the write operation.
~ need has thus arisen for a data buffer to minimize the buffer filling delays and I/O device start/stop delays for various different I/O device unit applications and system conditions. Such a data buffer must be dynamically adjustable to overcome the problems associated with fixed length buffers.
In accordance with the present invention, a variable capacity data buffer is provided for buffering data being transferred to or received from a processor and an I/O device. The buffer size or capacity is dynamically adjustable to minimize buffer filling delays and I/O device start/stop delays and yet provide adequate buffering for various applica-tions and system conditions.
In accordance with the present invention, a data buffer is provided for controlling the transfer of data between a processor, wherein the processor generates command siynals, and an input/output device., The data buffer includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the input/output device for receiving data input from the processor and for outputting data to the input/
- output device. The data storage device thereby transfers data from the processor to the input/output device and temporarily stores a predetermined amourlt of data while simultaneously transferring data between .~ 11248~7 the processor and the input/output device. Loyic circuitry is provided for selectively establishing a threshold storage eapacity value of the data storage device wherein the threshold storage capacity value is less than the maximum data storage capacity value.
Logic circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storaye capacity value while the data storage device receives data from the processor and outputs data to the input/output deviee.
In accordance with another aspect of the present invention, a method of transferring data froM a processor to an input/output device includes the step of inputting data from the processor into a data storage device having a maximum data storage eapacity. The amount of data input into the data storage device is controlled to a threshold value less than the maximum data storage capacity of the data storage device. A predetermined amount of data is stored within the data storage device. Data is - then output from the data storage device while continuously rnaintaining the predeten~ined amount of data within the data storage device.
BC9 7~-010 r, 1 ~ A A A
11248~7 Brief Description of Drawinys For a more complete description of the present invention and for further objects and advantages thereof, reference is made to the following S Description, taken in conjunction with the accompanying Drawings, in which:
FIGURE 1 is a block diagram illustrating a computer system incorporating the data buffer system of the present invention;
FIGURE 2 is a block electrical diagram illus-trating in greater detail the data buffer system of the present invention;
FIGURE 3 is a schematic logic diagram illus-trating the circuitry corresponding to the register, compare circuits, write address register/
counter, read address reyister/counter, inventory register/counter and switch illustrated in block diagram form of FIGURE 2;
EIGURE 4 is a schematic logic diagram illus-trating the device control shown in the blockdiagram of FIGURE 2;
FIGURE 5 is a schernatic logic diagram illus-trating the inventory control shown in the block ..
diagram of FIGURE 2; and FIGURE 6 is a schematic logic diagram iilus-trating the transfer control shown in the block diagram of FIGURE 2.
" 11248~7 Description of the Preferred EmbodiJnent FIGURE 1 illustrates the present data buffer - system including a data buffer storage device 10 interconnected ~etween a processor 12 and an input/
output (I/O) device 14. Data is supplied to processor 12 from data buffer storage device 10 an~ supplied to data buffer storage device 10 from processor 12 via a bidirectional data bus 16. Data is transferred between ~ata buffer storage device 10 and I/O device 10 14 via a bidirectional data bus 18. Processor 12 may comprise, for example, a Series/l Model 5 mini-computer manufacture~ and sold by International Business Machines Corporation of Armonk, New York.
The Series/l minicomputer is described in the IB~I
15 Manual entitled "Series/l Model 5, 4955 Processor Description", IBM Order lio. GA34 0021 (first edition dated November, 1976); IBM Manual entitled "Series/l 4955 Processor Theory", IBM Order No. SY34-0041 (first edition dated January, 1977); and United 20 States Patent No. 4,038,642, entitled 'lInput/Output Interface Logic for Concurrent Operations", granted to Bouknecht et al on July 26, 1977 and assigned to International Business ~achines Coryoration of Armonk, New York. I/O device 14 is characterized 25 as being a serially reusable resource that is over- -runnable and difficult to restart. Such an I/O
device may comprise, for example, a magnetic tape, floppy disc or teleprocessing network.
Associated with data buffer storage device 10 is a write address registèr/counter 26 and a read address reyister/counter 28. Write address register/counter 26 supplies address information to a switcn 30 via an address bus 32. l~ead address register/counter 28 supplies read address informatior) to switch 30 via an address bus 34. Data being loaded from processor 12 - llZ48~7 to data buffer storage device 10 is loaded to an address specified ~y write address register/counter 26.
Similarly, data read from data buffer storage device 10 to IJO device 14 is read out on data bus 18 by an address specified by read address register/counter 2S.
~witch 30 applies the address from either write address register/counter 26 or read address register/
counter 28 via data bus 36 to data buffer storage device 10. Switch 30 functions to select, during the write cycle, the write address from write address register/counter 26 and select, during the read cycle the read address from read address register/counter 28.
FIGURE 1 further illustrates a control circuit 40 and an inventory reyister/counter 42 associated ~ith the present variable capacity buffer system. Control circuit 40 supplies signals to switch 30 via signal line 44, to write address register/Gounter 26 via signal line 46, to read address register/counter 28 via signal line 48 and to inventory register/counter 42 via signal line 50. Inventory register/counter 42 receives signals from write address register/counter 26 via signal line 54 and from read address register/
counter 28 via signal line 56. Inventory register/
counter 42 also communicates with control circuit 40 via signal line 50.
As will subsequently be explained with reference to FIGURE 2, control circuit 40 and inventory register/
counter 42 function to maintain a predetermined amount or "inventory" of data instantly present in data buffer storage device 10 while data is being input from processor 12 into data buffer storage device 10 and read out from data buffer storage device 10 to I/O
device 14. The amount of data contained within data buffer storage device 10 during operation is pre-selected to a value less than the maximum storage ~C9-7~-010 ~10444 ` ~ ~1248~7 capacity value of data buffer storage device 10.
This dynamic adjustment capability in tlle operation of data buffer storage device 10 minimizes data buffer storage device 10 filling delays and allows data buffer storaye devices to accommodate differences in system confiyurations.
Control circuit 40 and inventory register/
counter 42 in combination with write address register/
counter 26 and read address register/counter 28 function to maintain the inventory within data buffer storaye device 10 at a predetermined differential value between the data being input to data buffer storage device 10 and the data output from data buffer storage device 10. Data will not be permitted to be transferred to I/0 device 14 if the inventory value is zero or less than the predetermined threshold value. Data is permitted to be transferred from data buffer storage device 10 to I/0 device 14 when the amount of data transferred into data buffer storage device 10 is equal to the threshold value.
Through the use of the present invention, control circuit 40 and inventory register/counter 42 dynami-cally control the size of data buffer storage device 10 to optimize the size of data buffer storage device 10 to system configurations.
Referring to FIGURE 2, a detailed logic schematic diagram of the present variable capacity data buffer system is illustrated wherein like numerals are utilized for like and corresponding components previously identified. Processor 12 includes an associated storage 60 and channel interface 620 Data is transferred between channel interface 62 and data buffer storage device 10 via data bus 16 as previously described. Data buffer storage device 10 is illustrated in FIGURE 2 as a buffer random access memory ~RAM); however, ~C9-7~-Olo llZ48~7 alternatively, data buffer storage device 10 may com~rise, for example, a register array, first-in first-out reyister stack or the like. Data is transferred between data buffer storage device 10 and a device controller 64 associated with I/O device 14 via data bus 18.
Channel interface 62 provides an 8-bit command on a data bus 68 to a comMand function register 70. The output of command function register 70 is ap~lied by a data bus 72 to an AND circuit 74 whose output is applied via a command data bus 76 to device controller 64. The information stored in command function register 70 instructs device controller 64 with such information as write forward, read reverse, read forward, rewind, go off line or write a file where I/O device 14 is a magnetic tape device. Device controller 64 generates an output siynal, T~ANSFER COMPLETE, via signal line 78 which is applied to channel interface 62. This signal indicates to processor 12 that the amount of data stored in data buffer storage device 10 has been transferred from processor 12 to I/O device 14.
FIGURE 2 also illustrates a clock 82 for generating the necessary clock timing signals, Phase 1 to Phase N via signal lines 84 for maintaining synchronization of the various circuit components.
Clock 82 also generates the READ/~RITE CYCLE signal applied via signal line 86 to switch 30 for controlling the application of the write address or read address from write address register/counter 26 and read address register/counter 28 to data buffer storage device 10. Clock 82 may be crystal controlled to eliminate clock phase drift.
.~ ~ ~ A . .
~ llZ48~7 Stora~e 60 associated with processor 12 includes an inventory threshold value selectable throuyh the software program of processor 12 for determining the extent or percentage of the total S storage capacity of data buffer storage device 10 that will be utilized. This inventory threshold value is out~ut through channel interface 62 and via signal line 90 to a register 92. In the preferred embodiment, processor 12 outputs throug~l storage 60, channel interface 62 and signal line 90 a 2-bit value to represent 0, 1/16, 9/16 or 15/16 of the to-tal storage capacity of data buffer storage device 10 .
The output of register 92 is applied via a data ~us 94 to a compare circuit 96. The output of inventory register/counter 42 is applied via a data bus 98 to compare circuit 96 and a compare circuit 100. Inventory register/counter 42 is incremented by an output from write address register/counter 26 via signal line 54 and is decrimented by an output from read ac3dress register/counter 28 via signal line 56. Therefore, it can be seen that the value stored within inventory register/counter 42 will represent the instantaneous amount of data present within data ~uffer storage device 10.
The output of compare circuit 100 is applied Vid signal line 104 to inventory control 106 and an AND circult 108. The output siynal on siynal line 104 represents that the inventory contained ~ithin data buffer storage ~evice 10 is greater than zero but less than the full storage capacity value of data buffer storage device 10. The out~ut of cor.pare circuit 96 is applie~ via signal line 110 through an inverter 112 to inventory control 106 via siynal line 114. The output of inverter 112 indicates that the inventory ~oes not exceed the threshold value.
A . .
11~48~7 Inventory control 106 also receives the TRANSFER
CO~IPL~TE signal via signal line 7~. The o~tput of inventory controi 106 generates the ~RITE STROBE
siynal via signal line 46 which is applied to data buffer storage device 10 and write address reyister/counter 26. A second output of inventory control 106 is the BUFFER TRANSFER REQUEST FROM
PROCESSOR siynal ap~lied via signal line 116 to processor 12 via channel interface 62.
In operation, inventory control 106 functions to allow data to be input into data buffer storage ~evice 10 until ~he amount of data equals the threshold value. Initially, the inventory value of data stored within data buffer storage device 10 will be zero as will be the contents of the write address register/counter 26 and read address register/
counter 28. lnventory control 106 will output a BUFFER REQUEST FROM PROCESSOR signal~ to fill data buffer storage device 10. As each of the transfer signals from inventory control 106 is generated, a ~JRITE STROBE signal will be generated by inventory control 106 to select the write address of write address register/counter 26 in proper synchronization during the write cycle. Additionally, the write address register/counter 26 and inventory register/
counter 42 will be incremented. This process of requesting data from processor 12 will continue until the amount of data contained within data buffer storage device 10 or the inventory equals the threshold value.
When the inventory value equals the threshold value, compare circuit 96 will generate the I~VEI~TORY
EQUAL THRESHOLD signal via signal line 120 for application to a device control 122. Device control 122 outputs a GO signal via signal line 124 to AND
circuit 74. The output of device control 122 is ~C9-7~-010 ~ ` 11248~7 anded with the output of command function register 70 by AND circuit 74 to generate a coMmand via data bus 76 to device controller 64. This command to device controller 64 where I/O device 14 is a maynetic ta~e device will indicate to I/O device 14 to begin acceleration of the tape. When the magnetic tape has accelerated to the appropriate speed, device controller 64 will generate the DEVICE TRANSFER
REQUEST si~nal via signal line 130 to AND circuit 108. Since the inventory at this time is less than full, being the threshold value which is less than the maximum capacity of data buffer storage device ~ 1~, an output is yrovided from compare circuit 100 via signal line 104 to AND circuit 108. AND circuit 10~ therefore generates an output to a trans~er control 132.
Transfer control 132 generates the READ STROBE
signal via signal line 48 which is applied to read address register/counter 28 to apply a read address ~0 to data buffer storage device 10. The READ STRO~E
signal is also applied via siynal line 56 to decrement inventory register/counter 42. Transfer control 132 also generates the TRANSFER DATA signal via signal line 136 applied to device controller 64. ~ith the generation of the OUTPUT STXO~E siynal from transfer control 132 via siynal line 140 to data buffer storage device 10, data will be transferred from data buffer storaye device 10 via data bus 18 to device controller 64 and ultimately tc I/O device 14.
Duriny ~ata transfer to I/O device 14, the threshold value can be dynamically changed to change the amount of data invQntOry malntained within data buffer stora~e device 10 d~ring ~peration.
While transfer control 132 functions to outp~t data from data buffer stora~e device 10, inventory -~ llZ48~37 _ 13 control 106 functions to control the input of data from processor 12 into data ~uffer storage device 10. Therefore, transfer control 132 and inventory control 106 functions to maintain the value of inventory previously selected through software by register 92 and yet supply sufficient data from data buffer storage device 10 to I/O device 14.
In summary, control circuit 40 (FIGVRE 1) includes compare circuits 96 and 100, inventory control 106, device control 122 and transfer control 13~2. Control circuit 40 functions to compare the contents of inventory register/counter 42 to the threshold value stored in register 92, to maintain the inventory at the preselected value within data buffer storage device 10 and to output data from data buffer storage device 10 when the inven~ory value equals the threshold value. While control 40 (FIGURE 1) has been illustrated in FIGURE 2 as discrete logic devices, it will be understood that the functions performed by control circuit 40 can also be performed ~y a microprocessor.
~ eferriny to FIGURE 3, logic circuitry cornprising write address reyister/counter 26, re~d address register/counter 28, switch 30, inventory register/counter 42, register 92 and compare circuits 96 and 100 of FIGURE 2 are illustrated.
The threshold value data bits are applied via signal lines 90 to flip flops 154 and 156. Flip flops 154 and 156 may comprise, for example, 7474 I/Cs and comprise th~ register 92 (FIGURE 2).
The output of flip flops 154 and 156 is applied through an AND circuit 158 and directly to a comparator 160. Comparator 160 is interconnected to a comparator 162. Comparators 160 and 162 are 4-bit magnitude compar~tors and may cor,lprise, for ~C9-78-010 48~
example, 74g5 I/Cs. Comparators 160 and 162 com~rise compare circuits 96 an~ 100 (FIG~RE 2).
- The WRIr~E STROBE signal via signal line 46 and the ~EAD STROBE siynal via signal line 48 are ap~lied to a counter 168 whose output is applied to a counter 170. Counters 168 and 170 are synchronous binary up/down counters and may com~rise, for example, 74193 I/Cs and comprise inventory register/counter 42 (FIGURE 2). The output of counter 170 is applied via siynal lines 172 to colllparator 160. The output of comparator 160 via signal line 104 generates the I~lVE`~TORY
LESS 'r~AIi THRESHOL~ SIG~lAL, via signal line 110 generates the INVE~lTORY GREATER THAN THRESHOLD
signal and via siynal line 120 generates the INVENTORY EQUALS THRESHOLD signal.
The WRITE STROBE signal is applied via signal line 46 to a counter 176 whose output is interconnected to a counter 178. Counters 176 and 178 are binary counters and may comprise, for example, 74193 I/Cs. Counters 176 and 178.comprise the write address register/counter 26 (FIGURE 2).
The READ STROBE signal is applied via siynal line 48 to a cour,ter 180 whose output is applied to a counter 182. Counters 180 and lB2 are binary counters and may comprise, for example 74193 I/Cs.
Counters 180 and 182 comprise the read ad~ress register/counter 2~ (FIGURE 2).
Out~uts of counters 176 and 180 are appLied to a multiplexer 188. Outputs of counters 178 an~ 182 are applied to a multiplexer 190. rlulti-plexers 188 and 190 are 2-line to l-line ~ata selector/multi~lexers and may comprise, for exam~e, 74157 I/Cs. I~lultiplexers 188 and 190 comprise switch 30 (FIGURE 2) and generate the address ~its ~C9-7~-0'0 ~10~4 -- ~lZ4887 for data buffer storage device 10 via data bus 36.
The output of multiplexers 188 and 190 are strobed using the READ/WRITE signals applied via signal line 86 from clock 82 (FIGURE 2).
Referring to FIGURE 4, the logic circuitry corresponding to device control 122 (FIGURE 2) is illustrated. The INVENTORY EQUAL T~RESHOLD signal is applied via signal line ~20 to an AND gate 194 together with the Phase 4 clocking signal via siynal line 84. The output of AND gate 194 is applied to a flip flop 196 which also receives the Phase 6 clocking signal from cloc~ 82 (FIGURE
Description Technical Field This invention relates to computer systems, and more particularly to a data buffer having a variable capacity for controlling the transfer of data between a central processing unit and input/output (I/O) devices.
'I A A A
48~7 Background Art Digital processing or computing systems in which input/output devices are utilized for entering data into the processing system and for retrieving data generated by the processing system typically utilize data buffers for data being supplied to or received from the I/O device. In those processing systems in which the I/O device is a magnetic tape device, it is necessary for the buffer to supply data at a data transfer rate compatible with that of the recording rate of the magnetic tape device. Because there are various other I/O devices requesting data from the processor and because the data transfer rate of the processor is greater than the drive rate of the magnetic tape device, buffering of the data is necessary.
Previously developed I/O device buffering schemes have utilized fixed length buffer storage devices, such as first-in first-out (FIFO) buffer storage and dual FI~O storage buffers referred to as a "Ping-Pong"
- buffer. A further buffering scheme is described in U.S. Patent No. 4,125,870 issued to Suzuki et al on November 14, 1978 and entitled "Information Transfer Control System". These previously developed approaches using fixed length FIFO buffer storage introduce a fixed time delay in the data stream being transferred from the processor to the I/O device.
An additional problem observed with previously developed data buffering devices is that such buffers must be initially full prior to a write command to the I/O device. This condition is necessary to insure that the I/O device will not exhaust the amount of data being transferred after beginning the write - ~ 1124887 operation. The amount of data needed to be held in a data buffer at the start of the write operation varies with the application of the processing system.
However, for fixed buffer arrangements it is typically necessary to fill the entire buffer even though the I/O device may not require this amount of data to beyin the write operation.
~ need has thus arisen for a data buffer to minimize the buffer filling delays and I/O device start/stop delays for various different I/O device unit applications and system conditions. Such a data buffer must be dynamically adjustable to overcome the problems associated with fixed length buffers.
In accordance with the present invention, a variable capacity data buffer is provided for buffering data being transferred to or received from a processor and an I/O device. The buffer size or capacity is dynamically adjustable to minimize buffer filling delays and I/O device start/stop delays and yet provide adequate buffering for various applica-tions and system conditions.
In accordance with the present invention, a data buffer is provided for controlling the transfer of data between a processor, wherein the processor generates command siynals, and an input/output device., The data buffer includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the input/output device for receiving data input from the processor and for outputting data to the input/
- output device. The data storage device thereby transfers data from the processor to the input/output device and temporarily stores a predetermined amourlt of data while simultaneously transferring data between .~ 11248~7 the processor and the input/output device. Loyic circuitry is provided for selectively establishing a threshold storage eapacity value of the data storage device wherein the threshold storage capacity value is less than the maximum data storage capacity value.
Logic circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storaye capacity value while the data storage device receives data from the processor and outputs data to the input/output deviee.
In accordance with another aspect of the present invention, a method of transferring data froM a processor to an input/output device includes the step of inputting data from the processor into a data storage device having a maximum data storage eapacity. The amount of data input into the data storage device is controlled to a threshold value less than the maximum data storage capacity of the data storage device. A predetermined amount of data is stored within the data storage device. Data is - then output from the data storage device while continuously rnaintaining the predeten~ined amount of data within the data storage device.
BC9 7~-010 r, 1 ~ A A A
11248~7 Brief Description of Drawinys For a more complete description of the present invention and for further objects and advantages thereof, reference is made to the following S Description, taken in conjunction with the accompanying Drawings, in which:
FIGURE 1 is a block diagram illustrating a computer system incorporating the data buffer system of the present invention;
FIGURE 2 is a block electrical diagram illus-trating in greater detail the data buffer system of the present invention;
FIGURE 3 is a schematic logic diagram illus-trating the circuitry corresponding to the register, compare circuits, write address register/
counter, read address reyister/counter, inventory register/counter and switch illustrated in block diagram form of FIGURE 2;
EIGURE 4 is a schematic logic diagram illus-trating the device control shown in the blockdiagram of FIGURE 2;
FIGURE 5 is a schernatic logic diagram illus-trating the inventory control shown in the block ..
diagram of FIGURE 2; and FIGURE 6 is a schematic logic diagram iilus-trating the transfer control shown in the block diagram of FIGURE 2.
" 11248~7 Description of the Preferred EmbodiJnent FIGURE 1 illustrates the present data buffer - system including a data buffer storage device 10 interconnected ~etween a processor 12 and an input/
output (I/O) device 14. Data is supplied to processor 12 from data buffer storage device 10 an~ supplied to data buffer storage device 10 from processor 12 via a bidirectional data bus 16. Data is transferred between ~ata buffer storage device 10 and I/O device 10 14 via a bidirectional data bus 18. Processor 12 may comprise, for example, a Series/l Model 5 mini-computer manufacture~ and sold by International Business Machines Corporation of Armonk, New York.
The Series/l minicomputer is described in the IB~I
15 Manual entitled "Series/l Model 5, 4955 Processor Description", IBM Order lio. GA34 0021 (first edition dated November, 1976); IBM Manual entitled "Series/l 4955 Processor Theory", IBM Order No. SY34-0041 (first edition dated January, 1977); and United 20 States Patent No. 4,038,642, entitled 'lInput/Output Interface Logic for Concurrent Operations", granted to Bouknecht et al on July 26, 1977 and assigned to International Business ~achines Coryoration of Armonk, New York. I/O device 14 is characterized 25 as being a serially reusable resource that is over- -runnable and difficult to restart. Such an I/O
device may comprise, for example, a magnetic tape, floppy disc or teleprocessing network.
Associated with data buffer storage device 10 is a write address registèr/counter 26 and a read address reyister/counter 28. Write address register/counter 26 supplies address information to a switcn 30 via an address bus 32. l~ead address register/counter 28 supplies read address informatior) to switch 30 via an address bus 34. Data being loaded from processor 12 - llZ48~7 to data buffer storage device 10 is loaded to an address specified ~y write address register/counter 26.
Similarly, data read from data buffer storage device 10 to IJO device 14 is read out on data bus 18 by an address specified by read address register/counter 2S.
~witch 30 applies the address from either write address register/counter 26 or read address register/
counter 28 via data bus 36 to data buffer storage device 10. Switch 30 functions to select, during the write cycle, the write address from write address register/counter 26 and select, during the read cycle the read address from read address register/counter 28.
FIGURE 1 further illustrates a control circuit 40 and an inventory reyister/counter 42 associated ~ith the present variable capacity buffer system. Control circuit 40 supplies signals to switch 30 via signal line 44, to write address register/Gounter 26 via signal line 46, to read address register/counter 28 via signal line 48 and to inventory register/counter 42 via signal line 50. Inventory register/counter 42 receives signals from write address register/counter 26 via signal line 54 and from read address register/
counter 28 via signal line 56. Inventory register/
counter 42 also communicates with control circuit 40 via signal line 50.
As will subsequently be explained with reference to FIGURE 2, control circuit 40 and inventory register/
counter 42 function to maintain a predetermined amount or "inventory" of data instantly present in data buffer storage device 10 while data is being input from processor 12 into data buffer storage device 10 and read out from data buffer storage device 10 to I/O
device 14. The amount of data contained within data buffer storage device 10 during operation is pre-selected to a value less than the maximum storage ~C9-7~-010 ~10444 ` ~ ~1248~7 capacity value of data buffer storage device 10.
This dynamic adjustment capability in tlle operation of data buffer storage device 10 minimizes data buffer storage device 10 filling delays and allows data buffer storaye devices to accommodate differences in system confiyurations.
Control circuit 40 and inventory register/
counter 42 in combination with write address register/
counter 26 and read address register/counter 28 function to maintain the inventory within data buffer storaye device 10 at a predetermined differential value between the data being input to data buffer storage device 10 and the data output from data buffer storage device 10. Data will not be permitted to be transferred to I/0 device 14 if the inventory value is zero or less than the predetermined threshold value. Data is permitted to be transferred from data buffer storage device 10 to I/0 device 14 when the amount of data transferred into data buffer storage device 10 is equal to the threshold value.
Through the use of the present invention, control circuit 40 and inventory register/counter 42 dynami-cally control the size of data buffer storage device 10 to optimize the size of data buffer storage device 10 to system configurations.
Referring to FIGURE 2, a detailed logic schematic diagram of the present variable capacity data buffer system is illustrated wherein like numerals are utilized for like and corresponding components previously identified. Processor 12 includes an associated storage 60 and channel interface 620 Data is transferred between channel interface 62 and data buffer storage device 10 via data bus 16 as previously described. Data buffer storage device 10 is illustrated in FIGURE 2 as a buffer random access memory ~RAM); however, ~C9-7~-Olo llZ48~7 alternatively, data buffer storage device 10 may com~rise, for example, a register array, first-in first-out reyister stack or the like. Data is transferred between data buffer storage device 10 and a device controller 64 associated with I/O device 14 via data bus 18.
Channel interface 62 provides an 8-bit command on a data bus 68 to a comMand function register 70. The output of command function register 70 is ap~lied by a data bus 72 to an AND circuit 74 whose output is applied via a command data bus 76 to device controller 64. The information stored in command function register 70 instructs device controller 64 with such information as write forward, read reverse, read forward, rewind, go off line or write a file where I/O device 14 is a magnetic tape device. Device controller 64 generates an output siynal, T~ANSFER COMPLETE, via signal line 78 which is applied to channel interface 62. This signal indicates to processor 12 that the amount of data stored in data buffer storage device 10 has been transferred from processor 12 to I/O device 14.
FIGURE 2 also illustrates a clock 82 for generating the necessary clock timing signals, Phase 1 to Phase N via signal lines 84 for maintaining synchronization of the various circuit components.
Clock 82 also generates the READ/~RITE CYCLE signal applied via signal line 86 to switch 30 for controlling the application of the write address or read address from write address register/counter 26 and read address register/counter 28 to data buffer storage device 10. Clock 82 may be crystal controlled to eliminate clock phase drift.
.~ ~ ~ A . .
~ llZ48~7 Stora~e 60 associated with processor 12 includes an inventory threshold value selectable throuyh the software program of processor 12 for determining the extent or percentage of the total S storage capacity of data buffer storage device 10 that will be utilized. This inventory threshold value is out~ut through channel interface 62 and via signal line 90 to a register 92. In the preferred embodiment, processor 12 outputs throug~l storage 60, channel interface 62 and signal line 90 a 2-bit value to represent 0, 1/16, 9/16 or 15/16 of the to-tal storage capacity of data buffer storage device 10 .
The output of register 92 is applied via a data ~us 94 to a compare circuit 96. The output of inventory register/counter 42 is applied via a data bus 98 to compare circuit 96 and a compare circuit 100. Inventory register/counter 42 is incremented by an output from write address register/counter 26 via signal line 54 and is decrimented by an output from read ac3dress register/counter 28 via signal line 56. Therefore, it can be seen that the value stored within inventory register/counter 42 will represent the instantaneous amount of data present within data ~uffer storage device 10.
The output of compare circuit 100 is applied Vid signal line 104 to inventory control 106 and an AND circult 108. The output siynal on siynal line 104 represents that the inventory contained ~ithin data buffer storage ~evice 10 is greater than zero but less than the full storage capacity value of data buffer storage device 10. The out~ut of cor.pare circuit 96 is applie~ via signal line 110 through an inverter 112 to inventory control 106 via siynal line 114. The output of inverter 112 indicates that the inventory ~oes not exceed the threshold value.
A . .
11~48~7 Inventory control 106 also receives the TRANSFER
CO~IPL~TE signal via signal line 7~. The o~tput of inventory controi 106 generates the ~RITE STROBE
siynal via signal line 46 which is applied to data buffer storage device 10 and write address reyister/counter 26. A second output of inventory control 106 is the BUFFER TRANSFER REQUEST FROM
PROCESSOR siynal ap~lied via signal line 116 to processor 12 via channel interface 62.
In operation, inventory control 106 functions to allow data to be input into data buffer storage ~evice 10 until ~he amount of data equals the threshold value. Initially, the inventory value of data stored within data buffer storage device 10 will be zero as will be the contents of the write address register/counter 26 and read address register/
counter 28. lnventory control 106 will output a BUFFER REQUEST FROM PROCESSOR signal~ to fill data buffer storage device 10. As each of the transfer signals from inventory control 106 is generated, a ~JRITE STROBE signal will be generated by inventory control 106 to select the write address of write address register/counter 26 in proper synchronization during the write cycle. Additionally, the write address register/counter 26 and inventory register/
counter 42 will be incremented. This process of requesting data from processor 12 will continue until the amount of data contained within data buffer storage device 10 or the inventory equals the threshold value.
When the inventory value equals the threshold value, compare circuit 96 will generate the I~VEI~TORY
EQUAL THRESHOLD signal via signal line 120 for application to a device control 122. Device control 122 outputs a GO signal via signal line 124 to AND
circuit 74. The output of device control 122 is ~C9-7~-010 ~ ` 11248~7 anded with the output of command function register 70 by AND circuit 74 to generate a coMmand via data bus 76 to device controller 64. This command to device controller 64 where I/O device 14 is a maynetic ta~e device will indicate to I/O device 14 to begin acceleration of the tape. When the magnetic tape has accelerated to the appropriate speed, device controller 64 will generate the DEVICE TRANSFER
REQUEST si~nal via signal line 130 to AND circuit 108. Since the inventory at this time is less than full, being the threshold value which is less than the maximum capacity of data buffer storage device ~ 1~, an output is yrovided from compare circuit 100 via signal line 104 to AND circuit 108. AND circuit 10~ therefore generates an output to a trans~er control 132.
Transfer control 132 generates the READ STROBE
signal via signal line 48 which is applied to read address register/counter 28 to apply a read address ~0 to data buffer storage device 10. The READ STRO~E
signal is also applied via siynal line 56 to decrement inventory register/counter 42. Transfer control 132 also generates the TRANSFER DATA signal via signal line 136 applied to device controller 64. ~ith the generation of the OUTPUT STXO~E siynal from transfer control 132 via siynal line 140 to data buffer storage device 10, data will be transferred from data buffer storaye device 10 via data bus 18 to device controller 64 and ultimately tc I/O device 14.
Duriny ~ata transfer to I/O device 14, the threshold value can be dynamically changed to change the amount of data invQntOry malntained within data buffer stora~e device 10 d~ring ~peration.
While transfer control 132 functions to outp~t data from data buffer stora~e device 10, inventory -~ llZ48~37 _ 13 control 106 functions to control the input of data from processor 12 into data ~uffer storage device 10. Therefore, transfer control 132 and inventory control 106 functions to maintain the value of inventory previously selected through software by register 92 and yet supply sufficient data from data buffer storage device 10 to I/O device 14.
In summary, control circuit 40 (FIGVRE 1) includes compare circuits 96 and 100, inventory control 106, device control 122 and transfer control 13~2. Control circuit 40 functions to compare the contents of inventory register/counter 42 to the threshold value stored in register 92, to maintain the inventory at the preselected value within data buffer storage device 10 and to output data from data buffer storage device 10 when the inven~ory value equals the threshold value. While control 40 (FIGURE 1) has been illustrated in FIGURE 2 as discrete logic devices, it will be understood that the functions performed by control circuit 40 can also be performed ~y a microprocessor.
~ eferriny to FIGURE 3, logic circuitry cornprising write address reyister/counter 26, re~d address register/counter 28, switch 30, inventory register/counter 42, register 92 and compare circuits 96 and 100 of FIGURE 2 are illustrated.
The threshold value data bits are applied via signal lines 90 to flip flops 154 and 156. Flip flops 154 and 156 may comprise, for example, 7474 I/Cs and comprise th~ register 92 (FIGURE 2).
The output of flip flops 154 and 156 is applied through an AND circuit 158 and directly to a comparator 160. Comparator 160 is interconnected to a comparator 162. Comparators 160 and 162 are 4-bit magnitude compar~tors and may cor,lprise, for ~C9-78-010 48~
example, 74g5 I/Cs. Comparators 160 and 162 com~rise compare circuits 96 an~ 100 (FIG~RE 2).
- The WRIr~E STROBE signal via signal line 46 and the ~EAD STROBE siynal via signal line 48 are ap~lied to a counter 168 whose output is applied to a counter 170. Counters 168 and 170 are synchronous binary up/down counters and may com~rise, for example, 74193 I/Cs and comprise inventory register/counter 42 (FIGURE 2). The output of counter 170 is applied via siynal lines 172 to colllparator 160. The output of comparator 160 via signal line 104 generates the I~lVE`~TORY
LESS 'r~AIi THRESHOL~ SIG~lAL, via signal line 110 generates the INVE~lTORY GREATER THAN THRESHOLD
signal and via siynal line 120 generates the INVENTORY EQUALS THRESHOLD signal.
The WRITE STROBE signal is applied via signal line 46 to a counter 176 whose output is interconnected to a counter 178. Counters 176 and 178 are binary counters and may comprise, for example, 74193 I/Cs. Counters 176 and 178.comprise the write address register/counter 26 (FIGURE 2).
The READ STROBE signal is applied via siynal line 48 to a cour,ter 180 whose output is applied to a counter 182. Counters 180 and lB2 are binary counters and may comprise, for example 74193 I/Cs.
Counters 180 and 182 comprise the read ad~ress register/counter 2~ (FIGURE 2).
Out~uts of counters 176 and 180 are appLied to a multiplexer 188. Outputs of counters 178 an~ 182 are applied to a multiplexer 190. rlulti-plexers 188 and 190 are 2-line to l-line ~ata selector/multi~lexers and may comprise, for exam~e, 74157 I/Cs. I~lultiplexers 188 and 190 comprise switch 30 (FIGURE 2) and generate the address ~its ~C9-7~-0'0 ~10~4 -- ~lZ4887 for data buffer storage device 10 via data bus 36.
The output of multiplexers 188 and 190 are strobed using the READ/WRITE signals applied via signal line 86 from clock 82 (FIGURE 2).
Referring to FIGURE 4, the logic circuitry corresponding to device control 122 (FIGURE 2) is illustrated. The INVENTORY EQUAL T~RESHOLD signal is applied via signal line ~20 to an AND gate 194 together with the Phase 4 clocking signal via siynal line 84. The output of AND gate 194 is applied to a flip flop 196 which also receives the Phase 6 clocking signal from cloc~ 82 (FIGURE
2). The output of flip flop 196 is applied to an AND gate 200 which also receives as an input the Phase 5 clocking signal via signal line 84. The output of AND gate 200 generates the ~O signal applied via signal line 124 to AND circuit 74 (~IG~RE 2). The output of an AND gàte 200 is also applied to a flip flop 202 which also receives a reset signal via signal line 204 frorn clock 82.
The output of flip flop 202 generates the ~ GO
LATCH signal through an inverter 206 via signal line 208 and the - GO LATCH siynal via signal 210 which is applied to AND gate 194.
Referring to FIGURE 5 the logic circuitry corresponding to inventory control 106 (FIGURE 2) is illustrated. A Phase ~ clocking signal is applied .
via signal line 84 to an AND gate 214. The INVE~iTORY
DOES NOT EQ~AL THRESHOLD signal is applied via signal line 114 to an AND gate 21~ together with the ~ GO
LATCH signal via signal line 208. The - GO LATCli sic~nal is applied via signal line 210 to an A~D gate 218 to~ether with the INVEI~TOKY GREATE~ THAN ZEKO, LESS THAN F~LL signal applied via signal line 104.
The out~ut of A~D gates 216 and 128 is applied to an OR gate 220 whose ~utput is applied to AND gate ~C9-7~-010 ~1044~
~lZ48~37 214. The output of an AN~ gate 214 yenerates the WRITE ENf~BLE signal which is applied to a flip flop 222. The output of flip flop 222 yenerates the BUFFER
TX~NSFER R~Q~EST FROM PROCESSOR signal via signal line 116. Flip flop 222 also receives a clear signal via the Phase 7 clocking signal via signal line 84 from clock 82 (FIGURE 2).
The output of flip flop 222 is applied to an AND gate 226 which also receives the Phase 5 clocking signal via ~ignal line 84 to generate the STOP CLOCK
si~nal applie~ to clock 82 (FIGI~RE 2). The TRANSFER
COMPLETE signal is applied via signal line 78 to an AND gate 228 to generate the START CL~CK signal applied to clock 82 (FIGURE 2). The output of flip flop 222 is also applied to an AND yate 230 which also receives the Phase 6 clocking signal via signal line g6 to yenerate the WRITE STROBE signal via signal line 46.
Referring to FIGURE 6, the logic circuitry corresponding to transfer control 132 (FIGURE 2) is illustrated. The Phase 0, READ ENABLE, signal is a~plied via signal line 84 to an AND gate 240. The DEV~CE TRANSFER REQUEST signal is applied via signal line 13~ together with the INVENTORY GREATER THAN
ZER0, LESS THAN FULL signal via signal line 104 to an AND yate 242. The output of AND gate 242 is applied to AND gate 240. The output of AWD gate 240 is applie~ to a flip flop 244 which also receives as an input the Phase 4 clocking signal via signal line 84. The output of flip flop 244 is a~plied to AND
gates 246, 248 and 250. AND gate 246 also receives the Phase 1 clocking siynal via signal line 84 t~
generate the O~TPUT STROBE signal via siynal line 14U. AN~ gate 248 also receives ~he Phase 2 clocking signal via signal line 84 to generate the TRANSF~R
DAT~ signal via signal line 136. AND gate 25 BC9-7~-010 ~10444 - - llZ48~7 receiveS th~ Phase 3 clocking siqnal via siynal line &4 t~ generate the READ STRO8E signal via signa~
line 48.
Although the operation of the present invention has been described in performing a write operation to an I/O device, the present buffer system can also be utilized for performing a read operation to a processor. Since the buffer delay in performing a read operation to a processor is not as significant as in a write operation, it will be understood that the advantages realized by the present system are also attained in performing read operations to a processor.
It therefore can be seen that the present lS inventiGn providec for a variable capacity data buffer system in which the buffer size or capacity of a data storage device can be dynamically adjusted to minimize buffer filling delays and input/output device start/stop delays for various different I/O
device apylications and system conditions. The system maintains a predetermined amount of data within the data buffer while continuously reading in data from a processor and reading out data to an I/0 device.
~hereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scoye of the appended claims.
The output of flip flop 202 generates the ~ GO
LATCH signal through an inverter 206 via signal line 208 and the - GO LATCH siynal via signal 210 which is applied to AND gate 194.
Referring to FIGURE 5 the logic circuitry corresponding to inventory control 106 (FIGURE 2) is illustrated. A Phase ~ clocking signal is applied .
via signal line 84 to an AND gate 214. The INVE~iTORY
DOES NOT EQ~AL THRESHOLD signal is applied via signal line 114 to an AND gate 21~ together with the ~ GO
LATCH signal via signal line 208. The - GO LATCli sic~nal is applied via signal line 210 to an A~D gate 218 to~ether with the INVEI~TOKY GREATE~ THAN ZEKO, LESS THAN F~LL signal applied via signal line 104.
The out~ut of A~D gates 216 and 128 is applied to an OR gate 220 whose ~utput is applied to AND gate ~C9-7~-010 ~1044~
~lZ48~37 214. The output of an AN~ gate 214 yenerates the WRITE ENf~BLE signal which is applied to a flip flop 222. The output of flip flop 222 yenerates the BUFFER
TX~NSFER R~Q~EST FROM PROCESSOR signal via signal line 116. Flip flop 222 also receives a clear signal via the Phase 7 clocking signal via signal line 84 from clock 82 (FIGURE 2).
The output of flip flop 222 is applied to an AND gate 226 which also receives the Phase 5 clocking signal via ~ignal line 84 to generate the STOP CLOCK
si~nal applie~ to clock 82 (FIGI~RE 2). The TRANSFER
COMPLETE signal is applied via signal line 78 to an AND gate 228 to generate the START CL~CK signal applied to clock 82 (FIGURE 2). The output of flip flop 222 is also applied to an AND yate 230 which also receives the Phase 6 clocking signal via signal line g6 to yenerate the WRITE STROBE signal via signal line 46.
Referring to FIGURE 6, the logic circuitry corresponding to transfer control 132 (FIGURE 2) is illustrated. The Phase 0, READ ENABLE, signal is a~plied via signal line 84 to an AND gate 240. The DEV~CE TRANSFER REQUEST signal is applied via signal line 13~ together with the INVENTORY GREATER THAN
ZER0, LESS THAN FULL signal via signal line 104 to an AND yate 242. The output of AND gate 242 is applied to AND gate 240. The output of AWD gate 240 is applie~ to a flip flop 244 which also receives as an input the Phase 4 clocking signal via signal line 84. The output of flip flop 244 is a~plied to AND
gates 246, 248 and 250. AND gate 246 also receives the Phase 1 clocking siynal via signal line 84 t~
generate the O~TPUT STROBE signal via siynal line 14U. AN~ gate 248 also receives ~he Phase 2 clocking signal via signal line 84 to generate the TRANSF~R
DAT~ signal via signal line 136. AND gate 25 BC9-7~-010 ~10444 - - llZ48~7 receiveS th~ Phase 3 clocking siqnal via siynal line &4 t~ generate the READ STRO8E signal via signa~
line 48.
Although the operation of the present invention has been described in performing a write operation to an I/O device, the present buffer system can also be utilized for performing a read operation to a processor. Since the buffer delay in performing a read operation to a processor is not as significant as in a write operation, it will be understood that the advantages realized by the present system are also attained in performing read operations to a processor.
It therefore can be seen that the present lS inventiGn providec for a variable capacity data buffer system in which the buffer size or capacity of a data storage device can be dynamically adjusted to minimize buffer filling delays and input/output device start/stop delays for various different I/O
device apylications and system conditions. The system maintains a predetermined amount of data within the data buffer while continuously reading in data from a processor and reading out data to an I/0 device.
~hereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scoye of the appended claims.
Claims (14)
- The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
l. A data buffer system for controlling the transfer of data between a processor, wherein the processor generates command signals, and an input/out (I/O) device comprising:
data storage means having a maximum data storage capacity value;
said data storage means being disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device;
said data storage means temporarily storing within said data storage means a predetermined amount of data while simultaneously transferring data between the processor and the I/O device;
means for selectively establishing a threshold storage capacity value of said data storage means wherein said threshold storage capacity value is less than said maximum data storage capacity value; and means for maintaining said predetermined amount of data temporarily stored in said data storage means equal to said threshold storage capacity value while said data storage means receives data from the processor and outputs data to the I/O device. - 2. The data buffer system of Claim 1 wherein said means for selectively establishing said threshold storage capacity value includes:
means responsive to the processor command signal for generating a control signal represen-tative of said threshold storage capacity value. - 3. The data buffer system of Claim 2 wherein said means for maintaining said predetermined amount of data temporarily stored in said data storage means includes:
means for determining the amount of data input from the processor into said data storage means;
means for determining the amount of data output to the I/O device from said data storage means;
means for inputting data to said data storage means when the amount of input data is less than the amount of data represented by said control signal;
means for determining the difference in the amount of data input into said data storage means and the amount of data output to the I/O
device and for generating a difference signal;
means for comparing said control signal and said difference signal and for generating a transfer signal when said control signal equals said difference signal; and means for outputting data from said data storage means in response to said transfer signal. - 4. The data buffer system of Claim 1 wherein said data storage means comprises a first-in first-out data register.
- 5. The data buffer system of Claim 1 wherein said data storage means comprises a random access memory .
- 6. The data buffer system of Claim 1 wherein the input/output device comprises a magnetic tape device.
7. A data buffer system for controlling the transfer of data between a processor, wherein the processor generates command signals, and an input/output (I/O) device comprising:
data storage means having a maximum data storage capacity value;
said data storage means being disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O
device;
said data storage means temporarily storing a predetermined amount of data within said data storage means while simultaneously transferring data between the processor and the I/O device;
means responsive to the processor command signals for generating a control signal represen-tative of a threshold storage capacity value of said data storage means wherein said threshold storage capacity value is less than said maximum data storage capacity value;
logic means for determining the amount of data input from the processor into said data storage means and the amount of data output to the I/O device and for generating a difference signal representing the difference in the amount of data input to said data storage means and the amount of data output from said data storage means;
first comparator means for comparing the amount of data input to said data storage means and said control signal;
means responsive to said first comparator means for controlling the amount of data input to said data storage means; - Claim 7 Continued second comparator means for comparing said control signal and said difference signal; and means responsive to said second comparator means for outputting data from said data storage means to the I/O device.
- 8. The data buffer system of Claim 7 wherein said means responsive to said first comparator means causes the input of data to said data storage means when the amount of data stored within said data storage means is less than said threshold value.
- 9. The data buffer system of Claim 7 wherein said means responsive to said second comparator means outputs data to the I/O device when said control signal equals said difference signal.
- 10. The data buffer system of Claim 7 wherein said logic means includes counting means.
- 11. The data buffer system of Claim 7 wherein said data storage means comprises a first-in first-out data register.
- 12. The data buffer system of Claim 7 wherein said data storage means comprises a random access memory.
- 13. A data buffer system for controlling the transfer of data between a processor, wherein the processor gen-erates command signals, and an input/out (I/O) device comprising:
data storage means having a maximum data storage capacity value;
said data storage means being disposed between the processor and the I/O device for receiving data input from the processor and for ouputting data to the I/O
device to thereby transfer data from the processor to the I/O device;
said data storage means temporarily storing within said data storage means a predetermined amount of data while simultaneously transferring data between the pro-cessor and the I/O device;
means for selectively establishing a threshold storage capacity value of said data storage means wherein said threshold storage capacity value is less than said maximum data storage capacity value: and said predetermined amount of data temporarily stored in said data storage means being output to the I/O device when said predetermined amount of data temporarily stored in said data storage means equals said threshold storage capacity value. - 14. The data buffer system of Claim 13 where said pre-determined amount of data temporarily stored in said data storage means is less than said threshold storage capacity value during output of said predetermined amount of data to the I/O device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US973,938 | 1978-12-28 | ||
| US05/973,938 US4258418A (en) | 1978-12-28 | 1978-12-28 | Variable capacity data buffer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1124887A true CA1124887A (en) | 1982-06-01 |
Family
ID=25521396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA338,894A Expired CA1124887A (en) | 1978-12-28 | 1979-10-31 | Variable capacity data buffer system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4258418A (en) |
| EP (1) | EP0013347B1 (en) |
| JP (1) | JPS5591026A (en) |
| CA (1) | CA1124887A (en) |
| DE (1) | DE2965878D1 (en) |
| IT (1) | IT1165427B (en) |
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|---|---|---|---|---|
| US3059221A (en) * | 1956-12-03 | 1962-10-16 | Rca Corp | Information storage and transfer system |
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| JPS5247635A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Control method for transmitting informat ion |
| AT352449B (en) * | 1977-01-21 | 1979-09-25 | Schrack Elektrizitaets Ag E | DEVICE FOR TEMPORARY BUFFERING OF SERIAL INCOMING BIT SEQUENCES IN ONE OR MORE SILO STORAGE |
| JPS607812B2 (en) * | 1977-07-11 | 1985-02-27 | 富士電機株式会社 | Data buffering device |
-
1978
- 1978-12-28 US US05/973,938 patent/US4258418A/en not_active Expired - Lifetime
-
1979
- 1979-09-20 JP JP12018479A patent/JPS5591026A/en active Granted
- 1979-10-31 CA CA338,894A patent/CA1124887A/en not_active Expired
- 1979-12-04 EP EP79104895A patent/EP0013347B1/en not_active Expired
- 1979-12-04 DE DE7979104895T patent/DE2965878D1/en not_active Expired
- 1979-12-18 IT IT28122/79A patent/IT1165427B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| US4258418A (en) | 1981-03-24 |
| EP0013347A1 (en) | 1980-07-23 |
| IT7928122A0 (en) | 1979-12-18 |
| JPS5591026A (en) | 1980-07-10 |
| JPS6318220B2 (en) | 1988-04-18 |
| EP0013347B1 (en) | 1983-07-13 |
| IT1165427B (en) | 1987-04-22 |
| DE2965878D1 (en) | 1983-08-18 |
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