CA1112370A - Synchronization control system for firmware access of high data rate transfer bus - Google Patents
Synchronization control system for firmware access of high data rate transfer busInfo
- Publication number
- CA1112370A CA1112370A CA303,332A CA303332A CA1112370A CA 1112370 A CA1112370 A CA 1112370A CA 303332 A CA303332 A CA 303332A CA 1112370 A CA1112370 A CA 1112370A
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- Canada
- Prior art keywords
- data
- gate
- logic
- output
- input
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
ABSTRACT OF THE DISCLOSURE
In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the data in its output register. The signals are logically combined, and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states requiring the transfer of data under hardware control between the FIFO buffer and main memory. When the input register of the FIFO buffer is filled during a data transfer from main memory to the disk device, or when the FIFO buffer is empty during a transfer of data from the disk device to main memory, hardware controlled data transfers are not required. In that event the firmware control system is permitted to access the common bus to service unsolicited bus requests.
In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the data in its output register. The signals are logically combined, and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states requiring the transfer of data under hardware control between the FIFO buffer and main memory. When the input register of the FIFO buffer is filled during a data transfer from main memory to the disk device, or when the FIFO buffer is empty during a transfer of data from the disk device to main memory, hardware controlled data transfers are not required. In that event the firmware control system is permitted to access the common bus to service unsolicited bus requests.
Description
~s~
BACKbROU~o or I~E I~V~'NTION
Field of the Invention The invention rela~es ~o data transfer con~rol ~ys~ems for routiIlg data between mass storage devices and main memory in a data processing system, and more particularly to a synchronization logic control system f'or multiplexing bus control between a hardware control system and a irmware control system without incurring da~a errors or affecting the da~a transfer rate.
PrLor ~rt In data processing systems wherein a plurality of functional units are electrically coupled by a common communication bus, extremely complex hardware and firmware synchronization control sys~ems have been required to share ~he common bus between hardware and finmware duri~g a high data ra~e ~ransfer. When unsolicited bus requests requiring firmware interaction have occurred during the data transfer, ~he synohronlza~ion con~rcl systems have been required to track the data at the byte level in order to assure that no underrun or overr~n errors occur when ~he firmware ls allowed to access ~he common bus. As ~he data transfer rate increases, the timing of the synchronization control system becomes more critical and additio~al complexi~y in the control system network has been required. In seeking alterna~ives to the added complexity, system designers have had to sacrifice the da~a transfer ra~es.
BACKbROU~o or I~E I~V~'NTION
Field of the Invention The invention rela~es ~o data transfer con~rol ~ys~ems for routiIlg data between mass storage devices and main memory in a data processing system, and more particularly to a synchronization logic control system f'or multiplexing bus control between a hardware control system and a irmware control system without incurring da~a errors or affecting the da~a transfer rate.
PrLor ~rt In data processing systems wherein a plurality of functional units are electrically coupled by a common communication bus, extremely complex hardware and firmware synchronization control sys~ems have been required to share ~he common bus between hardware and finmware duri~g a high data ra~e ~ransfer. When unsolicited bus requests requiring firmware interaction have occurred during the data transfer, ~he synohronlza~ion con~rcl systems have been required to track the data at the byte level in order to assure that no underrun or overr~n errors occur when ~he firmware ls allowed to access ~he common bus. As ~he data transfer rate increases, the timing of the synchronization control system becomes more critical and additio~al complexi~y in the control system network has been required. In seeking alterna~ives to the added complexity, system designers have had to sacrifice the da~a transfer ra~es.
2~ The present in~ention is directed to a slmpllstic synchronization control system wherein ~he data transfer on a commo~ communication bus may be în~errupted for firn~are accommod~ion of unsolicited bus requests without incurring data errors or affecting the ~ranser ra~e. The need or complex
3~ logic circuitry or increased firmware control s~orage is obvia~ed.
SUMM~RY OF TEIE INVENTION
A logical synchronization control system for a data processor having functional units interconnected by a common communication bus is provided, wherein access to the bus by a ~irmware control system may be permitted during a hardware controlled da-ta transfer without sacrificing t.ransfer rates or incurring data errors.
More particularly, a logic control system issues data strobes under hardware control to accommodate the transfer of data between main memory and a mass storage device. Data is routed through a FIFO (first-in-first-out) buFfer in the logic control system in response to the data strobes. When no data .
transfer is required between main memory and the FIFO buffer, to accommodate the data transfer rate, the firmware control system is alerted to acknowledge and service unsolicited bus requests on the common bus. When a data transfer between the FIFO bu.~fer and main memor~ is required, however, data strobes again are generated and bus control is transferred from fir~ware ~.
to hardware. The proce~s is repeated until the data transfer between main memor~ and the mass storage device is completed.
In accordance with the present invention there is pro-vided a data transfer control system ~or signall.ing the occur-r~nce of a time period durin~ which a common communication bus may~be~accessed by a fi~m~are control system during a data tr~ns~er bet~een a main memory and a mass s~orage device ~ith-out compromisi~ng t~e data transfer rate ox .~ncurring data errors, said bus electrically linking a central processing unit, said firmware control ~ystem, a mass storage control unit, and said ma;~n memoryr whi:ch comprises: (a) memor-y- means in electrical 30...... commun1cation with said mass storage device and said control , .
3~
unit for transferring data therebetween and indicating both the presence of input data and the occurrence of a filled memory condition; (b) logic gate means responsive to said memory means and said control unit for p;roviding data s-trobes to synchronize the flow of data between said memory means and said control unit; and (c) logic timing means in electrical communication with said control unit and said logic gate means for issuing a control signal to said firmware control system indicating the occurrence of said time period~ :
~n accordance with the present invention there is also provided in a data processing system operating under the con-trol of both hardware and firmware control means, said system having a common communication bus linking a central processing unit, a~main memory, a disk controller~ a disk adapter and a mass storage disk system, -the combination which comprises: .
(a) first-in-~irst-out buffer means in electrical communication ..
with said disk adapter and said disk controller for transferring data between said disk system and said main memory; (b) first ogic means responsive to said disk controller and said buffer means for requesting a data transfer between said buffer means and said disk controller; and (c) second logic means in electri-cal communication with. said firm~are control means, said disk controller and said first logic means for signalling the presence of a data transfer state during which said firm~are control means can service bus requests on said common bus without incurring data errors or inter~ering with the data transfer rate between said disk system and said main memory~ -DESCRI~PTION OF THE~ DRA~INGS
. . .~
The no~e1 features~believed characterist.ic of the 3Q inventi:on are set forth.in the appended claims. The in~ention - ' ~ - 3~ -\
3 ~
itself, however, as well as further objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrative embodiment, when read in conjunction with the accompanying drawi.ngs wherein:
Figure 1 is a functional block diagram of a data pro-cessing system embodying the invention;
Figure 2 is a more detailed functional block diagram of the disk controller and disk adapter of Figure l;
- 3b -.
Figure 3 i.s a logic schematic diagram of the ~nvention;
Figure ~-~ ts a timing diagram illustrat~ng thc opera~ion of the system of Figure 3 during a transfer o~ da~a from main memor~ to the disk adaptcr; and Figure S is a timing diagram ill.ustrating the operation of the system of Figure 3 during a transfer of data from the disk adapter to main memory.
DESCRIPTION OF THE PREFER~ED EMæODIMENT
_____ _ FIGU~E 1 Figure l illustrate9 in functional block dlagram form a computer system ha~ing a medlum-perf-ormance disk controller (MP~C) 10 in electrical comm~nication wi~h a central processor unit ll and a memory unit 12 by way of a common communication bus 13, The~ MPDC lO is a 1~icroprog~ammed peripheral control subsystem for storing and retrieving data from mass storage media. The controller ineludes a Read Only Store (ROS) memory to be later described which contains microprogram instructions, and comm~nica~es with mass s~orage adapters such as the disk adapter :L4. Adapt~r 14 has the facility to support ~vur daisy-cha.ined disk devices 15.
The communication bus 13 provides an information path between any ~wo units in the system. The bus is asynchronous in design, thus enabling units of various speeds to opera~e ef~iciently. The bus accommodates information transfers including communication requests, control commands, s~atus signals and data transfers between memory 12 and disk deviees 15.
Any system unit wishing ~o communicate requests a bus cycle. When that bus cyc~e is gran~ed, the. requesting : unit becomes the master and the addressed system unit becomes ~ ; ~ 30 the slave. Some bus in~erchanges require a response cycle :~ : as well as a request cycle~ By way of exampl~ the master u~it may identify itsel~ to a slave unit and indica~e tha~
: a response is requiredO When the required lnforma~ion becomes
SUMM~RY OF TEIE INVENTION
A logical synchronization control system for a data processor having functional units interconnected by a common communication bus is provided, wherein access to the bus by a ~irmware control system may be permitted during a hardware controlled da-ta transfer without sacrificing t.ransfer rates or incurring data errors.
More particularly, a logic control system issues data strobes under hardware control to accommodate the transfer of data between main memory and a mass storage device. Data is routed through a FIFO (first-in-first-out) buFfer in the logic control system in response to the data strobes. When no data .
transfer is required between main memory and the FIFO buffer, to accommodate the data transfer rate, the firmware control system is alerted to acknowledge and service unsolicited bus requests on the common bus. When a data transfer between the FIFO bu.~fer and main memor~ is required, however, data strobes again are generated and bus control is transferred from fir~ware ~.
to hardware. The proce~s is repeated until the data transfer between main memor~ and the mass storage device is completed.
In accordance with the present invention there is pro-vided a data transfer control system ~or signall.ing the occur-r~nce of a time period durin~ which a common communication bus may~be~accessed by a fi~m~are control system during a data tr~ns~er bet~een a main memory and a mass s~orage device ~ith-out compromisi~ng t~e data transfer rate ox .~ncurring data errors, said bus electrically linking a central processing unit, said firmware control ~ystem, a mass storage control unit, and said ma;~n memoryr whi:ch comprises: (a) memor-y- means in electrical 30...... commun1cation with said mass storage device and said control , .
3~
unit for transferring data therebetween and indicating both the presence of input data and the occurrence of a filled memory condition; (b) logic gate means responsive to said memory means and said control unit for p;roviding data s-trobes to synchronize the flow of data between said memory means and said control unit; and (c) logic timing means in electrical communication with said control unit and said logic gate means for issuing a control signal to said firmware control system indicating the occurrence of said time period~ :
~n accordance with the present invention there is also provided in a data processing system operating under the con-trol of both hardware and firmware control means, said system having a common communication bus linking a central processing unit, a~main memory, a disk controller~ a disk adapter and a mass storage disk system, -the combination which comprises: .
(a) first-in-~irst-out buffer means in electrical communication ..
with said disk adapter and said disk controller for transferring data between said disk system and said main memory; (b) first ogic means responsive to said disk controller and said buffer means for requesting a data transfer between said buffer means and said disk controller; and (c) second logic means in electri-cal communication with. said firm~are control means, said disk controller and said first logic means for signalling the presence of a data transfer state during which said firm~are control means can service bus requests on said common bus without incurring data errors or inter~ering with the data transfer rate between said disk system and said main memory~ -DESCRI~PTION OF THE~ DRA~INGS
. . .~
The no~e1 features~believed characterist.ic of the 3Q inventi:on are set forth.in the appended claims. The in~ention - ' ~ - 3~ -\
3 ~
itself, however, as well as further objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrative embodiment, when read in conjunction with the accompanying drawi.ngs wherein:
Figure 1 is a functional block diagram of a data pro-cessing system embodying the invention;
Figure 2 is a more detailed functional block diagram of the disk controller and disk adapter of Figure l;
- 3b -.
Figure 3 i.s a logic schematic diagram of the ~nvention;
Figure ~-~ ts a timing diagram illustrat~ng thc opera~ion of the system of Figure 3 during a transfer o~ da~a from main memor~ to the disk adaptcr; and Figure S is a timing diagram ill.ustrating the operation of the system of Figure 3 during a transfer of data from the disk adapter to main memory.
DESCRIPTION OF THE PREFER~ED EMæODIMENT
_____ _ FIGU~E 1 Figure l illustrate9 in functional block dlagram form a computer system ha~ing a medlum-perf-ormance disk controller (MP~C) 10 in electrical comm~nication wi~h a central processor unit ll and a memory unit 12 by way of a common communication bus 13, The~ MPDC lO is a 1~icroprog~ammed peripheral control subsystem for storing and retrieving data from mass storage media. The controller ineludes a Read Only Store (ROS) memory to be later described which contains microprogram instructions, and comm~nica~es with mass s~orage adapters such as the disk adapter :L4. Adapt~r 14 has the facility to support ~vur daisy-cha.ined disk devices 15.
The communication bus 13 provides an information path between any ~wo units in the system. The bus is asynchronous in design, thus enabling units of various speeds to opera~e ef~iciently. The bus accommodates information transfers including communication requests, control commands, s~atus signals and data transfers between memory 12 and disk deviees 15.
Any system unit wishing ~o communicate requests a bus cycle. When that bus cyc~e is gran~ed, the. requesting : unit becomes the master and the addressed system unit becomes ~ ; ~ 30 the slave. Some bus in~erchanges require a response cycle :~ : as well as a request cycle~ By way of exampl~ the master u~it may identify itsel~ to a slave unit and indica~e tha~
: a response is requiredO When the required lnforma~ion becomes
4-.
:, ~
3~
- available, the slave assumes the role of master and intiates a transfer to the requesting unit.
In the servicing of bus cycle requests~ ~e centxal processor has the lowest priority, thè MPDC 10 has the next lowest priority, and the memory 12 has the highest priority.
4 A more detailed description of the system of Figure 1 is given in U. S. Patent No. 3,993~981 which is assigned to the assignee of the present invention.
FI~.URE 2 Figure 2 illustrates in a more detailed block diagram form the MPDC 10, the disk adapter 14, and a service request logic unit 200 which emobdies the invention.
The service request logic unit 200 receives error signals by way of a control line 202 from an error logic unit 201 in a disk adapter 14. Unit 200 also receives control signals from a microprogram instruction register 203 by way of a control line 204, and data transfer range and control signals from MPDC 20 by way of a conducting cable 205. The logic unit 200 supplies data requests to the MPDC 10 by way of a control line 206 and data strobes to the MPDC by way of a control line 207. Serial data is received from the disk adapter 14 on a data cable 208, and supplied to the disk adapter on a data cable 209. Further, parallel data transfers between -the logic unit 200 and MPDC 100 occurs on data cables 210 and 211.
`~ When a time period occurs during which a firmware control system may be permitted to access the common bus 13, logic unit 200 issues a status signal along a conducting line 212 leading to a condition compare logic unit 213D The output of the logic unit 213 is supplled to a microprogram memory control unit 214~and to a microprogram address switch unit 215~ A second input to switch unit 215 is connected to the output of a microprogram counter 216. The output of the switch unit is ~5--.~
~ 3~f'~
applled to a microprogram address register 217 which address~s a Read Only Store (ROS) 218 by way of an address cable 219. The output of the ROS 218 is applied to the mlcroprogram instruction regis~er 203.
The control unit 214 supplies control signals to counter 216 by way of a control line 220~ to switch unit 215 by way of a control li,ne 221, to register 217 by way of a control line 222 J and to register 203 by way of a control line 223. The register 203 also supplies control signals to ~ogic uni~ 213 by way of a control line 224~ and to switch unit 215 by way o a control li,ne 22O, During a da~a transfer, catas~rophic errors such as data tr,ansfer rate errors, timing errors and disk drive inhibits may occur. The error logic unit 201 monitors the data flow through logic unit 200 by way of a control cable 22Gg and receives error information from MPDC 10 on a control cable 227 The logic unit 201 1ags the occurrence of errors by issuing error control s:ignals to line 202 and to a control cable 228 leading to MPDC 10.
In operation, data may be transferred from memory 12 of Figure 1 to the MPDC 10, and hence by way of da~a cable 211 to logic unit 200. From logic un.it 200, the data is supplied serially by way of data cable 209 to the disk adapter 14 When data is to be supplied rom a disk de~ice to memory 12 the data is applied serially from disk adap~er 14 to da~a cable 208 leading to logic unit 200. Unit 200 in turn supplies the data in parallel along data cable 210 leading to ~he MPDC 10. During the data transfer, the logic unit 200 requests byte transfers from MPDC 10 by way of control line 206 or indicates the presence of data ready for ~ransfer by way of contro~ line 207. When a reserve memory unit in logic unit 200 i,s filled, the logic ~ni~ issues a signal on line 212 to the condition compare logic unit 213.
.
Sequences of microinstructions comprising a micro-program are stored in the ROS memory 218. Under the control of the mieroprogram memory control unit 2L4, the count of ~he microprogram counter 216 is load~d in~o ~he microprogram address register 217 to address a particular mlcroinstruction in memory 218. The addressed micro-inqtruction is loaded into the microprogram instructlon registar 203 ~ set înput and ou~put switches directing ~he flow of da~a, a~d to provide control signals a~ the elemen~al machine instruction level to direct the operation o~ the functional units comprising the data processing system of Figure 1. At the end of the activity directed by the micro-program control signals, the counter 216 is stepped by the control unit 214 and loaded into the address register 217 to address a nex~ microinstruction in memory 218~ A sequence of micxoinstructions thereby may be executed.
When sequencing of microinstructions depends upon conditions that arise during data processing, there is a condition ~ield in the sequence of microinstructio~s.
This field activates the logic unit 213 by way of control line 224, thereby permit~ing ~he con~rol line 212 to be sa~pled and compared. In respo~se to a condit~on field signal on line Z24, the address switch 215 alters the output of the microprogram counter 216 to construct a ~ext microinstruction address. A new microinstruction sequence thereby is addressed in memory 218.
FIGU~E 3 Figure 3 is a detailed logic schematic diagram of ~he service reques~ logic unit 200 of Figure ~.
Referring to Figure 3, a first-in first-out ~FIFO) buffer 300 reeeives serial data from disk adapter 14 on da~a cable 208, or data in parallel form from MPDC 10 : o~ data cab~e 211~ e preferred embodiment described ' .
~.h~
herein, bufer 300 has a l~-byte capacity, and ls o~ a type manufactllred and sold by Fairchild SemLconductor o Mountain Vi.e~, California as model 9403. Data bytes ar~
rece.îved b~ the i.nput regi.ster of buffer 300, and shlfted through the buffer to the O~ltpUt register at a rate deter-mined by ~he ~all through ti.me between ~he registers, The output register supplies -~he data in parallel Eorm to da~a cahle 210 leading to MPDC 10~ or in serial fo~n to data cable ~09 lea~in~ to ~he disk adap~er 14.
1.0 When the input register o~ buffer 300 is empty, a logic one sî~nal is issued ~o a control line 226a o~ ca~l.e 226 and ~o a con~rol line 301a leadin~g to one inpu~ of an AND gate 302a.
Further, t~7he~ the outpu~ register is illed, a logic one signal is issued to a control line 226b of cable 226, and to a control line 303a l.eading to one input of an AND ga~e 302b. AND gate 302a also receives a write to disk control signal from MPDC 10 on a con~rol line 301b whe~ data is to be transferred from m~in memory 12 to disk adapter 14~ I~ addition, g~te 302a receives l~gic zero end o data field signals on a control line 301c leading from the disk adapter 140 A~D gate 302b further receives an enabling control signal frDm MPDC lO on a con~rol l.ine 303b, and 2 logic one read slgnal rom the MPDC on a con~rol line 303c when da~a is to be read rom disk storage.
The outpu~s of AND gates 302a and 302b are connected ~o correspondl~g înputs of an OR gæte 302c. Ga~es.302a-302c compr~Lse a logic a~ray 302. The outpu~ of array 302 is applie~
to one input of a NOR ga~e 304, and ~hrough four serially eonnected in~erters 305 to one input of an AND ga~e 3060 : 30 A second ~nput to gate 306 is ~onnected to t~e output of an : AMD gat~ 307, one input of which is eonnected to one input of an AND g~te 308 and ko a con~rol line 205a of cable 205 leading to outpu~ terminals of MPDC lQ~ A second input to gate 307 is connected to a con~rol llne 205b of cable 205 9 and a second inpu~ D ga~e 308 ~s connee~ed ~o ron~rol line 202 .
leading to error logic unit 201 of Fîgure 2. The output of gate 308 i5 co~nected to the set :input of a ~lip~flop 309.
The D input to flip-flop 309 i5 connected to the outpu~
o~ NOR ~ate 304l a second input of which is connected to the output o an AND gate 310~ The T trigger input to 1ip-flop 309 is co~nected to the Q output of a one-sho~ multivibrator 311, the Sl a~d S2 set inputs of which are connected to output~
of MPDC 10 by way of control lines 20Sc and 205d, respec~ively, of cable 205. The rese~. input to ~lip-:Elop 309 is supplied by instruction regis~er 203 by way o a control line 204a of cable 204. I'he Q output of fllp-fl.op 309 i9 connected to one input of AND ga~e 310, the second input o wh;ch is connected to the output o AND gate 306. The Q output of flip flop 309 is connec~ed to control line 212 leading to the condition compaxe logic unit 213 of Figure 2.
The output of AND gate 310 also is applied to o~e input of an AND gate 312 and ~o one input of an AND gate 3].3.
A second input to AND gate 312 is supplied by ins~ruction register 203 by way of a co~trol line 204b, and a second input to ~ND ga~e 313 is supplied by ~he instruction register by way o a control li~e 204~. The output of AND gate 312 is connec~ed to control line 206 leading to MPDC 10, and the output o~ AND gate 313 is connected to control line 207 also leading to the MPDC.
In ope~ation~ when data is to be read ~rom the memory 12 o Figure 1 to the disk adapter 14, MPDC 10 sets up the requi.red data path. Data ~hereafter is loaded ~rom ~he MP~C 10 to the disk adapter 14 via the logic system of Figure 3, I~ initializing ~he sys~em the finmware control system of Figuxe 2 appl;.es a lo~c one leve.L ~o control line 204a to free the flip-flop 309 for trigger;.ng by the one shot multi-vibrator 311. The ~ir~are control sys~em a~so applies a : logic one signal ~o line 204b to enable gate 312, and a logic ,. _ g _ . , ~ 37'~
2ero signal to line 204c to disable gate 313. ThP MPDC 10 applies a logic one range signal to lîne 205a to enable gates 307 and 308, and a logic one signal to line 205b to acknowledge a data transfer condition. Further) the MPDC 10 applies a positive-going logic one pulse to th~e Sl input o~ multivibrator 311 by way of control line 205c when a data byte is strobed into the.input ~egister of buffer 300. The MPDC also applies a logic zera level to the S2 input o multivibrator 311 by way of contr~l line 2V5d, logic one levels ~o lines 301b and 301c g and logic zero lev~ls to lines 303b and 303c.
When a logic one pulse is applied to the Sl :input of multi-: vibrator 311, the Q output of the mul~ivibrator ~ransi~ions rom a logic o~e level to a logic zero levelO The Q output remains at a logic zero level as long as the Sl input is successlvely s~robed at 0~5 microsecond intervals. Prior to system initialization, ~he reset input to flip-~lop 309 is anabled. The Q output of the flip-flop thereupon transitions to a logic one level to enable gate 310. After system initializa~ion~ the reset input o flip~flop 309 is disabledR
As long as the Q output of multîvibrator 311 remains at 2 logic zero level, however, the flip-1Op is not triggered and the Q output of the flip-~lop remains at a logic one level.
The input register of the FIFO bufer 300 supplies a ~ogic one s~atus sig~al ~o line 301a during time periods in which the register is empty. With lines 301b and 301c a~
logic one levels, the input register status signal is applied through OR gate 302c and inverters 305 to an input of AND gate 306.
The MP~C 10 range count signal applied to line 205a remains :~ . 30 at a logic one level until the transfer of data between main :~ memory 12 and disk adapter 14 is complete. The output o :: gate 307 is thus at a logic one level ~o enable gate 306 The logic one signal at thelou~put of inverters 30S, therefore, is applied ~hrough gates 306, 310 and 312 to -10~
.
-reques~. a dat:a b~te from MPDC 10, I~ clata from main rnemory 12 îs ava.ilable, the ~DC iSS~Je5 a logic one pulse to the ~1 se~ input of mult:i.vlbrrltor 311 to main~ai~ the Q output thereof ln a 1.ogic zero stat~.
When ~he reques~ed data b~te is applied to the lnput register of bu~fer 300 by way of data cable 211, line 301a transitions to a logi.c zero le~vel to disable ~ate 310. Thus no further da~a reques~s ar~ made un~ he data by~e is tran~-fexred ~rom the lnpu~ register i.nto the FIF0 stack~ At that tlme~ the input register again is emptied and li~e 301a transitions to a logi..c one level to again raise the outpu~ o~ AND gate 310 to a logi~ one level. An additional data byte thereby is requested ~rom the MPDC 10, and the hardware agaln strobes the Sl set input o~ the multivibrator. An additional data byte lS then is ~ransferred by way of data cable 211 to the iIlpUt register o b~ fer 300. The proce3s is repea~ed un~il 16 bytes of data have been placed in~o the FIF0 buffer~
When the buffer 300 is filled, lines 226a and 301a transition to a logic zero level~ and lines 226b and 303a transition to a ~og~c on~ level, ~urther,A~ gate 302a is disabled as is gate 310, and no further data requests can be made~ The MoeDC 10 senses that no data requests have occurred within a time period o 0~50 mlcroseconds, a~d ceases to strobe the S1 set input of multivibrator 3110 The multivibra~or there-25 upon t~mes out, and ~he Q output ~hereof transitions from alogic zero to logic one level to trigger the flip-flop 309.
Since the QUtpUt Of NOR gate 304 is at a logic one level 3 the Q ou~put of the 1ip-10p ~ransi~ions from a logic one to a logic æer~ level and ~he Q ou~put thereo~ ~ransitions ~o a lo~ic one level.
The fin~are of Figure 2 continually senses line 212 each 500 nanosecorlds in a ~wo microins~ tion sequence. When the line 21.2 i:ransi~lons rom a lo~ic zero ~o a logic one level~ firmware is alerted that the common bus 13 may be .
~ 3~lJ~
accessed to accommodate nnsolicited bMs re~ues~s wi~hotlt caus~.ng da~a errors. Upon sensing the logic one level on line ~12~ ~irmware resets 1ip-flop 309 by applying a logic zero signal to line 204a to preve~ ~urther triggering by the mul~ivibra~or 311. The ~ ou.tpu~ of ~he ~lip flop thereupon transitions frODl a logic zero to a logic one state to enable gate 310, Durin~ the period ~ha~ the logic system of Figure 3 is retained in a ~uiescent stake, the fi.rmware acknowledges u~solicited bus requests on the common bus 13 of Figure lo While the firmware i5 responding to the bus requests, data in the FIF0 bu~er 3~0 con~inues to be ~ransferred serially ~rom the ou~put regis~er. When the input register of the FIF0 buer ~.s empty, the ou~put of ga~e 302a transitlons to a. logic one level which i.s gated ~hrough AN~ gates 310 and 312 to re~uest an addi~ional data byte from MPDC 10. The firmware control system o MæDC 10 thereupon applies a logic one level to line 204a to permit the flip-~lop 309 to respond to trigger pulses from multivibrator 311. The MPDC hardware again strobes the Sl set input of multivibrator 311a and the above-described process is repeated until the full range o data bytes from ~he MPDC 10 to the disk adapter 1~ has been trans~erred. When the transfer is complete; line 205a transitions to a logic zero level to disable gates 307, 306 : 25 and 310. The logic system then enkers a quiescent state in which no urther data transfers are requested.
When data is to ~e transferred from the disk adapter 14 to MPDC 10, the MPDC applies logic zero signals to lin~s 301b and 301c and logie one signals to lines 303b and 303c.
Gate 302a thereby is disabled and ~ate 302b is enabled. Tlle MP~C also applie~ a logic zero level to line 205c to disable the Sl set input to m~ ivibra~or 311. Further, ~he MPDC
applies a loglc zero level to the line 204b to dLsable gate ~ : 312 and applies a logic one level to line 204c ~o enable ::
.
.
~'~f~ 3~
gate 313. Byte data transfer strobes at the output of ga~e 310 thereby are applied through gate 313 to the MPDC.
The remainder of the system initialization is ~s befor~
described, At the time lines 303b and 303c transitiorl to a logio one level, the MYDC 10 requests a first data byte rom the disk adapter 14. Further, the firmware con~rol system enables the reset input to flip flop 309, thereby disabling the ~rigger inpu~ of the f:Lip~flop and enabling gate 310. Duri~g the data transfer, serial data is recei~ed from the disk adapter 14 by way of data cable 2087 and applied through input register of the buffer 300 to the ou~put register. As the buffer 300 is being filled, the firmware control system accesses common bus 13 to servica unsolicited bus requests.
The time period during which the firmware control sys~em is permitted to service bus reques~s is determined by the difference in the rate at which the FIF0 bu~fer 300 is filled, and the rate at whi;: h the MPDC empties the buf fer . As the serial data flow from disk adapter 14 on cable 208 is at a 2,50 MHz bit tra~sfer rate, and the parallel data flow on cable 210 is at a 2.00 MHz byte transfer rate, the ~PDC may empty the buf fer 300 fas ter than the disk adap~er supplies data. The firmware thus is provided the time period between an emptying and refilling of the bu~fer to service unsolici~ed reques~s.
When the buffer 300 is refilled, the line 303a transitions ~o a logic one level which is reflected at ~he ou~put of A ~ gate 3100 A data strobe thereby is supplied to the MPD~
10 via gate 313 to emp~y the buffer. The firmware control system of MPDC 10 thereupon raises the line 204a to a logic one level ~o ~nable the trigger input of flip-flop 309.
Fu*ther~ the MPDC strobes ~he S2 se~ input of multi~brator 311 with nega~ive-go~ng logic zero pulses to transi~ion the 4 output of ~he multivibrator from a logic one to a log~c zero level.
The Q output remalns at a logi.c zero level as long as the S2 input of the multivibrator is strobed each O.S0 micro-seconds. The Q output o flip-flop 309 thus remains at a logic one level to enable gate 3100 Con~rol of the common bus 13 thus switches from firmware to hardware, and the MPDC
access~s the output register of bufer 300 to emp~y the buffer.
When the outpu~ register of buffer 300 is emp~y of data3 lines 226b and 303a ~ransition ~o a logic zero level which is reflected a~ the ou~put of ga~e 310. The MPDC 10 thereupon ceases to strobe the S2 se~ input of multivibrator 311, and the multivibrator times out. Flip-flop 309 is triggered thereby, and the Q output of the flip-flop transi~ions to a logic one level wh~ch is sensed by the firmware control system.
The firmware thereupon enables the rese~ input of ~he flip-10p, a~d accesses the common bus 13 to service bus requests1 The serial data flow to the FIF0 buffer 300 continues in an un-interrupted flow ~nd the above described proce s is repeated until the data transfer is complete. .
If catas~rophic errors such as a transfer rate error, a read/write timing error~ or a write inhibit at the disk drive occurs during a da~a transfer, the error logic u~it 201 applies a logic zero signal to line 202 to disable gate 308 and thereby set flip-flop 309. The ga~ 310 is disabled thereby and no further data transfers can take place~ :
The logic unit 201 in addition senses lines 226a and 225b during a data transfer ~o sense data underruns and overruns~
If ~h~ input regis~er to buffer 300 remains filled longer than 0.40 microseconds, during a data transfer rom disk adapter 14 to MPDC 10~ a da~a overrwn is indicated and the error logic unit 201 sets ~he flip~flop 309 as before described. The logic uni~ also se~s ~he 1ip-flop 309 when ~he ou~put reglster of buffer 300 remalns empty longer than 0.40 microseconds during a data transfer from the ~DC to the dîsk adapter.
Figure 4 illustra~es in graphic form the timing o the operation of the logic system of Figure 3 during a data ~ransfer be~ween the MPDC 10 and ~he disk aclapter 14.
A discrete waveform 400 illustrates the output of AlND gate 302a3 and discrete waveform 401 illustrate~ the output o AND gate 310. Discrete waveform 402 illustrates the logic one strobe pulses supplled by the MP:DC ~o control line 205c leading to the Sl inpu~ o multivibrator 311, Discrete waveform 403 illus~rates the Q output of the mult~-vlbrator 311, a~d discreta wavefonm 404 illus~rates the Q
~utput of flip-10p 309. Discrete wavefonm 405 illustrates ~he Q ou~put of flip flop 309~ and diserete waveform 406 illus~rates ~he logic signals applied by firmware to control line 204a leading ~o the reset input of flip~flop 30~.
When data is to be read from ~he memory 12 of Figure 1 a~d ~rans~erred ~o ~he disk adap~er 14, the MPDC initializ s the system of Figure 3 as before described. Before a firs~
data byte is received from ~he MP~C at the inpu~ regis~er of the FIF0 buffer ~00, the line 301a and ~he output o A~D
gate 302a are at a logic one level as is în~ica~ed by pulse 400a of wa~eform 400. The outpu~ of AND gate 310 thus transitions to a log~c one level synchonous wi~h pulse 400a as indieated by pulse 401a of waveform 401. The pulsa 401a signals the MP~C to transfer a data byte ~o the FIFO buffer 300. Synchronous wi~h ~he ~raillng edge o ~he pulse 401a, the MPDC issues a pulse 402a of waveorm 402 to load a da~a 37'~
~yte into buffer 300 and to strobe the Sl se~ input of the one shot mul~ivi..brator 311~ Concurrently, ~he Q ou~put of the rnultivibrator transitions to a logic zero level as indîcated by waveportlon 403a of waveQrm 40~. With the
:, ~
3~
- available, the slave assumes the role of master and intiates a transfer to the requesting unit.
In the servicing of bus cycle requests~ ~e centxal processor has the lowest priority, thè MPDC 10 has the next lowest priority, and the memory 12 has the highest priority.
4 A more detailed description of the system of Figure 1 is given in U. S. Patent No. 3,993~981 which is assigned to the assignee of the present invention.
FI~.URE 2 Figure 2 illustrates in a more detailed block diagram form the MPDC 10, the disk adapter 14, and a service request logic unit 200 which emobdies the invention.
The service request logic unit 200 receives error signals by way of a control line 202 from an error logic unit 201 in a disk adapter 14. Unit 200 also receives control signals from a microprogram instruction register 203 by way of a control line 204, and data transfer range and control signals from MPDC 20 by way of a conducting cable 205. The logic unit 200 supplies data requests to the MPDC 10 by way of a control line 206 and data strobes to the MPDC by way of a control line 207. Serial data is received from the disk adapter 14 on a data cable 208, and supplied to the disk adapter on a data cable 209. Further, parallel data transfers between -the logic unit 200 and MPDC 100 occurs on data cables 210 and 211.
`~ When a time period occurs during which a firmware control system may be permitted to access the common bus 13, logic unit 200 issues a status signal along a conducting line 212 leading to a condition compare logic unit 213D The output of the logic unit 213 is supplled to a microprogram memory control unit 214~and to a microprogram address switch unit 215~ A second input to switch unit 215 is connected to the output of a microprogram counter 216. The output of the switch unit is ~5--.~
~ 3~f'~
applled to a microprogram address register 217 which address~s a Read Only Store (ROS) 218 by way of an address cable 219. The output of the ROS 218 is applied to the mlcroprogram instruction regis~er 203.
The control unit 214 supplies control signals to counter 216 by way of a control line 220~ to switch unit 215 by way of a control li,ne 221, to register 217 by way of a control line 222 J and to register 203 by way of a control line 223. The register 203 also supplies control signals to ~ogic uni~ 213 by way of a control line 224~ and to switch unit 215 by way o a control li,ne 22O, During a da~a transfer, catas~rophic errors such as data tr,ansfer rate errors, timing errors and disk drive inhibits may occur. The error logic unit 201 monitors the data flow through logic unit 200 by way of a control cable 22Gg and receives error information from MPDC 10 on a control cable 227 The logic unit 201 1ags the occurrence of errors by issuing error control s:ignals to line 202 and to a control cable 228 leading to MPDC 10.
In operation, data may be transferred from memory 12 of Figure 1 to the MPDC 10, and hence by way of da~a cable 211 to logic unit 200. From logic un.it 200, the data is supplied serially by way of data cable 209 to the disk adapter 14 When data is to be supplied rom a disk de~ice to memory 12 the data is applied serially from disk adap~er 14 to da~a cable 208 leading to logic unit 200. Unit 200 in turn supplies the data in parallel along data cable 210 leading to ~he MPDC 10. During the data transfer, the logic unit 200 requests byte transfers from MPDC 10 by way of control line 206 or indicates the presence of data ready for ~ransfer by way of contro~ line 207. When a reserve memory unit in logic unit 200 i,s filled, the logic ~ni~ issues a signal on line 212 to the condition compare logic unit 213.
.
Sequences of microinstructions comprising a micro-program are stored in the ROS memory 218. Under the control of the mieroprogram memory control unit 2L4, the count of ~he microprogram counter 216 is load~d in~o ~he microprogram address register 217 to address a particular mlcroinstruction in memory 218. The addressed micro-inqtruction is loaded into the microprogram instructlon registar 203 ~ set înput and ou~put switches directing ~he flow of da~a, a~d to provide control signals a~ the elemen~al machine instruction level to direct the operation o~ the functional units comprising the data processing system of Figure 1. At the end of the activity directed by the micro-program control signals, the counter 216 is stepped by the control unit 214 and loaded into the address register 217 to address a nex~ microinstruction in memory 218~ A sequence of micxoinstructions thereby may be executed.
When sequencing of microinstructions depends upon conditions that arise during data processing, there is a condition ~ield in the sequence of microinstructio~s.
This field activates the logic unit 213 by way of control line 224, thereby permit~ing ~he con~rol line 212 to be sa~pled and compared. In respo~se to a condit~on field signal on line Z24, the address switch 215 alters the output of the microprogram counter 216 to construct a ~ext microinstruction address. A new microinstruction sequence thereby is addressed in memory 218.
FIGU~E 3 Figure 3 is a detailed logic schematic diagram of ~he service reques~ logic unit 200 of Figure ~.
Referring to Figure 3, a first-in first-out ~FIFO) buffer 300 reeeives serial data from disk adapter 14 on da~a cable 208, or data in parallel form from MPDC 10 : o~ data cab~e 211~ e preferred embodiment described ' .
~.h~
herein, bufer 300 has a l~-byte capacity, and ls o~ a type manufactllred and sold by Fairchild SemLconductor o Mountain Vi.e~, California as model 9403. Data bytes ar~
rece.îved b~ the i.nput regi.ster of buffer 300, and shlfted through the buffer to the O~ltpUt register at a rate deter-mined by ~he ~all through ti.me between ~he registers, The output register supplies -~he data in parallel Eorm to da~a cahle 210 leading to MPDC 10~ or in serial fo~n to data cable ~09 lea~in~ to ~he disk adap~er 14.
1.0 When the input register o~ buffer 300 is empty, a logic one sî~nal is issued ~o a control line 226a o~ ca~l.e 226 and ~o a con~rol line 301a leadin~g to one inpu~ of an AND gate 302a.
Further, t~7he~ the outpu~ register is illed, a logic one signal is issued to a control line 226b of cable 226, and to a control line 303a l.eading to one input of an AND ga~e 302b. AND gate 302a also receives a write to disk control signal from MPDC 10 on a con~rol line 301b whe~ data is to be transferred from m~in memory 12 to disk adapter 14~ I~ addition, g~te 302a receives l~gic zero end o data field signals on a control line 301c leading from the disk adapter 140 A~D gate 302b further receives an enabling control signal frDm MPDC lO on a con~rol l.ine 303b, and 2 logic one read slgnal rom the MPDC on a con~rol line 303c when da~a is to be read rom disk storage.
The outpu~s of AND gates 302a and 302b are connected ~o correspondl~g înputs of an OR gæte 302c. Ga~es.302a-302c compr~Lse a logic a~ray 302. The outpu~ of array 302 is applie~
to one input of a NOR ga~e 304, and ~hrough four serially eonnected in~erters 305 to one input of an AND ga~e 3060 : 30 A second ~nput to gate 306 is ~onnected to t~e output of an : AMD gat~ 307, one input of which is eonnected to one input of an AND g~te 308 and ko a con~rol line 205a of cable 205 leading to outpu~ terminals of MPDC lQ~ A second input to gate 307 is connected to a con~rol llne 205b of cable 205 9 and a second inpu~ D ga~e 308 ~s connee~ed ~o ron~rol line 202 .
leading to error logic unit 201 of Fîgure 2. The output of gate 308 i5 co~nected to the set :input of a ~lip~flop 309.
The D input to flip-flop 309 i5 connected to the outpu~
o~ NOR ~ate 304l a second input of which is connected to the output o an AND gate 310~ The T trigger input to 1ip-flop 309 is co~nected to the Q output of a one-sho~ multivibrator 311, the Sl a~d S2 set inputs of which are connected to output~
of MPDC 10 by way of control lines 20Sc and 205d, respec~ively, of cable 205. The rese~. input to ~lip-:Elop 309 is supplied by instruction regis~er 203 by way o a control line 204a of cable 204. I'he Q output of fllp-fl.op 309 i9 connected to one input of AND ga~e 310, the second input o wh;ch is connected to the output o AND gate 306. The Q output of flip flop 309 is connec~ed to control line 212 leading to the condition compaxe logic unit 213 of Figure 2.
The output of AND gate 310 also is applied to o~e input of an AND gate 312 and ~o one input of an AND gate 3].3.
A second input to AND gate 312 is supplied by ins~ruction register 203 by way of a co~trol line 204b, and a second input to ~ND ga~e 313 is supplied by ~he instruction register by way o a control li~e 204~. The output of AND gate 312 is connec~ed to control line 206 leading to MPDC 10, and the output o~ AND gate 313 is connected to control line 207 also leading to the MPDC.
In ope~ation~ when data is to be read ~rom the memory 12 o Figure 1 to the disk adapter 14, MPDC 10 sets up the requi.red data path. Data ~hereafter is loaded ~rom ~he MP~C 10 to the disk adapter 14 via the logic system of Figure 3, I~ initializing ~he sys~em the finmware control system of Figuxe 2 appl;.es a lo~c one leve.L ~o control line 204a to free the flip-flop 309 for trigger;.ng by the one shot multi-vibrator 311. The ~ir~are control sys~em a~so applies a : logic one signal ~o line 204b to enable gate 312, and a logic ,. _ g _ . , ~ 37'~
2ero signal to line 204c to disable gate 313. ThP MPDC 10 applies a logic one range signal to lîne 205a to enable gates 307 and 308, and a logic one signal to line 205b to acknowledge a data transfer condition. Further) the MPDC 10 applies a positive-going logic one pulse to th~e Sl input o~ multivibrator 311 by way of control line 205c when a data byte is strobed into the.input ~egister of buffer 300. The MPDC also applies a logic zera level to the S2 input o multivibrator 311 by way of contr~l line 2V5d, logic one levels ~o lines 301b and 301c g and logic zero lev~ls to lines 303b and 303c.
When a logic one pulse is applied to the Sl :input of multi-: vibrator 311, the Q output of the mul~ivibrator ~ransi~ions rom a logic o~e level to a logic zero levelO The Q output remains at a logic zero level as long as the Sl input is successlvely s~robed at 0~5 microsecond intervals. Prior to system initialization, ~he reset input to flip-~lop 309 is anabled. The Q output of the flip-flop thereupon transitions to a logic one level to enable gate 310. After system initializa~ion~ the reset input o flip~flop 309 is disabledR
As long as the Q output of multîvibrator 311 remains at 2 logic zero level, however, the flip-1Op is not triggered and the Q output of the flip-~lop remains at a logic one level.
The input register of the FIFO bufer 300 supplies a ~ogic one s~atus sig~al ~o line 301a during time periods in which the register is empty. With lines 301b and 301c a~
logic one levels, the input register status signal is applied through OR gate 302c and inverters 305 to an input of AND gate 306.
The MP~C 10 range count signal applied to line 205a remains :~ . 30 at a logic one level until the transfer of data between main :~ memory 12 and disk adapter 14 is complete. The output o :: gate 307 is thus at a logic one level ~o enable gate 306 The logic one signal at thelou~put of inverters 30S, therefore, is applied ~hrough gates 306, 310 and 312 to -10~
.
-reques~. a dat:a b~te from MPDC 10, I~ clata from main rnemory 12 îs ava.ilable, the ~DC iSS~Je5 a logic one pulse to the ~1 se~ input of mult:i.vlbrrltor 311 to main~ai~ the Q output thereof ln a 1.ogic zero stat~.
When ~he reques~ed data b~te is applied to the lnput register of bu~fer 300 by way of data cable 211, line 301a transitions to a logi.c zero le~vel to disable ~ate 310. Thus no further da~a reques~s ar~ made un~ he data by~e is tran~-fexred ~rom the lnpu~ register i.nto the FIF0 stack~ At that tlme~ the input register again is emptied and li~e 301a transitions to a logi..c one level to again raise the outpu~ o~ AND gate 310 to a logi~ one level. An additional data byte thereby is requested ~rom the MPDC 10, and the hardware agaln strobes the Sl set input o~ the multivibrator. An additional data byte lS then is ~ransferred by way of data cable 211 to the iIlpUt register o b~ fer 300. The proce3s is repea~ed un~il 16 bytes of data have been placed in~o the FIF0 buffer~
When the buffer 300 is filled, lines 226a and 301a transition to a logic zero level~ and lines 226b and 303a transition to a ~og~c on~ level, ~urther,A~ gate 302a is disabled as is gate 310, and no further data requests can be made~ The MoeDC 10 senses that no data requests have occurred within a time period o 0~50 mlcroseconds, a~d ceases to strobe the S1 set input of multivibrator 3110 The multivibra~or there-25 upon t~mes out, and ~he Q output ~hereof transitions from alogic zero to logic one level to trigger the flip-flop 309.
Since the QUtpUt Of NOR gate 304 is at a logic one level 3 the Q ou~put of the 1ip-10p ~ransi~ions from a logic one to a logic æer~ level and ~he Q ou~put thereo~ ~ransitions ~o a lo~ic one level.
The fin~are of Figure 2 continually senses line 212 each 500 nanosecorlds in a ~wo microins~ tion sequence. When the line 21.2 i:ransi~lons rom a lo~ic zero ~o a logic one level~ firmware is alerted that the common bus 13 may be .
~ 3~lJ~
accessed to accommodate nnsolicited bMs re~ues~s wi~hotlt caus~.ng da~a errors. Upon sensing the logic one level on line ~12~ ~irmware resets 1ip-flop 309 by applying a logic zero signal to line 204a to preve~ ~urther triggering by the mul~ivibra~or 311. The ~ ou.tpu~ of ~he ~lip flop thereupon transitions frODl a logic zero to a logic one state to enable gate 310, Durin~ the period ~ha~ the logic system of Figure 3 is retained in a ~uiescent stake, the fi.rmware acknowledges u~solicited bus requests on the common bus 13 of Figure lo While the firmware i5 responding to the bus requests, data in the FIF0 bu~er 3~0 con~inues to be ~ransferred serially ~rom the ou~put regis~er. When the input register of the FIF0 buer ~.s empty, the ou~put of ga~e 302a transitlons to a. logic one level which i.s gated ~hrough AN~ gates 310 and 312 to re~uest an addi~ional data byte from MPDC 10. The firmware control system o MæDC 10 thereupon applies a logic one level to line 204a to permit the flip-~lop 309 to respond to trigger pulses from multivibrator 311. The MPDC hardware again strobes the Sl set input of multivibrator 311a and the above-described process is repeated until the full range o data bytes from ~he MPDC 10 to the disk adapter 1~ has been trans~erred. When the transfer is complete; line 205a transitions to a logic zero level to disable gates 307, 306 : 25 and 310. The logic system then enkers a quiescent state in which no urther data transfers are requested.
When data is to ~e transferred from the disk adapter 14 to MPDC 10, the MPDC applies logic zero signals to lin~s 301b and 301c and logie one signals to lines 303b and 303c.
Gate 302a thereby is disabled and ~ate 302b is enabled. Tlle MP~C also applie~ a logic zero level to line 205c to disable the Sl set input to m~ ivibra~or 311. Further, ~he MPDC
applies a loglc zero level to the line 204b to dLsable gate ~ : 312 and applies a logic one level to line 204c ~o enable ::
.
.
~'~f~ 3~
gate 313. Byte data transfer strobes at the output of ga~e 310 thereby are applied through gate 313 to the MPDC.
The remainder of the system initialization is ~s befor~
described, At the time lines 303b and 303c transitiorl to a logio one level, the MYDC 10 requests a first data byte rom the disk adapter 14. Further, the firmware con~rol system enables the reset input to flip flop 309, thereby disabling the ~rigger inpu~ of the f:Lip~flop and enabling gate 310. Duri~g the data transfer, serial data is recei~ed from the disk adapter 14 by way of data cable 2087 and applied through input register of the buffer 300 to the ou~put register. As the buffer 300 is being filled, the firmware control system accesses common bus 13 to servica unsolicited bus requests.
The time period during which the firmware control sys~em is permitted to service bus reques~s is determined by the difference in the rate at which the FIF0 bu~fer 300 is filled, and the rate at whi;: h the MPDC empties the buf fer . As the serial data flow from disk adapter 14 on cable 208 is at a 2,50 MHz bit tra~sfer rate, and the parallel data flow on cable 210 is at a 2.00 MHz byte transfer rate, the ~PDC may empty the buf fer 300 fas ter than the disk adap~er supplies data. The firmware thus is provided the time period between an emptying and refilling of the bu~fer to service unsolici~ed reques~s.
When the buffer 300 is refilled, the line 303a transitions ~o a logic one level which is reflected at ~he ou~put of A ~ gate 3100 A data strobe thereby is supplied to the MPD~
10 via gate 313 to emp~y the buffer. The firmware control system of MPDC 10 thereupon raises the line 204a to a logic one level ~o ~nable the trigger input of flip-flop 309.
Fu*ther~ the MPDC strobes ~he S2 se~ input of multi~brator 311 with nega~ive-go~ng logic zero pulses to transi~ion the 4 output of ~he multivibrator from a logic one to a log~c zero level.
The Q output remalns at a logi.c zero level as long as the S2 input of the multivibrator is strobed each O.S0 micro-seconds. The Q output o flip-flop 309 thus remains at a logic one level to enable gate 3100 Con~rol of the common bus 13 thus switches from firmware to hardware, and the MPDC
access~s the output register of bufer 300 to emp~y the buffer.
When the outpu~ register of buffer 300 is emp~y of data3 lines 226b and 303a ~ransition ~o a logic zero level which is reflected a~ the ou~put of ga~e 310. The MPDC 10 thereupon ceases to strobe the S2 se~ input of multivibrator 311, and the multivibrator times out. Flip-flop 309 is triggered thereby, and the Q output of the flip-flop transi~ions to a logic one level wh~ch is sensed by the firmware control system.
The firmware thereupon enables the rese~ input of ~he flip-10p, a~d accesses the common bus 13 to service bus requests1 The serial data flow to the FIF0 buffer 300 continues in an un-interrupted flow ~nd the above described proce s is repeated until the data transfer is complete. .
If catas~rophic errors such as a transfer rate error, a read/write timing error~ or a write inhibit at the disk drive occurs during a da~a transfer, the error logic u~it 201 applies a logic zero signal to line 202 to disable gate 308 and thereby set flip-flop 309. The ga~ 310 is disabled thereby and no further data transfers can take place~ :
The logic unit 201 in addition senses lines 226a and 225b during a data transfer ~o sense data underruns and overruns~
If ~h~ input regis~er to buffer 300 remains filled longer than 0.40 microseconds, during a data transfer rom disk adapter 14 to MPDC 10~ a da~a overrwn is indicated and the error logic unit 201 sets ~he flip~flop 309 as before described. The logic uni~ also se~s ~he 1ip-flop 309 when ~he ou~put reglster of buffer 300 remalns empty longer than 0.40 microseconds during a data transfer from the ~DC to the dîsk adapter.
Figure 4 illustra~es in graphic form the timing o the operation of the logic system of Figure 3 during a data ~ransfer be~ween the MPDC 10 and ~he disk aclapter 14.
A discrete waveform 400 illustrates the output of AlND gate 302a3 and discrete waveform 401 illustrate~ the output o AND gate 310. Discrete waveform 402 illustrates the logic one strobe pulses supplled by the MP:DC ~o control line 205c leading to the Sl inpu~ o multivibrator 311, Discrete waveform 403 illus~rates the Q output of the mult~-vlbrator 311, a~d discreta wavefonm 404 illus~rates the Q
~utput of flip-10p 309. Discrete wavefonm 405 illustrates ~he Q ou~put of flip flop 309~ and diserete waveform 406 illus~rates ~he logic signals applied by firmware to control line 204a leading ~o the reset input of flip~flop 30~.
When data is to be read from ~he memory 12 of Figure 1 a~d ~rans~erred ~o ~he disk adap~er 14, the MPDC initializ s the system of Figure 3 as before described. Before a firs~
data byte is received from ~he MP~C at the inpu~ regis~er of the FIF0 buffer ~00, the line 301a and ~he output o A~D
gate 302a are at a logic one level as is în~ica~ed by pulse 400a of wa~eform 400. The outpu~ of AND gate 310 thus transitions to a log~c one level synchonous wi~h pulse 400a as indieated by pulse 401a of waveform 401. The pulsa 401a signals the MP~C to transfer a data byte ~o the FIFO buffer 300. Synchronous wi~h ~he ~raillng edge o ~he pulse 401a, the MPDC issues a pulse 402a of waveorm 402 to load a da~a 37'~
~yte into buffer 300 and to strobe the Sl se~ input of the one shot mul~ivi..brator 311~ Concurrently, ~he Q ou~put of the rnultivibrator transitions to a logic zero level as indîcated by waveportlon 403a of waveQrm 40~. With the
5 Q OU~pll~ of ~he multivibrator at a logîc zero level~ the 1ip flop 309 remaills in a quiesce~t state and the Q output of the 1ip flop remains at a logîc one level as lndicated by wa~e~orm 404. The Q output of the flip~flop remains at a logic zero level as indicated by waveform 405.
As data bytes are reoeived by the input register of the FIFO buffex 300 from the MP~C, the output of gate 302a transiticns ~o ~ l.ogic zero as indicated by waveportion 400b.
In response thereto, the output of gate 3l0 also tran,si.tlons ~o a logic zero as indicated by waveportion 401b, When the data byte is ~ransferred înto ~he FIFO stack and the input register agaln is empty, however, the outputs of gates 302a and 310 agai.n transi.tion to a logic one as indica~ad by pulses 400c and 401c, respectively. The MPDC thus receives a~ additional data byt~ request~ and upon the oc~urrence o the traillng edge of pulses 400c a~d 401c3 the MPDC issues a logic one pulse 402b to agai~ strobe the Sl set inp~t of multivibrator 311~ The data fl~w contînues as above described until the FIFO bufEer 300 is filled, In that even~) ~he outputs of gates 302a and 310 again transi~ion to a logic ~ero as indioa~ed by reference num~ers 400d and 401d~
respectively. When no fur~her da~a requests are issued~
~ ~ the MPDC l~ ceases to strobe the SL set input o~ multivibrator : 311. ~ine 205c thus remains a~ a logie zero level as .
, ~ 3~o''~
indicated by reference number 402dc When the MPDC delays more than O~SO microseconds in s~robing the m~lti~ibrator 311, ~he ~l~ivibrator times ou~ and the Q ou~put therof tra~sitions to a logie one level as indicated by wavepor~ion 403b. The ~lip-flop 309 is triggered thereby~ and the Q outpu~ ~hereof transi-tions to a logic zero level as indicated by waveportion 404a. The Q output of the flip-flop transitions ~o a logic one level as indica~ed by waveportion 405a.
The firmware control system of the MPDG 10 senses the logic level of waveportion 405a, and issues a logi,c zero signal to the co~trol line 204a to reset the flipW10p 309 as indicated by waveportion 406a. Synchronous there-with ~he Q output of .flip-flop 309 transitions to a logic zero level as indica~ed by reference number 405b, and the Q output of the flip-flop ~ransitions to a logic one level as indicated by reference number 404b. The firmware eontrol system o the MPDC a~ ~h;s time accQsses the common bus 13 to service bus requestsO
When the input register of FIFO bu~fer 300 ls emp~ied, the outputs of ga~es 302a and 310 again ~ransition to a logic one level as indicated by pulses 400e and 401e, r~spectively~ The ~inmware control system of the MPDC
thereupon applies a loglc one signal to line 204a a~ indicated by:waveportion 406b ~o enable the trigger input ~o flip-flop : :309~ Synchronous therewith, the MPDC strobes ~he Sl set input of multi~ibrator 311, and ~he Q ou~pu~ of the multl~
: ~ vibrator ~ransi~ions ~o a logic zero level as indicated by ~ ~ .
~ .
: ::
:
.
.L~ 3~
waveportion 403c. The Q output of .~lip-:flop 309 thus remains at a logic one level as indicated b~y waveform 404 ~nd the Q
output of the flip-10p remains at a logic zero level as indicated by wave:eorm 405. The data process then contir~ues 5 as beore described.
Figure 5 illustxates in graphic onn the timing of the operation of ~he logic system of Figure 3 during a data ~rans fer from the disk adap~er 14 $o ~he MPDC 10.
A discrete waveform 500 illustrates the output of AND
gate 302b, and a discrete wavefor~ 501 illustrat~ ~he output of AND gate 310. ~ discreke waveform 502 illustrates the negative-going logic zero strobe pulses supplied by the MPDC
to control line 205d leading ~o the S2 i~put of multivibrator 311, A dlscrete waveform 503 illus~rates the Q ou~pu~ of ~he multivibrator 311, and a discre~e wavefol~ 504 illus~rates the Q output of flip-~lop 3090 A discre~e waveform 505 illustrates the Q output of flip-flop 309~ and a discrete waveform 506 illustrates ~he logic signals supplied by firm-ware to co~trol line 204a leading to the reset inpu~ of ~lip-flop 309~
When data is to be transerred from the disk adapter 14 to the MPDC 10, ~he MPDC applies logic zero signals~to lines 301b and 301c to disable gate 302a~ The MPDG further applies 2S logic one signals to lines 303b and 303c to enable gate 302bo The MPDC also applies a logic zero signal to line 205c to dis-able the Sl se~ input to multivibra~or 311. The remainder of the syst~m ini~ializa~ion is as before described in eonnection : wi~h the description of Figure 3.
3~ ~t the tim~ es 303b and 303c transi~ion ~o a logic one level, the MPDC 10 requests a first da~a byte from ~he disk adapter 14. In addition the firmware con~rol syste~n o the MPDC lssues a logic zero signal as illustrated by waveportion 506a ~o reset flip~ flop 3090 The Q outpu~ o~ 1ip-flop 309 -18~
" ~3 ~t J,1~
thus is raised to a log~c one level to enable gate 310 to signal th~ occurrence of data in the output register of buffer 300.
I~ response ~o the MPDC data r~ques~, data is ~ed serially from th~ dlsk adapter 14 to the input register of the FIF0 bu.~fer 300 at a 2,5QM~Iz bit ~ransfer ra~e. During the t.ime period in which buffer 300 is be~ng filled, the firm~are control system accesses the common bu,s 13 to service unsolici~ed bus requests. When the FIF0 bllfer 300 is filled, line 303a lPading from the output register o~ the buffer transî.tions t-o a logic one l.evel. The output of the gate~
302b and 310 thereupon transition to a logic one level as indicated by waveportions 500a and 501a, respectively. The MPDC 10 senses the logic one output of gate 310, and in re-sponse thereto the fîrm~are control system of the MPDC
issue~ a logic one level to line 204a, as i.llustrated by waveportion 506b to permit flip-flop 309 to respond to ~rigger pulses from multivibrator 311. The MPDC also issues a series of negative-go~ng logic zero pulses as illus~rated by pulses S02a to the S2 set input cf multivibrator 311. The Q ou~pu~
: ~ o~ multivibrator 311 thereby is held at a logîc zaro level as illustrated by waveportion 503.a, and the Q ou~pu~ of ~lip-~lop 309 remains at a logic one level as illustrated by waveportion 504a, The MPDC further accesses the output regist~r of FIF0 bufer 300 to empty the. buf fer.
When the output register of FIF0 bufer 300 is emptied, lines 226b and 303a transi~ion to a logic zero level which ; is gated to the outpu~s o~ gates 302b and 310 as illustrated : ~ by wa~eportions 500b and 501b, respectively. Thc MPDC 10 ~ 30 thereupon ceases to supply negative-going logic zero pulses : ~ ~ to multivibrator 311 as illus~rated by waveportion 502b.
~: The mul~ivi.brator thus ~imes out, and Q ou~pu~ thereof :~ transitio~s to a logic one level as illustrated by waveportion :~
: : -19-: :
.
~ 3~
503b. The flip-flop 309 is triggered ther~by, and the logic one level at the output of ~OR gate 304 is ~rans-ferred to the Q output Qf the flip-flop as illustrated by waveportion 505a. The Q ou~put of tble flip-flop transitions ~o a logic zero level as indica~d at 504b. The firm~are co~trol system of the MPDC 10 senses the logic one level at the Q ou~put of ~he flip-flop, and applies a logic zero signal illustrated by waveportion 506c to line 204a to reset the flip-~lop. The Q ou~put of the flip-flop thereupon lV transitions to a logic zero as indicated at 505b o~ wavc-form 505~ a~d the Q output of the flip-flop again transi-tions to a logic one level as indicated by waveportion 504c.
The firmware control systam thereupon accesses the ~ommon bus 13 ~o service unsolicited bus requestsO The serial data flow from the disk adapter 14, however, is not interrupted, and continues to fill the input register of the buffer.
No further data strobes are issued to the MPDC until the FIFO bu~fer 300 again is filled. In that event, ~he lines 225b a~d 303a again transltion ~o a logic one level which is ga~ed through ~ND gates 302b and 310. The MPDC thereupon is : signalled to again empty the FIFO bufer 300, a~d ~h~ process proceeds as before described.
Having described the i~vention in conne~tion with certain specific embodimen~s thereof, it is to be understood that ~urther modifications may now suggest themselves ~o ~hose skilled in the art and i~ is intended ~o cover such mod~fi-cations as fall within the scope of ~he appended claims~
What is claimed is:
As data bytes are reoeived by the input register of the FIFO buffex 300 from the MP~C, the output of gate 302a transiticns ~o ~ l.ogic zero as indicated by waveportion 400b.
In response thereto, the output of gate 3l0 also tran,si.tlons ~o a logic zero as indicated by waveportion 401b, When the data byte is ~ransferred înto ~he FIFO stack and the input register agaln is empty, however, the outputs of gates 302a and 310 agai.n transi.tion to a logic one as indica~ad by pulses 400c and 401c, respectively. The MPDC thus receives a~ additional data byt~ request~ and upon the oc~urrence o the traillng edge of pulses 400c a~d 401c3 the MPDC issues a logic one pulse 402b to agai~ strobe the Sl set inp~t of multivibrator 311~ The data fl~w contînues as above described until the FIFO bufEer 300 is filled, In that even~) ~he outputs of gates 302a and 310 again transi~ion to a logic ~ero as indioa~ed by reference num~ers 400d and 401d~
respectively. When no fur~her da~a requests are issued~
~ ~ the MPDC l~ ceases to strobe the SL set input o~ multivibrator : 311. ~ine 205c thus remains a~ a logie zero level as .
, ~ 3~o''~
indicated by reference number 402dc When the MPDC delays more than O~SO microseconds in s~robing the m~lti~ibrator 311, ~he ~l~ivibrator times ou~ and the Q ou~put therof tra~sitions to a logie one level as indicated by wavepor~ion 403b. The ~lip-flop 309 is triggered thereby~ and the Q outpu~ ~hereof transi-tions to a logic zero level as indicated by waveportion 404a. The Q output of the flip-flop transitions ~o a logic one level as indica~ed by waveportion 405a.
The firmware control system of the MPDG 10 senses the logic level of waveportion 405a, and issues a logi,c zero signal to the co~trol line 204a to reset the flipW10p 309 as indicated by waveportion 406a. Synchronous there-with ~he Q output of .flip-flop 309 transitions to a logic zero level as indica~ed by reference number 405b, and the Q output of the flip-flop ~ransitions to a logic one level as indicated by reference number 404b. The firmware eontrol system o the MPDC a~ ~h;s time accQsses the common bus 13 to service bus requestsO
When the input register of FIFO bu~fer 300 ls emp~ied, the outputs of ga~es 302a and 310 again ~ransition to a logic one level as indicated by pulses 400e and 401e, r~spectively~ The ~inmware control system of the MPDC
thereupon applies a loglc one signal to line 204a a~ indicated by:waveportion 406b ~o enable the trigger input ~o flip-flop : :309~ Synchronous therewith, the MPDC strobes ~he Sl set input of multi~ibrator 311, and ~he Q ou~pu~ of the multl~
: ~ vibrator ~ransi~ions ~o a logic zero level as indicated by ~ ~ .
~ .
: ::
:
.
.L~ 3~
waveportion 403c. The Q output of .~lip-:flop 309 thus remains at a logic one level as indicated b~y waveform 404 ~nd the Q
output of the flip-10p remains at a logic zero level as indicated by wave:eorm 405. The data process then contir~ues 5 as beore described.
Figure 5 illustxates in graphic onn the timing of the operation of ~he logic system of Figure 3 during a data ~rans fer from the disk adap~er 14 $o ~he MPDC 10.
A discrete waveform 500 illustrates the output of AND
gate 302b, and a discrete wavefor~ 501 illustrat~ ~he output of AND gate 310. ~ discreke waveform 502 illustrates the negative-going logic zero strobe pulses supplied by the MPDC
to control line 205d leading ~o the S2 i~put of multivibrator 311, A dlscrete waveform 503 illus~rates the Q ou~pu~ of ~he multivibrator 311, and a discre~e wavefol~ 504 illus~rates the Q output of flip-~lop 3090 A discre~e waveform 505 illustrates the Q output of flip-flop 309~ and a discrete waveform 506 illustrates ~he logic signals supplied by firm-ware to co~trol line 204a leading to the reset inpu~ of ~lip-flop 309~
When data is to be transerred from the disk adapter 14 to the MPDC 10, ~he MPDC applies logic zero signals~to lines 301b and 301c to disable gate 302a~ The MPDG further applies 2S logic one signals to lines 303b and 303c to enable gate 302bo The MPDC also applies a logic zero signal to line 205c to dis-able the Sl se~ input to multivibra~or 311. The remainder of the syst~m ini~ializa~ion is as before described in eonnection : wi~h the description of Figure 3.
3~ ~t the tim~ es 303b and 303c transi~ion ~o a logic one level, the MPDC 10 requests a first da~a byte from ~he disk adapter 14. In addition the firmware con~rol syste~n o the MPDC lssues a logic zero signal as illustrated by waveportion 506a ~o reset flip~ flop 3090 The Q outpu~ o~ 1ip-flop 309 -18~
" ~3 ~t J,1~
thus is raised to a log~c one level to enable gate 310 to signal th~ occurrence of data in the output register of buffer 300.
I~ response ~o the MPDC data r~ques~, data is ~ed serially from th~ dlsk adapter 14 to the input register of the FIF0 bu.~fer 300 at a 2,5QM~Iz bit ~ransfer ra~e. During the t.ime period in which buffer 300 is be~ng filled, the firm~are control system accesses the common bu,s 13 to service unsolici~ed bus requests. When the FIF0 bllfer 300 is filled, line 303a lPading from the output register o~ the buffer transî.tions t-o a logic one l.evel. The output of the gate~
302b and 310 thereupon transition to a logic one level as indicated by waveportions 500a and 501a, respectively. The MPDC 10 senses the logic one output of gate 310, and in re-sponse thereto the fîrm~are control system of the MPDC
issue~ a logic one level to line 204a, as i.llustrated by waveportion 506b to permit flip-flop 309 to respond to ~rigger pulses from multivibrator 311. The MPDC also issues a series of negative-go~ng logic zero pulses as illus~rated by pulses S02a to the S2 set input cf multivibrator 311. The Q ou~pu~
: ~ o~ multivibrator 311 thereby is held at a logîc zaro level as illustrated by waveportion 503.a, and the Q ou~pu~ of ~lip-~lop 309 remains at a logic one level as illustrated by waveportion 504a, The MPDC further accesses the output regist~r of FIF0 bufer 300 to empty the. buf fer.
When the output register of FIF0 bufer 300 is emptied, lines 226b and 303a transi~ion to a logic zero level which ; is gated to the outpu~s o~ gates 302b and 310 as illustrated : ~ by wa~eportions 500b and 501b, respectively. Thc MPDC 10 ~ 30 thereupon ceases to supply negative-going logic zero pulses : ~ ~ to multivibrator 311 as illus~rated by waveportion 502b.
~: The mul~ivi.brator thus ~imes out, and Q ou~pu~ thereof :~ transitio~s to a logic one level as illustrated by waveportion :~
: : -19-: :
.
~ 3~
503b. The flip-flop 309 is triggered ther~by, and the logic one level at the output of ~OR gate 304 is ~rans-ferred to the Q output Qf the flip-flop as illustrated by waveportion 505a. The Q ou~put of tble flip-flop transitions ~o a logic zero level as indica~d at 504b. The firm~are co~trol system of the MPDC 10 senses the logic one level at the Q ou~put of ~he flip-flop, and applies a logic zero signal illustrated by waveportion 506c to line 204a to reset the flip-~lop. The Q ou~put of the flip-flop thereupon lV transitions to a logic zero as indicated at 505b o~ wavc-form 505~ a~d the Q output of the flip-flop again transi-tions to a logic one level as indicated by waveportion 504c.
The firmware control systam thereupon accesses the ~ommon bus 13 ~o service unsolicited bus requestsO The serial data flow from the disk adapter 14, however, is not interrupted, and continues to fill the input register of the buffer.
No further data strobes are issued to the MPDC until the FIFO bu~fer 300 again is filled. In that event, ~he lines 225b a~d 303a again transltion ~o a logic one level which is ga~ed through ~ND gates 302b and 310. The MPDC thereupon is : signalled to again empty the FIFO bufer 300, a~d ~h~ process proceeds as before described.
Having described the i~vention in conne~tion with certain specific embodimen~s thereof, it is to be understood that ~urther modifications may now suggest themselves ~o ~hose skilled in the art and i~ is intended ~o cover such mod~fi-cations as fall within the scope of ~he appended claims~
What is claimed is:
Claims (5)
- Claim 1. A data transfer control system for signalling the occurrence of a time period during which a common communication bus may be accessed by a firmware control system during a data transfer between a main memory and a mass storage device without compromising the data transfer rate or incurring data errors, said bus electrically linking a central processing unit, said firmware control system, a mass storage control unit, and said main memory, which comprises:
(a) memory means in electrical communication with said mass storage device and said control unit for transferring data therebetween and indicating both the presence of input data and the occurrence of a filled memory condition;
(b) logic gate means responsive to said memory means and said control unit for providing data strobes to synchronize the flow of data between said memory means and said control unit: and (c) logic timing means in electrical communication with said control unit and said logic gate means for issuing a control signal to said firmware control system indicating the occurrence of said time period. - Claim 2 J The combination set forth in Claim 1, wherein said memory means is a first-in-first-out buffer having an input register which signals the absence of data and an output \ register which signals the presence of data.
- Claim 3. The combination set forth in Claim 2, wherein said logic gate means includes:
(a) a first AND gate in electrical communication with said input register and said control unit;
(b) a second AND gate in electrical communication with said output register and said control unit;
(c) an OR gate having inputs connected to the outputs of said first AND gate and said second AND gate;
(d) a plurality of serially connected inverters connected to the output of said OR gate;
(e) a third AND gate having first input connected to the output of said plurality of inverters;
(f) a fourth AND gate in electrical communication with said control unit and having an output connected to a second input of said third AND gate; and (g) a fifth AND gate having a first input connected to the output of said third AND gate. - Claim 4. The combination set forth in Claim 3 wherein said logic timing means includes:
(a) a sixth AND gate in electrical communication with said control unit;
(b) a monostable multivibrator in electrical communication with said control unit;
(c) a NOR gate having one input connected to the output of said OR gate and a second input connected to the output of said fifth AND gate; and (d) a flip-flop in electrical communication with said NOR gate and responsive to said multivibrator, said sixth AND gate and said firmware control system, and having one output connected to a second input of said fifth AND gate and a second output in electrical communication with said firmware control system. - Claim 5. In a data processing system operating under the control of both hardware and firmware control means, said system having a common communication bus linking a central processing unit, a main memory, a disk controller, a disk adapter and a mass storage disk system, the combination which comprises:
(a) first-in-first-out buffer means in electrical communication with said disk adapter and said disk controller for transferring data between said disk system and said main memory;
(b) first logic means responsive to said disk controller and said buffer means for requesting a data transfer between said buffer means and said disk controller; and (c) second logic means in electrical communication with said firmware control means, said disk controller and said first logic means for signalling the presence of a data transfer state during which said firmware control means can service bus requests on said common bus without incurring data errors or interfering with the data transfer rate between said disk system and said main memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US816,985 | 1977-07-19 | ||
| US05/816,985 US4161778A (en) | 1977-07-19 | 1977-07-19 | Synchronization control system for firmware access of high data rate transfer bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1112370A true CA1112370A (en) | 1981-11-10 |
Family
ID=25222098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA303,332A Expired CA1112370A (en) | 1977-07-19 | 1978-05-15 | Synchronization control system for firmware access of high data rate transfer bus |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4161778A (en) |
| JP (1) | JPS5422132A (en) |
| AU (1) | AU518803B2 (en) |
| CA (1) | CA1112370A (en) |
| DE (1) | DE2831280C2 (en) |
| FR (1) | FR2398349A1 (en) |
| GB (1) | GB2001463B (en) |
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| US10362273B2 (en) | 2011-08-05 | 2019-07-23 | Honeywell International Inc. | Systems and methods for managing video data |
| CN104137154B (en) | 2011-08-05 | 2019-02-01 | 霍尼韦尔国际公司 | Systems and methods for managing video data |
| US9344684B2 (en) | 2011-08-05 | 2016-05-17 | Honeywell International Inc. | Systems and methods configured to enable content sharing between client terminals of a digital video management system |
| US10523903B2 (en) | 2013-10-30 | 2019-12-31 | Honeywell International Inc. | Computer implemented systems frameworks and methods configured for enabling review of incident data |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3351917A (en) * | 1965-02-05 | 1967-11-07 | Burroughs Corp | Information storage and retrieval system having a dynamic memory device |
| US3710327A (en) * | 1970-12-14 | 1973-01-09 | Ibm | Synchronous communications adapter |
| US4053950A (en) * | 1976-04-30 | 1977-10-11 | International Business Machines Corporation | Residual status reporting during chained cycle steal input/output operations |
| US4038642A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Input/output interface logic for concurrent operations |
-
1977
- 1977-07-19 US US05/816,985 patent/US4161778A/en not_active Expired - Lifetime
-
1978
- 1978-05-15 CA CA303,332A patent/CA1112370A/en not_active Expired
- 1978-05-15 JP JP5747678A patent/JPS5422132A/en active Granted
- 1978-07-04 AU AU37760/78A patent/AU518803B2/en not_active Ceased
- 1978-07-05 FR FR7820043A patent/FR2398349A1/en active Granted
- 1978-07-17 DE DE2831280A patent/DE2831280C2/en not_active Expired
- 1978-07-19 GB GB787830410A patent/GB2001463B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2398349A1 (en) | 1979-02-16 |
| DE2831280C2 (en) | 1985-05-23 |
| JPS6133222B2 (en) | 1986-08-01 |
| FR2398349B1 (en) | 1983-03-18 |
| GB2001463B (en) | 1982-02-24 |
| AU3776078A (en) | 1980-01-10 |
| DE2831280A1 (en) | 1979-02-08 |
| JPS5422132A (en) | 1979-02-19 |
| GB2001463A (en) | 1979-01-31 |
| US4161778A (en) | 1979-07-17 |
| AU518803B2 (en) | 1981-10-22 |
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