CA1108306A - Process for manufacturing printed circuit boards - Google Patents

Abstract

ABSTRACT OF THE INVENTION
Printed circuits are fabricated by a process which employs initial chemical deposition of copper on a predrilled substrate followed by electroplating build-up of conductors to desired pattern. The conductors are then passivated by thinly plating them with a mechanically durable, chemically passive metal.
To provide solder compatibility in areas where connections are to be made to the printed circuits, a plating of tin/lead is applied in those areas while masking all other areas to eliminate plating. The remaining exposed copper is then etched away. An insulating solder mask is then applied.

Description

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BACKGROUND OF THE ~NVENTION
Field of the Invent~on ..
This invention relates to the field of printed circuit assemblies manuf~cturing and, in particular, to pxocesses for manufacturing printed circuit boards.
Prior Art ~
Since their disco~ery, printed circuit techniques have ~` t become a commercially important part of almost every area of the electronics industry. Printed circuitry has become virtua1ly the only economically viable technique for the interconnection of components in even fairly low volume production. In high volume production, printed circuitx~ is universally employed.
; Recent technological developments in integrated circuits ` and their consequent ~lidespread acceptance and use in essentially every phase of consumer, commercial, industrial and military . .
and aerospace electronics have resulted ln two conflicting demands being placed upon printed circuit manufacturers. First, the - complexity of the interconnection required, coupled with the in-herent miniaturization of integrated circuits themselves have led to increased demands for further and further miniaturization of printed circuits in order to accommodate the desired integrated circuit functions within a package which does not become so large that the advantage of miniaturization is lost in the interconnec-tion process Second, as circuit densities increase in response - to the demand for miniaturization and the ccmplexity and number of interconnection likewise increase, the opportunities for failure similarly increase thereby giving rise to a demand for inherently higher reliability intercolmection techniques. The response to these demands has been a series of improvements in printed circuît manufacturing processes with consequently higher densities and reliabilities being obtained. Still further .

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improvement is neaded, however, in order to allow ~urther mini~
turization and rel~a~lity improvements.
Of part~cular concern in the past have been the techniques employed for plated-through holes, and the compatibility of the printed circuits themselves with mass-production soldering equip-ment such as "wave" soldering. To use plated~khrou~h holes as conductors or as component lead receptables it is necessary that a solder-compatible material, preferably solder itself r be plated on the walls of the holes and on adjacent terminal pad areas.
To do this realiably, the usual solut~on has been to apply solder to all areas of the conductor traces. Both the presence of the solder an~ the method of applying it, however, contribute to a loss of reliability and a limitation on the useful life of the board as well as placing severe restriction on the minimum spaces allowable between adjacent conductors.
Prior Art Techniques ;~ The superiority of the present invention in overcoming these problems may best be seen in its relationship to the three commonly used processes which make up the bulk of the present day volume in printed circuit ~oard manufacturing.
All of the presently known printed circuit fabrication processes are commenced with the rendering of a schematic circuit diagram into a master art-work layout in a facsimile of the desired conductor pattern. The layout may be done in larger-than-actual size for ease of layout and to enhance accuracy~
Typically, it is done at ratios varying from 2:1 to 4:1, on a dimensionally stable, transparent base such as Mylar. After the art-work layout is completed and checked,~it is photographically ; reduced to an actual s~ize film which may be positive or negative, - 30 or both, dependin~ upon the photographic processes to follow.
From this point on, two different uses are made of the films. ~-They may be used directly in con-tact ~ith the printed circuit ~ ~ ,.
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board, as a cont~ct p~int film fox the eXpQ$U~e of photo~resist, or they may be used indirectly as the ~asteX ;~or photographlc porcessing of siLk-scxeens to be used ~n application o~ Various processing chemicals or substances~
Copper-Tin~Lead Proce'ss A typical plated-through hole printed circuit assembly using the conventional and well known copper~tin~lead techni~ue is acco~plished as follow$.
A substrate of copper-clad insulating material, usually fiberglass-epoxy, is drilled to a pre~esta~lished hole pattern suitable for -the accommodation of component leads to be mounted on the board in accordance With requirements es-tablished during -~
the preparation of the art-work layout. On the driIled board, ' a thin layer of copper is deposited'by electroless chemical deposition. The purpose of this first thin layer is to ; provide a continuous conductiny path over the entire surface of the board, including the walls of the previously drilled holes.
A negative image of plating resist is then applied to the thinly-plated board by either silk-screening or by a dry-film process, leaving exposed only those portions of the board on which it is desired to have circuit conductors. ~' After selectively masking the board, the exposed areas ~ ' of previously deposited copper, including the hole walls, are `~ ' electroplated with copper to build up the circuit traces to the desired thickness. A plating of tin/lead is then applied over the exposed copper in the desired thickness to provide a solder compatible surface for component attachment.
The negative image resist is next chemically stripped ;
~ 30 leaving expo$ed the rem~ining thin layer of chemically deposited copper which is then etched awa~ by immersion in the etching bath.

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Hea-t is then applied to the printed circuitry to cause the tin/lead plating to amalgamate into solder~
If desired, a solder mask may be applied over the board by silk-screen techniques, leaving only those portions of the circuit to which connection of component leads or discrete wiring, or on which connectors will be installed, uncovered.
By using a solder mark in this and other processes, "bridging"
of closely spaced circuit paths is a~oided when components are mounted and the printed circuitry is soldered in a "wave"
soldering process, Mask-Over~Copper Another ~idely used techni~ue is -the so-called "mask-over~copper" process. This process combines copper-clad wall plating to the desired thickness. A hole pattern is first drilled, then copper is chemically deposited to line the hole walls. Organic etching resist is then applied to plug the holes, ~ protecting the hole walls from subsequent etching steps. A
- layer of organic etchlng resist in a positive pattern is then ;~
applied thereby definin~ the circuit conductor to be "printed"
on the board. The entire board is then submerged in an etching bath which removes the exposed copper leaving behind only those areas of copper covered by the etching resist.
All organic resist is then chemically stripped from the board leaving behind a bare copper conductor pattern with copper walled holes. A solder mask of heat resistant insulating ~aterial, typically a two-part epoxy is then applied to the board in a pattexn which leaves only the ~
~; terminal pad areas ~or component mounting and all~ole areas ~;
uncovered. Followi`ng application of the solder mask, -the board receives an application of solder flux~ The entire board is then dipped into molten solder causing the exposed, fluxed copper to hecome coated by the soldex. Since an excess of solder may adhere to the board causing bridged traces and 33~i~

plugged holes, lt must be removed eithex by "~lin~ing" or "hydro-squeegee". "Slin~ing" is a relati~ely crude method which basically entails rapidly moving the board ~n an arcuate path thereby causing a high centrifu~al force which ~n turn causes the excess molten solder to separate ~rom the board~
"Hydro-squeegee" refers ~o a method of directing a hi~h-pressure stream of hot oil onto the board, causing the solder to become or remain molten ~hile the force of the oil on the board causes the excess solder to be sepaxated ~rom the board.
The board is then trimmed to final conf1guration and is ready for component mounting and final soldering.
Both the "slinging" and "hydro-squeegee" methods suffer from the severe drawback that they are highly inexact. The thickness of the solder coating is subject to gross variations depending upon difficult-to-control factors such as the temperature profile of the board, the geometry of the traces, cool-down rates and the like. Thus, in hotter~areas of the board, a thinner coating will result. In areas where sharp bends in traces occur, thicker coatin~ tends to accummulate.
At the edge of all wide trac~s, the coatin~ tends to be thicker than in the middle of the traces.
The non-uniformity of the solder coating is most critical in the vicinty of the holes. At the top and bottom -of the hole, a sharp discontinuity in the surface tends to cause a thinner coatin~ at precisely the point that a thicker coating would be desirable from a mechanical strength standpoint.
At the other extreme, inside the hole, a thicker than desired coating can be easily built up due to surface tension effects and the difficulty of removing any excess solder which finds its way into the hole. At the extreme, completely plugged holes result which required individual clearing before the board can be used.

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~ n additional drawback is that when the board is dipped into the molten solder, -the board and its traces are subjected to extreme thermal shock. The result~n~ stresses can c~use delamination o~ the traces from the board, and delamination of the solder mask.
The "mask-over-copper" process can be relatively economical since electroplating is not required to be used. It is satis:Eactory for commercial ~uality printed wiring boards where trace uniformity is not critical and where entrapment of foreign materials in the solder coating is not a problem.
Additive Process . . .
A third widely used technique is the so-called "additive"
process. Printed circuitry is made in accordance with this process by chemically depositing copper to the required thickness ; on an insulating substrate. Typical steps in fabricating printed circuit boards in accordance with this process are as follows.
An insulating substrate, typically a glass-epoxy lamina is drilled in the required hole pattern. A coating of a strippable organic mask is then applied in a pattern corresponding to a negative image of the desired circuitry~
The coated board is then chemically plated with copper with the thickness of the plating being built up to the desired thickness by adjusting the time of immersion in the bath.
Plating of the exposed board surfaces includes the walls of the previously drilled holes as well. After building up the circuit traces to the desired thlckness, the board is chemically stripped of all organic material leaving ~ehind the chemically plated copper in the desired trace pattexn. A solder mask ` 30 is then applied as in "mask-over-copper" processing, leaving only pad and interconnect areas exposed~ These exposed areas are then coated with flux, and d~pped into molten solder.

The excess solder is removed by "sling~ng~' or "h~dro~squeegee."
After trimming to final ou-tline, the board is ready for component mounting and final solderlng.
As is the case with mask-over-copper processing, the "additive" type board is subjected to severe thermaI shock by dipping the board into molten solder. The same problems of solder coat uniformity and impur~ty entrapment exi~t as with mask-over~copper boards.

~dditive boards, like mask-over-copper boards, are inexpensive to produce since electroplating steps are not required. However, chemical plating of copper is a slow ;~
process requirin~ approx~mately six hours in the bath to achieve each 1 mil of thickness. -~
~; SUMMARY OF THE PRESENT INVENTION
Accordingly, it is~an object of the present invention to provide a new method for the fabrication of printed circuit boards ha~ing longer life and higher reliability than previously : , manufa~tured boards.
It is ano~her object to provide a new method for the fabrication of printed circuit boards having higher wiring - densities than previously manufactured boards.
It is still another object of the present invention to provide a new method for the fabrication of printed circuit boards haviny better repairability and solderability.
Briefly, these and other objects are accomplished in , . . .
accordance with the present invention by first chemlcally depositing copper onto a pre-drilled aopper-clad substrate, then -~ applying a negative-image~ ating resist in the pattern desired.
., .
Circuit traces are built up to the desired thickness by electroplating the desired metal onto the circuit pattern.

Over the copper a platin~ of durable, chemic~lly passive metal ~;
such as tin~nickel is next plated which serves as etching resist -^ 7 .

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in later steps and pxovides a desirable su~face finish ~or the copper. A coating of plating resist ~n the negat~ve lmage of the desixed terminal pad and connector areas is then applied followed by final electroplating of t~n~lead onto the terminal pads and connector areas. The plating resists are then chemically stripped and the remaining exposed copper is etched away.
More particularly, there is prov~ded:
A process for the manufacturing of printed circuit boards, comprising:
a. pre-drilling a dielectric substrate to the de-sired hole pattern;
b. chemically depositing a first conductive material in a layer onto the surface of the substrate including the walls of the holes;
c. coating the substrate with a first layer of ; plating resist in a negative image of the desired circuit pattern;
r d. plating a second conductive material onto said first conductive material, in those areas not covered by said first layer of plating resist, in the desired thickness;
e. plating a durable, chemically passive third conductive material over said second conductive material;
fO coating said first layer of plating resist and conductive material with a second layer of plating resist registered with the desired circuitry and in a negative pattern of the desired terminal pad and connector areas whereby said areas are left uncoated;
g. cleaning and reactivating the uncoated areas of conductive material left uncoated following application of the second layer of plating resist coating;
~ pl~t~ng a eutectic alloy~ the aesired thickness to said uncoated areas of the conductive material;
i. -chemicall~ stripp~n~-the f-i~st and second layers 3~

of pl~tin~ resist from the substxate;
j. ~mmersing the substrate into a chemical etching bath, said bath being adapted to chem~cally etch away said first conductive material but to leave said third conductive material intact.

BRIEF DESCRIPTION OF THE DR~WXNGS
These and other objects are achieved by the present invention by means which are best understood by making reference ;;
to the drawings wherein~
FIG. 1 ~s a table showing the sequence of processing steps of the present method.
- FIG. 2, parts (a~ through (i~ show ~ cross-sectional - view of a representative part of a printed circuit board at various stages of processing in accordance with the present invention.
DESCRIPTION OF THE PREFERRED E~BOD~MENT~
An embodiment of the present invention is shown in the drawings and is described herein. It should be noted that FIG. 2 has been s~mplified for clarity and does not depict a circuit having any known use. Furthermore, the dimensions de-picted are exaggerated, particularly the thicknesses of the metallic layers and the resist coatings, with respect to the thickness of the substrate.
It will be recognized and understood that although - specific materials are named and specific processes are used, ~ -~
that other equivalent materials and processes may be employed without departing from the sco~e of the~method descrihed and claimed. ~ ~
In FIG. l, a~convenient swnmary of the steps utilized ~ ;
in practicing the present invention is shown. It will be desirable to refer to this summary from time to t~me while _9~

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simultaneously re~erxin~ to the follo~in~ pa~agraphs and the steps of the process which are ~raphically depicted in FIG~ 2 (a) through (i).
To manuf~cture a printed circuit in accordance with the present invention, it is first necessary that art~work master layouts be prepared which are exactly-to-scale, graphical representations o~ the circuit patterns which are desired, including the location and size of any holes which are required for component lead attachment. It will ~urther be required that photographic, or othexwise, duplication of the art-work master be accomplished in order to produce an exact size film o~ the desired c~rcuit patterns. These requirements are conventional and ~ell known in the art o~ printed circuit manufacture and ~ill not be further discussed herein.
The actual processing of printed circuit boards in accordance ~ith -the present invention begins with selecting -a laminar copper-clad substrate of dielectric material, suitable in area, thickness, and electrical properties for the require-; ments, in accordance with well known pxinciples of material selection. A typical choice will be a copper-clad lamina of fiberglass-reinforced epoxy having a thickness of 1.6 mm (1/16 inch~.
The lamina is then drilled in accordance with the pre-viously established hole pattern, resulting in the required number, location and slze of holes being arrayed over the ; lamina in exact registration with the circuit pattern to be deposited, as is also ~ell kno~n.
- After drilling, the laminar substrate is cleaned and immersed in a copper depositing ~ath such as Shipley Chemical Company's Process 32B-S, an aqueous solution containing sodium hydroxide with specific gravity of approximately 1.2, Ph factor 12 or greater, which bath chemically deposits a layer of . ~, 3~?~

copper over the entire surface of the substrate, including the walls of the previously drilled holes. A thin la~er of copper of barely more than molecular thickness is allowed to be deposited before the substrate is removed ~xom the bath. This step of the process is depicted in FIG~ 2 (a~ in which the stubstrate is removed from the bath. This step of the process is depicted in FIG. 2 ~a~ in which the substra-te 11 is shown coated entirely w~th the copper layer 12, which comprises the copper-clad and chemically deposited copper layers.
Since the initial copper layer is provided only for the purpose of providing conductivity during processing over the entire surface of the substratel and since much, and frequently most, of the copper so deposited will be etched away at the conclusion of the electroplating steps, it is unnecessary and undesirable to provide a thick copper layer at this stage.
Thus, a copper-clad substrate having a thin copper layer is ~
preferably selected and a very thin layer is chemically deposited.
After removal ~rom the initial platin~ bath and cleaning, ~` the substrate is placed in a silk-screening fixture having a ~-silk-screen containing an actual size positive image of the desired circuit pattern. The circuit pattern is exac-tly registered with the previously drilled hole pattern on the substrate. Using the silk-screen, a uniform, relatively thick layer of organic plating resist, such as ~arno Pr-1000 is applied over the copper layer. This plating resist is a modified vinyl intended for silk-screen printing which is chemically strippable without damage to the underlying copper.
Since the plating resist is applied only to those areas under the silk-screen where the silk-screen image is absent, a negative image pattern of plating resist ~ill result.

It should be noted at this point that photo-resist may also be employed where silk-screen techniques are specified.

, ' ~:, Furthermore, for simplici-t~ only, the processing of a single side of the substrate ~ill be described, although it is more usual to employ two-sided or multi-layer boards, both o~ which simply .
xequire duplication of the process ~escri~ed ~or all sides of the board(s) having circuitry.
The present stage of the process is depicted at FIG. 2(b) wherein the copper layer 12 is covered with the plating resist 13 in all areas except those shadowed by the silk-screen image, such as area 14 and area 15. Area 14 will become, following further processing, a circuit trace. Area 15 ~ill become the terminal pad area into which a component lead will be inserted. ~ .
At each such area in which it is desired to have a circuit conductor, the chemically deposited copper is left exposed. .
Since the thin copper layer now provides continuous electrical conductivity across the entire board surface, it is possible to electroplate conductive materials onto any a.rea of the exposed copper, with electroplating circuit continuity ~.;
beiny provided simply by attaching an appropriate electrode to some part of the board, generally in an area along the board .
edge away ~rom the desired circuit pattern.
Copper is next electro-plated onto the substrate to a thickness determined by the current carrying needs fo the cir-cuitry by immersing the substrate in an electrolytic copper plating bath such as Copper Gleam PC manufactured by Lee-Ronal, a solution of copper sulphate in sulphuric acid and chloride.
A phosphorized copper anode is employed. This stage of process-ing is shown in FIG. 2(c) in which a thick deposit of copper 16 is built up on the pr~eviously deposited thin copper layer 12.
After removing the board from the copper plating bath and cleaning, the board is reconnected to an electrode and placed :~ into a tin~nickel plating bath such as "P-Sn-Ni"~ manufactured by M & T Chemicals, Inc., used in conjunction with 65~ tin, , .; . ,~ . : -.

as~

35~ nickel electrodes~
Tin/nickel is plated over the copper in the same pattern as the copper was originally plated~ At this point in the process, the desired circuit pattern is produced in tinjnickel over copper, as shown in FIG. 2 (d~o In the ~gure, -the tin/nickel layer 17 has been deposited over the thick copper build-up 16.
In order to provide a solder-compatible surface in the terminal pad and CQnneCtor areas~it is desirable to pla-te tin/
lead onto those areas~ It is not necessary, however~ to plate tin/lead over all areas of the traces. Indead, to do so is costly of materials and undesirable from a quality standpoint since tin~lead is a less inert sur~ace than tin/nickel and since it is subject ~Q reflo~ing at the ti~e of component soldering.
In addition, since the tln/lead is softer than tin/nickel, it provides an unacceptable surface for use as connector contacts.
When a conventionally fabricated printed circuit board having closely spaced conductors is wave soldered, considerable bridging of exposed conductors frequently~ c~rs. ~Applying a conformally coated solder mask alleviates this problem. But, if 2Q tin/lead coated conductors are used, flowing of the tin/lead underneath the mask and release of impurities which are entrapped in the tin/lead during processing can cause blistering, distortion, brittlization and weakening of the mask.
To avoid these dxawbacks, the present process employs a second plating mask having a negative image of the areas which require solder compatibility. The second mask is applied directly over the first, without removing any previous masks, by using a silk-screen fixture having a silk-screen embodying a positive i~age representation of the desired terminal pad and connector areas. Following application of this second mask, only connector areas and terminal pad areas Including the holes and hole walls are uncovered. This stage of processing is shown 3~

in FIG~ 2 (e) wh.e~ein ~e~ 14 ~nd surxoundin~ ~e~ are no~
covered by the second l~yer of pl~ting ~es~st 18~ ~rea 15, a terminal.pad area, however, is left exposed.
The areas of tin~nickel now remaining exposed are cleaned and chemically reactivated u~sing, for example, a 3S% to 50%
solution of h~drochloric acid to remove oxides and provide a surface compatible ~ith tin~lead plating. An electrode is then attached and the hoard is immersed into a tin~lead plating bath such as "Sn-Pb", a solution of stannous fluohorate and lead fluoborate concentrate in a ~luoboric acid, used in conjunction with a tin/lead anode. In the bath a layer of tin/lead is plated onto all exposed pad areas including the interior hole walls to the desired thickness.
Electro-plating tin/lead onto the board allows a very uniform coating to be established even at points which would otherwise be subject to excessive or de~icient plating build-up.
The absence of non-unifQrmities is particularly advantageous ~ in cases where tolerances on conductor spacinys~or hole diameters are critical. FIG~ 2 (.f~ depicts thls stage of . 20 processing showing the tin~lead plating 1~ in area 15 including plating of the hole wall 20.
Following the ~in/lead plating, both the first and ; second plating resist masks are chemically stripped from the board using a stripping solution which does not damage the .
underlying circuitry. One such solution is an alkaline bath sold under the brand name Liqui-Kleen,~ manufactured by Chemline Industries, used in a 10% to 20% solution by volume.
At this stage all electroplated materials have been applied to the board and it is possible to remove the thin :
copper still re~aining since its use as a conductive layer is no longer needed. To avoid removing the desired conductive traces, ho~ever, a material which is relatively unaffected ~ .

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33-~i b~ the etching bath must be u$ed to coveX the t~aces. That function ;s prov~ded usuall~ b~ an organic coating of etching resist overlaid onto the traces in reg~strat~on with the traces~ Because exact registration is impossible io achieve, the edge definit;on of the traces su~fers somewhatO A
manufacturing allowance must ordinarily be made for the loss of definition thereby reducing the permissible circuit densi-ty.
In the present method, these registration problems are entirely avoided b~ using the tin/nickel layer as the etchant resist. Since tin~nickel and tin/lead are relatively inert materials in comparison with copper~ the thin copper layer 12 may be etched away leaving the tin/nickel coated traces substantially unaffected as shown in FIG. 2 ~h). The etchant must be selected to have little reaction with tin/nickel but great reaction with copper. An example of such an etchant is Continuetc~ MU-9106-a ~ an alkaline etchant having high copper capacity, Ph factor 8.0 to 8~5, manufactured by MacDermid ~etex.
The tin/lead plating ls then fused by heating the board to a temperature of approximately 480F, in order to amalgamate the tin and lead into solder.
If required, edge connectors may be plated with a high - conductivity material such as gold to provide lower contact resistance.
After a thorough cleaning, a permanent solder mask may be applied by silk-screening. It is usually desirable to apply a mask in order to realize the highest possible wiring densities since the mask will prevent most solder "bridging" which would otherwise occur. A suitable material for the mask is Chemline Industries' PC-401, a thixotropic two part epoxy base formulation. The board cross-section with mask 21 applied is ' ;

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depicted at FIGI 2 (il.
In addlt~on to those advant~es ment~oned ~n the above description, ~he present method is superior to the prior art methods in several ways. In comparison to the conventional copper/tin-lead process, the present invention o~fers improved reliability, at approximately equi~alent cost, through elimination of solder undernea-th the solder mask, while retaining the advan-tages of uni~orm solder thickness in solder-compatible areas. In addition, in those applications requiring board edge connectoxs, the hard, durable tin/nickel plating ~ill provide, without further processing being required, an adequate contact area for most circuit requirements, excluding only those which re~uire the optimally low contact resistance offered b~ gold platin~. Because plating irregularities are subst~ntially avoided by plating only the term~nal pad areas, the required insulator distance .:
between conductors may be minimized.
In comparison to the "additive" and "mask-over-copper"
`~ processes, the present invention offers improved reliability and utility while achieving the same conductor definition and, therefore, circuit density. In both prior art processes, extreme thermal shock is created by the immersion of the boards into molten solder and by removing excess solder with hot air blasts or hot oil sprays, steps which are avoided by the new process. Furthermore, since flu~ing of the board is not required, no corrosive impurity entrapment results.
Through use of electroplated tin/nickel, the present ;
process provides a passivated surface which is not subject to o~idation and which provides an inherently stronger circuit in the terminal pad and hole areas, the point of greatest weakness in the additive and mask-over-copper processes.

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~ Since a layer of tin~nickel seals the copper at connection ~ .
~ 16- ~

pointsl coppex o~i,de ~igX~tion ~ro~ th~ coppe~ la,~er into the soldex~ a common c~use o~ joint failu~e is prevented.
Complete control o~ plating th~ckness is provided by the -' present method. The uniform solder layer provided by electro~
plating tin~lead over the tin/nickel and copper instead of dipping the board into molten solder also elim~nates jcint failures resulting from inadequate solder coverage while reducing plugged holes, a fre~uent occurence in solder-dipped boards.
In comparison ~ith the additiYe proce9s, much less time is required ~or manufacturing.
Repair of defective components is facilitated by the new method since the tin/nickel plating over the hole walls dramatically improves the mechanical durability of -the hole thus reducing the dangex of inadvertant removal of the hole wall.
Since the solder mask r if used, is applied over a uniform, ; stable conduc-tor, the mask confo~ms more closely to the board and adheres more ti~htly. Solder liquification during wave ~, soldering, a common occurrence with the copper-tin/lead and ' ~0 additive processes which leads to solder bridging under the mask, flaking and loosening of large ground plane areas and general loosening of the mask, is avoided.
It will be appreciated by those skilled in the art that ;' other materials may be substituted for the specific examples provided. Although copper is the most desirable basic conductor, other conductive elements, alloys and compounds may be used. In selecting a substitute for tin/nickel, an acceptable substance must be electroplateable and must be ' mechanically durable. It must also be relatively inert in ~' comparison with the copper underlayment when exposed to the etchant9 Tin/lead in varying ratios and other eutectic alloys having lo~ melting points may be ~elected for ~. .
~ ~ -17-~ .: . . . . .,: . .

propertles ~rhich a~xe comp~tible ~ith soldering processes in accordance with principles which are well known~

Claims (10)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A process for the manufacturing of printed circuit boards, comprising:
a. pre-drilling a dielectric substrate to the desired hole pattern;
b. chemically depositing a first conductive material in a layer onto the surface of the substrate including the walls of the holes;
c. coating the substrate with a first layer of plating resist in a negative image of the desired circuit pattern;
d. plating a second conductive material onto said first conductive material, in those areas not covered by said first layer of plating resist, in the desired thickness;
e. plating a durable, chemically passive third con-ductive material over said second conductive material;
f. coating said first layer of plating resist and conductive material with a second layer of plating resist registered with the desired circuitry and in a negative pattern of the desired terminal pad and connector areas whereby said areas are left uncoated;
g. cleaning and reactivating the uncoated areas of conductive material left uncoated following application of the second layer of plating resist coating;
h. plating a eutectic alloy in the desired thickness to said uncoated areas of the conductive material;
i. chemically stripping the first and second layers of plating resist from the substrate;
j. immersing the substrate into a chemical etching bath, said bath being adapted to chemically etch away said first conductive material but to leave said third conductive material intact.

2. The process of claim 1 wherein the first conductive material is copper.

3. The process of claim 1 wherein the first and second conductive materials are copper.

4. The process of claim 1 wherein the third conductive material is tin/nickel.

5. The process of claim 1 wherein the eutectic alloy is tin/lead.

6. The process of claim 5 wherein the tin/lead alloy is fused by application of heat to the board.

7. The process of claim 1 wherein the first and second conductive materials are copper and the third conductive material is tin/nickel.

8. The process of claim 1 wherein the first and second conductive material is tin/nick 1 alloy, and the eutective alloy is tin/lead.

9. The process of claim l wherein the plating of con-ductive material in steps d, e and h is done by electroplating.

10. The process of claim 1 wherein the dielectric substrate includes a copper-clad dielectric substrate.