CA1108289A - Subscription television billing system - Google Patents

Abstract

ABSTRACT At the sending end randomly generated binary code numbers and program identification numbers are inserted into the television signal. The code numbers are also processed in accordance with a program assignment code to change or leave unchanged a predetermined characteristic of the television signal. At the receiving end the program identification numbers address a random access memory and read out program assign-ment signals stored therein. The program assignment signals control logic circuits which process the received code numbers in correspondence to the pro-cessing at the transmitter. The program assignment numbers must be updated periodically by a central computer-to-decoder transmission for proper decoding to take place. The program identification numbers are stored in the same memory for billing purposes only if the subscriber accepts the program. Since updating of the program assignment numbers does not take place until all previously stored program identification numbers have been transmitted to the computer along with a customer identification number for billing, initiation of communication between decoder and computer can be subscriber controlled. -1-

Description

The present invention xelates to pay television systems and particularly to those systems wherein the charge to the subscriber depends upon the programs accepted by him. In Xnown billing Sy,BtemS billing cards are utilized which are punched upon acceptance of ~he program ~y the suhscriber. These require considerable - amount of su~criber effort both in inserting the card ~ -and in mailing it laterO Further, the storage space on the card is limited. Errors can occur arising from ~-mutilation of the cards, mailing aelays, etc.
.: .
It is an object of the present invention to furnish a coding-billing system which is reliable, re~uires a relatively ~mall memory capacity, operates with a minimum o subscriber effort, and has a relatively tight security. The present invention is a subscription television s~stem for furnishing television programs to subscribers having access to a communications network, each o these sub-scribers having a standard television receiver. It com-prises encoding-transmitting means for encoding the tele-vision signals together constituting a given program, in~erting a program identification number signifying said program into said television signal at predetermined time instants thereof, and transmitting the so~encoded television signals with the so-inserted program identification numbers ~ ,:

~: to said subscribers. The system further comprises for each of said subscribers receiving means for receiving the so-transmitted television signal. Detect:iny means are also comprised in the system, for detectinq said pro~ram identifica-tion number and furnishing corresponding detected program identification signals. Further, accept signal furnishing ~; means are provided, for furnishing an accept signal indica-tive of acceptance of said program by said subscriberO
The accept signal furnishing means furnish the accept signal only upon activation by said subscriber. Main stor~ge means are provided which have a first set of storage location3 for storing said program identification numbers and a second set of storage locations for ~toring a customer identification number. Recording m~ans are provided which are connected to said detecting means and said accept signal furnishing means, for xecording said detected program identificatiun signals in said first ~et of storage locations only upon receipt of said accept signal, whereby only program identification number si~nifying program accepted by said subscriber are stored in said first storage location~. Read-out means are provided which are intercoupled between said main storage mean~ in said communications network for reading-out the customer identification number and said program identification numbers, furnishiny corresponding respective customer and program identification signals, and applying said signals ~o said communications network. Finally, central computing means connected to said communication network are provided, for receiving said customer identification signals and program identification ~ignals and computing the charge for each to said ~ubscriber~ for the so-accepted programs in response thereto.
The invention both as to its construction, method of operation and various advantages, will best be underctood for the ~ollowing description of a æpelcific embodiment when read in connection with the accompan~ing drawings~
: FIG. 1 is a block diagram of the circuitry at the sending end, FIG. 2 is a block diagram sh~wing the CirCUitQ for deteeting the code number signals at the receiving end and the logic circuits controlled thereby, FIG. 3 shows the program logic circuit of FIGo 2 in greater detail: :
FIG. 4 is a more detailed ~chematic diagram of the individual program assignment circuits of FIG. 3, FIG. 5 s~ows the storage location a~sigNments for the random access memory in the decoder;
FIG. 6 is a schematic block diagram of the decoder circuitry responsive to the received televi~ion signal, FIGS. 7 and 8 together constitute a block diagram of the billing circuitry: and ~;
FIG. 9 ~9 a schematic diagram ~howing the interconnection of the decoding equipment with the telephone line.
The ~ystem of th~ present invention will first be deæcribed in general terms. At the transmitting end, random-ly generated code numbers are applied to encoder logic circuits which operate ln a ~elected one of a plurality of encoder modes~ The ~elevision sigTal is encoded ~y reversing ~he : polarity of the video signal in responæe to certain ones of the code numbers selected în accordan~e wi~h the then-present encoder mode~ The code numbers are also inserted into the

2~

television signal, prior to transmission to the receiver~-decoders. Also, periodically, a program identification ~, number ~ignifyin~ the charge for the program is entexed into the televi~ion ~ignal prior to transmi~aion. At the receiving end, the code numb~rs are detected andapplied to decoder logic circuits set to a decoder mode corresponding to the then-present encoder mode ~y means of program assigNment signals. The program a3signment ~ignal~ are read out from storage locations in the random acce s memory addre~ed by the program identification number. The program identification number is also stored in the random acce~
memory for later billing. The decoder does not, however, operate until the subscriber pushes a button indicating his acceptance of the program.
For billing, the program identification numbers are transmitted by telephone to a central computer. Following receipt of the program identification nwmbers, the computer furnishes new assignment numbers for storage in the random acc~ss memory. Without these new numbers, the decoder cannot be 3et to the correct mode. Billing must therefore take place periodic~lly and nay be initiated ~y the subscriber.
The circuitry for inserting the code numbers and the program identification number~ into the television signal prior to transmission i~ shown in FIG. 1~ ~he code nu~bers are binary coded decimal digits. One of these diyits is to be in~erted into each of six lines in the vertical retrace interval. Each binary coded decimal digit of course require~
four bits. Each horizontal line which is to receive a binary digit i~ therefore divided into four slot~, each c~ the slots containing one bit.

Oscillator 201, whose output ~xeq~lency is high with respect to the h~rizontal drive ~requency, and counter 202 together constitute a random number generator since whatever number is registered on the counter i~i transferred to the parallel in-serial ou~ register 203 w~len a horizontal drive ;~
pulse is received at the load input of tha register~ ~he so-entared code number is read out serially under control o~ a 4H oscillator 204. Oscillator 204 has a fre~lency ~hich is somewhat higher ~han four times the horizontal line frequency and furnishes pulses whose trailing edge falls in the center o the slots discussed above.
4H o~cillator 204 is enabled b~ the output of six line counter 206~ Six line counter 206 ~urnishes ~ignals only during the first ~ix lines o~ the vertical retrace interval.
The serial output from register 203 will thus be a random number from 1 to 8 in each of the first six lines of the vertical retrace interval. The signal at ~he output of gate ; 205 will be identical to the output of register 203 unless inhibit pulses are present. Inhibit pulses are present first when it is desired to send the validation code. This i~ a sequence of code numbers designed to test whether the decoder i~ in the proper mode and will not ~e further dis-cu~ ed here. The ~econd inhibt signal, namely that from J
t~e output of gate 212, is furnished when it is desired to insart the program identification number into the telavision signal. When gate 212 is enabled, the contents of register 213 are read out serially and applied to the t~ird input of an OR-gate 214 whose other inputs receive the code numbers and the validation code. During the first line of the vertical blanking interval during which gate 212 is enabled, -6~

~he number 9 is inserted into the television ~ignal~ There-after follow two hexadecimal digits toge~hex constituting the program identification number. Fi.nally, in the fourth :
line, a catagory seleckion number i5 entered.
The decoder circuitry for detecting the code numbers is shown in Fig. a. The encoded television signal including the code numbers in the first six lines of the vertical retrace interval is received at term~nal 300. The signal ~:
is applied to a level detector 301 which must be capable ; 10 of detecting the "1" and "O" signals reliably independent of large changes in overall signal amplitudes. The output ~:
of detector 301 will thus constitute a pulse series of "1"
and "O" signals. T~e signals are applied to the input of the series~parallel shift register 302. Shift register 302, however, accepts pulses only when enabled by the output of an o~cillator 303 . Oscillator 303 is enabled for the first ::
six lines following each vertical retrace interval by the 1 H enable signal and corresponds to oscillator 204 at the transmittin~ end.
The four bits ~onstituting the binary coded decimal number in each of the lines is thus clocked lnto shift register 302. When the four bits of a particular line have been transferred into shift register 302, that is at ~he I time of the trailing edge of the 1 H enable pulse, ~he contents of the shift register are transferred to the four bit latch 307. The code transfer pulse which cause~ the ; tran~fer from the shift register to the four bit latch is derived from the 1 H ~nable pul~e by a differentiating ; circuit including a capacitor 308, a resîstor 309 t and a diode 310. The output of four bit latch 307 is connected to a decoder 311. Decoder 311 converts the binary coded decimal code at its input to a straight decimal code at the output, that is one of output lines 0-~ is en~rgized in response to each signal combination at its input~
The signals on lines 0-8 are applied to ~he inputs of a program assignment logic curcuit 312 whose outputs constitute the signals "A", "B", '1C'I and "D" which deter-mine the mode of a polarity flip-1Op at the decoder.
The state of the flip-flop determi~3~whether or not the video signals are to be inverted, i.e. whether ox not they wexe pre~iously inverted by the encoder. The "A", "B" and "D"
signa~ respectively reset, set and toggle this flip-flop.
The "C" signals do not affect it~ ~tate at all~
Fig. 3 shows the program a~signment logic circuit block 312 of Fig. ~ in greater detail. Lines numbered 1-8 showm in Fig. 4 are the output lines of the decoder 311 of Fig. 3.
The lines labelled 1001, 1002, ... 1015, 1016 are inputs derived fro~ the program indentification numbQr as will be discu~sed in greater detail below. Essentially, each pair ~'~
of program assignment numbers 1001, 1002: 1003, 1004, etc.
controls t~e transmission of one of the program numbers 1-8 furnished by decoder 311 through a corresponding one of the indiv~dual assignme~t circuits 401-408 to sne of the outputs A, B or Do Individual assignment circuit 401 is shown in greater detail in Fig. 4. The remaininy individual assignment circuits are identical to circuit 401 with the exception that of course the input~ are as specified in Fig. *.
Referring now to Fig~ 4, it is sean that in the ab~ence of a signal on line 1001 and the presenc~ of a siqnal on line 1002, ~ND~gate 414 is conductive, while A~D-ga~-es 412 and 413 are btocked7 Upon receipt of code number 1, A~D-gate 417 will therefore furni~h an output which ener-gizes the "A" outputO Similarly, the pre~ence of a signal on line 1001 and the absence of a si~al on line 1002 will result in a B output upon receipt of code number ~, while the presence of ~ignals on both lines 1001 and 1002 will result in a "D" output. It is thus seen that the assignment of the 3ignal from BCD-to-decimal converter 311 to A, ~ or D outputs takes place under control of the program as~iyn~
ment signals, which in turn are read out from the random acces~ memory in the decoder when addressed by the program identification number.
As refere~ce to Fig~. 3 ~how, each program assignment number is ~ 16 bit word, the bits being taken in pairs tlOOl.
1002, ... 1015, 1016). The ~ixteen bit word i9 extracted a3 a byte from a 48 bit string stored in a random access memory in the decoder. ~Storage locations 0-48 of RAM shown in Fig. 5.) ~he firs~ byte include~ bits 1 15. The second byte i9 obtained by shifting one place to the right (to start at bit 2). Thirty-two such bytes are possible from a forty-eight bit string. Since every bit in each program a~signment number is shifted by one place, adjacent numbers are quite different from one another even though there is only one new bit in each. It is of course the function of the program identification number, namely the t~o digit hexadecimal number, to select one of these th~rty-two program assignment number~ (bytes). Sinc~ 256 diffexent program identif cation numbers can be formed from the combination~ 00 to FF of two hexadecimal digits, eight ~ ~ !f ~ t~'~

program identification numbers are al]Located to each program assignment number ~32 x 8 = 256). When a program identification number from 00 to 07 is received~ program assignment nu~ber 1 i5 selected~ A number from 08 to lS (decimal) causes the selection of progr~m as~ignment number 2, etcO In the hexa-d~cimal system, the lea~t signiicant digit repre~ents the number of ones, while the next digit repre~ents the number of sixteens. Each digit i5 repre~ented ~y four bit~. The three lea~t significant bits of ~he least significant digit can therefor be ignored when reading out the program assign-ment number~ frGm the random access memory.
~ he fourth line o~ the 8iX lines which normally caxry the randomly selected code numbers contains a hexadecimal number from 0 to F which is u~ed for category selection.
Category selection i~ an optional feature, but the type of !;
coding used in the pres~ t invention i~ particularly suitable ; for implementing ~his capability. The bits in line ~ are treated independentlyO ~here are three types of programs and three categories in two o~ these types.
Type (a) Home General Parental Guidance Restricted (b) 5pecial Doctors Lawyers Educational ~c) Tavern The selection of programs on the decoder is as follows:
A selector switch is mountsd on the front panel, When the switch is set a "General", only programs meant for general audi~nces can be decoded. When set at the "Parental Guid-ance" po~ition, both "Patental Guidance" and "General"
programs will be decoded. When set to "Restricted", all three types of programs can be received. When the switch is set to receive "Special" programs, hard wired jumpers within the decodex determine which type of progr~m may be watched. For instance, if the decoder is wired up for a "Doctors" special and an "Educational" program i~ being transmittedl the decoder will not unscramble even though the switch i5 in the special position.
It is also pos~ible ~o inhibit ~avern decoder *rom unscrambling while other audiences are allowed to watch t~e program.
The random access memory is shown in Fig. 5. As menkioned above storage location~ 0 to 48 contain the program as~i~nment numbers. r~he customer identification n~mber is stored in storage locatlons 64-88, while the program identifi~ation numb2rs are stored in locatlons 88-255. ~a~h storage location store~ one bit. Since the - program identification numbers are two-digit numbers each of the digits heing represented by four bits, twenty-one such numbers can be st~red in the available billing space.
The arbitrary start point illustrated in Fig. 5 i~ a start point which is hard-wired into the address counter for the memory. This will be discus~ed in greater detail below~
The security number is a four digit binary coded decimal number, each of the four digits including four bits. The customer identiciation number is a twenty-four bit number.
It should again be noted that the program a~ nment numbers must be updated periodically by the computer to correspond to the encoding at the transmit~ ng end. Further, this updating by the computer is not to take place until the program identif~ication numbers required -for billing purpo~es have been transmitted to the computer~
In Fig. 6, the random access memory 600 is the 2S6 bit memory described above. A part of the function of the cir-cuitry in Fig. 6 is to transfer the 16 bit program ~ssign-ment number selected by the program identification number on the incoming television ~gnal to the 16 bit shift regi~ter 601. The parallel output of the 16 bit shift register 601 ; ~:
constitutes lines 1001, ... 1016 of Fig. 3. Ran~om access memory 600 is addressed by eight address lines constituting the output of an up/down counter 602. The counting input : of counter 602 is connected to the output of a six phase clock 603. Also shown in Fig~ 6 is a four bit shift register 605~ ;, The data input of four bit shift register 604 i3 connected to the output of detector 301 in Fig. 2. The clock input to shift registers 604 and 605 is the output of a twelve puIse counter 606. The counting input of counter 606 i9 ; connected to the output of 4 H oscillator 303 of Fîg. 2.
The counter operates after being enabled b~ t~e "9" signal from decoder 305. Since the program identification number number is transmitted on lines 2 and 3 of the vertical retrace interval and thus corresponds to the first eig~t pulses from o~cillator 303 following the detection of the "9" signal, ~he program identification number will have been shifted into shift register 605 at the time the twelfth pulse is received from counter 606. At thiæ time also, the category selection number will be stored in register 604~ The operation of counter 606 ceases af~er twelve pulses have been counted.
The over1Ow pulse from counter 606 is u~ed to set a clock enable flip-flop 607 to start enabling six phase clock 603~ ;;
Pulses from the six phase clock 603 are applied to up/down counter 602 causing it to count in the up mode~ Addresses for memory 600 are thus furnished at ~he output of counter 602. In comparator 608, the five most siynificant bits stored in shift register 605 are compared to ~he five least significant bits in the address furnished by counter 602 ~it will ~e remembered that the five most signi~icant bits of the pro~ram identification number together detenmine the address for memory 600~. As mem~ry 600 is addressed, the progr~m assignment numbers stored in the addressed locations in the memory are shifted serially into ~hift register 601.
When comparator 608 furnishe~ an output signal indicating agreement between the five most significant bit~ in shift register 605 and the five least significant bits in the addres~ furnished at the output of counter 602, clock enable flip-flop 607 is switched to the state wher~in clock 603 is disabled. The count of the counter then corre~ponds to the address in memory 600 wherein t~e program assignment number specified by the program identification number is ~tored. Further, the program assignment number is also located in shift register 601, cau ing line~ 1001-1016 of Figs~ 3 a~d 4 to be energized in accordance with the same code used at the transmitter so that code numbers received over the air in the next-following vertical retrace inter-vals will be properly routed to t~e A, B and D outputs.
A si~nal indicative of validation, that is of the correct ~etup at the decoder and the correct reception ~f the code, i~ furnished at terminal 608. These signals are preferably generated at one second time intervals but, if ~he program identification number is ^~ent on ~he ~econd, validation will take place on the half secondO Receipt of a validation signal cau~es data lock~out 609 to disable counter 606, that is to prevent any fur~her counting by this counter.
In a preferred embodiment of the present invention, data lock-out 609 is a monostable multivibrator whose tlme con-stant is set for a time interval less than one-sixtieth of a second but sufficient to insure that the validation signal is no longer present at terminal 608.
A si~nal at terminal 608 also allows an "accept" signal generated by the pu~hing of the "push to accept" button to be applied to a clock-enable flip-flop 611 via A~D-gate 610. Thi~ causes this flip-flop to assume a ~tate wherein ~ix phase clock 603 again starts furnishing pulses to up/
down counter 602. Since the subscriber has pushed the "push to accept" button, it i~ now reguired that the program identification number be entered into memory 600 for later billing purposes. The identification number bits ~ust of -:
. course be entered into the first empty locations of ~he 16 : locations in memory 600 which are devoted.to billing.
:: Following the enabling by clock enable flip-flop 611 ~:
six phase clock 603 furnishes pulses to up~down counter 602 which continue~ coun~ing in the up mode. The numbers stored in the locations addressed by the output lines of the counter are~shifted serially into an eight bit shift register 612.
~he shifting into shift regi~ter 612 is controlled b~ the clock pulses from clock 603 in the presence of an enable ~:
~ignal from clock anable flip-flop 611, i.e. by the output of A~D gate 611a. The parallel output of shift register 612 i~ applied to the input of a zero detector 613 which in a preferred embodiment of the present invention i~ a ~AND-gate furnishing an output signal only when all of its inputs are 0 signals. Upon detection of the eight zero bits, zero detector 613 ~u~nishes an empty position si~nal to flip-flop 61~o Flip-flop 614 is se~, cau~ing up/down counter 602 ko count in the reverse mode. Further, sett~ng of ~lip-~lop 614 enables an eight bit counter 615 which counts ~he next-subsequent eight output pulses of cloc~
603. Upon reaching the count of ~ counter 615 furnishe~ a signal resetting flip-flop 614 removing the down control signal on counter 602, causing it again to count the up mode. Further a flip-flop 616 is set which energizes the write enable circuit 617 thereby allowing recording into memory 600. Also a counter 618 which is an eight bit counter identical to counter 615 is energized. Counter 618 commence~
the counting of the next subsequent eight clock pulse~ from ~lock 603. The ~ignal from flip-flop 616 is further used to put an ~ND-gate 61g to the conductive state, allowing clock pulses from clock 603 to be applied to the clock input o~ eight bit shift register 605. The information in eight bit shift register 605 is therefore transferred serially to ~0 memory 600. The output pulse of ~lip-flop 616 further activate3 the recirculating circuit 620 which ca~ses each bit shi~ted out of shift register 605 to be reapplied to its input. The eight bits constituting t~e program identi-fication number are thus xestored in shift regi3ter 605 simultaneously wit~ being stored in memory 600. The count of 8 from counter 618 then cause~ a resetting of flip-flop 616, bxeaking the connection between shift register 605 and memory 600 as well as deenergizing write enable circuit 617 Since throughout the above operation flip-flop 611 was still in the set state and since memory 600 i~ the type of ~15-z~

memory wherein a read-out take~ plac~ simultaneously with the write-in operation, th~ program identification number can now also be found in ~hift register 612.
The number in register 612 and the nu~ber in register 605 are compared b~ an eight bit comparator 6210 As soon as the program identification number has been stored in memory 600, eight bit comparator 621 will furnish a coinci~-ence signal which resets flip-flop 611. Clock ~03 stops.
E'urther, the coincidence signal from eight bit comparator 621 switches a program enable flip~flop 622 to the set state.
When flip-flop 622 is in the set state a control signal is furni~hed to the decoder which allows viewing of the decoded picture.
The program identification number is thu3 stored in the memory befora the program can be watched~ Each progr~m identification number is stored only once, since, if the number has been previously stored, comparator 621 w~ll reset flip-flop 611 when the number is read out from storage 600.
Further, the program identification number cannot be stored in the memory unless validation is present, that is unless the corxect program identi~ication number is transmitted over the air, received, and the decoder at the receiver is proper-ly set in correspondence to this number.
A further eature shown in Fig. 6 is the comparison by a comparator 623 of the number set into shift register 604, that is the category selection number transferred in the ourth line of ~he vertical retrace interval, to a numbex set into the comparator ~y operation of the catego~y selection switch by the viewer or hy the hardwire jumpers mentioned above. A signal from this comparator is also Z~

required for enabling write enable 617. If it is absent, the number in shift register 605 will never be entered into memory 600 and there will never be an output signal from comparator 621. This of course will prevent the program enable flip-flop 622 rom being set and therefore the pro~ram will under no circum~tances be viewed by a subscriber.
Since the program identification number i~ also not entered into memory 600 no billing will take place.
As also shown in Fig~ 6, th~ selectox switch has a select-or arm 649 which can be moved to select between terminals G, PG and R~ The G terminal constitutes one input of an OR-gate 650 whose other input is deriv~d from the R terminal. 'rhe R terminal is also connected to one input of an OR-gate 651 whose other input is derived from the PG terminal. The out-put of OR-gate 650 is applied to the least significant bit input on the A side of a comparator 623, while the output of OR-gate 651 is applied to the next significant bi on the A side of this comparator. The B side of thi~ compara-tor receives the two least significant bits from register 604, that is the two least siynificant bits from the cate-gory selection number, which is coded 01,10 and 11 for G, PG and R programs respectively, the least significant bit keing the rightmost bit. The output of comparator 623 is taken from the terminal which furnishes a "1" output when-e~er A i~ equal to or greater than B~ Thus if a G setting is selected by the subscriber, only G programs will cause a "1" output to be furnished by comparator 623! while setting to the R selector input allows a "1" output to appear at comparator 623 independent of the digit value applied to t~e B terminals. ~ "1" output will ~hus appear at comparator ~17-623 if the R terminal is selected ~y the subscrib~r and a G, PG or R program is being broadcast. The DR, LWY and ED
terminals are terminals inside of the set ~hich are hard-wired depending upon which catego~y is ~elected by the subscriber. The D~ terminal fonms one input on OR-gate 652 whose other input is derived frGm the L~ tenminal. The LWY terminal is also connected to one input o~ an ~R-gate 653 whose o~her input is derived from the ED terminal. ~he output of OR-gates ~52 and 653 are applied to the A input of a comparator 624. The other side of comparator 624, namely the B side, receives the inputs from the two most ~ignificant digits from register 604. The output for com-parator 624 is taken from the A=B terminal. Comparator 624 will thuq furnish a "1" output only if the program specified by the hard-wire connection is being transmitted. The out-put of comparator 623 as well as the output of comparator 624 are applied to an OR-gate 625 whose output serves as one enable input for write enable circuit 617. Thus if there i~
disagreement ~etween the category selected by the suhscriber and the category of the program being received, there will be no ~ignal at the output of selection comparator 623.
The ~ystem sequence which ensue~ upon subscriber initiation is the following:
(a) Decoder to computer (Decoder reads out data from ~hift register starting fr~m 0 to 255)~
(13 Initiate (long tone) ~2) 64 bits 0 and 1 sequence ~line test)

(3) 24 bits customer ID

(4) 168 bits billing data ~program identificatiDn number~) ~b) Computer to decoder (in reverse order).

,.

~1) Initiate (long tone~. At end o~ long tone d~coder switches to arbitrary start point and addresses mem-ory backward~.
~2) X bits inverse position ~f billing data just sent out ~ customer ID in reverse (decoder compares to stored data~.
(3) 16 bits security number ~decoder still reading and comparing).
If data checXs throughout, it now switches memo~y into WRI~E mode).
~4) 48 bits of new progxam codes (decoder writes this in).

(5) Y bits of confu.sion signals (decoder stays in write mode but ignores confusion ~ignals and wrîtes lloll 1 9 into billing area.
~X + Y = 192. The decoder, starting from the hard wired arbitrary point in its memory, has gone through the whole memory once backwards and en~ed up at the arbitrary p9int again. It has er~sed all the billing data from 255 backward~ to the start point, leaviny the billin~
data rom the arbitrary point to bit 88 still intact.
r~'he decoder remains in the write mode, but the memory counter stops counting)O
Decoder to computer ~in reverse orderO This cycle occurs automatically~ after computer transmissio~ ends).
(1) Initiate (long tone) ~2~ V bits of confusion signal~ ~deco~er is in memory write mo~e and writes 0's in the memory running backwards from arbitrary start p9int, while trans-mitting confusion signals. It thus writes 0's into ~ he billing cells from ~he arbitrary start point :

~',;

to 88. Decoder rides through security number and customer ID areas o~ memory with~ut doing anything to memory).
( 3 ) ~8 bits of progxam codes complement ~these code~
are read out fr~m memory and compared to previously ; transmitted data at computer.
(4) W bit~ of confusion signalsO
(v ~ w = 20~).
~eferring now to FIGS. 7 and 8, the subscriber pushes the button or switch marked "initiate", thereby setting the system sequence in motion. Pushing the "initiate" button enables the transmission circuit (see Fig~ 9) and sets a flip-flop 40 who~e Q output is applied to one input of AND gate 41. The other input of AND gate ~1 is connected to the output of long tone oscil~ator 42. While flip-flop 40 is set, a signal appears at the output of AND gate 41. This signal is applied directly to the input of FSK modulator 42, and transmitted through the telephone line to the computer. Further, the output of AND gate 41 is applied through an integrating circuit 43 and a threshold circuit 44 to the ~et input ; of a flip-flop 441. The threshold circuit is preferably a Schmitt trigger circuit~ The output of the threshold circuit is applied to the reset input of flip-flop ~0.
The transmission of the long tone to the co~puter is thus :` ~
terminated a predetermined pariod after its beginning, while an AND gate 4~ is enabled. The second input of A~D
gate 45 is connected to the output of clock oscillator 15, while its output i~ connected to the counting input of up/
down counter 11, namely the address counter for the random acces2 memory lO,~and to the counting input of counter 47, .
0- , ~ .", . . , . ~ .

herein referred to as the first cycle counter. The first count on counter 47 sets a flip-flop 48 whose Q output i~
connected to the enable input of a "0", "1" oscillator 49.
The output of oscillator 49 is applied to the input of FSK
mod~lator 42, thereby causing the zero-one sequence required for line test to be transmitt~d through the telephone line to the computer. Meanwhile, address counter 11 is counting up, causing the random access memory storage locations 0 64 to be addressed. However, no data is transmitted out, since A~D gates 50 and 51, each of which has a irst input connect-ed to the data output of the random access memory 10, are both non-conductive.
When counter 47 reaches the count of "64", a flip-flop 52 i~ set. The Q output of flip-flop 52 is connected to the second input of AND gate 50, causing this AMD gate to become conductive~ The data in the storage locations addressed by address counter 11 is therefore tran3ferred through AND gate 50 to the input of FSK modulator 42 and thus through the telephone line to the computer. The customer identification number as well as 168 bits of billing data are transferred, since flip-flop 52 remains conductive until count 255 is reached on counter 47. When counter 47 reaches the count of 255, flip-flop 52 is reset, causing AND gate 50 to be blocked, and, further resetting flip-flop 441, there by sto~ping the transmission of clock pulses from oscillator 46 to counters 47 and 11. The 255 count on counter 47 also resets said counter to zero. The first cycle of the system sequence is thus completed.
All signals sent from the computer, including data signals and sy~chronizing signals, may be found at the out~
".~, ~ ~21-: `~
put of frequency shift keying detector 52~1, whic~ is connected to the input of a long tone detector 53O The output of long tone detec~or 53 is applied to the set input of a flip-flop 54 as well as that of a flip-flop 55. The Q output of flip-flop S4 is connected to one input of an A~D gate 56 whose other input is connected ~o oscillator ,~
15. The output of A~D gate 56 is connected to the counting -input of address counter 11 and of a counter 57 herein referred to as the second cy~le counter. The output of long tvne detector 53 is also connected to an input of counter 11 which cau~es it to be set to the preset nu~ber and to count down any pulses applied at the counting input. Since AND gate 56 is conductive, pulses from oscillator 15 will be applied to the counting lnput of counters :Ll and 57.
Counter 57, therefore, commence~ to count in the upwards .
direction, while counter 11 counts from the preset number in the reverse direction. Storage locations in random acces3 memory 10 are there~ore addressed in reverse order from the arbitrary start point~ The data read out from ~:
random access memory 10 is supplied to one input of com-parator 58 whose other comparing input is connected to the ~;
output of frequency shift keying 52. Comparator 58 thus compares the ~illing data sent in reverse order from the ~.
computer to the data stored in the random ac~ess memory, that is data that was set to the computer in the first . .
cycle of the system sequence. It further compares the - customer identification number stored in the random access memory to the customer identifi~ation number ~ent back from the computer. Further, the security number is read out at the decoder and again compared to the security number~ sent, .. ~ , .

: -22-''~' in reverse order, by the computer. As long as the comparator furnishes a "yes" output indicative of the act that the si~nals at the two comparing inputs are the same, the read out and comparison continue undisturbed unt.il a "48" detect signal is generated at the output of "48" detector 59.
The Q output of flip-flop 55 as well as the output of "48" detect circuit 59 are applied to the two inputs of an AND gate 60. AND gate 60 thus furnishes an output upon detection of the number "48" during the second cycle, as indicated ~y the presence of a signal on the Q output of flip-flop 55. The output of AND gate 60 is connected to the set input of a flip-flop 61 whose Q output furnishes a write enable signal to random access memory lOo Random access memory 10 will thus start to record any data applied to its input.
The incoming data is supplied to rando~ access memory 10 b~ the output of an AND gate 62. ~ND gate 62 has a first input connected to the output of FSK detector 52 and a second input connected to the Q output of a flip-flop 63. The set input of flip-flop 63 is connected to the output of AND gate 60. Data is thus gated to the input of random acce~s memory 10 after address 48 ha~ been passed, but only if co~parator 58 indicated that all data read out from random access memory 10 from the arbitrary start point to s~orage location 48 has agreed with the corresponding data transmitted back from the computer~ In the event that there was no equali.ty between ~ the two inputs prior to this point, comparator 58 furnished ;~, a "no" signal. This signal is applied to the reset inputs of :: flip-flop~ 54r~ 55, 61, an~ 63 as well as to the "set to zero"
inputs of counters 11 and 57O It i9 *urther util.ized to ~' -~3-z~

light a lamp in the decoder, causing the subscriber to re- ;
initiate the whole system sequence. Of course, the sub-scriber would re-ini~iate within a short time in any case, since the "no" signal from comparator 58 prevents the writing of new program codes into the random access memory and since, therefore, the proper program codes for setting up the decoder logic will soon not be in the rando~ access memory. This will of course prevent the subscriber from getting a usable , picture.
As said above, the data tnew program codes) will be recor~ed starting with storage address 48 if all comparisons up to that point have checked out. At address point 48, the comparator is disabled. The comparator was previously enabled by a signal from the Q output of a flip-flop 64 which was set b~ the oubput of long tone detector 53, that is ~t the beginning of the second cycle of the system sequen e.
The output of the "48" detect circuit 59 causes flip-flop 64 to reset, thereby disabling comparator 58.
The recording of data in the memory proceeds until a signal is ~urnished Erom "0" detect circuit 65. The output of this detector is applied to one input of an A~D gate 66 who~e other input is connected to the Q output of flip-flop 55. A~D ~ate 66 therefore yields an output signal when a zero address is detected in the second cycle. ~his signal causes a resetting of flip-flop 63, thereby causing the out-put of AND gate 62 to be a "0" output~ Data received from the computer will therefore be blocked from random access memory 10. At this point, it must be reme~bered, the com-. ~
puter is sending confusion signals~ Since the output of AND gate 62 is a "0", the data recorded in the random access ~ . ~
~' ~
.-;

.
"

memory starting with address zero will be logic zeros, that 2s, the data in the memory will be erased. The era~ure continues until counter 57 reaches the 255 count. At this point, flip-flop 54 will be reset by the output of counter 57, as will flip-flop S5O No further signals will be applied from oscillator 46 to ~ither counter 11 or counter 57 and the Q output of flip-flop 55 will go to zero. Flip-flop 61 will remain in the set condition, causing random access memory 10 to be in the recordin~ mode. This completes the second cycle in the eystem sequence.
The signal signifying the count of 255 on counter 57 is also utilitzed automatically to initiate the third cycle in the system sequence. Referring again to FIG. 7, the ~ignal ~ignifying the c~unt 255 from counter 57 i8 applied to the set input of a flip-flop 67 whose Q output is connected to one input of an AND gate 68~ The other input of AND gate 68 i9 connected to the output of long tone oscillator 42.
The output of AND gate 68 is directly applied to the input of the frequency ~hif~ keying modulator 42 and i~ applied to the set input of a flip-flop 69 through an integrating and - threshold cir¢uit 70. ~he output of circuit 70 is applied :
to the reset input of flip-flop 67, causing the transmis~ion of the long tone from the decoder to the computer to be interrupted. The output signal from circuit 70 i5 also applied to the ~et input of a flip-flop 71.
~ , The setting of flip-flop 69 causes an AND gate 72 which , ~
has an input connected tP the Q output of flip-flop 69 to ., be enabled. The ~econd input of A~D gate 72 is the output of oscillator 15. ~he output of A~D gate 72 is connected to . . -~ 30 t~e counting input of the third cycle counter, namely counter ~, .
:
~ 25-:

7~. Counter 11 which was reset to zero at the end of ~he second cycle therefore start~ counting upwards, addre~sing random acces~ memory 10. Counter 73 also counts upwards.
Since flip-flop 61 ~FIG. 8) is still set, the random access memory 10 is still in the writing mode and further zeros are recorded at the billing area.
The setting of flip-flop 71 enables an AND gate 74 whose output is connected to the input of the FSK modulator~
The second input of A~D gate 74 is connected to the output of confusion ~ignal generator 7S. Therefore, while flip-flop 71 i8 in the set state, signals from confusion generator 75 a.re tran~mitted through the telephone ].ine ~.o the computer.
This transmission of signals from confusion signal generator 75 continues until "48" detect circuit 59 furnishe~ a signal to one input of an ~ND gate 77. The other input of A~D gate 77 is connected to the Q output of flip-flop 69. When the count of 48 is reached in the address counter during the third cycle, ~ND g~te 77 will fuxnish a signal resetting flip-flop 71 and thereby stopping the signals from the con-fusion signal generator. The actual signal output of generator 75 is unimportant, and may be a random noise signal, ~ince neither the computer nor the decoder in any way respond to the con~usion signals.
. ~
Whil~, as stated above, the sending of confusion signals continues until the count of 48 is detected in the address counter, the writing of zeros, that is, the era~ure of data, must of course stop when the count of 88 is reached. Referr-ing to FIGo 8~ the output of an "88" detect c.ircuit 78 is ~: applied to one input of an AND gate 79 whose other input i.s the Q output o the cycle 3 flip-flop, namely a flip-flop 69.

-26~

The output of AND gate 79 is applied to the reset input of flip-flop 61, ~heraby switching the xandom access memory back into the read mode. The decoder thus rides throug~
memory locations 88 - 48 without either rec~xding or read-ou~ . :
The 48 bits of the program codes recorded in the memoryin the second cycle are now to be reacl out again and trans-mitted to ~he computer from co~parison there. For this purpose, the output of "48" detector circuit 59 is applied to one input of an AND gate 77 whose second input is enabled by the Q output of flip-flop 69. (It shoûld be noted here that "48" detect circuit 59's other output, namely the output to AND gate 60, is ineffective since there is no Q output from flip-flop 55)~
The output of AND gate 77 is applied to the reset input of flip-flop 71, thereby interrupting the transmission from the output of confusion signal generator 75 to the com~uter.
Furthex, the output of A~D gate 77 i5 supplied to the set input of a flip-flop 78c ; 20 ~he Q output of flip-flop 78 enables the second input of A~D gate 51, whose first input receives data from random access memory 10. Data from random access memory 10 is therefore read out through AND gate 51 and modulator 42 until such time as flip-flop 58 is reset. This happens in response to a signal from "o" detectox circuit 65. Upon receipt of this signal, the read out of the program codes from the random access memory and their transmission thxough the telephone ~,. , networX to the ~omputer is stopped.
It is now required that confusion signals be sent from the decoder to the computer until the arbitrary start point :

~ -27-:. ;, ha~ again been reached. For this purpose, the signal from the "0" detector circuit 65 is appliecl to one input o an AND gate 80 (FIG. 7~. The second input of A~D gate 80 is connected to the Q output of flip-flop 69. The si~nal at the output of AND gate 80 is applied t:o the set input of a ~lip-Elop 81 whose Q output is connected to the first input of an AND gate 820 ~he second input of A~D gate 82 is also connected to the output of confusion signal generator 75. ~
Signals from confusion signal generator 75 will thus be ~ -transmitted to the output of AND gate 82 ~ollowing the "0"
detector circuit output in ~e third cycle. The output of A~D gate 82 is also connected to the input of modulator 42 Confusion signals will therefore again be transmitted ~rom the decoder to the computer until flip-flop 81 is reset.
The resetting of flip-flop 81 takes place in response to a count of 2S5 on counter 73. Thus the transmission of conusion signals is interrupted at the end of the third cycle. The count of 255 on counter 73 also resets flip-flop 69, thereby interrupting the transmission of pulses from oscillator 46 to counters 11 and 73. ~he count of 255 on counter 73 is also utilized to reset counters 73 and 11 to zero, thereby returning the equipment to its starting condition. This completes the d~scription of the decoder billing logic cir-cuit operation during the complete system sequence.
The central c~mputer can be a general purpose computer programed to furnish the various data required during the system sequence. Alternatively, it can be a special purpose computer constructed along the same lines as the decoder lvgic circuits des~ribed herein. FIG. g shows the interconnection o the decoder billing logic circuits to a -2~-telephone line. A sa-turating transormer 20 has a first winding hard wired to the telephone l,lne and the second winding connected to one input of an operational amplifier 21 whose output is connected to the input of a frequency shift keying detPctor (52, Fig. 8). rFhe second input of of operational amplifier 21 is grounded. This part of the circuitry is assigned for the reception of information from the computer by the decoder. To transmit to the computer, the FSK modulator at the output of the decoder is connected to one electrode of the source-drain circuit of a Eield effect transi~tor 23 whose other side is connected to the secondary of transformer 20. Pushing o~ the "initiate"
button by the subscriber causes a -12 voltage to be removed from the base of transistor 23 cau~ing it to switch to the conductive state. The SatUratlng transformer isolates the system from the telephone line and limits the ringing signal. The frequency shift modulators and detectors com-prise voltage controlled oscîllators which generate a first frequency upon application of a logic "1" and a second frequency upon application of a logic "0". ~either of these frequencies lies within the normal voice transmission band.
The present syskem is highly secure, requiring Xnowledge of a security number, knowledge of the arbitrary start point, `
~ knowledge of the customer identification number and knowledge `~ of the direction of the read-out from the random access memory in order to enter new program a~signment numbers into the memory or to effect billing era~er.

~29-

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Subscription television system for furnishing television programs to subscribers having access to a communications network and each having a standard television receiver, comprising, in combination, encoding-transmitting means for encoding the television signals together consti-tuting a given program, inserting a program identification number signifying said program into said television signal at predetermined time instants thereof, and transmitting the so encoded television signals with the so inserted pro-gram identification numbers to said subscribers:
for each of said subscribers: receiving means for receiving the so-transmitted television signal; detecting means for detecting said program identification number and furnishing corresponding detected program identification signals; accept signal furnishing means for furnishing an accept signal indicative of acceptance of said program by said subscriber upon activation by said subscriber; main storage means having a first set of storage locations for storing said program identification numbers and a second set of storage locations for storing a customer identifica-tion number; recording means connected to said detecting means and said accept signal furnishing means, for recording said detected program identification signals in said first set of storage locations only upon receipt of said accept signal, whereby only program identification numbers signify-ing programs accepted by said subscriber are stored in said first set of storage locations; read-out means intercoupled between said main storage means and said communications network for reading out said customer identification number and said program identification numbers, furnishing corres-ponding respective customer and program identification sig-nals, and applying said signals to said communications net work; and central computing means connected to said commun-ications network for receiving said customer identification signals and program identification signals and computing the charge to each of said subscribers for the so-accepted programs in response thereto.

2. A subscription television system as set forth in claim 1, wherein said encoding-transmitting means comprises means for encoding said television signals in accordance with a selected one of a plurality of encoder modes; wherein said main storage means further has a third set of storage locations addressable by said program identification numbers for storing plurality of program assignment numbers, each corresponding to one of said plurality of encoder modes; further comprising read-out means interconnected between said detecting means and said storage means, for addressing the storage locations signified by said program identification number, reading out the program assignment number and furnishing corresponding program assignment signals and decoding means having control inputs connected to receive said program assignment signals, for decoding said received television signal under control thereof; and wherein said central computing means furnishes updated ones of said program assignment signals corresponding to changed ones of said plurality of encoder modes for storage in said third set of storage locations only upon receipt of said program identification signals, whereby proper decoding of said encoded television signals is prevented until billing data is received by said central computing means.

3. A subscription television system as set forth in claim 2, wherein said read-out means comprises pulse generating means furnishing clock pulses, counting means connected to said pulse generating means for counting said clock pulses and furnishing counting output signals corresponding to the number of so-counted clock pulses, program identification storage means connected to said detecting means for storing said detected program ident-ification signals thereby furnishing stored program identification signals; comparator means connected to said counting means and said program identification storage means for comparing said counting output signals to said stored program identification signal and fur-nishing a comparator output signal when a predetermined relationship exists between the so-compared signals;
and means for stopping said pulse generating means in response to said comparator output signal, whereby the counting output signal at said counting outputs con-stitutes an address signal for addressing said main storage means.

4. A subscription television system as set forth in claim 3, further comprising enabling means connected to said accept signal furnishing means and said pulse generating means, for enabling said pulse generating means only in response to said "accept" signal.

5. A subscription television system as set forth in claim 4, further comprising shift register means for storing program identification signals read-out from said main storage means under control of said counting output signals; additional comparator means interconnected between said shift register means and said program identification storage means furnishing an additional comparator output signal when the so-compared signals are equal; and inhibiting means for inhibiting the operation of said recording means upon receipt of said additional com-parator output signal, whereby a program identification number is stored only once in said random access memory.

6. A subscription television system as set forth in claim 2, wherein said read-out means comprises read-out means operative in response to an initiation signal;
further comprising means operative under subscriber control for furnishing said initiation signal.

7. A subscription television system as set forth in claim 2, wherein said read-out means further comprises addressing means for addressing said random access memory selectively in a first order, or in a second order opp-osite to said first order.

8. A subscription television system as set forth in claim 7, wherein said addressing means comprises count-ing means having a counting input and an arbitrary start number, for counting signals applied at said counting input in a first predetermined direction starting at said arbitrary start number in response to an arbitrary start signal, and in a second predetermined direction opposite to said first predetermined direction in the absence of said arbitrary start signal.

9. A subscription television system as set forth in claim 8, wherein said communications network is a telephone network; wherein said random access memory has a data output terminal; wherein said read-out means further comprises output tone generator means, output logic circuit means interconnected between said output tone generator means and said data output terminal for controlling transmission of signals from said data out-put terminal to said output tone generator means, and coupling means for coupling said output tone generator means to said telephone network in response to said initiation signal.

10. A subscription television system as set forth in claim 9, wherein said means for furnishing initiation signals comprises subscriber activatable means for fur-nishing a first initiation signal; further comprising oscillator means for furnishing counting signals, and first control circuit means connected to said oscillator means for applying said counting signals to said counting input of said counting means in response to said first initiation signal; and wherein said output logic circuit means comprises means for connecting said data output of said random access memory to said output tone generator means when said counting means is addressing said second and first set of storage locations and for blocking the transmission of signals from said data output terminal to said output tone generator means when said counting means is addressing said third set of storage locations, whereby said customer identification number and said billing signals are transmitted to said central computing means.

11. A subscription television system as set forth in claim 10, wherein said counting means addresses said third, second and first storage locations in said random access memory in said order when counting in said second predetermined direction; further comprising line check signal generator means for furnishing a line check signal;
and wherein said output logic circuit means comprises means for connecting said line check signal generator means to said output tone generator means while said counting means is addressing said third set of storage locations.

12. A subscription television system as set forth in claim 10, wherein said central computer means comprises means for furnishing a second initiation signal following receipt of said billing signals; further comprising detecting means connected to said receiving-decoding means for detecting signals from said central computing means, said detecting means comprising means for detecting said second initiation signal; further comprising means for connecting said detecting means to said counting means in such a manner that said second initiation signal con-stitutes said arbitrary start signal; wherein said arbitrary start number is a number in said first set of storage locations; further comprising second control circuit means for connecting said oscillator means to said counting means upon receipt of said second initiation signal; wherein said random access memory is selectively in a write mode or a read mode; wherein said central computing means further comprises means for transmitting billing signals starting at said arbitrary start number, said customer identification signals, and said program code signals to said receiving-decoding means follow-ing transmission of said second initiation signal; further comprising comparator means in said receiving-decoding means, and interconnected between said detecting means and said data output terminal of said random access memory, for comparing signals read from said random access memory to signals received from said central computing means and furnishing an equal signal only in response to equality therebetween; and write control circuit means interconnected between said comparator means and said random access memory, for switching said random access memory to said write mode while said central computing means is transmitting said program code signals to said receiving-decoding means, only if said comparator means furnishes said equal signal when comparing said billing signals and said customer ident-ification signals.

13. A subscription television system as set forth in claim 2, wherein said main storage means comprises a random access memory having said first, second and third set of storage locations and further having a fourth set of storage locations for storing a security number; wherein said central computing means comprises means for furnishing security number signals corres-ponding to said security number in response to received means further comprises means for reading out said security number and furnishing corresponding security number signals; further comprising comparator means connected to said read-out means for comparing security number signals received from said central computing means to security number signals read-out by said read-out means and furnishing an equality only in response to correspondence therebetween, and erasing means for erasing said program identification numbers from said first set of storage locations only upon receipt of said equality signal.