CA1102011A - High sheet resistance structure for high density integrated circuits - Google Patents

High sheet resistance structure for high density integrated circuits

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Publication number
CA1102011A
CA1102011A CA307,633A CA307633A CA1102011A CA 1102011 A CA1102011 A CA 1102011A CA 307633 A CA307633 A CA 307633A CA 1102011 A CA1102011 A CA 1102011A
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Canada
Prior art keywords
region
conductivity
regions
silicon
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA307,633A
Other languages
French (fr)
Inventor
Narasipur G. Anantha
Augustine W. Chang
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International Business Machines Corp
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International Business Machines Corp
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Publication of CA1102011A publication Critical patent/CA1102011A/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions

Abstract

HIGH SHEET RESISTANCE STRUCTURE FOR HIGH DENSITY
INTEGRATED CIRCUITS
Abstract A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface.
Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity.
Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

Description

24 Backqround_of the Invention The invention relates to resistance struc'ures for 26 high density integrated circuits and to methods for forming 27 a highl~ dense masterslice structure which may ~e advantag-28 eously utilized to form resistors or transistors in an 29 integrated circuit structure.

. . .

~)2~311 1 D cription of the Prior Art In the monolithic integrated circuit teehnology, it is usually necessary to isolate various aetive and passive elements from one another in the integrated circuit structure. These devices have been isolated by back-biasing PN junctions, partial dielectric isolation and complete dielectric isolation. The dielectric materials used have been silicon dioxide, glass, and so forth. The preferred iso-lation for these active devices and circuits particularly as integra-tion density has increased is some form of dielectric isolation. The dieleetric isolation has substantial advantage over the PN junetion isolation beeause it allows the abutting of the eireuit elements against the isolation and thereby results in greater density of paeking of the active and passive devices on the integrated eireuit ehip. Di-eleetrie isolation reduees assoeiated parasitie eapaeitanee and henee improves eireuit performanee.
Dieleetrie isolation teehniques of today usually involve the for-mation of grooves or ehannels in a silieon DLM/Wl 11~2~

1 body and the filling thereof with a dielectric material.
One technique is to form the openings by chemical etch-ing and is described fully in E. Kooi U.S. Patent No.
3,970,486, Clevenger U.S. Patent 3,534,234, Peltzer et al U.S. Patent 3,648,125, and I. Magdo et al Canadian Patent Application No. 143,388, filed May 30, 1972.
Another technique involves selectively forming an epi-taxial layer with grooves or openings therein and is described in V.Y. Doo U.S. Patent 3,386,865 and "A Com-posite Insulator-Junction Isolation" by R.E. Jones et al, published in Electrochemical Technology, Vol 5, No. 5-6, May-June 1967, pp. 308-310. Another technique for forming grooves is shown by Hochberg U.S. Patent 3,966,577, T. Kaji et al U.S. Patent 3,997,378, and S.A. Abbas, IBM* Technical Disclosure Bulletin, Vol. 20, ;
No. 1, p. 144, June 1977, and Bondur et al U.S. Patent No. 4,104,086, issued August 1, 1978, uses reactive ion etching.
Isolated pockets of monolithic silicon is the result of the isolation process described in the previous para-graph. Active devices, such as bipolar transistors, field effect transistors, and passive devices such as resistors, diodes, and so forth, may then be formed in these mono-crystalline silicon pockets. The essential steps in the formation of silicon planar devices may be seen, for example, in the book "Micro Electronics" by Max Fogiel published by Research and Education Assoc., 342 Madison Avenue, New York, N.Y. 10017, 1972 (see particularly pages 463-472). Briefly, the process involves obtain-ing, for example, a P substrate of silicon, oxidizing the surface *Registered trade mark '.~

1 opening a window in the silicon dioxide using standard
2 photolithography and etching techniques, diffusing an
3 N+ buried region through the op~ning. The silicon dioxide
4 i8 removed and an epitaxial layer of N-type silicon is grown thereover. During the epitaxial layer growth there 6 is some outdiffusion of the buried layer into the epitaxial 7 layer. The buried layer is destined to become the 8 subcollector of an NPN transistor in this example. Another 9 silicon dioxide layer is grown on the surface of the epitaxial layer, openings for isolation diffusion in the silicon 11 dioxide are formed by photoresist and etching techniques, 12 and the isolation diffusion or dielectric isolation is 13 formed to isolate pockets of monocrystalline silicon.
14 Openings are formed in the silicon dioxide coating where the base of the NPN transistor is to be formed and any 16 P-type resistors are to be formed, and a P-type diffusion 17 forms PN junctions in the N epitaxy layer. The surface`
18 is reoxidized and the use of photolithography and etching 19 techniques made to open the regions destined to be the emitter and the collector reach-through. The emitter and 21 reach-through diffusions are made. The surface is again 22 oxidized. Openings are made in the silicon dioxide mask 23 using conventional photolithography and etching techniques 24 for the ohmic contact purposes. The entire surface is metallized, such as with aluminum film, and using 26 conventional photolithography and etching techniques, the 27 interconnections are formed through the etching away of 28 the metal film.

2~

1 Diffused resistors are generally used in the 2 manufacture of integrated circuits, however, they are 3 normally formed during the base diffusion of a bipolar 4 transistor integrated circuit structure. This is lllustrated in the previous paragraph and in Schlegel 6 U.S. 3,591,430, S. P. Davis U.S. 3,772,097, G. K. Lunn 7 U.S. 3,700,977 and P. W. Robertson U.S. 3,959,040. This 8 type of resistor has disadvantages when it is desired '!
9 to go to greater density in the integrated circuits. Some of the disadvantages are that the diffusion depth has 11 to be deep enough to allow another diffusion of opposite 12 polarlty, for example, the enlitter. Furthermore, the base 13 region normally requires doping around 1013atoms/cm3.
14 High value resistors cannot be made at high doping levels of 101~ atoms/cm3. This type of resistor is not suitable 16 for low power, high density IC's. The resistors and struc-17 tures described herein have high value, tight tolerance 18 resistance sheet rhos. This is advantageous to high density 19 IC and results in low cost per logic circuit.
Resistors have also been formed in the N epitaxy 21 region such as is shown by R. A. Pedersen, U.S. 3,860,836.
22 In this patent the resistor is isolated from other devices 23 by P-N junction isolation. This type of device has the 24 disadvantage when a highly integrated structure is desired of high valued N- epitaxy resistors. Autodoping from 26 adjacent pockets (N+ or P+) will modulate the N- layer 27 during epitaxial layer growth. The effect will be a poor 28 tolerance sheet resistance (usually plus or minus 40~).

1~02~

1 Further, the epitaxial layer is necessarily very thick for fabricating a transistor. Hence, the sheet rho can-not be high even without the autodoping effect.
A wide variety of diffused, ion implanted or epi-taxial grown regions of various N and P conductivities in various configurations have been formed in isolated mono-crystalline silicon pockets. Examples of this are shown in the patents and publications cited above. Further citations of this type of structure is shown by M.V. Vora U.S. Patent 3,703,420 and W.T. Matzen et al U.S. Patent 3,982,266 which show ]unction isolation. R.D. Schinella et al U.S. Patent 3,919,005 and I.E. Magdo et al U.S.
Patent 3,954,523 show dielectric isolated monocrystalline silicon pockets.
Summary of the Present Invention In accordance with the present invention, a resistance structure for high density integrated circuits is described.
The resistance structure includes a silicon region separated from other silicon regions by a dielectric barrier. A
resistor of one conductivity encompasses substantially the surface of the silicon region. A region of the oppo-site conductivity is located below a portion of the sili-con region and a reach-through connects the buried region to the surface. The electrical contacts are made to the resistor. Other electrical contacts are made to the buried regions which is utilized for biasing purposes to isolate the resistor region from the remaining lower portion of the silicon body. A second resistor can be made in the same silicon region as the first resistor. This second resistor is ~102~1 1 located below the buried region with reach-throughs 2 to connect the second r~si~tor to the surface of the 3 silicon region where electrical contacts can be made 4 thereto. , An integrated circuit structure is also described.
6 This structure is composed of silicon regions separated 7 from like silicon regions by a dielectric barrier. Each 8 of the silicon regions include a base region of one 9 conductivity, a second region over the base region of a second conductivity, a third region of the first 11 conductivity buried within the second region and 12 a reach-through region of the first conductivity 13 connecting the surface of the silicon regions with 14 the third region. This integrated circuit structure is useful as a masterslice which can be personalized 16 at the time of forming electrical contacts to the 17 regions as either a transistor or a resistor with 18 electrical connections hetween ~hese two alternate 19 types of devices.
Methods are also described for fabricating the 21 resistor structure for integrated circuits and the 22 masterslice integrated circuit structure. A monocrystal-23 line silicon body is provided which includes a substrate 24 of the first conductivity and the region of a second con-ductivity thereover. A pattern of dielectric regions are 26 formed in this monocrystalline body which isolate surface 27 regions of the body from one another. A buried region 28 is formed of the first conductivity within the region Z~l;l 1 of the second conductivity ana a reach-through region of 2 the first conductivity is forme1 to connect the surface 3 of the silicon region to the buried region. El~ctrical 4 contacts are then made to the various regions within the isolated silicon regions to fabricate, as desired, 6 resistors and/or transistors.
7 Brief Description of the Drawings 8 FIGURES 1-4 illustrate the method of fabricating g and the final structure of one form of a resistor of the present invention;
11 FIGURES 5 and 6 illustrate the final structure 12 of a second form of the resistor of the present 13 invention;
14 FIGURES 7 and 8 are circuit schematics of the two resistors illustrated structurally in FIGURES 5 and 6;
16 FIGURE 9 is a third embodiment of the integrated 17 circuit structure which is useful as a vertical transistor;
18 and 19 FIGURE 10 is a circuit schematic of the NPN transistor of the FIGURE 9 structure.

22 Description of the Preferred Embodiments 23 Referring now more particularly to FIGURES 1-4, 24 the manufacturing steps for one form of the invention involves starting with the wafer or substrate 10 of 26 P- slllcon monocrystalline material. The substrate 10 is 27 fabricated, for example, by pulling a monocrystalline rod 28 from a suitable melt containing a P-type material such as 29 boron and using a seed crystal having a<100~ crystallographic ~lOZV~

1 orientation. The resulting rod is then sliced into very 2 thin wafers which also have the surface crystallograp~ic 3 orientation of <100~. The P- s~licon wafer has preferably a 4 resistivity of 10-20 ohms centimeter.
The structure is then placed in an epitaxial growth 6 chamber wherein an epitaxial layer 12 is grown on the 7 surface of the substrate 10. The epitaxial layer may 8 be any desired thickness, however, for the purpose of 9 high performance device of the type involved in the present invention, the thickness should be less than about 2 micro-11 meters. The preferred thickness of the epitaxial layer is 12 about 1.2 micrometers. I,ayer 12 is grown onto the subEtrate 13 10, by conventional techniques such as the use of SiCl~/H2 14 or SiH4/H2 mixtures of about 1000 to 1200C.
The next series of steps is directed to the 16 technique for reactive ion etching of the silicon 17 structure. A silicon ~ioxide layer (not shown) is 18 formed by conventional techniq~es of either thermal 19 growth at a temperature of 970C in wet or dry oxygen ambient or by chemical vapor deposition. Other mask 21 materials can also be used such as silicon nitride and 22 aluminum oxide or combinations thereof. It is preferred 23 that a 1000 to 3000 A silicon dioxide coating be formed 24 by a chemical vapor deposition of using a mixture of silane and N2O at 800C in a nitrogen ambient. Suitable 26 openings are formed by conventional photolithography 27 and etching techniques in the silicon dioxide layer 28 where the isolation regions are to be formed. The structure l~LV2q~ L

1 is then put into a silicon reactive ion etching ambient.
The RF induced plasma is reactive chlorine, bromine or iodine specie. The thickness of the masking layer is between 2000-20,000 Angstroms, the exact thickness de-pending on the depth requirement of the silicon groove.
The reactive ion etch or plasma ambient is preferably a combination of an inert gas such as argon and a chlorine specie. Application of suitable power is in the order of about 0.1 - 0.75 watts/cm2 from an RF volt-age source which produces sufficient power density to cause the reactive ion etching operation of silicon to be carried out at the suitable rate. The desired re-sult of the etching is the shallow opening wherein the opening or channel partially penetrates the P-base re-gion 10. This results in the FIGURE 1 structure.
The next step in the process is to thermally oxi-dize the openings or channels by subjecting the body to an oxidation ambient which may be, for example, 970C

in wet oxygen. The body is subjected to the ambient for about 10 to 30 minutes to produce the preferred silicon 1 dioxide thickness within the opening or channel between about 500-2000 Angstroms. The purpose of the thermal oxide is to assure good silicon dioxide interface pro-perties, the qualities of which are usually not as good with chemical vapor deposited dielectric material. Good quality dielectric material is necessary to permit the subsequent abutting of diffused junctions against the dielectric isolation. The complete filling of the open-ing with a suitable dielectric material is accomplished using vapor deposited silicon dioxide. The details of this process is described in the beforementioned Bondur et al U.S. Patent No. 4,014,086.
It may be preferred in some instances, prior to pyrolytic deposition step to ion implant boron ions through the bottom of the oxide at the bottom of the channel. This causes the formation of the P+ region underneath the iso-lation region which prevent the P- region under the iso-lation region from inverting to an N type material.
The pyrolytic silicon dioxide is deposited in a thick-ness of preferably 2 to 3 micrometers. The preferred filling process is a chemical vapor deposition of sili-con dioxide using gas mixtures of CO2/SiH4/N4 or N2o/SiH4/N2 between 800 and 1000C. The typical deposi-tion rate is to the order of 50-100 Angstroms per minute.
The next step is the reactive ion etching of the chemical vapor deposited silicon dioxide layer to remove excess silicon dioxide from the surface. The system used for this process would be of the low pressure sputter etch ilO201~
1 type system with the wafer positioned on a silicon cathode cover plate. A fluorinated hydrocarbon such as CF4 would be used as an etchant so that an SiO2/Si ratio of approxi-mately 1:1 results. The gas pressure could run from 10 to 70 micrometers with gas flow rates of 2 to 50 cc/min.
The RF power level runs from 0.1 watts/cm .
FIGURE 2 now shows the complete isolation of the de-sired monocrystalline silicon regions by means of dielec-tric isolation regions 14. The surface of the body is reoxidized by growth of 0.1 to 0.2 microns of thermal sili-con dioxide to bring the silicon dioxide layer 16 to thedesired thickness.
Referring now to FIGURE 3, the buried implant for the PN junction isolation of the resistor is accomplished.
Photolithography and etching techniques are utilized to expose and develop the photoresist pattern and then re-move portions of the photoresist areas to expose the re-gdons wherein P+ type ion implantation is to be accomplished.

The structure is then placed in a suitable ion implanta-tion apparatus wherein a boron ion implantation is accom-plished using 200 to 500 KeV and 5 x 1014 atoms/cm2.It should be noted that a thin silicon oxide coating of 250 to 300 Angstrom units is allowed to remain on the surface of the structure. This silicon dioxide coating has the function of a screen for the ion implantation step. The result of the process is the P type buried region 18. The reach-through diffusion for the buried P region 18 is ..g~

- ~1;02~11 1accomplished by applying a simple photoresist exposing, developing and etching the photoresist to expose the regions which are to be the P reach-through through the photoresist. The structure is again placed in the suit-able ion implantation apparatus and a boron ion implant-ation applied to the surface of the structure using 150 KeV and a dosage of 5 x 101 atoms/cm . A subsequent high temperature processing step acts as an annealing cycle. The structure now has the reach-through region 20 which connects the buried P region 18 with the sur-face of the silicon region.
The surface silicon dioxide layer is reoxidizedand openings made through the surface oxide layer 16 for the resistor contact diffusions or ion implanta-tions. The openings are made by conventional photo-lithography and etching techniques. The structure is placed, for example, in an ion implantation apparatus wherein phosphorus or arsenic ions of a dosage of 1 x 1015 atoms/cm2 and power of 200 KeV are implanted into the structures to form the resistor contact regions 22.

The wafers are annealed at 1000C for about 10-20 minutes in an inert ambient to remove the ion implanta-tion damage and activate the impurities. The opening to the P+ reach-through 20 is made through the surface oxide 16 resulting in the FIGURE 3 vertical structure and the FIGURE 4 horizontal structure.
A suitable ohmic contact metal is then evaporated or deposited by other means onto the upper surface of ~, ~oz~

1 the structure. Typical contact material is aluminum or 2 aluminum-copper. However, other well known materials 3 in the art can be used such as platinum, palladium, 4 molybdenum, and so forth. Photolithography and etching techniques are utilized for the desired conductive lines 6 on the surface of the semiconductor structure from the 7 blanket layer.
8 It is preferred in the interest of high density 9 that the one contact region 22 be contiguous to the dielectric barrier and one end of the silicon region.
11 Also the reach-through region of the opposite conductivity 12 20 should be contiguous to the dielectric barrier at 13 that end of the resistor structure.
14 Referring now to FIGURES 5 and 6 a second embodiment is illustrated wherein two resistors are 16 formed in a single dielectrically isolated monocrystalline 17 silicon region. The FIGURE 5 structure is composed of 18 silicon regions 30 separated f~om like silicon regions 19 by a dielectric barrier 32 ~urrounding each of the regions 30. Each of these silicon regions 30 include 21 base region 34 of a first conductivity, a second region 36 22 of a second conductivity, a third region 38 of the first 23 conductivity buried within the second region 36, and a 24 reach-through region 40 of the first conductivity connecting the surface of the silicon regions with the third region 26 38. The dielectric barrier 32 is composed preferably of 27 at least an outer layer 42 of thermally grown silicon 28 dioxide in an inert layer of pyrolytically grown silicon 2~Ll 1 dioxlde. In the FIGUR~ 5, the first conductivity is 2 P type and the second conductivity is N type which 3 produces an N type resistor. The N+ contact regions 4 for the surface resistor are indicated as 46. The N+
type contact regions for the buried resistor are indicated 6 as contact regions 48. The second and buried resistor is 7 located below the first conductivity buried region 38 and 8 is indicated as principally region 50 with the diffused 9 contact regions 48. The plane view of the present embodiment is shown in FIGURE 6.
11 The FIGURE S and FIGURE 6 structure may be 12 fabricated according to the same processes described 13 with regard to FIGURES 1-4. However, additional 14 spacè is required between the dielectric isolation region 32 and the buried P+ region 38 and reach-through 16 contacts 40, so as to allow for the second resistor 17 contact regions 48.
18 - Referring now to FIGURES 7 and 8, there is shown 19 the circuit diagram of the FIGURES 5 and 6 physical structure. FIGURE 7 is the circuit of the surface 21 resistor 56 with the contacts A, B and C given in FIGURE
22 5. The diode 60 represents the PN junction between the 23 region 38 and the region 50. FIGURE 8 is the circuit 24 representation for the buried resistor 50 which is located between contacts D and E. The isolating diode 60 is the 26 PN junction between the region 38, 40 and the resistor 27 region 50.

1~2~1 1 Referring now to FIGURE 9, a third embodiment of 2 the structure is shown wherein ~ masterslice type of 3 per80nalization process is possible. A pattern of 4 dielectric regions 70 in the silicon monocrystalline body isolate surface regions 72 of the body from one another.
6 The monocrystalline silicon regions isolated from one 7 another include a substrate of a first conductivity 74 8 for example, P type, and a region 74 of a second conductivity 9 thereover. This region is typically grown by epitaxial techniques. A region of the first conductivity 78 is 11 buried within the region of second conductivity 76. This 12 region 78 is preferablv formed by means of ion implantation 13 as described above in regard to FIGURES 1-4. A reach-through 14 80 connects the buried region 78 with the surface. ~his reach-through is formed by either diffusion or ion 16 implantation processes. Second conductivity dopant, 17 for example N+, is utilized to form contacts for the 18 surface resistor contacts 82 and 84 and a contact for 19 the N- region 76 below the P+ buried region 78. A choice can now be made at the time of personalization to either 21 make a resistor utilizing the contacts 82 and 84 or to 22 form a transistor utilizing the contact 84 as an emitter 23 contact 80, as a base contact 86 and as the collector 24 contact. In the case where a resistor is desired, the 8ilicon dioxide layer 88 would cover the contact region 86 26 and no metal ohmic contact would be made to this portion 27 of the silicon monocrystalline region. In the case that 28 a transistor is desired as shown in the FIGURE 9 for FI9-77~019 - 16 -2~1~

1 illustrative purposes, the silicon dioxide layer 88 would 2 cover one of the resistor contacts, for example contact 82.
3 No ohmic contact would then be made to that portion of 4 the,region. FIGURE 10 shows the circuit wherein 86 is the collector, 80 i8 the base and 84 is the emitter~
6 Whlle the invention has been particularly shown and 7 descrlbed with reference to the preferred embodiment thereof, 8 it will be understood by those skilled in the art that 9 various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

GOS:bvs ~. ,~. . ...

Claims (17)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. An integrated circuit structure comprising:
silicon regions separated from like silicon regions by a dielectric barrier surrounding each of said regions;
each of said silicon regions including a base region of a first conductivity, a second region over said base region of a second conductivity, a third region of said first conductivity buried within said second region; and a reach-through region of said first conductivity con-necting the surface of the silicon regions with said third region; and means for electrically contacting said base, second and reach-through regions in different said silicon regions to perform a desired circuit function.
2. An integrated circuit structure comprising:
silicon regions separated from like silicon regions by a dielectric barrier surrounding each of said regions;
each of said silicon regions including a base region of a first conductivity, a second region over said base region of a second conductivity, a third region of said first conductivity buried within said second region so as to form electrically and physically separated upper and lower regions in said second region; and a reach-through region of said first conductivity connecting the surface of the silicon regions with said third region;
and means for electrically contacting said base, second upper, second lower and reach-through regions in said silicon regions to perform a desired circuit function.
3. The integrated circuit structure of Claim 1 wherein said dielectric barrier is composed of at least an outer layer of thermally grown silicon dioxide.
4. The integrated circuit structure of Claim 1 wherein a second resistor is located in certain of said silicon regions having said resistor, said second resistor formed in said region of a second conductivity located below said third buried region of a first conductivity, reach-through region of a second conductivity from the surface of said silicon region to said region of a second con-ductivity and electrical contacts thereto.
5. The integrated circuit structure of claim 1 wherein said first conductivity is N, said second conductivity is P, said resistor is N-type and said transistor is a PNP.
6. The integrated circuit structure of claim 1 wherein said first conductivity is P, said second conductivity is N, said resistor is P-type and said transistor is a NPN.
7. The integrated circuit structure of claim 2 wherein said means for electrically connecting is so connected that a resistor is located in certain of said silicon regions, said resistor formed in said lower region of a second conductivity located below said third buried region of a first conductivity, said means for electri-cally contacting said lower region including reach-through regions of a second conductivity from the sur-face of said silicon region to said lower region of a second conductivity and electrical contacts thereto.
8. The integrated circuit structure of claim 2 wherein said means for electrically connecting is so connected that resistors are located with certain of said silicon regions, said first conductivity is N, said second con-ductivity is P, said resistors are N-type and are lo-cated within said upper and lower regions of said cer-tain of said silicon regions.
9. The integrated circuit structure of claim 2 wherein said means for electrically connecting is so connected that resistors are located within certain of said sili-con regions, said first conductivity is P, said second conductivity is N, said resistors are P-type and are located within said upper and lower regions of said cer-tain of said silicon regions.
10. The integrated circuit structure of claim 2 wherein said means for electrically connecting is so connected that transistors are located within certain of said sili-con regions, said first conductivity is N, said second conductivity is P, said transistors are PNP type and are located within said certain of said silicon regions.
11. The integrated circuit structure of claim 2 wherein said means for electrically connecting is so connected that transistors are located within certain of said sili-con regions, said first conductivity is P, said second conductivity is N, said transistors are NPN type and are located within certain of said silicon regions.
12. The method of fabricating an integrated circuit structure comprising:
providing a silicon monocrystalline body which in-cludes a substrate of a first conductivity and a region of a second conductivity thereover;
forming a pattern of dielectric regions in said silicon monocrystalline body which isolate surface regions of said body from one another;
forming a buried region of said first conductivity within said region of a second conductivity;
forming a reach-through region of said first con-ductivity to connect the surface of said silicon region to said buried region; and forming electrical contacts to the said regions within said isolated regions of said body.
13. The method of fabricating an integrated circuit structure as defined in claim 12 wherein:
said electrical contacts are formed on the surface of said region of second conductivity to form a resistor therein; and further forming an electrical contact to said reach-through region for biasing purposes.
14. The method of claim 12 or claim 13 wherein said di-electric regions are formed at least in part by a thermal oxidation process to produce silicon dioxide.
15. The method of claim 12 or claim 13 wherein said buried region is formed by ion implantation of a P type conductivity, said first conductivity is P and said second conductivity is N.
16. The method of claim 12 or claim 13 wherein said buried region is formed by ion implantation of a N-type conduct-ivity, said first conductivity is N and said second con-ductivity is P.
17. The method of claim 13 further comprising making elec-trical contact to said region of second conductivity under said buried region for forming a second resistor.
CA307,633A 1977-10-25 1978-07-18 High sheet resistance structure for high density integrated circuits Expired CA1102011A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US844,768 1977-10-25
US05/844,768 US4228450A (en) 1977-10-25 1977-10-25 Buried high sheet resistance structure for high density integrated circuits with reach through contacts

Publications (1)

Publication Number Publication Date
CA1102011A true CA1102011A (en) 1981-05-26

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CA307,633A Expired CA1102011A (en) 1977-10-25 1978-07-18 High sheet resistance structure for high density integrated circuits

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IT (1) IT1159142B (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55138267A (en) * 1979-04-12 1980-10-28 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit containing resistance element
JPS5632762A (en) * 1979-08-27 1981-04-02 Fujitsu Ltd Semiconductor device
US4476478A (en) * 1980-04-24 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor read only memory and method of making the same
JPS58103169A (en) * 1981-12-15 1983-06-20 Matsushita Electric Ind Co Ltd Semiconductor variable resistant element
JPS58127363A (en) * 1982-01-25 1983-07-29 Hitachi Ltd Semiconductor ic device
JPS6097659A (en) * 1983-11-01 1985-05-31 Matsushita Electronics Corp Semiconductor integrated circuit
US4737469A (en) * 1984-01-19 1988-04-12 Honeywell Inc. Controlled mode field effect transistors and method therefore
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4949150A (en) * 1986-04-17 1990-08-14 Exar Corporation Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers
US5066603A (en) * 1989-09-06 1991-11-19 Gte Laboratories Incorporated Method of manufacturing static induction transistors
JP3360970B2 (en) * 1995-05-22 2003-01-07 株式会社東芝 Method for manufacturing semiconductor device
US5883566A (en) * 1997-02-24 1999-03-16 International Business Machines Corporation Noise-isolated buried resistor
US6100153A (en) * 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
JPH11297847A (en) * 1998-04-13 1999-10-29 Nec Kyushu Ltd Semiconductor device and its manufacture
DE19917370C1 (en) 1999-04-16 2000-10-05 St Microelectronics Gmbh Largely voltage-independent electrical resistance formed in an integrated semiconductor circuit
JP3528750B2 (en) * 2000-03-16 2004-05-24 株式会社デンソー Semiconductor device
JP4599660B2 (en) * 2000-05-24 2010-12-15 ソニー株式会社 Semiconductor device having semiconductor resistance element and manufacturing method thereof
US7384854B2 (en) * 2002-03-08 2008-06-10 International Business Machines Corporation Method of forming low capacitance ESD robust diodes
FR2884050B1 (en) * 2005-04-01 2007-07-20 St Microelectronics Sa INTEGRATED CIRCUIT COMPRISING SUBSTRATE AND RESISTANCE
US7910450B2 (en) * 2006-02-22 2011-03-22 International Business Machines Corporation Method of fabricating a precision buried resistor
US10170464B2 (en) 2015-06-05 2019-01-01 International Business Machines Corporation Compound semiconductor devices having buried resistors formed in buffer layer
US10410966B2 (en) 2017-12-19 2019-09-10 International Business Machines Corporation BEOL embedded high density vertical resistor structure
CN108922925B (en) * 2018-07-09 2021-06-25 深圳市物芯智能科技有限公司 Power device protection chip and manufacturing method thereof

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1086128A (en) * 1964-10-23 1967-10-04 Motorola Inc Fabrication of four-layer switch with controlled breakdown voltage
US3430110A (en) * 1965-12-02 1969-02-25 Rca Corp Monolithic integrated circuits with a plurality of isolation zones
US3443176A (en) * 1966-03-31 1969-05-06 Ibm Low resistivity semiconductor underpass connector and fabrication method therefor
US3786318A (en) * 1966-10-14 1974-01-15 Hitachi Ltd Semiconductor device having channel preventing structure
US3629667A (en) * 1969-03-14 1971-12-21 Ibm Semiconductor resistor with uniforms current distribution at its contact surface
US3601669A (en) * 1969-05-07 1971-08-24 Texas Instruments Inc Integrated heater element array and drive matrix therefor
JPS4840307B1 (en) * 1970-06-12 1973-11-29
US3631309A (en) * 1970-07-23 1971-12-28 Semiconductor Elect Memories Integrated circuit bipolar memory cell
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
JPS4869477A (en) * 1971-12-21 1973-09-20
US3787710A (en) * 1972-01-25 1974-01-22 J Cunningham Integrated circuit structure having electrically isolated circuit components
JPS5120267B2 (en) * 1972-05-13 1976-06-23
CA997481A (en) * 1972-12-29 1976-09-21 International Business Machines Corporation Dc testing of integrated circuits and a novel integrated circuit structure to facilitate such testing
JPS5321838B2 (en) * 1973-02-28 1978-07-05
JPS49131789A (en) * 1973-04-23 1974-12-17
JPS49131788A (en) * 1973-04-23 1974-12-17
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
US3953875A (en) * 1974-01-02 1976-04-27 Motorola, Inc. Capacitor structure and circuit facilitating increased frequency stability of integrated circuits
US3990092A (en) * 1974-01-11 1976-11-02 Hitachi, Ltd. Resistance element for semiconductor integrated circuit
US3990102A (en) * 1974-06-28 1976-11-02 Hitachi, Ltd. Semiconductor integrated circuits and method of manufacturing the same
JPS514978A (en) * 1974-07-02 1976-01-16 Mitsubishi Electric Corp HANDOTAISHUSEKIKAIRONO SEISAKUHO
JPS5167080A (en) * 1974-12-07 1976-06-10 Fujitsu Ltd Handotaisochino seizohoho
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device
DE2605641C3 (en) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen High frequency transistor and process for its manufacture

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US4228450A (en) 1980-10-14
DE2861533D1 (en) 1982-02-25
EP0001574A1 (en) 1979-05-02
JPS5466087A (en) 1979-05-28
IT7828238A0 (en) 1978-09-29
EP0001574B1 (en) 1982-01-13
IT1159142B (en) 1987-02-25
JPH0140498B2 (en) 1989-08-29

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