CA1100648A - Method for providing a metal silicide layer on a substrate - Google Patents

Method for providing a metal silicide layer on a substrate

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Publication number
CA1100648A
CA1100648A CA301,740A CA301740A CA1100648A CA 1100648 A CA1100648 A CA 1100648A CA 301740 A CA301740 A CA 301740A CA 1100648 A CA1100648 A CA 1100648A
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Prior art keywords
substrate
metal
silicide
silicon
temperature
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CA301,740A
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French (fr)
Inventor
Billy L. Crowder
Stanley Zirinsky
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/14—Schottky barrier contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Abstract

METHOD FOR PROVIDING A METAL
SILICIDE LAYER ON A SUBSTRATE

Abstract of the Disclosure A method for providing on a substrate a layer of a metal silicide such as molybdenum silicide and/or tantalum silicide and/or tungsten silicide and/or rhodium silicide which includes coevaporating silicon and the respective metal onto a substrate, and then heat treating the substrate to form the metal silicide.

Description

~ ~ _eld of Inve_tion .j I
11 The present invention is concerned with provlding 12 a layer of cer-taln metal silicides such as molybdenum sili-13 cide, tantalum silicide, rhodium silicide, and tungsten 14 silicide on a substrate. The rnethod of the present invention is particularly advantageous for providing metal silicide 16 layers on semiconductive substrates such as doped silicon 17 and doped polycrystalline silicon.
., .'1 I
18 Back~round of the Inv_ tion '1 1 19 Polycrystalline silicon has in recent years been used to a great extent as the interconnec-tion material in A 21 integrated circuits. Polycrystalline silicon is desirable 22 since it is very stable at high temperatures and since 23 silicon dioxide can be chemically vapor deposited or ther-24 mally gro~ thereon. Polycrystalline silicon interconnections ~ i t ~ . ~o-976-072 ": ,~ ~., . ,~ _ _ _ , . , ,,, _ __ . ,,, , _ ,,, . _ .__ _,, ,. , _ _ _ `, _ , , :~ _ _ _ :_ _; ____ __ : i .
.: .: . .. .
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1 have been used in many types of integrated circuit applications such as charge-coupled device arrays, logic arrays~ and one-device memory cell arrays.
An undesirable feature of polycrystalline silicon is its relatively high electrical resistance. Attempts to improve the performance of various integrated circuits by scaling down the de-vice dimensions have not been entirely successful since the IR drops in the interconnections do not scale down while the voltage levels appropriate for operation are reduced. Therefore, it would be de-sirable to decrease the sheet resistance of the polycrystalline silicon interconnections in order to gain increased circuit speed.
It has been suggested that various refractory metals such as molybdenum and tungsten could be used in place of the polycrystalline silicon. However, these metals oxidize during chemical vapor deposi--tion of the silicon dioxide, and since these oxides are much less stable than silicon dioxide, they pose a reliability problem with the finished integrated circuit.
In order to attempt to overcome the problem posed by employing such refractory metals alone, it has been suggested to replace some portion of the polycrystalline silicon layer with a layer of silicide ; of certain metals. For instance, Rideout in IBM* Technical Disclosure Bulletin, Volume 17, No. 6, November 1974, Reducing the Sheet Resis-tance of Polysilicon Lines in Integrated Circuits, pages 1831-33 suggested the use of hafnium silicide obtained by depositing *Registered Trade Mark 1 hafnium on top of polycrys-talline silicon and then heat-ing to react the hafnium and polycrystalline silicon.
In addition, Rideout suggested that other candidates for such purpose included, among others, tantalum silicide, tungsten silicide, and molybdenum silicide. Rideout further suggests that the lines can then be covered wikh chemically vapor deposited oxide.
It was also suggested in U.S. Patent 3,381,1~2, issued April 30, 1968 to C.G. Thorn-ton to form molybdenum silicide over polycrystalline silicon by methods sirnilar to that disclosed by Rideout or by chemical vapor deposi-tion through hydrogen reduction of molybdenum chloride and silane. Further discussion of forming various sili-cides including tungsten silicide by sputtering tungsten onto a silicon containing substrate and then heating to cause formation of the silicide can be found in French patent 74-36005, publication number 2,250,198, and granted June 9, 1980, to R. Amantfa and J.H. Ranfield and in the Journal Electrochemical Society, Solid-State Science and Technology-Fabrication and Thermal Stability of W-Si Ohmic Contacts by V. Kumar, February 1975, pages 262-69.
However, the sputtering techniques suggested suffer from a number of disadvantages. In particular, the ability to accurately vary the silicide composition is quite restrictive. Also, when employing sputtering tech-niques, it is necessary to employ etching to remove metal from those desired areas which are not to include the silicide.
Accordingly, it is an object of the present inven~
tion to provide a method for forming silicides of certain .~

~10~64~3 1 refractory metals which is capable of accurateLy controlling
2 and varying the composition of the sïlicide. It is a fur-
3 ther object of the present invention to provide a process
4 whereby the silicide can be removed from desired areas on the substrate by simple lift-off methods employing a solvent 6 as opposed to the more complex etching proaedures which re-7 quire further masking.

Summar~ of the_Invention The present invention is concerned with providing a layer of a metal silicide on a substrate. The metal is 11 molybdenum, tantalum, tungsten, rhodium, and mixtures thereof.
The metal silicide is formed by coevaporating silicon and 13 one of the above metals onto the desired substrate followed 14 by heat treating the coated substrate.
In addition, silicon dioxide can be formed over 16 the silicide layer by high temperature thermal oxidation.
17 The ability to form sufficient thickness for integrated 18 circuits of oxide by thermal oxidation is not apparent from 19 prior knowledge concerning the silicides in bulk formO For instance, bulk molybdenum disilicide and tungsten disilicide 21 are known for their excellent oxidatio~ resistance. For 22 example, see the Fourth International Chemical Vapor 23 Deposition Conference, E.C.S. Mag., Boston, Mass., October 24 1973, Lo et al, A CVD Study of the Tungsten-Silicon System;
and Engineering Properties of Selected Ceramic Materials, 26 The American Ceramic Society, Inc,, page 5.7.3-10. In 1 particular, with respect to molybdenum disilicide, the 2 literature results on the oxidation rate indicate that 3 at 1050C, an oxide of 10 ~m thickness would be formed in 4 60 minutes based upon the amount of o~ygen used in the film formation. While such a thickness would be suitable 6 for aerospace applications, it would not be entirely 7 satisfactory for integrated circuit applications.
:~
8 Brief Descri~tio.n_of Drawinqs Figures lA and lB illustrate sequential cross-sectional views of one fabrication scheme for an integrated 11 circuit employing the process of the present invention.
1 Figures 2A 2C illustrate sequential cross-13 sectional views of another fabrication scheme for an 14 integrated circuit employing the process of the present invention.
16 Figures 3A and 4A illustrate the relationship 17 between temperature and time o oxidation and thickness 18 of oxide layer for W~i2.
19 Figures 3B and ~B illustrate the relationship between oxidation temperature and time, and sheet resistance 21 for MoSi2-22 Description of Preferred Embodiments 23 The process of the present invention is appli-24 cable to forming films of the desired silicide on any sub strate which is capable of withstanding the high tempera-26 tures employed in the coevaporation process and which i9 ~0-976~072 1 adherent to the desired silicide. ~he present process is 2 particularly advantageous in the preparation of integrated 3 circuits and accordingly is of particular value when the 4 substrate is silicon or polycrystal]ine silicon. For in-stance, the process of the present invention finds partic-6 ular applicability in forming layers which are employed as an overlayer over doped polycrystalline silicon gate elec-8 trodes, as an alternative for polycrystalline silicon as a gate electrode material, and as an overlay directly over doped silicon diffused lines.
11 The metal silicides to which the present invention 12 is directed are molybdenum silicide and/or tantalum silicide 13 and/or tungsten silicide and/or rhodium silicide. The pre-14 ferred metals of the silicides include molybdenum, tantalum, and tungsten and the most preferred silicides are the tung-16 sten silicides. The metal silicide films generally contain 17 from about 60 to about 25 atomic percent of the metal and 18, correspondingly from about 7S to about 40 atomic percent of 19 the silicon.
According to the present invention, the metal and 21 silicon are vaporized under high vacuum and codeposited on 22 the substrate~ The vacuum employed is of the order of about 23 10 5 to 10 7 torr (millimeters of mercury). In the vacuum 24 evaporation method, the metal and the silicon are heated in a high vacuum to a temperature sufficient to cause evapora-26 tion thereof~ A preferred method of heating is by electron-27 beam evaporator and preferably employing a separate electron-4~

1 beam gun for the silicon and for the metal due to the diEfer-ence in evaporatlon rates of the materials. Use of electron-beam evaporator involves utilizing as a heat source, the heat dissipated when a highly collimated beam of elec-tron impinges in the material. The apparatus and conditions for evaporating silicon and the metal are known and need not be described herein in any further detail. It is preferred that the rate of evaporation of the metal and silicon be between about 25 and about 50 angstroms per second. The substrate to be coated is usually maintained at a temperature between about room temperature and about 400C and preferably between about 150 C and 250 C during the coating of the metal and silicon thereon.
After the desired amount of metal and silicon are de-posited onto the substrate, the substrate is removed fronl the vacuum evaporation equipmen-t and then subjected to a high temperature heat treatment. The coated substrate is heated in an inert atmosphere at temperatures from about 700 to about llOO~C and preferably from about 900 to about 1100C.
The maximum temperature suitable is dependent primarily upon practical considerations and particularly is selected so as to avoid excessive grain growth in the silicide layer.
Suitable inert atmospheres under which the heat treatment can be conducted include argon, helium, and hydrogen.
The inert atmosphere should be free of water vapor, oxygen, carbon compounds, nitrogen, and other 1 substances which would cause the formation of carbides, oxides, or ni-trides with the metal during the heating.
The coated substrate is heated at the above tempera-tures for a time sufficient to react the deposited metal and deposited silicon to form the desired silicide and is usually between about 15 minutes and 2 hours. The time required for the heating is inversely related to the tem-perature employed.
After the heat treatment, the coated substrate can, if desired, be subjected to oxidation to thereby provide a self-passivating oxide layer over the siliclde layer. It has been noted that any loss in the conductivity of the silicide layer due to the oxidation is much less than would be expected from the percentage of the layer oxidized. In other words, oxidation of 50~ of the layer does not result in a correspo~dingly 50% decrease in the conductivity of the layer. It is believed that this result may be due to the preferential oxidation of primarily the silicon in the silicide layer and back diffusion of the metal thereby resulting in a metal enriched silicide layer beneath the oxidized layer. For a discussion oE some prior work of interest on the oxidation of molybdenum silicide, see J.
Berkowitz - Matluck et al, "~Iigh Temperature Oxidation II.
Molybdenum Silicide", J. Electrochemical Soc., Vol. 112, No. 6, page 583, June 1965.
Figures 3B and 4B illustrate the change in resis-tivity of some oxidized silicides at various temperatures.

. . . ,~

- 1 . .

1 The overall results indicate about a 30% improvement in 2 the conductivity as compared to expected conductivity 3 based on the pexcentage oxidized. The oxidation of the 4 molybdenum silicide at 1000C for over 15 minutes was detrimental to the film and changed its propertiés. There-6 fore, such conditions for molybdenum silicide should be 7 avoided to maintain high conductivity. The oxidation was 8 conducted in steam under the conditions specified.
The preferred method of oxidation is steam oxidation (or a dry-wet dry oxidation) since such results in better 11 electrical breakdown properties as compared to the use of other 12 means of oxidation. The preferred temperatures employed in the 13 steam oxidation are from about 800 to about 1100C at about 14 atmosphere pressure. The time employed for the oxidation depends ¦upon the desired thickness of the oxide and generally takes 16 between about 15 minutes and about 2 hours. For instance, 1 17 ¦1000-3000 angstroms thickness take about 2 hours at about 18 l800C and about 30 mlnutes at about 950C.
19 ¦ Figures 3A and 4A illustrate the growth of the ¦insulating oxide over the silicide during exposure to 21 ¦steam at the indicated temperatures and times.
22 ¦ Table I below represents resistance measurements 23 ¦obtained for silicide films prepared according to the 24 ¦present invention using electron beam evaporation. The ¦films were deposited on silicon substrate to about 0.5 26 ¦thickness.
I .

YO976-07Z -"-,1 !

able I
Silicide Resistance as Function of Composition and Heat Txeatment (Electron Beam Deposition) (0.5 ~ fllms) Bulk As deposited prior Resistance to heat treatment (microohms Bulk 5he~t centimeters) Resistance Resistance (from the (microohms(ohms/
Com_osition Literature) centimeters) square) w-si 92 Com~osition 30 370 7 4 62 WSi2+Si ~ 150 30 ;~
'~ Ta-Si 92 TasSi3 372 67 05 76 TaSi2 8.5 900 18.0 62 TaSi2+Si , _ Mo-Si yO Mo Composition 250 5.0 85 Mo5Si3 18 325 6.5 63 MoSi2 22 800 16.0 50 MoSi2+Si ----; ~ Rh-Si ~
78.7 RhSi 155 175 3.5 Interdiffused film (Petersson, Phys. Stat. Sol (a) 36, 217 (1976) ~0-976-072 1 Table I (Continued) Silicide Resistance as Function of Composi-tion and Heat Treatment (Electron Beam Deposition) (0.5 ~ films) Heat Treated (100 C -20 min. H2) Oxidized Si Substrate ;~
Bulk Resistance 5heet Resistance Compositionmicroohm centimeters) (ohms/square) W-Si %W Composition 92 W5Si3 55 1.09 76.5 Wsi2 54 1.07 62 WSi2~Si 86 1.72 Ta-Si ~Ta Composition 92 5 3 72.5 1.45 76 TaSi2 79 1.58 20 62 TaSi2~Si 166 8.3 Mo-Si_ %Mo Composition Mo5Si3 60 1.2 63 MoSi2 70 1.4 MoS.i2+Si 159 3.0 Rh-Si -% Composition 78.7 RhSi 77.5 1.55 YO9-76-072 -lOa-~QC~6gL~

1 Table II below demonstrates the improved conductivity of the silicide obtained by the method of the present inven-tion as compared to doped silicon. The improved conduc-tivity is important for improving signal transmission speed on a circuit transmission line.
Table II
:
' Sheet Resistances for Device Processing Runs :
Silicide Lines Diffused Lines '; lO (tungsten silicide) (phosphorus doped silicon) (ohms/square) _ (ohms/square) FET Simulation Sample l 2.0 FET

Sample 2 2.87+ .04 19.7 + .4 Sample 3 2.73 + .10 20O3 _ 2 - -4-point probe test sites.

20 to 90 sites kested.

~0 YO9-76-072 -ll-6~8 1 Table III below illustrates that the use of the metal silicide obtained by the method of the present invention is at least as good as polycrystalline based upon flatband voltage and electrieal breakdown voltage for the oxide over -the silicide. The flatband voltage is one of the parameters directly related to the gate control voltage necessary to turn on the FET device and its specificatlon within a narrow range is important to the operation of FETs for integrated eircuit applications.
Table III

Summary of Capacitor Data (254 micrometers)2 --O vo~ts/
Vfb(volts) Navg(em ) toX(A) Vbd( ) cm) .
EET
Simulation Sample 1 -MoSi2 -1.11+.0~ ---- 323 ---- - --FET
Sample 2 - 16 20 WSi2 -1.07+.03 1.5xlO 376 26-~8 7 Sample 3 - 16 WSi2 -1.1+.1 1.6xlO 375 32+7 8.6 Sample 4 -2 ~~~~ ~~~~ 370 29+7 7.8 Sample 5 (Control) -1.1* ---- 375 16.5+14 4.4 *Predicted for polysilicon FET control gate.

Vfb is Voltage (flatband).

NaVg is Average surface doping.

toX is Gate oxide thickness.

30 Vbd is Breakdown voltage for Gate oxide (is an average value for 100 capacitors - 20 V/sec. 1 microamp trigger).
Ebf is Electrical breakdown field.

YO9-76~072 -12-1 Results other than Vbd are .fo.r 20 to 90 sites on each wafer.
V~b and N (avera~e surface doplng) determined from CV
avg profile measurements-i M volts is volts time 106.

YO9-76-072 -12a-~ ..
.~:

1 Furthermore~ it was observed that the average break-down field for self oxidi~ed silicide of about 3000 angstroms spaced between an aluminum conductor and the silicide layer was greater than 2-3 MV/cm.
Reference to Figures lA and lB illustrates one use of the present invention in integrated circuits ~e.g., the formation of a composite gate of polycrystalline silicon and the metal silicide).
For convenience, the discussion of the fabrication steps is directed to employing a p-type silicon substrate as the semiconductive substrate and n-type impurities as the diffused or implanted dopant impurities. This leads to the n-channel FET technology. Accordingly, it is under-stood that an n-type substrate and p-type diffused or im-planted dopant impurities can be employed according to the present invention in the p-channel FET technology.
It is understood that when the discussion refers to n-type impurities, the process steps are applicable to p-type impurities and vice versa. Also, the present invention is applicable to substrates other than silicon which are known in the art. Also, as used herein, the terms "metallic type interconnection lines" and "high-conductivity interconnection lines" re~er to metal lines such as aluminum as well as to non-metallic materials which nevertheless can have conduc-tivities of the magnitude generally possessed by conductive metals.
Also, when reference is made to impurities of a 6~

1 "first type" and to-impurities of the "second type", it i5 understood that the ~"first type" refers to n or p-type impurities and "second type" refers to the opposite conduc-tivity type. That is, if the "first type" is p, then the "second type" is n. If the "first type" is n, then the "second type" is p.
Referring to Figure lA, there is shown a fragment of a structure. A p-type silicon substrate 1 having any desired crystal orientation (e.g., ~100> ) can be prepared by 10 slicing and polishing a p-type silicon boule grown in the presence of a p-type dopant such as boron following conven-tional crystal growth techniques. Other p-type ~opants for silicon include aluminum, gallium, and indium.
A thin gate insulator layer of silicon dioxide 2 is grown on or deposited onto the silicon substrate 1. This gate insulator, which is usually about 200 to 1000 angstroms thick, is preferably formed by thermal oxidation of the silicon surface at 1000C in the presence of dry oxygen.
A layer of polycrystalline silicon 3 is then deposited.
20 The polysilicon layer is usually approximately 500 to 2000 angstroms thick, and may be formed by chemical-vapor deposition. The polysilicon layer is now doped with an n-type dopant such as arsenic, phosphorus, or antimony by one of several conventional techniques. For example, the polysilicon is doped with phosphorus using the technique of depositing a POC13 layer and heatin~ it to approximately 1000C to drive the phosphorus into the polysilicon 1 making it n-type. A~ter this, the residual of the POC13 layer is removed by etching the wafer in bu~fered hydro-fluoric acid. Next a silicide layer ~ of about 2000-4000 angstroms thick is formed on the polycrystalline silicon by the coevaporation and heating procedure of the present invention as disclosed hereinabove.
A gate pattern can be fabricated by employing one of the several well known procedures: e.g. chemical etching, plasma etching, reactive ion etching, etc. The process details vary with the technique employed, but the final result is similar; namely, a patterned layer of silicide/
polysilicon. If chemical etching is employed, we have found that hot H3PO4 will selectively etch silicides relative to polycrystalline silicon or SiO2. The preferred technique is to etch the silicides by a "dry" technique such as reactive ion etching employing species such as CF4.
The n-type source and drain regions are now formed by well-known ion implantation or diffusion techniques.
For instance, the n-type source and drain regions 7 and 8, respectively, can be formed 2000 angstroms deep by an As75 implant of about 100 KeV energy and 4 x 1015 atoms/cm2 dose.
During implantation, the polysilicon gate 3 and silicide layer 4 act as a blocking mask to prevent n-type dopant impurities from entering the FET channel region under the polysilicon gatç 3.
The boundaries between the n-type source and drain regions and the channel of the FET are determined by the ~' 6~ 51 1 polysilicon gate. This is generally referred to in the prior art as the "sel~-aligned gate technique".
Next, a self passivating silicon dioxide layer 5 is formed on the gate regions by the oxidation procedures discussed hcreinabove. For instance, the structure is subjected to steam oxidation at about 950C for about 30 minutes to provide an oxide thickness of between about 1000 ~`
and 3000 angstroms.
This is followed by a CVD silicon dioxide layer of 10 between about 1000 and about 1500 angstroms thick to prevent subsequently applied metallic interconnection such as aluminum from interreacting with the silicide layer. The oxide layers and metallic layers are defined by conventional masking and etching techniques. For instance, the silicon dioxide can be removed employing buffered HF whereas the aluminum can be etched with mixtures of phosphoric and nitric acids. The aluminum may be deposited by sputtering or evaporation.
Reference to Figures 2A-2C demonstrates another scheme for employing the present invention in fabricating integrated circuits. The following technique is made advantageous in view o~ the ability of the coevaporated silicide to be removed from predetermined portions of the substrate by lift-off methods.
The substrate 11 is coated with a layer cf material 13 which provides a suitable llft-off geometry. In the simplest Il YO9~76-072 -16-, ~ .....
, ~ .

1 case, the layer 13 is a resist material in which the pattern desired is generated by conventional techniques (~.g. PMMA
with electron beam lithography). It should be noted that layer 13 might be a multiple layer stack of materials patterned by employing resist layers and etching procedures in order to achieve a lift off geometry with materials capable of withstanding moderately high temperature processing environ-ments.
After the lift-off layer 13 is patterned, the substrate is then doped in those regions unprotected by the lift-off mask to form an n-type region 12. Techniques such as ion implantation of As, P, or Sb can be used to provide doping in this region.
A layer 14 of coevaporated metal and silicon is applied to the substrate by the coevaporation step discussed here~
inabove. The coevaporated layer 14 is not interconnected between the portions which are above the lift-off material and those portions which are not as would occur in a sputter-ing technique. Sputtering results in some coating of the edges which could cause such interconnection. Accordingly, the lift-off material and that material above it can be readily removed by a simple lift-off procedure with solvent for the resist material such as acetone.
The structure is then subjected to heat treatment at tempera-tures from about 700 to about 1100 C in an inert atmosphere such as argon, hydrogen, or helium as required by the present invention to form the silicide. Next, the silicide layer 14 can be subjected to oxidation to provide a self passivating oxide layer on the silicide layer~
3 An oxidation barrier mask 15 such as a layer of silicon nltride over a layer of silicon dioxide is provided 64~1 l over the portion of ~he substra-te which is subsequently to be the ~evice area.
Doping impurities 16 such asboron can be provided in the field area by ion implantation techniques. Silicon dioxide is then grown such as by CVD over those portions of the substrate not protected by the silicon nitride oxida-tion barrier layers.
The oxidation barrier layer material is considered to be a nonoxidized material under the conditions to which 10 it is subjected in the method of the present invention.
The oxidation barrier layer prevents oxidation of the silicon thereunder.
The oxidation barrier layer is then stripped by employing a suitable solvent. For example, when silicon nitride is employed, it can be etched in a phosphoric acid solution at 180C. Silicon dioxide can be etched in a solu- ~`
tion of buffered hydrofluoric acid.
A gate insulating layer 18 of silicon dioxide is then grown on the substrate. Doping for the channel region is 20 provided by ion implantation. This is followed by deposit-ing the gate material and then delineating by known masking and etching techniques. The gate material can be provided by the coevaporation and heatiny of silicon and the metal, by deposition of polycrystalline silicon alone or by a com-bination of polycrystalline silicon followed by a layer formed by coevaporation and heating of silicon and the metal in accordance with the techniques of the present ;
~.

, _ 1 invention. Ne~t, the source and drain dopants are provided by ion implantation. Then, self-passivating silicon dioxide layer 17 is provided by steam oxidation of the type dis-cussed hereinabove. This is foll.owed by another CVD layer 18 of silicon dioxide.

.. ~', , .

,.1,~, ~.

Claims (23)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A method for preparing metal silicide interconnections in an integrated circuit which comprises providing a layer of a metal silicide on a substrate wherein said metal is selected from the group consisting of molybdenum, tantalum, tungsten, rhodium, and mixtures thereof, by co-evaporating said metal and silicon onto the desired substrate and then heat treating the coated substrate for a time suffi-cient for reacting deposited metal and deposited silicon to thereby obtain said metal silicide interconnections and wherein said interconnections are provided on the same side of the substrate as are electrically active devices.
2. The method of claim 1 wherein said substrate is poly-crystalline silicon.
3. The method of claim 1 wherein said substrate is sili-con.
4. The method of claim 1 wherein said metal is selected from the group consisting of molybdenum, tantalum, and tungsten.
5. The method of claim 1 wherein said metal is molybdenum.
6. The method of claim 1 wherein said metal is tantalum.
7. The method of claim 1 wherein said metal is tungsten.
8. The method of claim 1 which includes heat treat-ing the coated substrate at a temperature from about 700 to about 1100°C in an inert atmosphere.
9. The method of claim 8 wherein said inert atmos-phere is hydrogran, argon, helium, or mixtures thereof.
10. The method of claim 1 which further includes oxidation of a portion of the silicide layer.
11. The method of claim 10 wherein said oxidation is dry-wet-dry oxidation.
12. The method of claim 10 wherein said oxidation is dry-wet-dry oxidation conducted at a temperature between about 800 and about 1100°C for about 15 minutes to about 1 hour.
13. The method of claim 1 wherein said coevaporation is conducted under high vacuum employing electron-beam as the heat source.
14. The method of claim 1 wherein the silicide layer includes an excess of free silicon.
15. The method of claim 1 wherein said silicide includes from about 60 to about 25 atomic percent of said metal and correspondingly from about 75 to about 40 atomic percent of silicon.
16. The method of claim 1 wherein the rate of evapora-tion of said metal and said silicon is between about 25 and about 50 angstroms per second.
17. The method of claim l wherein the temperature of said substrate during coating is between about room temperature and about 400°C.
18. The method of claim l wherein the temperature of said substrate during coating is between about 150°C and 250°C.
19. The method of claim 8 wherein said temperature is from about 900°C to about 1100°C.
20. The method of claim 1 wherein said heat treating is conducted between about 15 minutes and 2 hours.
21. The method of claim 1 wherein the temperature of said substrate during the coating is between about room tempera-ture and about 400°C and which includes heat treating the coated substrate at a temperature from about 700° to about 1100°C in an inert atmosphere.
22. The method of claim 21 where said temperature of said substrate is between about 150°C and 250°C.
23. The method of claim 8 wherein the temperature of said substrate during coating is between about room temperature and about 400°C.
CA301,740A 1977-06-30 1978-04-21 Method for providing a metal silicide layer on a substrate Expired CA1100648A (en)

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US05/811,914 US4180596A (en) 1977-06-30 1977-06-30 Method for providing a metal silicide layer on a substrate

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