CA1094188A - Multiprocessor system - Google Patents
Multiprocessor systemInfo
- Publication number
- CA1094188A CA1094188A CA263,405A CA263405A CA1094188A CA 1094188 A CA1094188 A CA 1094188A CA 263405 A CA263405 A CA 263405A CA 1094188 A CA1094188 A CA 1094188A
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- Canada
- Prior art keywords
- control
- computer
- control computer
- individual computers
- individual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000006870 function Effects 0.000 claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000004891 communication Methods 0.000 abstract description 11
- 230000006854 communication Effects 0.000 abstract description 11
- 230000015654 memory Effects 0.000 description 52
- 238000010276 construction Methods 0.000 description 8
- 230000000875 corresponding effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000008520 organization Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
Abstract
ABSTRACT OF THE DISCLOSURE
A computer system comprises a control or supervisory computer and a plurality of individual computers which are connected to and cooperate with each other under control of a process which establishes a three phase opera-tion. In a control phase only the control computer operates, executes its program and informs the individual computers which function they must carry out during the next phase, the autonomous phase. In the autonomous phase the individual computers simultaneously and independently fulfill their assigned functions and report completion thereof to the control computer. Finally, a communication phase is utilized for a data exchange between the computers.
A computer system comprises a control or supervisory computer and a plurality of individual computers which are connected to and cooperate with each other under control of a process which establishes a three phase opera-tion. In a control phase only the control computer operates, executes its program and informs the individual computers which function they must carry out during the next phase, the autonomous phase. In the autonomous phase the individual computers simultaneously and independently fulfill their assigned functions and report completion thereof to the control computer. Finally, a communication phase is utilized for a data exchange between the computers.
Description
3~
Data processing systems which, for purposes of simultaneous problem processing, provide a plurality of calculating units, cen-tral units or com-puters (multiprocessors), have gained significance in the past. On the other hand, the development of highly integrated calculating units in the form of so-called microprocessors have provided the possibility of construct-ing such multi-computer systems from a plurali.ty of sub-computers. With an increasing number of sub-computers, however, the problems of data traffic between the individual sub-computers and external memories and the like increase considerably.
The object of tlle present invention is thus to provide a computer system consisting of a plurality of individual computers which are connect-ecl to one another and cooperate with one another, in which the above-discuss-ed problems, which result from the frequency of the data traffic between the individual sub-computers, do not occur.
The invention realizes this object by a computer system comprising a supervisory control computer and a plurality of individual computers which are connected to and arranged for cooperation with one another, a plurality of stores each associated with a respective one of the control computer and the individual computers, each store having an input and an output, and a plurality of switching devices each associated with a respective one of tlle individual computers~ the inputs and outputs of the stores associated with the individual computers being connectable via the switching devices to the control computer and the switching devices being controlled by the control computer, the computer system having three phases of operation, namely a control phase during which only the control computer operates, executes its programme and informs the individual cornputers which functions they are to carry out, an autonomous phase during which the individual computers carry out said functions simultaneously and independently of one another without being connected to the control computer or its store and then report the execution of their function by a "stop" signal to the control computer, and an information transmission phase which commences after the control computer has received a "stop" signal from all the individual com--1- ~
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. ~
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puters or from ~elected individual computers and during which, under the control of the control computer, data exchange is effected between the stores of the indivldual computers and the control computer.
In the computer system in accorda.nce with the invention, during the execut.ion of their programs the individual computers cooperate exclusive-ly with their private memories. Thus, it is unnecessary to gain access to common external memories. Therefore, no access problems occur.
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the l~ following clescription, taken in conjunction with the accompanying drawings, on wllich:
Figure l shows the fund~mental construction of a computer system in accordance with the invention;
Figure 2 shows the compu~er system in accordance with the inven-tion during the autonomous phase;
Figure 3 shows the computer system in accordance with the invention during the control-and communication phase;
Figure 4 is a block circuit diagram of a computer system in accord-ance with the invention;
Figure 5 shows the complete circuit of the individual computer w.ith the associated switches and memories;
Figure 6 is a schematic illustration of the switch;
: Figure 7 is a block circuit diagram of the switch control logic;
Figure 8 is a schematic illustration of the switch control logic; ~ :
Figures 9 to 14 show the switch and the switch control logics of various operation states;
Figure 15 shows the complete circui~ of the interface structure;
Figures 16a, b, c, d, e show the data flow under various operating ~`Lb ,. .
.. . .
conditions, and Figure 17 schematically illustrates the construction of the soft-ware.
Figures 1, 2 and 3 show the general construction of the computer system in accordance with the invention and serve to explain the function thereof. As will be seen, the computer system of the inven~ion consists of a control computer with its own main store and an arbitrary number of modules, each of which consist of an individual computer and an associa~ed communica-tion memory and private memory. Figure 2 shows the operation of the computer system in its autonomous phase, during which phase each individual computer has access to its communication memory and to its private memory and operates separately from the other computers and from the control computer. During this time each of the individual computers executes the program which it has been assigned. Figure 3 shows the computer system in accordance with the invention during the control phase or the communication phase. During the control phase only the control computer is in operation, and during this time has access both to its own main memory and also to the communication memories of the individual computers. Also during the communication phase the data flows corresponding to Figure 3 follow. During this phase the con-trol compu*er controls the communication between the communication memorieso the individual computers one between another and between the comm~lication memories and the main memory.
Figure 4 shows the construction of a computer system in accordance with the invention in the form of a block circuit diagram. The control com-puter and its memory is connected via three data busbars 4, 5, 6 to the individual modules. Each of these modules consists of an individual computer, a memory, a switch and a switch control logic. Each of these memories compri-ses the communication and private memories which are illustrated in Figures 1 to 3 and are assigned to each module. The switches serve to selactively con-nect the memory, in dependence upon the momentary phase either to the indivi-dual com~uter or to the data bus 6. The switch is controlled by a switch control logic. The switching s~ate of the switch is retained until a new s~Yitchlng command is received. The data bus 6 and the address bus 5 transmit 8 bit-data items of 16 bit-addresses. The address bus also transmits control commands for the module control logic. These commands consist of 7 bit switching addresses which represents the number of the particular module to have been approached, and of a switching command consisting of I bit. The control bus 4, which is also provided, serves to transmit the signals for the coordination of the various parts of the computer system. These are pri-marily signals which ~rigger and terminate the individual program phases ~start phase for the individual module, stop signals, interrupt signals for the control computer). Also, together with the address bus they transmit signals for the control of the switches. Finally they transmit the ~wo-phase timing signal for the individual computers. The illustrated computer system also comprises a block 8 referred to as "interface" which in addition to a control logic comprises bus drive devices 1, 2 and 3. The con~rol computer is also connected via an input and output line to input-and output devices.
In the exemplary embodiment the contTol computer is in the form of ` a micro-computer Intellec 8/M80 whose 12 K-byte store serves as main memory.
Figure 5 shows the complete circuit of a computer module. A compu-ter module of this type basically comprises three units, th~ individual com-puter I, the switch II and the switch control logic III. In the exemplary embodin~ent the construction has been effected almost exclusively with modules of the firm Intel Corporation corresponding to Intel Catalogue of 1975. An essential component of the individual computer is the micro-processor element 8080 of the firm Intel. The individual co~puter also contains two two-path bus drive devices 12 and 19 of the Type 8216 of the firm Intel, and also one pulse train drive device 11 of the type MH0026CM of the firm National corres-ponding to the data sheet February 1972. The terminal designations in ~he figure conform with those of the above-mentioned supplier firms.
~ ~r~ck fr~r~rk ; ~ i . .
The switch II is constructed from input/output elements 20, 21, 22, 23, 24 and 25 of the type 8212 of the firm Intel and of two bus drive devices 26, 27 of the type 8216 of the firm Intel.
Finally the switch control logic III consists of two l-out-of 8 binary decoders 17~ 18 of the type 3205 of the firm Intel, of two bus switches 15, 16 and of two D-flip-flops 13, 14 of the type Siemens SN 747~. The cir-cuit also contains a series of gates, resistors, capacitors and diodes9 as can be directly seen from the figure.
The module represented in Figure 5 is connected via the lines Do to D7, ~IADo to ~U~D15, ~R and READ to the module store. The lines SADo to SAD15 lcad to the address bus (5 in Figure 4). The lines SD to SD7 lead to the data bus (6 in Figure 4). The remaining lines lead to the control bus ~4 in Figure 4). the designations of the last-mentioned lines are as follows:
~ YRITE: The occurrence of the WRITE signal (WRITE - L) informs the module that the control computer is printing out data onto the data bus.
MMA, ALTA, RNN: These lines serve to indicate the operating s~ate of the module via indicators.
RNN = L: The module is calculating autonomously.
ALTA = I: The moduIe has completed the calculation and transmits a stop signal to the control co~puter.
~ MA = I: The module memory is connected for purposes of data ex-chan~e to the system-address-and data bus.
RF,ADY: Via the READY input the individual computer I is brought in-to the t~AIT-state (by READY = L) during the data exchange be~ween the modules one with another and between the modules and the control computer.
RESET: During the transmission of the reset signal, in ~he indivi-dual computer I the program counter is erased and the command register is set to 0. After the reset, the program sequence commences at the position 0 in the store.
01' 02: are two phase-displaced timing signals DBIN, WAIT, WR, ,, .
"~
SYNC Input, Output. These signals serve to test the individual computers.
During the normal operation of the computer system in accordance with the invention they are of no significance. Their designations correspond to the signal designations given in the Intel catalogue 1975 in the description of the microprocessor module 8080.
WOUTPUT: Via this line the module can transmit an output signal ~WOUTPUT = L).
WHLTA, WHLTA: These signals indicate the STOP state of the computer.
MODUS: By MODUS = H items of data are fed through from the data bus to the module memory, if the reverse data flow direction is not already switched through.
WSIN: This signal (WSIN = L) indicates that the module is ready to apply data from the module memory onto the data bus.
WSOUT: Tlle signal WSOUT = L indica~es that the module is ready to transfer data from the data bus into the module memory.
SYSEN: SYSEN = H serves to enable the switch to connect the module memory to the address-and data bus, if WSIN = L or WSOUT = 1,.
I/O IN: As a result of the transmission of this signal, the control computer informs the module that it wishes to read ou~ data from a module memory.
I/O OUT: As a result of the transmission o this signal, the control computer informs the module that it wishes to write-in data into a module memory.
T I/O: With the timing signal the swi~ch control logic receives the switch control information transmitted from the contTol computer via address-and control bus in a register.
CLEAR: Via the CLEAR input the switch control register is erased. ~-WSEL: Via the WSEL output, ~he switch control logic reports as to whether the module has been selected by the contents of the address bus or the input CSEL.
, . :: , ~ . .. .
CSEL: By means of CSEL = L, the module is selected independently of the contents of the address bus.
Note: The signals ~YOUTPUT, MHLTA, W~ILTA, WSIN, WSOUT, WSEL are out-put signals of the module, which are produced with the aid of open-collec~.or gates whicll are shown by a spot above the gate in the circuit diagram. In the case of the parallel connection of a plurality of modules, these signals can thus be logic-linked by a wired OR or by a wired AND.
Figure 6 schematically illustrates a switch which forms a component of each module. The function of this switch is to connect the module memory 1~ cither to the individual computer or to the system address-or data~bus. As can be seen from Figure 6, items of address information can pass from the individual computer or from the system to the module memory, whereas items of data information can pass from the individual computer or the system to the module memory, but can also flow in the reverse direction. The switch illus-trated in Figure 6 is controlled via the three control inputs. l`he connection path is controlled via the control input SBUS. If the signal H is present at this control input, the connection of the module memory to the system bus is established. If, on the other hand, this control input bears the signal L, the module memory is connected to the individual computer. The direction of ~ the bus is controlled via the inputs DBIN and SIN. The input D~IN is active whe~ oduLe memory and individual computer are connected. When the signal H
ls prescnt at the control input DBIN, the data ~`low takes place ~rom th~
n~o(lule memory to the data bus of the individual computer. If this input ter-min~l carries tlle signal L, the direction of the data flow is reversed. The input SIN is active when the module memory and system bus are connected. If the signal H is present at the terminal SIN, the data flow takes place from the module memory to the data bus of the system. If, on the other hand, ~his terminal bears the signal L the data flow is the reverse. The switch is con-trolled by the switch control logic. Figure 7 is a block circuit diagram of this switch control logic. Figure 8 also schematically illustrates the switch 99~38 control logic ~Yith all its inputs and outputs. The function of the switch control logic is to recognize whether the module to which it belongs has been selected. Selection criteria are constituted by the information content of the address bus and also the switching state of the line CSEL. The switching unit status latch receives the applied information with the timing signal.
CLEAR resets the outputs to O. Via the lines SIN and SBUS the transfer-enable logic controls the switch in dependence upon the contents of the status latch and that of the control lines (SYSEN MODUS) in the following manner:
,l) As a result of SYSEN = H the state of the status latch is directly employed 1~ for the control of the switch, b) The mode input is e~fective only when the output of the status latch I2 is equal to L. As a result of mode = H the switch is switched in such manner that a data transfer from ~he system bus to the module memory is possible. This switching state s~ves to allow parallel write-in into the various module memories during the read-ou~ ~rom a special module memories.
In addition the transfer-enable-logic supplies acknowledgement sig-nals to the e~terior WSIN, WSOUT which are required for the interconnection of a plurality of switches.
Fig~lres 9 to 14 illustrate the possible switch positions. Here it 2a shoul(l be noted that the signals provided with a star are transferred with tho tim.ing signal in the status latch, whereas the others directly influence thc switch position. Figure 9 shows the switch position in which items of inolmation are trallsferred from the module memory in~o the individual com-puter.
Figure 10 shows a switch position during which items of information are transferred from the individual computer into the module memory.
Figure 11 shows a switch posi~ion in which items of information re transferred from the module memory into the system.
Figures 12, 13 and 14 show switch positions during which items of information are transferred from the system into the module memory.
Figure 15 shows the interface which again is constructed from three input-output eiements 30, 31 and 32 of the type 8212 of the firm Intel and seven two-path bus drive devices of the type 8216 of the firm Intel. In addi-tion the circuit contcains three D-flip-flops 41, 42, ~3 of the type SN 747 o~ the firm Siemens AG and four monoflops 4~, 45, 46, and ~7 of the type SN
74123 of the firm Siemens AG. The terminal designations again correspond to the corresponding designations of the manufacturers of the components emplo-yed, and the gat0 amplifiers and other components which have also been used are shown in a standardized illustration. The interface shown in Figure 6 can also be classified into function blocks, which can be related to the il-lustration in Figure 4. Thus, the function block IV corresponds to the illus-tration of the bus drive device 1 in Figure 4, whereas the transmission logic V and IX and the interrupter logic VII correspond to the control logic in Figure 4. In addition the bus drive device VI corresponds to the bus drive device 2 in Figure 4, whereas the bus drive device VIII corresponds to the corresponding element 3 in Figure ~. The interrupt logic VII, under the con-trol of the modules, transmits interrupt signals to the control computer.
The transmission logic V and IX serves to differentiate memory positions in the main memory and the memories of the individual computers.
This logic acts in the communication phase and in the control phase, when items of data are transmitted under the control of the control computer. This logic connects the control computer alternately to the control computer memory in order to obtain commands from the control program and to this module memo-ries or to the control computer memory in ordeT to facilitate the data exchange.
The lines on the left~hand side emanate from the control computer and those on the right-hand side connect the interface to the computer modules and in fact the terminals SADo to SAD15 are connected ~o the address bus, whereas the terminals SD to SD7 are connected to the data bus and the remaining terminals on the right-hand side are connected to the control bus.
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The interTupt logic VII can transmit the following interrupt signals to the control computer:
Il interruption after stop message of an arbitrary module (via wired O~
I2 interrupt after stop message of all modules (via wired ~D), I3 interrupt after output message of an arbitrary module (via wired OR).
The interrupt signal Il facilità~es the handling of problems in which all the modules hunt a specific solution, which however is found at dif-0rent speeds or only by individual modules (e.g. hunting functions).
I2 is the interruption which does not instigate the exchange of theresult until all the modules have ended their calculations.
Via I3 an arbitrary module can, during the running of its program, transmit a specially agreed interruption to the control computer e.g. fault messages ~division by O or similar).
Figure 16 serves to explain the data flow. The data paths are dep-endent upon the switching state of the switch of the individual modules.
Thus in accordance with Figure 16a, items of data can be transf0rred from the maill memory to the memories of the indiviclual computers. In accordance with
Data processing systems which, for purposes of simultaneous problem processing, provide a plurality of calculating units, cen-tral units or com-puters (multiprocessors), have gained significance in the past. On the other hand, the development of highly integrated calculating units in the form of so-called microprocessors have provided the possibility of construct-ing such multi-computer systems from a plurali.ty of sub-computers. With an increasing number of sub-computers, however, the problems of data traffic between the individual sub-computers and external memories and the like increase considerably.
The object of tlle present invention is thus to provide a computer system consisting of a plurality of individual computers which are connect-ecl to one another and cooperate with one another, in which the above-discuss-ed problems, which result from the frequency of the data traffic between the individual sub-computers, do not occur.
The invention realizes this object by a computer system comprising a supervisory control computer and a plurality of individual computers which are connected to and arranged for cooperation with one another, a plurality of stores each associated with a respective one of the control computer and the individual computers, each store having an input and an output, and a plurality of switching devices each associated with a respective one of tlle individual computers~ the inputs and outputs of the stores associated with the individual computers being connectable via the switching devices to the control computer and the switching devices being controlled by the control computer, the computer system having three phases of operation, namely a control phase during which only the control computer operates, executes its programme and informs the individual cornputers which functions they are to carry out, an autonomous phase during which the individual computers carry out said functions simultaneously and independently of one another without being connected to the control computer or its store and then report the execution of their function by a "stop" signal to the control computer, and an information transmission phase which commences after the control computer has received a "stop" signal from all the individual com--1- ~
. .
. ~
~3f~
puters or from ~elected individual computers and during which, under the control of the control computer, data exchange is effected between the stores of the indivldual computers and the control computer.
In the computer system in accorda.nce with the invention, during the execut.ion of their programs the individual computers cooperate exclusive-ly with their private memories. Thus, it is unnecessary to gain access to common external memories. Therefore, no access problems occur.
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the l~ following clescription, taken in conjunction with the accompanying drawings, on wllich:
Figure l shows the fund~mental construction of a computer system in accordance with the invention;
Figure 2 shows the compu~er system in accordance with the inven-tion during the autonomous phase;
Figure 3 shows the computer system in accordance with the invention during the control-and communication phase;
Figure 4 is a block circuit diagram of a computer system in accord-ance with the invention;
Figure 5 shows the complete circuit of the individual computer w.ith the associated switches and memories;
Figure 6 is a schematic illustration of the switch;
: Figure 7 is a block circuit diagram of the switch control logic;
Figure 8 is a schematic illustration of the switch control logic; ~ :
Figures 9 to 14 show the switch and the switch control logics of various operation states;
Figure 15 shows the complete circui~ of the interface structure;
Figures 16a, b, c, d, e show the data flow under various operating ~`Lb ,. .
.. . .
conditions, and Figure 17 schematically illustrates the construction of the soft-ware.
Figures 1, 2 and 3 show the general construction of the computer system in accordance with the invention and serve to explain the function thereof. As will be seen, the computer system of the inven~ion consists of a control computer with its own main store and an arbitrary number of modules, each of which consist of an individual computer and an associa~ed communica-tion memory and private memory. Figure 2 shows the operation of the computer system in its autonomous phase, during which phase each individual computer has access to its communication memory and to its private memory and operates separately from the other computers and from the control computer. During this time each of the individual computers executes the program which it has been assigned. Figure 3 shows the computer system in accordance with the invention during the control phase or the communication phase. During the control phase only the control computer is in operation, and during this time has access both to its own main memory and also to the communication memories of the individual computers. Also during the communication phase the data flows corresponding to Figure 3 follow. During this phase the con-trol compu*er controls the communication between the communication memorieso the individual computers one between another and between the comm~lication memories and the main memory.
Figure 4 shows the construction of a computer system in accordance with the invention in the form of a block circuit diagram. The control com-puter and its memory is connected via three data busbars 4, 5, 6 to the individual modules. Each of these modules consists of an individual computer, a memory, a switch and a switch control logic. Each of these memories compri-ses the communication and private memories which are illustrated in Figures 1 to 3 and are assigned to each module. The switches serve to selactively con-nect the memory, in dependence upon the momentary phase either to the indivi-dual com~uter or to the data bus 6. The switch is controlled by a switch control logic. The switching s~ate of the switch is retained until a new s~Yitchlng command is received. The data bus 6 and the address bus 5 transmit 8 bit-data items of 16 bit-addresses. The address bus also transmits control commands for the module control logic. These commands consist of 7 bit switching addresses which represents the number of the particular module to have been approached, and of a switching command consisting of I bit. The control bus 4, which is also provided, serves to transmit the signals for the coordination of the various parts of the computer system. These are pri-marily signals which ~rigger and terminate the individual program phases ~start phase for the individual module, stop signals, interrupt signals for the control computer). Also, together with the address bus they transmit signals for the control of the switches. Finally they transmit the ~wo-phase timing signal for the individual computers. The illustrated computer system also comprises a block 8 referred to as "interface" which in addition to a control logic comprises bus drive devices 1, 2 and 3. The con~rol computer is also connected via an input and output line to input-and output devices.
In the exemplary embodiment the contTol computer is in the form of ` a micro-computer Intellec 8/M80 whose 12 K-byte store serves as main memory.
Figure 5 shows the complete circuit of a computer module. A compu-ter module of this type basically comprises three units, th~ individual com-puter I, the switch II and the switch control logic III. In the exemplary embodin~ent the construction has been effected almost exclusively with modules of the firm Intel Corporation corresponding to Intel Catalogue of 1975. An essential component of the individual computer is the micro-processor element 8080 of the firm Intel. The individual co~puter also contains two two-path bus drive devices 12 and 19 of the Type 8216 of the firm Intel, and also one pulse train drive device 11 of the type MH0026CM of the firm National corres-ponding to the data sheet February 1972. The terminal designations in ~he figure conform with those of the above-mentioned supplier firms.
~ ~r~ck fr~r~rk ; ~ i . .
The switch II is constructed from input/output elements 20, 21, 22, 23, 24 and 25 of the type 8212 of the firm Intel and of two bus drive devices 26, 27 of the type 8216 of the firm Intel.
Finally the switch control logic III consists of two l-out-of 8 binary decoders 17~ 18 of the type 3205 of the firm Intel, of two bus switches 15, 16 and of two D-flip-flops 13, 14 of the type Siemens SN 747~. The cir-cuit also contains a series of gates, resistors, capacitors and diodes9 as can be directly seen from the figure.
The module represented in Figure 5 is connected via the lines Do to D7, ~IADo to ~U~D15, ~R and READ to the module store. The lines SADo to SAD15 lcad to the address bus (5 in Figure 4). The lines SD to SD7 lead to the data bus (6 in Figure 4). The remaining lines lead to the control bus ~4 in Figure 4). the designations of the last-mentioned lines are as follows:
~ YRITE: The occurrence of the WRITE signal (WRITE - L) informs the module that the control computer is printing out data onto the data bus.
MMA, ALTA, RNN: These lines serve to indicate the operating s~ate of the module via indicators.
RNN = L: The module is calculating autonomously.
ALTA = I: The moduIe has completed the calculation and transmits a stop signal to the control co~puter.
~ MA = I: The module memory is connected for purposes of data ex-chan~e to the system-address-and data bus.
RF,ADY: Via the READY input the individual computer I is brought in-to the t~AIT-state (by READY = L) during the data exchange be~ween the modules one with another and between the modules and the control computer.
RESET: During the transmission of the reset signal, in ~he indivi-dual computer I the program counter is erased and the command register is set to 0. After the reset, the program sequence commences at the position 0 in the store.
01' 02: are two phase-displaced timing signals DBIN, WAIT, WR, ,, .
"~
SYNC Input, Output. These signals serve to test the individual computers.
During the normal operation of the computer system in accordance with the invention they are of no significance. Their designations correspond to the signal designations given in the Intel catalogue 1975 in the description of the microprocessor module 8080.
WOUTPUT: Via this line the module can transmit an output signal ~WOUTPUT = L).
WHLTA, WHLTA: These signals indicate the STOP state of the computer.
MODUS: By MODUS = H items of data are fed through from the data bus to the module memory, if the reverse data flow direction is not already switched through.
WSIN: This signal (WSIN = L) indicates that the module is ready to apply data from the module memory onto the data bus.
WSOUT: Tlle signal WSOUT = L indica~es that the module is ready to transfer data from the data bus into the module memory.
SYSEN: SYSEN = H serves to enable the switch to connect the module memory to the address-and data bus, if WSIN = L or WSOUT = 1,.
I/O IN: As a result of the transmission of this signal, the control computer informs the module that it wishes to read ou~ data from a module memory.
I/O OUT: As a result of the transmission o this signal, the control computer informs the module that it wishes to write-in data into a module memory.
T I/O: With the timing signal the swi~ch control logic receives the switch control information transmitted from the contTol computer via address-and control bus in a register.
CLEAR: Via the CLEAR input the switch control register is erased. ~-WSEL: Via the WSEL output, ~he switch control logic reports as to whether the module has been selected by the contents of the address bus or the input CSEL.
, . :: , ~ . .. .
CSEL: By means of CSEL = L, the module is selected independently of the contents of the address bus.
Note: The signals ~YOUTPUT, MHLTA, W~ILTA, WSIN, WSOUT, WSEL are out-put signals of the module, which are produced with the aid of open-collec~.or gates whicll are shown by a spot above the gate in the circuit diagram. In the case of the parallel connection of a plurality of modules, these signals can thus be logic-linked by a wired OR or by a wired AND.
Figure 6 schematically illustrates a switch which forms a component of each module. The function of this switch is to connect the module memory 1~ cither to the individual computer or to the system address-or data~bus. As can be seen from Figure 6, items of address information can pass from the individual computer or from the system to the module memory, whereas items of data information can pass from the individual computer or the system to the module memory, but can also flow in the reverse direction. The switch illus-trated in Figure 6 is controlled via the three control inputs. l`he connection path is controlled via the control input SBUS. If the signal H is present at this control input, the connection of the module memory to the system bus is established. If, on the other hand, this control input bears the signal L, the module memory is connected to the individual computer. The direction of ~ the bus is controlled via the inputs DBIN and SIN. The input D~IN is active whe~ oduLe memory and individual computer are connected. When the signal H
ls prescnt at the control input DBIN, the data ~`low takes place ~rom th~
n~o(lule memory to the data bus of the individual computer. If this input ter-min~l carries tlle signal L, the direction of the data flow is reversed. The input SIN is active when the module memory and system bus are connected. If the signal H is present at the terminal SIN, the data flow takes place from the module memory to the data bus of the system. If, on the other hand, ~his terminal bears the signal L the data flow is the reverse. The switch is con-trolled by the switch control logic. Figure 7 is a block circuit diagram of this switch control logic. Figure 8 also schematically illustrates the switch 99~38 control logic ~Yith all its inputs and outputs. The function of the switch control logic is to recognize whether the module to which it belongs has been selected. Selection criteria are constituted by the information content of the address bus and also the switching state of the line CSEL. The switching unit status latch receives the applied information with the timing signal.
CLEAR resets the outputs to O. Via the lines SIN and SBUS the transfer-enable logic controls the switch in dependence upon the contents of the status latch and that of the control lines (SYSEN MODUS) in the following manner:
,l) As a result of SYSEN = H the state of the status latch is directly employed 1~ for the control of the switch, b) The mode input is e~fective only when the output of the status latch I2 is equal to L. As a result of mode = H the switch is switched in such manner that a data transfer from ~he system bus to the module memory is possible. This switching state s~ves to allow parallel write-in into the various module memories during the read-ou~ ~rom a special module memories.
In addition the transfer-enable-logic supplies acknowledgement sig-nals to the e~terior WSIN, WSOUT which are required for the interconnection of a plurality of switches.
Fig~lres 9 to 14 illustrate the possible switch positions. Here it 2a shoul(l be noted that the signals provided with a star are transferred with tho tim.ing signal in the status latch, whereas the others directly influence thc switch position. Figure 9 shows the switch position in which items of inolmation are trallsferred from the module memory in~o the individual com-puter.
Figure 10 shows a switch position during which items of information are transferred from the individual computer into the module memory.
Figure 11 shows a switch posi~ion in which items of information re transferred from the module memory into the system.
Figures 12, 13 and 14 show switch positions during which items of information are transferred from the system into the module memory.
Figure 15 shows the interface which again is constructed from three input-output eiements 30, 31 and 32 of the type 8212 of the firm Intel and seven two-path bus drive devices of the type 8216 of the firm Intel. In addi-tion the circuit contcains three D-flip-flops 41, 42, ~3 of the type SN 747 o~ the firm Siemens AG and four monoflops 4~, 45, 46, and ~7 of the type SN
74123 of the firm Siemens AG. The terminal designations again correspond to the corresponding designations of the manufacturers of the components emplo-yed, and the gat0 amplifiers and other components which have also been used are shown in a standardized illustration. The interface shown in Figure 6 can also be classified into function blocks, which can be related to the il-lustration in Figure 4. Thus, the function block IV corresponds to the illus-tration of the bus drive device 1 in Figure 4, whereas the transmission logic V and IX and the interrupter logic VII correspond to the control logic in Figure 4. In addition the bus drive device VI corresponds to the bus drive device 2 in Figure 4, whereas the bus drive device VIII corresponds to the corresponding element 3 in Figure ~. The interrupt logic VII, under the con-trol of the modules, transmits interrupt signals to the control computer.
The transmission logic V and IX serves to differentiate memory positions in the main memory and the memories of the individual computers.
This logic acts in the communication phase and in the control phase, when items of data are transmitted under the control of the control computer. This logic connects the control computer alternately to the control computer memory in order to obtain commands from the control program and to this module memo-ries or to the control computer memory in ordeT to facilitate the data exchange.
The lines on the left~hand side emanate from the control computer and those on the right-hand side connect the interface to the computer modules and in fact the terminals SADo to SAD15 are connected ~o the address bus, whereas the terminals SD to SD7 are connected to the data bus and the remaining terminals on the right-hand side are connected to the control bus.
. .
The interTupt logic VII can transmit the following interrupt signals to the control computer:
Il interruption after stop message of an arbitrary module (via wired O~
I2 interrupt after stop message of all modules (via wired ~D), I3 interrupt after output message of an arbitrary module (via wired OR).
The interrupt signal Il facilità~es the handling of problems in which all the modules hunt a specific solution, which however is found at dif-0rent speeds or only by individual modules (e.g. hunting functions).
I2 is the interruption which does not instigate the exchange of theresult until all the modules have ended their calculations.
Via I3 an arbitrary module can, during the running of its program, transmit a specially agreed interruption to the control computer e.g. fault messages ~division by O or similar).
Figure 16 serves to explain the data flow. The data paths are dep-endent upon the switching state of the switch of the individual modules.
Thus in accordance with Figure 16a, items of data can be transf0rred from the maill memory to the memories of the indiviclual computers. In accordance with
2~ Figure 16b, items of data can be transmitted from the main memory simultaneou-sly to all the module memories. In accordance ~ith Figure 16 items of data can be transmitted from the memory of a selected computer module to the main memory and in accordance with Figure 16d items of data can be transmitted from tl~e melllory of an individual computer simultaneously the memory of all the other individual computers and the main memory. Pigure 16e finally shows the connection of the data paths in the autonomous phase.
The system- and user programs m~st be matched to the construction and the organization of the computer.
Fi~ure 17 gives a view of the construction of the soft-ware. The control computer executes the following programs:
. .
MONITO~ is a program parcel which facilitates the operation of ~he computer system from a console and contains auxiliary programs for the input and output.
START is a program which assists the flow of the control phase and the initiation of the autonomous phase.
DISP is a program which produces the data exchange between the dur-ing the information exchange phase.
The individual nmodules execute ~he following system programs.
AUTO interprets the item of information received by the control com-puter in the control phase and initiates the requested user routine.
~ LT reports the execution of the order to the control computer andbrings the module into the waiting state.
As can also be seen from Figure 17, the system program is hierarchi-cally organized in two levels. The upper level consists of the functions of the control computer, whereas the lower level comprises the system functions distributed between the modules.
The user programs mus~ also be organi~ed in modular fashion in the same way as the system program, as can also be seen from Figure 17.
Although we have described our invention by reference to particular embodiments thereof, many changes and modiications oE the invention may be-come apparent to those skilled in the art without departing from the spirit nnd scope of the invention. We therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of our contribution to the art.
The system- and user programs m~st be matched to the construction and the organization of the computer.
Fi~ure 17 gives a view of the construction of the soft-ware. The control computer executes the following programs:
. .
MONITO~ is a program parcel which facilitates the operation of ~he computer system from a console and contains auxiliary programs for the input and output.
START is a program which assists the flow of the control phase and the initiation of the autonomous phase.
DISP is a program which produces the data exchange between the dur-ing the information exchange phase.
The individual nmodules execute ~he following system programs.
AUTO interprets the item of information received by the control com-puter in the control phase and initiates the requested user routine.
~ LT reports the execution of the order to the control computer andbrings the module into the waiting state.
As can also be seen from Figure 17, the system program is hierarchi-cally organized in two levels. The upper level consists of the functions of the control computer, whereas the lower level comprises the system functions distributed between the modules.
The user programs mus~ also be organi~ed in modular fashion in the same way as the system program, as can also be seen from Figure 17.
Although we have described our invention by reference to particular embodiments thereof, many changes and modiications oE the invention may be-come apparent to those skilled in the art without departing from the spirit nnd scope of the invention. We therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of our contribution to the art.
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A computer system comprising a supervisory control computer and a plurality of individual computers which are connected to and arranged for cooperation with one another, a plurality of stores each associated with a respective one of the control computer and the individual computers, each store having an input and an output, and a plurality of switching devices each associated with a respective one of the individual computers, the inputs and outputs of the stores associated with the individual computers being connectable via the switching devices to the control computer and the switching devices being controlled by the control computer, the computer system having three phases of operation, namely a control phase during which only the control computer operates, executes its programme and informs the individual computers which functions they are to carry out, an autonomous phase during which the individual computers carry out said functions simultaneously and independently of one another without being connected to the control computer or its store and then report the execution of their function by a "stop" signal to the control computer, and an information transmission phase which commences after the control computer has received a "stop" signal from all the individual computers or from selected individual computers and during which, under the control of the control computer, data exchange is effected between the stores of the individual computers and the control computer.
2. A computer system as claimed in claim 1 wherein the information transmission phase commences after the control computer has received a "stop"
signal from all the individual computers or from selected individual com-puters determined in accordance with hardware of the computer system.
signal from all the individual computers or from selected individual com-puters determined in accordance with hardware of the computer system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2546202.6 | 1975-10-15 | ||
| DE19752546202 DE2546202A1 (en) | 1975-10-15 | 1975-10-15 | COMPUTER SYSTEM OF SEVERAL INTERCONNECTED AND INTERACTING INDIVIDUAL COMPUTERS AND PROCEDURES FOR OPERATING THE COMPUTER SYSTEM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1094188A true CA1094188A (en) | 1981-01-20 |
Family
ID=5959217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA263,405A Expired CA1094188A (en) | 1975-10-15 | 1976-10-14 | Multiprocessor system |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4219873A (en) |
| JP (1) | JPS6057610B2 (en) |
| BE (1) | BE847351A (en) |
| CA (1) | CA1094188A (en) |
| CH (1) | CH610424A5 (en) |
| DE (1) | DE2546202A1 (en) |
| FR (1) | FR2328249A1 (en) |
| GB (1) | GB1565536A (en) |
| IT (1) | IT1073014B (en) |
| NL (1) | NL7611444A (en) |
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-
1975
- 1975-10-15 DE DE19752546202 patent/DE2546202A1/en active Pending
-
1976
- 1976-08-12 CH CH1027076A patent/CH610424A5/xx not_active IP Right Cessation
- 1976-10-11 GB GB42138/76A patent/GB1565536A/en not_active Expired
- 1976-10-12 FR FR7630610A patent/FR2328249A1/en active Granted
- 1976-10-13 IT IT28248/76A patent/IT1073014B/en active
- 1976-10-14 CA CA263,405A patent/CA1094188A/en not_active Expired
- 1976-10-15 US US05/732,988 patent/US4219873A/en not_active Expired - Lifetime
- 1976-10-15 NL NL7611444A patent/NL7611444A/en not_active Application Discontinuation
- 1976-10-15 BE BE171561A patent/BE847351A/en not_active IP Right Cessation
- 1976-10-15 JP JP51123743A patent/JPS6057610B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2328249A1 (en) | 1977-05-13 |
| JPS5248947A (en) | 1977-04-19 |
| FR2328249B1 (en) | 1980-04-30 |
| DE2546202A1 (en) | 1977-04-28 |
| CH610424A5 (en) | 1979-04-12 |
| BE847351A (en) | 1977-01-31 |
| GB1565536A (en) | 1980-04-23 |
| IT1073014B (en) | 1985-04-13 |
| US4219873A (en) | 1980-08-26 |
| NL7611444A (en) | 1977-04-19 |
| JPS6057610B2 (en) | 1985-12-16 |
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