CA1091352A

CA1091352A - Two-stage weighted capacitor circuit for analog-to- digital and digital-to-analog converters

Info

Publication number: CA1091352A
Application number: CA277,420A
Authority: CA
Inventors: Yen S. Yee
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1976-05-10
Filing date: 1977-04-29
Publication date: 1980-12-09
Also published as: IT1113584B; FR2351544A1; GB1518482A; DE2719471A1; JPS52136552A; FR2351544B1; US4077035A

Abstract

TWO-STAGE WEIGHTED CAPACITOR CIRCUIT FOR
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS

ABSTRACT OF THE DISCLOSURE
A two-stage weighted capacitor network for use as an analog-to-digital or digital-to-analog converter is described. A
capacitor ladder is included having two similar groups of capacitors connected in parallel. In each group the parallel capacitors have values starting with value C and decreasing in binary fractional amounts C/21, C/22, C/23, C/24 etc. to C/2n-1. The two groups are interconnected through a coupling capacitor of value C/2n-1 and each of the capacitors in the two groups are selectively connected through switches to either a reference voltage or ground potential. A high gain amplifier connected as an inverting amplifier with a 2C capacitor feedback path is connected to the capacitor ladder. When the circuit is used in a digital-to-analog converter, the 2C capacitor is reset and then the digital input pattern, consisting of 2n bits, is manifested by connecting the capacitor ladder switches to the ground potential for "1" bits and leaving the other swithces connected to the reference potential for "0" bits. When the circuit is used in an analog-to-digital converter the output of the amplifier is connected to a comparator which serves as a polarity detector and which feeds a set of control logic. The control logic then sets the switches, which were originally all connected to the analog voltage, in a binary search mode.

Description

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. 2 Field Of The Invention 3 The present invention relates to weighted capacitor 4 circuit for use in digital-to-analog and analog-to-digital converters, - 5 and more particularly to a circuit employing two similar stages of - 6 weighted capacitors interconnected through a coupling capacitor and in combination with a feedback amplifier.

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8 Description Of The Prior Art 9 U.S. Patent 3,890,610 issued June 17, 1975 to Olivier Cahen on a priority application filed October 31, 1972 entitled "High Precision 11 Digital-To-Analog Converters" and assigned to ~lomson-CSF relates to a 12 digital-to-analog converter including resistors arranged in a series of 13 ladder networks which correspond to binary digits in combination with 14 a feedback amplifier which functions as a low impedance.
U.S. Patent 3,611,356 issued September 17, 1974 to Alan K. Jensen 16 on an application filed September 12, 1969 entitled"Digital-to-Analog 17 Translator" and assigned to Litton Business Systems, Inc. and U.S.
18 Patent 3,836,906 issued September 17, 1974 to Ando et al on a priority 19 application filed February 28, 1973 entitled "Digital-To-Analog Converter Circuit" and assigned to Sony Corporation are example of 21 converter circuits employing weighted capacitors.
22 Other references which illustrate the state of the prior art 23 are as follows:
24 U.S. Patent 3,651,518 U.S. Patent 3,665,458 26 U.S. Patent 3,906,488 27 None of the cited references disclose a two-stage weighted 28 capacitor converter according to the principles of the present invention.

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l _ummary Of The Invention

2 An object of the present invention is to provide a circuit

3 for analog-to-digital and digital-to-analog converters employing a

4 two-stage capacitor network interconnected through a coupling capacitor.
Another object of the present invention is to provide a two-6 stage weighted capacitor circuit for analog-to-digital and digital-to-7 analog converters employing a feedback inverting amplifier.
~-~ 8 A further object of the present invention is to provide a 9 circuit for digital-to-analog and analog-to-digital converters/ nclu~ding a capacitor network where the capacitor sizes vary from 1 to 2~- )for ll digital signals of n bit length and the area for the capacitors ~s substan-12 tially reduced.
13 Still another object of the present invention is to provide a circuit for digital-to-analog and analog-to-digital converters which may be fabricated using monolithic metal-oxide-silicon technology and 16 wherein the effect of parasitic capacitance is eliminated.
17 A further object of the present invention is to provide a ' 18 circuit for digital-to-analog and analog-to-digital converters 19 featuring high speed bipolar operation wherein no trimming is required.
The foregoing and other objects, features and advantages of 21 the invention will be apparent from the following more particular 22 description of a preferred embodiment of the invention, as illustrated 23 in the accompanying drawings.
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`~ 1 Brief Description of The Drawings ` 2 FIG. 1 is a schematic illustration of an embodiment of the :`~
3 circuit of the present invention which may be employed as a digital-to-4 analog converter.
FIG. 2 is a schematic illustration of an embodiment of the 6 circuit of the present invention connected in a combination as an analog-7 to-digital converter.
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8 Detailed Description of The Invention 9 Referring to FIG. 1, an embodiment of the present invention is illustrated as a digital-to-analog converter. The circuit includes a 11 two-stage capacitor network wherein the two stages contain similar 12 elements. The first stage includes capacitors 10, 12, 14, 16, 18 and 20 13 each connected on one side to switches 22, 24, 26, 28, 30 and 32 14 respectively. One advantage of the present inventlon is that it is possible to fabricate the circuit using monolithic metal-oxide-silicon 16 technology, and in such instances, the diffusion plates (D*) of capacitors 17 10 through 20 are connected to switches 22 through 32. The other side of 18 each of the capacitors 10 through 20 is connected in co~mon to a series 19 coupling capacitor 34.
In like manner, the other stage of the network includes capacitors 21 36, 38, 40, 42, 44 and 46 connected to switches 48, 50, 52, 54, 56 and 58 22 respectively. Capacitors 36, 38, 40, 42, 44 and 46-are connected in common 23 to the diffusion plate (D*) of capacitor 34 and to the input of a high gain 24 amplifier 62.

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1 Switches 22 through 32 and 48 through 58 are arranged so that 2 the diffusion plates of capacitors 10 through 20 and 36 through 46 are 3 connected at one switch position to a source of reference voltage 4 Vref and at a second switch position to ground potential 60.
The switches 22 through 32 and 48 through 58 are shown symbolic-6 ally as a simple means for indicating a digital signal in terms of switch 7 positions. It should be understood that in practice the digital signal 8 may be electronic and the aforesaid switches may be FETs and may be 9 fabricated within an integrated circuit, for example, wlth MOS technology.
Amplifier 62 is connected as an inverting amplifier with a 11 feedback capacitor 64 with its diffusion plate connected to the output 12 of amplifier 62. A switch 66 is connected across capacitor 64 and the 13 other input to amplifier 62 is connected to ground potential 60. The 14 output of amplifier 62 is designated V .
In FIG. 1, there is a switch associated with each binary 16 position of the n-bit digital word to be converted, therefore n is 12 in 17 the present example. Normally, in a weighted resistor or capacitor type 18 converter circuit the range of values for the resistors or capacitors 19 extends from 1 to 2n 1 for n bits. In the present invention the capacitor range is from 1 to 2(2 1) thereby improving the resolution of the circuit 21 and substantially reduce the silicon area required for the capacitors.
22 Thus, considering capacitors 10 and 36 or having a value C, the other 23 capacitors in e/nh ne\twork decrease in fractional value steps C/2, C/4, 24 C/8 etc. to C/2~ Jwhich in the present example is C/25 = C/32.
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, 25 Capacitor 64 has a value 2C and series capacitor 34 has a value C/32.

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1 In operation, switch 66 lnitially closes to reset capacitor 2 64, such that it has no net charge prior to a conversion cycle and 3 opens durlng a conversion cycle. All the switches 22 through 32 and 48 4 through 58 are connected to reference voltage Vref while switch 66 is closed. Thus, at ~he beginning of the conversion cycle a charge of Q ~ Vr f X C is placed on the upper plate of the most significant bit 7 capacitor 36 (capacitor 20 being the least significant bit capacitor).
8 A charge Q/2 is placed on the upper plate of capacitor 38, a charge of g Q/4 is placed on the upper plate of capacitor 40 and so on down to capacitor 46 which has a charge of +Q132 on its upper plate.
11 At this point it is important to note that the other side 12 of each of the capacltors 36, 38, 40, 42, 44 and 46 are connected at a 13 common node at the input of amplifier 62 and that thiæ common node does 14 not vary in potential and stays tied to ~ero. Also, the output voltage V from amplifier 62 is equal to the voltage across capacitor 64 plus 16 the voltage at the common node which is tied to zero. Thus, the output 17 voltage Va is equal to the Q transferred across capacitor 64 divided by 18 the value 2C of capacitor 64. Therefore, Va - Q transferred/2C and the Q
19 transferred is the charge from each of the capacitors 36 through 46 which will be transferred when their associated switches are moved from Vref to 21 ground 60.
22 For example, when switch 48 is moved from Vref to ground, 23 charge Q - Vref x C is transferred across capacitor 64 and V = +Q12C 3 24 Vref x C/2C - Vref/2 for the most significant bit position represented by switch 48.

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3~2 i~`, 1When switch 50 i9 moved from Vref to ground, the charge trans-2ferred is Q s Vref x C/2 and Va 5 Vref x C/2 x 1/2C = Vref~4. Likewise 3 when switch 52 is moved from Vref to ground, charge Q 3 Vref x Cl4 is 4 transferred and Va 3 Vref x C/4 x 1/2C - Vref/8.
- 5In like manner, when each of the remaining switches 54, 56 and 6 58 are moved individually from Vref to ground 60, values of Va equal to 7Vref/16, Vref/32 and Vref/64 are produced at the output of amplifier 62.
8In prior art digital-to-analog converters employing successive gapproximation, the further increments V ef/128, Vr f/256, Vr f/512, etc.
are produced by selecting capacitors of proportional si~e such that the 11 total range of the selected capacitors is from 1 to 2n 1 or from 1 to 2048 12 in twelve increments where n equals 12. In the present invention, the ....
13 seventh through twelfth significant bits are manifested using a second 14 capacitnr stage wherein the capacitor sl~es are again in the range from lS 1 to 2 2 ~ which in the example of Fig. 1 is C, C/29 C/4, C/8, C/16 16 and C/32 for capacitoræ-10, 12, 14, 16, 18 and 20. This means that when 17 switch 22 is moved from Vref to ground the charge transferred must be the 18 same as if capacitor 10 had a value C/64 rather than C in order to produce 19 a value Va - Vref x Cl64 x 1/2C = Vref/128.
This is accomplished by virtue of the fact that the input 21 node to amplifier 62 is tied to ground and does not vary in potential.
22 Thus, the capacitors in the right side stage have no effect on the 23 capacitors on the left stage. Now, when ~witch 22 is moved from V
ref 24 to ground, a voltage increment ~V is produced and is transferred across capacitor 34. Also, capacitor 34 is in parallel with capacitor 20 to 26 produce a resultant capacitance C/16 which is also parallel with capacitor 18 . .i .
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1 to produce a resultant capacitance C/8 which is also ln parallel with 2 capacitor 16 to produce a resultant capacitance C/4 which, being in parallel 3 with capacitor 14 produces a capacitance C/2, which in parallel with 4 capacitor 12 produceæ a capacitance C which in parallel with capacitor 10 produces a capacitance of 2C.
6 Thus, when switch 22 is moved from Vref to ground, the voltage ~V
7 across capacitor 34 is Vref x C/2C. ~V is therefore equal to V f/2 wh$ch 8 is the same as Vref x C/64 in terms of the Q which is transferred to 9 capacitor 64. Consequently, the voltage V from amplifier 62 is Vref x C/2C x C/32 x 1/2C ~ Vref/128. In like manner it can be shown 11 that the voltage V produced when switches 24, 26, 28, 30 and 32 are 12 separately moved from Vref to ground is Vref/256, Vref/512, Vref/1024, 13 V /2048 and V /4096 ref ref respectively.
14 Therefore, an analog voltage will be produced for any n bit lS digital signal (n = 12 in Fig. 1) by manifesting the digital signal by 16 moving the associated ones of switches 48 through 58 and 22 through 32 17 from Y ef to ground for "1" bits and leaving the switches associated 18 with digital "O's" connected to V f.
19 The aforesaid explanation can be expressed mathematically as follows. If the i bit is a digital "1", the associated ith switch 21 is moved to ground and amplifier 62 integrates the charge due to the 22 coupling into its input node. This results in a positive increment 23 of voltage equal to Vref(c/2 ) (1/2C) = Vref 2i at Va. Thus 24 Ya ~ bi Vref/2 bi = 1, digital "1"
n bi = ~ digital "0"

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1 It is seen from the previous discussion that the two-stage 2 capacitor network operates to convert a digital signal of n-bits into a 3 corresponding analog signal by employing a total network of capacitors 4 whose values range from 1 to 2 ~ 1 rather than 1 to 2n 1. In the specific embodiment where n is 12, the capacitor range is from 1 to 32 .
6 (i.e., C to C/32) rather than from 1 to 2048 (i.e., C to C/2048). In 7 addition to a smaller range offering increased accuracy, the area 8 for the capacitors needed is substantially reduced, which is very : .
9 important when the converter is embodied as an integrated circuit on a chip.
11 Also, the capacitors inherently include a diffusion plate, and 12 the diffusion plate to substrate connection acts as a diode which is a 13 non-linear capacitor. This non-linear capacitor is a parasitic capacitance 14 70, which is depicted by the dotted lines in Fig. 1. However, because the node to which this parasitic capacitor is coupled is fixed and does-not 16 move in potential, the parasitic capacitance has no effect. This is 17 another important advantage of the invention.
18 The digital-to-analog converter described and illustrated in 19 Fig. 1 can be used as an element in an analog-to-digital converter system as shown in Fig. 2. In Fig. 2 the digital-to-analog converter of Fig. 1 21 is provlded as element 72. The output voltage Va from converter 72 is 22 connected to a comparator 74 along with the analog signal V to be 23 converted. The output of comparator 74 is connected to a storage register 24 76 having twelve stages, each connected to a separate one of the twelve switches in converter 72. The operation of storage register 76 is 26 controlled by sequencing and timing logic means 78 which is in turn 27 operated by system clock pulses from clock 80 and an input command.

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The system of FIG. 2 operates ln a binary search mode. Initially 2 capacitor 64 within converter 72 is reset by the closure of switch 66 and 3 all the digital switches 48 through 58 and 22 through 32 are connected to 4 V f. Then all the switches 48 through 58 and 22 through 32 are reconnected to ground potential 60. This switch transition produces a V ef output - 6 potential from amplifier 62 and therefore from the output of converter 72 7 in FIG. 2. Next, the most significant bit switch 48 is moved from ground , potential to Vref. This produces a negative voltage - Vr f/2 which is 9 combined with Vref at the output of amplifier 62 and produces a positive potential Vref/2 at the output of converter 72 which is compared with 11 the input analog signal Vx at comparator 74. The output of comparator 74 12 will be either plus (+) indicating that V is greater than V f/2 (i.e.
13 V is between V f/2 and full scale Vref) or the output will be negative 14 (-) indicating that Vx is less than Vr f/2 (i.e. V is between 0 and Vref/2).
If the output from this first comparison is (+), then switch 48 ~ 16 is reconnected to ground potential 60 and next significant bit switch 50 ; is moved and connected to Vref. This produces a negative voltage - V f¦4 18 which is combined at the output of amplifier 62 and produces a positive potential Vref - Vref/4 = 3Vref/4 at the output of converter 72, which is used for the second comparison against V .
21 If the output from the first comparison wa~ (-), then switch 48 ' 22 is left in position and next significant bit switch 50 is moved andconnected to Vref. This produces a negative voltage - 3Vref/4 which is '~ 24 combined with Vr f at the output of amplifier 62 to produce a positive potential V f - 3V f/4 = Vr f/4 at the output of converter 72 which is 26 used for the second comparison. In this manner a sequence of output , .

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potentials sre produced at the output of converter 72 equivalent to 2 V f/2 + V f/4 + V f/8 + Vref/16 etc. and comparisons are performed 3 until the output of comparator 74 is zero. At this point the switches 48 4 through 58 and 22 through 32 which are connected to ground potent~al 60 represent digital "l"s and those connected to V f represent digital "0"8 6 and the total switch array is the digital representation of the analog 7 input signal Vx.
8 With slight difications the digital-to-analog converter of 9 FIG. 1 combined in the structure of FIG. 2 can be employed as another analog-to-digital converter which operates in a different mode. One ll modification is to provide a third contact position for each of the 12 switches 48 through 58 and 22 through 32, with each of the third contacts 13 being connected to the input analog signal V . The other modification is 14 to have the input lead to comparator 74 in FIG. 2 connected to ground potential rather than to V .
x 16 The mode of operation of this embodiment is that initially the 17 switches 48 through 58 and 22 through 32 are all connected to Vx and are 18 then all switched to ground connection 60. This results in a positive 19 potential of Vx at the output of converter 72. Next, the most significant bit switch 48 is moved to Vref producing a potential oE -Vrefj2 which 21 when combined with Vx at the output of converter 72 produces a resultant 22 potential which is either positive (+~ or negative t-) depending on the 23 value of Vx with respect to Vref/2 (i.e. either above or below). This 24 output of converter 72 is applied to comparator 74 (the other input of : ,......................................... . .
which is ground potential) and comparator 74 operates as a polarity 26 detector.
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1 If the polarity is (+), this i~ an indication~that Vx is between Vref/2 and Yref (full Rcsle) but if the polarity is (-) it is 3 an indication that Vx is between Vref/2 and ground potential. When a (+) 4 polarity is detected, switch 48 is returned to ground potential and the next significant bit switch 50 is moved to Vref. This produces a potential 6 of -3Vref/4 which when combined with Vx at the output of converter 72 7 produces a resultant potential which i9 either (+) indicating ~hat Vx i8 greater ~han 3Vr f~4 or (-) indicating that V is greater than Vref/2 9 but below 3Vref/4. This determination is made in comparator 74.
However when a (-) is initially determined switch 48 is left 11 connected to Vref and switch 50 is also connectet to Vref producing a 12 potential of -3Vref/4 which when combined with Vx at the output of 13 converter 72 results in a positive potential (+) indicating at comparator 14 74 that Yx is between Vref/4 and Vref/2 or a negatlve potential (-) indicating at comparator 74 that Vx is between ground level and Vref/4.
16 This sequence continues so that Y is effectively compared with 17 V ef/2 + Vr f/4 + V ef/8 + Vref/16 etc. until the output of converter 72 is 18 zero. The particular arrangement of the switches 48 through 58 and 22 19 through 32 indicate the digital representation of the input analog signal Vx. The switche- connécted to ground potential represent "1"
21 bits and the switches connected to Vref represent "O" bits.
22 What has been de~cribed is a unique circuit which may be 23 employed for digital-to-analog and analog-to-digital conversion. The 24 circuit incorporates two weighted capacitor networks which are connected through a coupling capacitor to a node which i8 tied to a 26 fixed potential by means of a feedback a~plifier. Because of this comr 27 bination the range of weights required in each capacitor network is smaller 28 than the range that would be required in a single network. This feature 29 reduces the total size of capacitor area required which is a very significant aspect when the circuit is fabricated in MOS technology.
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- 1 While the invention has been p~rticularly shown and described 2 with reference to preferred embodiments thereof, it will be understood by ` 3 those skilled in the art that the foregoing and other changes in form 4 and details may be made therein without departing from the spirit and scope of the invention.
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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A two-stage weighted capacitor signal conversion circuit comprising a first network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to c/2 ? - 1 where n is an integer.
an amplifier means including an input and output lead and a feedback capacitor connected between said input and output leads and wherein one side of each of said capacitors of said first network is connected to said amplifier input lead at a first node, a second network of capacitors including a plurality of n/2 capacitors, said capacitors having decreasing fractional values from C/2° to ?-1, one side of each of said capacitors of said second network being connected together at a second node, a coupling capacitor connected between said first and second node, a plurality of n switches, each switch connected to the other side of a separate one of said n capacitors of said first and second networks, said switches being adapted to be selectively connected to at least a first reference potential and a second reference potential, wherein said amplifier means functions to maintain said first node constantly fixed at said second reference potential and wherein said plurality of switches are selectively actuated in accordance with a digital signal representation to establish electrical paths through said capacitors connected thereto to provide an analog signal on the output lead of said amplifier means which is an analog representation of said digital signal representation.

2. A signal conversion circuit according to claim l wherein said amplifier means is an inverting amplifier having a second input lead con-nected to said second reference potential.

3. A signal conversion circuit according to claim 1 wherein said feedback capacitor has a value 2C and includes a reset switch connected across the terminals thereof.

4. A signal conversion circuit according to claim 1 further including a source of input analog signal, a comparator means connected to said source of said input analog signal and the output lead of said amplifier means and responsive to said analog signal therefrom for comparing said two analog signals and for pro-ducing a comparison signal, storage means connected to said comparator means for storing said comparison signal, said storage means also connected to said plurality of n switches for selectively operating said switches in accordance with said comparison signal for producing a successive analog signal on said amplifier means output lead until the output from said comparator means is zero and said plurality of n switches are set in a digital sequence representative of said input analog signal.

5. A signal conversion circuit according to claim 4 wherein said storage means includes a storage register, a sequencing means connected to said storage register for controlling the operation of said register, and a clock signal means connected to said sequencing means.

6. A signal conversion circuit according to claim 1 further including a source of input analog signal and wherein said plurality of n switches are adapted to be selectively connected to said first reference potential, said second reference potential and to said input analog signal, a polarity detector means connected to said second refer-ence potential and the output lead of said amplifier means and responsive to said analog signal therefrom for detecting the polar-ity of said analog signals and for producing an output signal based on said polarity, storage means connected to said polarity detector means for stor-ing said detector output signal, said storage means also connected to said plurality of n switches for selectively operating said switches in accordance with said polarity detector output signal for producing a successive analog signal on said amplifier means output lead until the output of said amplifier means is zero and said plurality of n switches are set in a digital sequence representative of said input analog signal.

7. A signal conversion circuit according to claim 6 wherein said storage means includes a storage register, a sequencing means connected to said storage register for controlling the operation of said register, and a clock signal means connected to said sequencing means.