CA1075373A - Semiconductor device having a hetero junction - Google Patents

Semiconductor device having a hetero junction

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Publication number
CA1075373A
CA1075373A CA251,094A CA251094A CA1075373A CA 1075373 A CA1075373 A CA 1075373A CA 251094 A CA251094 A CA 251094A CA 1075373 A CA1075373 A CA 1075373A
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CA
Canada
Prior art keywords
layer
emitter
oxygen
base
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA251,094A
Other languages
French (fr)
Inventor
Takeshi Matsushita
Hisao Hayashi
Mitsuru Shibasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
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Publication of CA1075373A publication Critical patent/CA1075373A/en
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Abstract

ABSTRACT OF THE DISCLOSURE

A semiconductor device comprising a silicon substrate with an oxygen doped polycrystalline or amorphous silicon layer formed on the substrate so as to form a hetero junction therewith. A transistor formed according to the invention has an emitter-base hetero junction and has a high current gain.

Description

~ 75373 B~CI~GROUNL) OF THE INVENTION
Field of the Invention:
This invention relates in general to a semiconductor device and especially tO a transistor having a hetero junction.

Description of the Prior Art Transistors having a wide gap emitter are known in which the band gap energy width of the emitter is larger than that of the base and there is a hetero junction between an emitter-base junction.
In such transistors the minority carrier current in the emitter can be sufficiently small even if the impurity concentration in the-base is greater than 1019 atoms/cm3 order of magnitude because of the band gap difference at the emitter-base junction. This results in the emitter junction efficiency ~, approaching unity and the current gain (emitter-grounded) hFE is large.
~ Iaterials for forming a hetero junction must be such that the differences of lattice constant and the thermal e~pansion coefficient are very small. The combinations of Ga As-Ge or Ga Al As - GaAs are known.

SUMMARY O~ THE INVENTION
The object of the present invention is to provide an improved hetero junction by employing polycrystalline or amorphous silicon con-taining oxygen.
The inventors have discovered that the band gap width of silicon increases and approaches that of silicon dioxide as the oxygen con-centration increases. Such discovery was made by optically observing.
A high grade hetero junction is formed between silicon and oxygen doped ~ .
-2--.

~7~i3~3 polycrystal]ine or amorphous silicon in the present inYentiOn.
In one aspect of this inYentiOn there is provided a semiconductor ~evice ~hich comprises a ~irst silicon layer and an oxygen doped pol~cr~stalline or amorphous second silicon layer on the first layer and forming a hetero junction with the first layer.
In another aspect of this invention there is provided a semiconductor device which comprises a substrate of a first conductivity type; and a first region of a second conductivity type formed in the substrate on a major surface thereof. The device is further provided with a fi~st poly-crystalline or amorphous silicon layer containing oxygen and of the first conductivity type formed on selected regions of the first region. The device also comprises electrodes formed on the first region and the first polycrystalline or amorphous silicon layer containing oxygen.
In a further aspect of this invention there is provided a semiconductor device comprising a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is provided on said substrate. A first poly-crystalline or amorphous silicon layer containing boron and oxygen is formed on the epitaxial layer with the oxygen doping increasing toward the surface within the range of 0 to 50 atomic percent. A second polycrystalline or amorphous silicon layer containing phosphor and uniformly doped oxygen is also formed on the first polycrystalline layer. The substrate is forming a collector, the first polycrystalline layer is forming a base, and the second polycrystalline layer is forming an emitter.
In a still further aspect of this invention there is pro~ided a semiconductor device comprising a substrate of a first conductivity type. A channel region of a second conduc-tivity is formed in the substrate. A channel region of a second ~ _ 3 _ ~ 7~3~3 eonduetiyitx type is form.ed in the substrate. A ~ate region of the first conductivity type o~gen doped polycrystalline or am~ ous silicon i5 also formed on the channel region.
A gate electrode is connected to the gate region, and source and drain electrodes are connected to the cKannel region with the gate electrode located intermediate the source and drain eleetrodes.
Other objects, features and advantages of the invengion will :-be readily apparent from the following description of certain preferred embodiments thereof taken in conjunction with accompanying drawings :~
although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure, and :

in which : ' .:
BRIEF DESCRlPrION OF THE DRAWINGS
Figure 1 is a sectional view illustrating a first embodiment of the invention;
Figure 2 is a top plan view illustrating the invention;
Figures 3A to 3D are sectional views illustrating the method of constructing the invention;
Figure 4 is a plot of oxygen concentralion In silicon versus the band gap energy characteristic;
Figure 5 illustrates an apparatus for manufacturing devices .
according to the invention;
Figure 6 illustrates the band gap characteristic of a second embodiment of the invention;
Figures 7A to 7D illustrate the method of constructing a second embodiment of the invention;
3 a -)~\ .
`
', '. ~ ,:

~5i3~;3 Figure 8 is a plot of oxygen concentration in silicon versus the resistivity characteristic;
~igure 9 illustra~es a third embodiment of the invention; and Figure 10 illustrates the band gap energy distribution for an embodimenl.

- 3b -3~73 DESCRIPTION OF l t-IE PREFERRED EMBODIMENTS
.
Figures 1, 2 and Figures 3~ through 3D illustrate a first embodiment of the invention applied to a transistor having a wide gap emitter.
A p+ base region 2 is formed by diffusion with an impurity concentration rnore than 1019 atoms/cm3 in an N type silicon substrate 1 to form a collector 6. ~ polycrystalline or amorphous silicon layer 3 contallling oxygen and N impurity is deposited on the region 2. On top of layer 3 is deposited the polycrystalline or amorphous silicon layer 4 without oxygen but containing N+ type impurity. Emitter and base electrodes 9e and 9b are deposited on the silicon layer 3 and a P++
type base region 7. If the electrode 9e is made of aluminum, the layer
4 is required. However, if Cr-~u alloy is used as the electrode 9e, the layer 4 can be eliminated because this alloy can make good contact to the layer 3.
The silicon layer 3 is the emitter and there is a hetero junction J between the base 2 and the emitter 3. ~ silicon dioxide layer 10 covers the substrate 1. The emitter and base electrodes 9e and 9b are comb-shaped as illustrated in the plan view of Figure 2.
Figures 3A through 3D illustrate a method of manufacturing the transistor shown in Figures 1 and 2. The base 2 is formed in the N- collector 6 and has P+ type impurity of concentration of 1019 to 102/
cm3 order. The P~ type region 7 illustrated in Figure 1 can be diffused before the diffusion of the region 2 and serves as the base region.
The layer 3 contains oxygen and phosphor of 102 atoms/cm3 O O
order. It has a thickness in the range of 1000 ~o 10,000 A, as for O O
example, 5000 ~. The layer a~ has a thickness of 5000 ~, as illustrated in Figure 3C.
The oxygen doping in the silicon layer 3 is such that the band gap thereof is larger than that of the silicon 2 by more than 0.2eV.
The oxygen concentration is desirably more than 15 atomic percent.
Figure 4 illustrates the oxygen concentration in the silicon versus its band gap. The band gap approaches that of silicon dioxide as the oxygen concentration increases.
The oxygen doped silicon layer 3 has an average silicon O O O
grain size of 50 A to 1000 A. If it is less than 50 A, its characteristic approaches that of silicon dioxide, and it will have a memory effect. It also requires a low reaction temperature and low growth rate which is not productive. If it is more than lO00 A, the leakage current increases.
Figure 5 illustrates a chemical vapor deposition system for obtaining oxygen doped silicon. A reactor 11 is connected to a carrier source N2, 12, through a valve 16 and to a silicon source SiH4, 13, through a valve 17. The reactor 11 is also connected to an oxygen source (N2O,NO or NO2) through a valve 18 and an impurity source (PH3, AsH3, B2H6-~CO2 or AICl3) 15 through a valve 19~ The substrate 1 is placed illtO the reactor 11 and is heated to the range between 600 to 750C, for example, 650. Monosilane SiH4 is used as the silicon source because it produces a desirable silicon grain si~e at a relatively low temperature as for example, 650~C. If SiC14 is used, a reaction temperature such as 900C is required which results in the grain size being too large and too fast a growth rate which is very difficult to control.
The oxygen concentration is controlled by controlling the flow rate of N2O to SiH4. Ihe following table shows this relationship. The silicon layers 3 and 4 are continuously formed.

~75373 N 2/ Oxygen /~1 Concentration / 4 Atomic 7~ EgleV) - 52-- 15 l 3 22 1. 4 1.5 250o 36 1. 6 250 44 1. 7 35 46 1. 75 450 47. 5 1. 77 1. 9 2000 _ SiO~ 8. 0 . .. . _ The transistor of the invention has high impurity concel$ra-tion and low sheet resistance such as ().15~ in the base, ~ ich results in high current gain ancl high cut off frequency such as 1 GHz. The difference in ~hermal expansion coefficients of the clifferent layers is negligible.
Flgures 6 and 7A through 7D illustrate a second embodi-ment of the invention as applied to a drift base transistor having a high frequency characteristic. A drift base transistor' having a base in which a,drift field for minority carriers is caused by the gradient of impurity concentration is known. In this embodiment the drift field (potential) is caused by the gradient of the band gap which is wider at the emitter side as shown in Figure 6. In Figure 6, the first portion of the curve to the left represents the band gap of an NPN ~' transistor emitter, and it is noted that this portion of the band gap .
~ , . . .

~7~ii3~3 is flat. The next or center por~ion of the curve illustrates the band gap in the base and it is to be noted that the gradient of the band gap is wider adjacent the emitter than it is adjacent the right side which joins the collector. Thus in the base of the transistor illustrated in Figure 6 electrons will tend to go down and holes will tend to go up.
The more oxygen, the wider the band gap.
Figures 7A through 7D illustrate the method for constructing the second embodiment. A silicon substrate 23 has an N-~ type body portion 21 and an N type epitaxial layer 22. ~ polycrystalline or amorphous silicon layer 24 is formed on the epitaxial layer 22. The layer 24 contains boron or oxygen and is formed by chemical vapor deposition. The oxygen doping increases toward the surface within the range from O to 50 atomic percent. The boron doping increases toward the surface also so as to compensate the decreasing of its activation under the existence of oxygen. ~ polycrystalline or amorphous silicon layer 25 containing phosphor and uniformly doped oxygen is deposi~ed on the layer 24 continuously as shown in Figure 7~. The layer 24 will be a base and the layer 25 will be the emitter.
The layers 24 and 25 are selectively etched by applying wax over the portion remaining in F igure 7B to leave an emitter -base junction Je as shown in Figure 7B.
The layer 24 and the substrate 22 are selectively etched by using wax 26 to leave a collector-base junction Jc as shown in Figure 7C. This transistor is a mesa type transistor.
A passivating layer 27 is deposited as shown in Figure 7D.
The layer 27 comprises a polycrystalline or amorphous silicon layer 28 containing oxygen and a polycrystalline or amorphous silicon containing 3L~75i373 nitrogen or silicon dioxide layer 29 which is formed over the layer Emitter and base electrodes 32 and 33 are deposited as shown in Figure 7D on the emitter and base, respectively. These layers are continuously formed by chemical vapor deposi~ion by using the apparatus shown in Figure 5. A nitrogen source (NH3) 31 is supplied to the reactor through the valve 30 when the layer 29 is nitrogen doped polycrystalline or amorphous silicon.
The layer 28 contains oxygen in the ~range of 2 to 45 atomic percent, and preferably in the range of 14 to 35 atomic percent.
The main silicon grain size if 50 to 1000 A.
Figure 8 illustrates the oxygen doping versus the resistivity of the layer 28. The main grain size is 200 to 300 A. As described in U.S. Patent 4,014,037 issued March 22, 1977 to Matsushita et al, which patent has been assigned to the same assignee as the present invention, the layer 28 has a good passivating property. If the layer 29 is nitrogen doped polycrystalline or an amorphous layer it will contain nitrogen of more than 10 atomic percent. Such polycrystalline or amor-phous layer has a water-protecting property.

Figure 9 illustrates a third embodiment of the invention applied to a junction type field effect transistor in which a gate -junction is a hetero junction. Three N type island regions 42A, 42B
and 42C are formed on a P type silicon substrate 41. A P type ehannel region 43 is formed in the island region 42B. A gate 44 of N type and oxygen doped amorphous or polycrystalline silio~n is 17~i373 deposited on the channel region ~3 to form a gate junction a~6. Gate, source, drain and lower gate electrodes ~15, 47, 48 and 49 are deposited as shown. This :Eield effect transistor 50 has a high input impeda nce.
There is a wide gap emitter transistor 51 having an emitter hetero junction J formed in the island 42~. There is a lateral transistor 54 having an emitter 52 and a collector 53 in the island 42C.
Figure 10 illustrates the band gap structure for a fourth embodiment of the invention applied to a bipolar transistor having an emitter of oxygen doped polycrystalline or amorphous silicon. The oxygen concentration in the emitter increases toward the surface (opposite of the base) by a method described in the second embodiment so that the band gap energy in the emitter increases toward the surface as shown in the Figure 10 band gap struc~ure. It should be realized that the emitter is illustrated in the left portion of the curve in Figure 10, and it is noted that the emitter curve slants generally upwardly toward the right. This provides a potential or a field to force back minority carriers injected from the base in~o the emitter and thus the transistor has a high emitter efficiency or a high current gain hFE, In the embodiment of Figure 10, the only difference between it and the embodiment illustrated in Figure 6 is that the oxygen doped polycrystalline concentration is in the emitter rather than the base and this inhibits holes from going to the emitter and the gradient emitter resists hole injection from the base.
The invention can also be applied to a transistor which has a collector of polycrystalline or amorphous silicon to form a hetero collector-base junction and in such embodiment the third portion 1~75373 of the curve in Figures 10 and 6 would be slanted since this third portion represents the cvllector band gap structure.
Altllough this invention has been described witll respect to preferred embodiments, it is not to be so limited as changes and modifications can be made which are within the full intended scope, as defined by the appended claims.

Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A semiconductor device comprising:
a first silicon layer;
an oxygen doped polycrystalline or amorphous second silicon layer on said first layer and forming a hetero junction with said first layer.
2. A semiconductor device according to claim 1, in which the oxygen concentration in said second layer is substantially uniform.
3. A semiconductor device according to claim 1, in which the oxygen concentration in said second layer is gradually varied as a function of thickness.
CA251,094A 1975-04-30 1976-04-27 Semiconductor device having a hetero junction Expired CA1075373A (en)

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NL7604558A (en) 1976-11-02
NL187461B (en) 1991-05-01
DE2618733C2 (en) 1987-03-26
DE2618733A1 (en) 1976-11-11
FR2309981B3 (en) 1980-07-18
US4062034A (en) 1977-12-06
JPS5637702B2 (en) 1981-09-02
NL187461C (en) 1991-10-01
JPS51128268A (en) 1976-11-09
GB1542651A (en) 1979-03-21

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