CA1074919A - Error checking and correcting device - Google Patents
Error checking and correcting deviceInfo
- Publication number
- CA1074919A CA1074919A CA276,907A CA276907A CA1074919A CA 1074919 A CA1074919 A CA 1074919A CA 276907 A CA276907 A CA 276907A CA 1074919 A CA1074919 A CA 1074919A
- Authority
- CA
- Canada
- Prior art keywords
- error
- bits
- code word
- output
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
Abstract
ERROR CHECKING AND CORRECTING DEVICE
Abstract of the Disclosure An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel.
In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection.
the check bits are appended to the data bits to form a 40 bit code word which is transmitted through the modular memory. At the receiver, a syndrome bit generator generates 8 syndrome bits from the received code word in accordance with the H-matrix. The output of the syndrome bit generator is coupled to both the error detection circuit and the error location circuit. Should a group in the memory be faulty in the process of transmission resulting in a number of bits in the group being in error, logic means are provided in the error detection circuit to identify correctable good data from uncorrectable bad data. According to the syndrome pattern the error detection circuit permits the utilization of re-ceived data if no error is detected, or enables the error location circuit to provide single error correction if a single error is de-tected; or sets an error flag to prohibit the utilization of receive?
Abstract of the Disclosure An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel.
In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection.
the check bits are appended to the data bits to form a 40 bit code word which is transmitted through the modular memory. At the receiver, a syndrome bit generator generates 8 syndrome bits from the received code word in accordance with the H-matrix. The output of the syndrome bit generator is coupled to both the error detection circuit and the error location circuit. Should a group in the memory be faulty in the process of transmission resulting in a number of bits in the group being in error, logic means are provided in the error detection circuit to identify correctable good data from uncorrectable bad data. According to the syndrome pattern the error detection circuit permits the utilization of re-ceived data if no error is detected, or enables the error location circuit to provide single error correction if a single error is de-tected; or sets an error flag to prohibit the utilization of receive?
Description
,l 35-105 107~ 9 1 Background of the Invention
2 The present invention relates to an error checking and
3 correcting device and more particularly to a modular data processinc ,
4 system for providing single error correction, double error detectior
5 and group error detection.
6 In data processing systems, it is necessary to transmit
7 data between two points. Often there is noise in the communication
8 channel through which the data is transmitted and as a result, the
9 informational content of the data is distorted.
In order to check the data word transmitted for accuracy, 11 various error detecting and correcting devices and techniques have 12 been developed which typically require some redundancy. These prio~
13 art techniques typically require the addition of check bits to the I
14 data word to form a code word with the entire code word being trans-¦
15 mitted whenever the data portion of the code word is utilized. The 16 heck bits are typically generated according to some predetermined 17 lgorithm and the received code word is processed according to some 18 redetermined algorithm to determine whether the data has been ac-19 urately transmitted.
Various single error correction, double error detection21 (SEC-DED) codes have been developed, such as the Hamming code ~2 (Reissue Pat. No. 23,601 to Richard Hamming et al) and Hsiao's 23 inimum-odd-weight-column code (U.S. Patent 3,623,155 to M. Y. Hsiad 24 hese SEC-DED codes assume errors within a code word occùr randomly ¦
nd independently so that the probability of failure of every bit in 26 he same code word is equal and independent of each other. The pre-27 erred environment for a random SEC-DED code is a communication 28 hannel in which each bit of a code word is discrete and homogeneous 29 n example of a discrete and homogeneous communication channel is a torage system with bit per card or bit per package arrangements.
31 From a packaging point of view, it is inefficient to partit 32 ion the communication channel into discrete bit portions. It has ~ _ 3 _ 107~19 1I t refore beco=e nece~ary to partition the commuDic~tion channel 2 into modular groups, with a plurality of bits forming a group and 3 a plurality oE groups forming a code word. An example of a modular 41 channel is a memory organized with multiple blts per card of multi-5~ ple bits per package arrangements.
61 For a code word transmitted through a modular memory 71 system~ the malfunction of a module can affect m~ny bits within the 81 group. Depending upon the original information transmitted and the 9¦ failure mode of the group, errors can be reflected in the receiver lO¦ as a single bit failure, double bit failure, or a plurality of bit ll¦ failures all in the same group.
13 ¦Summary of the Invention l~ 1 The present invention is directed to a system for pro-15 ¦viding single error correction, double error detection and group 16 ¦error detection in a code word having plural groups of lnformation 17 and check bits. The system is comprised of a generator for receiv l8¦ ing the code word and for generating a plurality of syndrome bits.
l9¦ A first circuit coupled to the output of the generator generates a 20¦ first error signal if the informational content of the syndrome 2l¦ bits indicate the detection of any error in the transmission of the 22¦ code word. A second circuit coupled to the output of the generato 231 generates a second error signal if the informational content of 241 the syndrome bits indicates a detection of two random errors in 251 the code word or an even number of errors in one of the plural 26¦ groups. A third circuit coupled to the output of the generator 271 generates a third error signal if the informational content of the 28 syndrome bits indicates the detection of an odd number of errors 29 greater than one in one of the plural groups. An error location circuit operatively coupled to the generator and the first, second 31 and third circuits provides an error correction in response to the 32 detection of a single error in the code word. More specifically, _ 4 _ 107'~ 9 l1 in the present lnvention the code word comprises a plurality 21 of data bits and a plurality of check blts arranged in groups 3~ to be transmitted in parallel through a modular communication 4~ channel. In the preferred embodiment, the code word contains 5 140 bits with 32 data bits and 8 check bits, and the modular 6 ¦communication channel is a computer memory comprising lO
7 ¦modules with 4 bits per module.
8 ¦ At the transmitter, a data register provides the 9 data bits and a check bit generator provides check bits in ac-~0 cordance with an H-matrix which is partitioned into h-sub-ll matrices as set forth in Table I below. The construction of 12 the h-submatrices is in accordance with rules necessary for 13 group error detection in addition to single error correctlon 14 and double error detection.
At the receiver, a syndrome bit generator generates 16 syndrome bits from the received code word in accordance with 17 the H-matrix shown in Table I. The syndrome bits are applied e~ t n error _ e~ /
2~ /
32 / . _ 4a -. .~, ,' . .
107~919 ~ J~ K~ CE.~
~o~ I
/ o ,~
~ ~ xx~ J~ ~
7 ~_ X X X' ~
~ ) ~ x xx 1' 5: ~ ~ U
c~ X X X ) cq~ ~
__ .
C'~ ~ X X ~
~C~ X X J ~ ~ X ~
O X ~ ~q bq-' .
¢ ~ ~a ~ X ~C } 'O h ~
tD ~q X X ~ O
O ~~ X X ~ X~
U ~C~O ;~ X X X
t;i _ C~ X X X J U~
I ~ }
~ U') ~ } Ul ~ .
~T5~ a~uo~pu~Ss - 4b -107 1~19 1l de~tection circuit which ~lrovides a first error flag signal if any 2¦ error is detected. A second error flag siynal is provided if 3 ¦ there is a randon\ double error detection (DED) or a group error 4 detection (GED).
The syndrome bits are also applied to an error lo-6¦ cation circuit and the error detection circuit is also coupled 7 to the error location circuit to provide single error correction 8 (SEC) if a single error is detected.
9¦ The data bits are applied to a data register which is ordinarily enabled to utilize the data it receives. The error 11 location circuit is also applied to the data register. If no 12 error is detected the data register remains enabled to utilize 13 the data it receives. If a single error is detected, the error 14 detection circuit enables the error location circuit to change the polarity of the binary bit in the location of the incorrect 16 bit in the data register in which the single error is detected 17 ¦to thereby provide a single error correction (SEC) function.
18 If the error detection circuit detects two random 19 errors in any locations in the code word, or if the error detec-tion circuit detects a plurality of errors in the same group of 21 data, the error detection circuit provides a second flag to 22 signal the user that there has been a double error detection 23 (DED) or group error detection (GED). The user may thereby dis-24 regard all cf the data in the register.
1¦ The apparatus and method of the present invention is 21 applieable to codes with any data word size transmitted through 31 a modular communication channel of any modular group size as 4¦ long as sufficient check bits are included in the code word to 5l satisfy the H-matrix of the present invention shown in Table I.
6~ However, a code word of 40 bits with 32 bits and 8 eheek bits 71 transmitted through a modular memory ehannel with eaeh module of 8 ¦the memory handling 4 bits in parallel has been ehosen for il-9¦ lustrative purposes. This 40-bit SEC-DED-GED eode is particu-
In order to check the data word transmitted for accuracy, 11 various error detecting and correcting devices and techniques have 12 been developed which typically require some redundancy. These prio~
13 art techniques typically require the addition of check bits to the I
14 data word to form a code word with the entire code word being trans-¦
15 mitted whenever the data portion of the code word is utilized. The 16 heck bits are typically generated according to some predetermined 17 lgorithm and the received code word is processed according to some 18 redetermined algorithm to determine whether the data has been ac-19 urately transmitted.
Various single error correction, double error detection21 (SEC-DED) codes have been developed, such as the Hamming code ~2 (Reissue Pat. No. 23,601 to Richard Hamming et al) and Hsiao's 23 inimum-odd-weight-column code (U.S. Patent 3,623,155 to M. Y. Hsiad 24 hese SEC-DED codes assume errors within a code word occùr randomly ¦
nd independently so that the probability of failure of every bit in 26 he same code word is equal and independent of each other. The pre-27 erred environment for a random SEC-DED code is a communication 28 hannel in which each bit of a code word is discrete and homogeneous 29 n example of a discrete and homogeneous communication channel is a torage system with bit per card or bit per package arrangements.
31 From a packaging point of view, it is inefficient to partit 32 ion the communication channel into discrete bit portions. It has ~ _ 3 _ 107~19 1I t refore beco=e nece~ary to partition the commuDic~tion channel 2 into modular groups, with a plurality of bits forming a group and 3 a plurality oE groups forming a code word. An example of a modular 41 channel is a memory organized with multiple blts per card of multi-5~ ple bits per package arrangements.
61 For a code word transmitted through a modular memory 71 system~ the malfunction of a module can affect m~ny bits within the 81 group. Depending upon the original information transmitted and the 9¦ failure mode of the group, errors can be reflected in the receiver lO¦ as a single bit failure, double bit failure, or a plurality of bit ll¦ failures all in the same group.
13 ¦Summary of the Invention l~ 1 The present invention is directed to a system for pro-15 ¦viding single error correction, double error detection and group 16 ¦error detection in a code word having plural groups of lnformation 17 and check bits. The system is comprised of a generator for receiv l8¦ ing the code word and for generating a plurality of syndrome bits.
l9¦ A first circuit coupled to the output of the generator generates a 20¦ first error signal if the informational content of the syndrome 2l¦ bits indicate the detection of any error in the transmission of the 22¦ code word. A second circuit coupled to the output of the generato 231 generates a second error signal if the informational content of 241 the syndrome bits indicates a detection of two random errors in 251 the code word or an even number of errors in one of the plural 26¦ groups. A third circuit coupled to the output of the generator 271 generates a third error signal if the informational content of the 28 syndrome bits indicates the detection of an odd number of errors 29 greater than one in one of the plural groups. An error location circuit operatively coupled to the generator and the first, second 31 and third circuits provides an error correction in response to the 32 detection of a single error in the code word. More specifically, _ 4 _ 107'~ 9 l1 in the present lnvention the code word comprises a plurality 21 of data bits and a plurality of check blts arranged in groups 3~ to be transmitted in parallel through a modular communication 4~ channel. In the preferred embodiment, the code word contains 5 140 bits with 32 data bits and 8 check bits, and the modular 6 ¦communication channel is a computer memory comprising lO
7 ¦modules with 4 bits per module.
8 ¦ At the transmitter, a data register provides the 9 data bits and a check bit generator provides check bits in ac-~0 cordance with an H-matrix which is partitioned into h-sub-ll matrices as set forth in Table I below. The construction of 12 the h-submatrices is in accordance with rules necessary for 13 group error detection in addition to single error correctlon 14 and double error detection.
At the receiver, a syndrome bit generator generates 16 syndrome bits from the received code word in accordance with 17 the H-matrix shown in Table I. The syndrome bits are applied e~ t n error _ e~ /
2~ /
32 / . _ 4a -. .~, ,' . .
107~919 ~ J~ K~ CE.~
~o~ I
/ o ,~
~ ~ xx~ J~ ~
7 ~_ X X X' ~
~ ) ~ x xx 1' 5: ~ ~ U
c~ X X X ) cq~ ~
__ .
C'~ ~ X X ~
~C~ X X J ~ ~ X ~
O X ~ ~q bq-' .
¢ ~ ~a ~ X ~C } 'O h ~
tD ~q X X ~ O
O ~~ X X ~ X~
U ~C~O ;~ X X X
t;i _ C~ X X X J U~
I ~ }
~ U') ~ } Ul ~ .
~T5~ a~uo~pu~Ss - 4b -107 1~19 1l de~tection circuit which ~lrovides a first error flag signal if any 2¦ error is detected. A second error flag siynal is provided if 3 ¦ there is a randon\ double error detection (DED) or a group error 4 detection (GED).
The syndrome bits are also applied to an error lo-6¦ cation circuit and the error detection circuit is also coupled 7 to the error location circuit to provide single error correction 8 (SEC) if a single error is detected.
9¦ The data bits are applied to a data register which is ordinarily enabled to utilize the data it receives. The error 11 location circuit is also applied to the data register. If no 12 error is detected the data register remains enabled to utilize 13 the data it receives. If a single error is detected, the error 14 detection circuit enables the error location circuit to change the polarity of the binary bit in the location of the incorrect 16 bit in the data register in which the single error is detected 17 ¦to thereby provide a single error correction (SEC) function.
18 If the error detection circuit detects two random 19 errors in any locations in the code word, or if the error detec-tion circuit detects a plurality of errors in the same group of 21 data, the error detection circuit provides a second flag to 22 signal the user that there has been a double error detection 23 (DED) or group error detection (GED). The user may thereby dis-24 regard all cf the data in the register.
1¦ The apparatus and method of the present invention is 21 applieable to codes with any data word size transmitted through 31 a modular communication channel of any modular group size as 4¦ long as sufficient check bits are included in the code word to 5l satisfy the H-matrix of the present invention shown in Table I.
6~ However, a code word of 40 bits with 32 bits and 8 eheek bits 71 transmitted through a modular memory ehannel with eaeh module of 8 ¦the memory handling 4 bits in parallel has been ehosen for il-9¦ lustrative purposes. This 40-bit SEC-DED-GED eode is particu-
10 ¦larly applieable to a 32-bit word computer main memory with 4
11 ¦bits per card organization or to a 32~bit word computer main
12 ¦memory using lk x 4 RAM or 4k x 4 R~l as storage devices and
13 ¦using quad bus drivers and quad receivers as storage buffers.
14 ¦ Accordingly, a primary object of the present invention
15 ¦is to provide an error cheeking and eorrecting device for data
16 transmitted through a modular memory channel. To aceomplish this
17 it is neeessary to identify the kinds of error that would appear
18 in the received code word of a modular memory in which one module
19 is faulty. Consider, for example, that group Go of the modular
20 memory, shown in the H-matrix of Table I, is erroneous so that
21 data bits (Bo Bl B2 B3) transmitted to the receiver are always
22 stuek at logie state '0'. Assuming all other modular groups are
23 functioning properly, Table II shows the number of errors in the
24 received eode word for various input eombinations of group Go at the transmitter.
ln7~tsl9 ~ .
2GO INPUT (Bo Bl B2 B3)NO. OF BIT
FAILURES DIAGNOSIS
_ ., 4 0000 0000 0 no error 0001 0000 1 correctable error 5¦ 0010 0000 1 correctable error 0100 0000 1 correctable error 6 1000 0000 1 correctable error 0011 0000 2 uncorrectable error 7 0110 0000 2 uncorrectable error 0101 0000 2 uncorrectable error 8 1100 0000 2 uncorrectable error l 1010 0000 2 uncorrectable error 9 l 1001 0000 2 uncorrectable error 0111 0000 3 uncorrectable error 10 l 1011 0000 3 uncorrectable error l 1101 0000 3 uncorrectable error 11l 1110 0000 3 uncorrectable error l 1111 0000 uncorrectable error 12 l 13 ¦ No. of bit failures in a group 14 l , 5 l ~:~
16 ¦ It can be appreciated that depending upon the original 17 ¦information transmitted and the failure mode of the module, no 18 ¦error, single bit error, or a plurality of bit errors all in the 19 ¦same group can appear in the code word. This invention provides 20 ¦an error checking device capable of differentiating between 21 ¦usable information and unusable information. It is therefore a-22 ¦nother object of the present invention to construct a single 23 ¦ error correction, random double error detection, and group error 24 ¦detection (SEC-DED-GED) code. The structure of the code is pre-
ln7~tsl9 ~ .
2GO INPUT (Bo Bl B2 B3)NO. OF BIT
FAILURES DIAGNOSIS
_ ., 4 0000 0000 0 no error 0001 0000 1 correctable error 5¦ 0010 0000 1 correctable error 0100 0000 1 correctable error 6 1000 0000 1 correctable error 0011 0000 2 uncorrectable error 7 0110 0000 2 uncorrectable error 0101 0000 2 uncorrectable error 8 1100 0000 2 uncorrectable error l 1010 0000 2 uncorrectable error 9 l 1001 0000 2 uncorrectable error 0111 0000 3 uncorrectable error 10 l 1011 0000 3 uncorrectable error l 1101 0000 3 uncorrectable error 11l 1110 0000 3 uncorrectable error l 1111 0000 uncorrectable error 12 l 13 ¦ No. of bit failures in a group 14 l , 5 l ~:~
16 ¦ It can be appreciated that depending upon the original 17 ¦information transmitted and the failure mode of the module, no 18 ¦error, single bit error, or a plurality of bit errors all in the 19 ¦same group can appear in the code word. This invention provides 20 ¦an error checking device capable of differentiating between 21 ¦usable information and unusable information. It is therefore a-22 ¦nother object of the present invention to construct a single 23 ¦ error correction, random double error detection, and group error 24 ¦detection (SEC-DED-GED) code. The structure of the code is pre-
25 ¦ sented through the H-matrix shown in Table I.
26 ¦ Referring to Table I, the H-matrix is partitioned into
27 ¦lower case h-submatrices corresponding to the group boundaries of
28 ¦the modular memory. The assignment of entries of x in the h-sub-291 matrices is important. For the purpose of group error detection, 301 the following rules are necessary:
~11 1. Each column in the H-matrix is distinct.
321 2. The h-submatrices corresponding to data bit groups (Go to G7) j 35-105 ~07~9~9 1' have three entries per column only.
2l 3. The h-submatrices corresponding to check bit groups (G8 and G9) ¦
3~ have one entry per column only.
4 4. In each h-submatrix corresponding to data bit groups, i.e. Go through G7, there is one common row of entries in the first 6 four rows and there is another common row of entries in the 7 last four rows.
8 A code with an ~-matrix satisfying the above constraints 9 has an overall minimum distance of four, and is therefo~e capable 10 of correcting a single error and detecting a random double error 11 in addition to detecting group errors. The above constraints ensure 12 that, in the diagnosis of received data, non-overlapping syndrome 13 subse~s are generated to separate usable data from unusable data.
14 At the receiver, the diagnosis is in accordance with the following 15 algorithm:
16 1. If all syndrome bits are false, there is no error.
17 2. If one syndrome bit is true, a single correctable error in a 18 check bit group is present.
19 3. If an even number of syndrome bits are true, uncorrectable error are present. The uncorrectable errors can be either random 21 double errors or a double error in a group or quadruple error in 22 a group.
23 4. If three syndrome bits are true and all of them are located in 24 either So Sl S2 S3 or S4 Ss S6 S7, uncorrectable triple errors in the check bit group are present.
26 5. If three syndrome bits are true and not all of them are located 27 in either So Sl S2 S3 or S4 S5 S6 S7, a single correctable error 28 in the data bit group is present.
~11 1. Each column in the H-matrix is distinct.
321 2. The h-submatrices corresponding to data bit groups (Go to G7) j 35-105 ~07~9~9 1' have three entries per column only.
2l 3. The h-submatrices corresponding to check bit groups (G8 and G9) ¦
3~ have one entry per column only.
4 4. In each h-submatrix corresponding to data bit groups, i.e. Go through G7, there is one common row of entries in the first 6 four rows and there is another common row of entries in the 7 last four rows.
8 A code with an ~-matrix satisfying the above constraints 9 has an overall minimum distance of four, and is therefo~e capable 10 of correcting a single error and detecting a random double error 11 in addition to detecting group errors. The above constraints ensure 12 that, in the diagnosis of received data, non-overlapping syndrome 13 subse~s are generated to separate usable data from unusable data.
14 At the receiver, the diagnosis is in accordance with the following 15 algorithm:
16 1. If all syndrome bits are false, there is no error.
17 2. If one syndrome bit is true, a single correctable error in a 18 check bit group is present.
19 3. If an even number of syndrome bits are true, uncorrectable error are present. The uncorrectable errors can be either random 21 double errors or a double error in a group or quadruple error in 22 a group.
23 4. If three syndrome bits are true and all of them are located in 24 either So Sl S2 S3 or S4 Ss S6 S7, uncorrectable triple errors in the check bit group are present.
26 5. If three syndrome bits are true and not all of them are located 27 in either So Sl S2 S3 or S4 S5 S6 S7, a single correctable error 28 in the data bit group is present.
29 6. If five syndrome bits are true, an uncorrectable triple error in the data bit group is present.
31 The check bits (C0 to C7) are determined by the odd parity 32 f those data bits which have an entry of 'x' in the associated row i 35-105 , 107~919 1l of the l~-matrix and are g~nerated by EXCLUSIVE OR circuitry. For 2 example, check bit Co is the odd parity of data bits Bo, Bl, B2, B
3 B4~ B5, B6~ B7~ B12~ ~16~ B20, and B24 (The odd parity is the 4 binary sum bit). It is thus seen that the 8 check bits (C0 to C7) 5 are obtained in accordance with the logic equations set forth in 6 Table III, wherein the sign ~ means EXCLUSIVE OR.
9 . , , 1 .
Co ~ bo (~)bl (~) b2 ~) b3 ~3 bl~ ~ b5 ~) b6~3 b7 ~3 bl2 t~3 b~ b~o (~3 b24 C~. ~ bo ~E) b4 6~ b~ 9 (~3 blo (3 b ~ ~) bl2 G~) bl3 (3 bl4 G~ bls (~) b21 (~3 b2~
2 n bl~b~bl6(3bl7~bl~)bl9(~b2o~)b21~3b22(~)b23~)b25~'29 C3 ~ b2(~)bs ~)bg ~)bl3 (3 b24 C3 b25 ~3 b2G~3b~7 Q b2a ~)b29 ~)b30C~)b31 Cl, ~ b4 ~ bs~bGC~ b~ ~ blo ~ bl4 ~ bl7 ~ b20 ~ b21 ~ b22 ~ b23 ~ b26 C5 ~ b3 ~ b6 ~ bll ~ bls ~ blG ~ bl7 ~ b~ l9 ~ b28 ~ b29 ~ b3o ~ b3 CG ~ bo~ bl~b2~ b3~ b~bg~ ~bl~b22~27Qb3 C~ ~ b ~ bl2 ~ bl3 (~ 14 ~ ~15 ~ blg ~ b23 ~ ~24 ~ ~25 ~ b2G ~ b27 I .
As indicated above, the code word during transmission is 21 subject to the introduction of errors. The syndrome bits (S0 to S7) 22 are generated in the syndrome bit generator at the receiver from 23 the received code word by referring to the H-matrix shown in 24 Table I in a similar manner. Syndrome bits (S0 through S7) are 25 determined by the odd parity of those data bits and check bits 26 which have an entry of 'x' in the associated row of the H-matrix.
27 The logic equations for generating the syndrome bits from the re-28 ceived code word is shown in Table IV, wherein again the sign 29 eans EXCLU VE OR.
g _ .a7'~919 2 O O (3 1~) 2 ~ 3 ~) b4 (3 b5 ~) b6 (~) b7 ~) bl2(3 bl6 ~) b20 (~) 3 b 2 4 ~ C o 4 S = bo (3 b4 ~) b8 ~) bg ~) blo ~) bll (~3 bl2 (~) ] 3 (3 14 ~) 15 5 ~ b21 (~3 b28 ~) Cl 6 ~ 2 1~) 8 (~) 16 (~3 bl7 (~3 bl8 (~)blg (~)b20 (~) b21 (~) b ~) b ~) q ¦ b25 (~) b29 (~3 C2 81 S = b2 ~) b5 (~ bg ~ bl3 (~) b24 (~) b25 (~) b26 (~) b27 (~) 28 (~) 29 (~) 9 ¦ b30 (~) b31 ~) C3 10 ¦ S = b (~)b (~b6~)b7(~3blo~)bl4~)bl7Qb2oQ 21(~) 22~) 11 ¦ b23(~)b2.6 0 C4 12 S = b ~ b ~ bll ~ bls ~ bl6 ~ b17 ~ bl8 Q 19 ~ 28 ~ 29 13 ¦ b30 ~ b31 ~ C5 14¦ S6 = bo ~ bl ~ b2 ~ b3 ~ b8 ~ bg ~ blo ~ bll Q bl8 ~ 22 15¦ b27 ~ b30 Q C6 16~ S = b ~ b ~ bl3 ~ bl4 ~ bls ~ bl9 ~ b23 ~ 24 ~ 25 ~ 26 171 b27 ~ b31 ~ C7 19 ¦ Accordingly, it is an object of the present invention 20 ¦ to provide error checking and correcting means for detecting all 21 ¦ the uncorrectable errors caused by the failure of a group in a 22 ¦ code word in addition to correcting single bit errors and detec-23¦ ting random double errors, 24¦ It is another object of the present invention to pro-251 vide error checking and correcting means for single error cor-26¦ rection, double error detection and group error detection with 271 optimal design in terms of delay and hardware implementation, 28¦ Other ob]ects, advantages and novel features of the 291 present invention will become apparent from the following detail-301 ed description of the invention when considered in conjunction 31¦ with the accompanying drawings, ~ , 35-105 9~9 l'l Brief Description of the Drawinqs 2 1¦ Figure 1 is a block diagram of the system of the present 3 invention 4l Figure 2 is a block diagram of the check bit generator.
51 Figure 3 is a block diagram of the syndrome bit generator~
6¦ Figure 4 is a block diagram of the error detection 7l circuit.
81 Figure 5 is a block diagram of the error location circuit 9 Description of the Preferred Embodiment lO¦ Referring to the block diagram of Figure 1, there is ll shown an error checking and correcting system for providing single 12l error correction, double error detection, and group error detection 13 in a code word transmitted through a modular communication channel.
14` Means for generating a code word formed of groups of bits SI is provided and in the preferred embodiment, this includes a data 16~ register lO and a check bit generator 12. The data register lO of 17 the preferred embodiment provides 32 data bits (Bo - B3l) as shown 18 in Table 1 above. The check bit generator 12 provides 8 check bits l9 ¦ (C0 through C7), in accordance with the algorithm shown in Table 20 ¦III, above, which was derived from the H-matrix shown in Table I
21 ¦above. The data bits and the check bits are combined to form a 22¦ code word which, in the preferred embodiment, is broken down into 23¦ groups of 4 bits each as shown in Table l.
241 Modular memory channel means is provided for transmitting 25¦ the code word in groups of bits and in the preferred embodiment 26¦ this is shown as modular memory channel 11. The modular memory 271 channel transmits each of the groups of bits in parallel to a 28¦ receiving terminal. In the process of transmission of the bits, 29~ the information content of the code word can be distorted. It is
31 The check bits (C0 to C7) are determined by the odd parity 32 f those data bits which have an entry of 'x' in the associated row i 35-105 , 107~919 1l of the l~-matrix and are g~nerated by EXCLUSIVE OR circuitry. For 2 example, check bit Co is the odd parity of data bits Bo, Bl, B2, B
3 B4~ B5, B6~ B7~ B12~ ~16~ B20, and B24 (The odd parity is the 4 binary sum bit). It is thus seen that the 8 check bits (C0 to C7) 5 are obtained in accordance with the logic equations set forth in 6 Table III, wherein the sign ~ means EXCLUSIVE OR.
9 . , , 1 .
Co ~ bo (~)bl (~) b2 ~) b3 ~3 bl~ ~ b5 ~) b6~3 b7 ~3 bl2 t~3 b~ b~o (~3 b24 C~. ~ bo ~E) b4 6~ b~ 9 (~3 blo (3 b ~ ~) bl2 G~) bl3 (3 bl4 G~ bls (~) b21 (~3 b2~
2 n bl~b~bl6(3bl7~bl~)bl9(~b2o~)b21~3b22(~)b23~)b25~'29 C3 ~ b2(~)bs ~)bg ~)bl3 (3 b24 C3 b25 ~3 b2G~3b~7 Q b2a ~)b29 ~)b30C~)b31 Cl, ~ b4 ~ bs~bGC~ b~ ~ blo ~ bl4 ~ bl7 ~ b20 ~ b21 ~ b22 ~ b23 ~ b26 C5 ~ b3 ~ b6 ~ bll ~ bls ~ blG ~ bl7 ~ b~ l9 ~ b28 ~ b29 ~ b3o ~ b3 CG ~ bo~ bl~b2~ b3~ b~bg~ ~bl~b22~27Qb3 C~ ~ b ~ bl2 ~ bl3 (~ 14 ~ ~15 ~ blg ~ b23 ~ ~24 ~ ~25 ~ b2G ~ b27 I .
As indicated above, the code word during transmission is 21 subject to the introduction of errors. The syndrome bits (S0 to S7) 22 are generated in the syndrome bit generator at the receiver from 23 the received code word by referring to the H-matrix shown in 24 Table I in a similar manner. Syndrome bits (S0 through S7) are 25 determined by the odd parity of those data bits and check bits 26 which have an entry of 'x' in the associated row of the H-matrix.
27 The logic equations for generating the syndrome bits from the re-28 ceived code word is shown in Table IV, wherein again the sign 29 eans EXCLU VE OR.
g _ .a7'~919 2 O O (3 1~) 2 ~ 3 ~) b4 (3 b5 ~) b6 (~) b7 ~) bl2(3 bl6 ~) b20 (~) 3 b 2 4 ~ C o 4 S = bo (3 b4 ~) b8 ~) bg ~) blo ~) bll (~3 bl2 (~) ] 3 (3 14 ~) 15 5 ~ b21 (~3 b28 ~) Cl 6 ~ 2 1~) 8 (~) 16 (~3 bl7 (~3 bl8 (~)blg (~)b20 (~) b21 (~) b ~) b ~) q ¦ b25 (~) b29 (~3 C2 81 S = b2 ~) b5 (~ bg ~ bl3 (~) b24 (~) b25 (~) b26 (~) b27 (~) 28 (~) 29 (~) 9 ¦ b30 (~) b31 ~) C3 10 ¦ S = b (~)b (~b6~)b7(~3blo~)bl4~)bl7Qb2oQ 21(~) 22~) 11 ¦ b23(~)b2.6 0 C4 12 S = b ~ b ~ bll ~ bls ~ bl6 ~ b17 ~ bl8 Q 19 ~ 28 ~ 29 13 ¦ b30 ~ b31 ~ C5 14¦ S6 = bo ~ bl ~ b2 ~ b3 ~ b8 ~ bg ~ blo ~ bll Q bl8 ~ 22 15¦ b27 ~ b30 Q C6 16~ S = b ~ b ~ bl3 ~ bl4 ~ bls ~ bl9 ~ b23 ~ 24 ~ 25 ~ 26 171 b27 ~ b31 ~ C7 19 ¦ Accordingly, it is an object of the present invention 20 ¦ to provide error checking and correcting means for detecting all 21 ¦ the uncorrectable errors caused by the failure of a group in a 22 ¦ code word in addition to correcting single bit errors and detec-23¦ ting random double errors, 24¦ It is another object of the present invention to pro-251 vide error checking and correcting means for single error cor-26¦ rection, double error detection and group error detection with 271 optimal design in terms of delay and hardware implementation, 28¦ Other ob]ects, advantages and novel features of the 291 present invention will become apparent from the following detail-301 ed description of the invention when considered in conjunction 31¦ with the accompanying drawings, ~ , 35-105 9~9 l'l Brief Description of the Drawinqs 2 1¦ Figure 1 is a block diagram of the system of the present 3 invention 4l Figure 2 is a block diagram of the check bit generator.
51 Figure 3 is a block diagram of the syndrome bit generator~
6¦ Figure 4 is a block diagram of the error detection 7l circuit.
81 Figure 5 is a block diagram of the error location circuit 9 Description of the Preferred Embodiment lO¦ Referring to the block diagram of Figure 1, there is ll shown an error checking and correcting system for providing single 12l error correction, double error detection, and group error detection 13 in a code word transmitted through a modular communication channel.
14` Means for generating a code word formed of groups of bits SI is provided and in the preferred embodiment, this includes a data 16~ register lO and a check bit generator 12. The data register lO of 17 the preferred embodiment provides 32 data bits (Bo - B3l) as shown 18 in Table 1 above. The check bit generator 12 provides 8 check bits l9 ¦ (C0 through C7), in accordance with the algorithm shown in Table 20 ¦III, above, which was derived from the H-matrix shown in Table I
21 ¦above. The data bits and the check bits are combined to form a 22¦ code word which, in the preferred embodiment, is broken down into 23¦ groups of 4 bits each as shown in Table l.
241 Modular memory channel means is provided for transmitting 25¦ the code word in groups of bits and in the preferred embodiment 26¦ this is shown as modular memory channel 11. The modular memory 271 channel transmits each of the groups of bits in parallel to a 28¦ receiving terminal. In the process of transmission of the bits, 29~ the information content of the code word can be distorted. It is
30¦ therefore necessary to provide error checking and correcting of the
31
32 ~ 07~9~9 .
1 code word.
2l Means for receiving the code word is provided which 3~ includes means for providing the error checking and correcting func-4 tion. The means for receiving the code word, in the preferred em-5 bodiment, includes syndrome bit generator means 13, error detection 6 circuit 14 and error location circuit 15. The means for receiving q the code word also includes a data register 17 for registering the 8 received data.
9 The received code word in the preferred embodiment having 10 32 da-ta bits and 8 check bits is applied to the syndrome bit gen-11 erator 13 and the data register 17.
12 The syndrome bit generator 13 generates a plurality of 13 syndrome bits in accordance with the algorithm shown in Table IV, 14¦ above, which was derived from the H matrix shown in Table I. The 5¦ syndrome bit generator provides the syndrome bits for use by the 6¦ error detection circuit 14 and the error location circuits lS to 7¦ perform the functions of SEC, DED, and GED.
8¦ The error detection circuit 14 includes means for gen-19 ¦erating error signals which includes error flags 18 which signal a 20 ¦detection of either a single error or the detection of a random 21 ¦double error or a plurality of errors in any one group of bits in 22 ¦the code word.
23 ¦ The error location circuit means 15 is coupled to the 24 ~utput of the syndrome bit generator and receives the syndrome bits.
251 The error location circuit means 15 is further coupled to the output 26 of the error detection circuit means 14 and receives error flag sig-27 nals from error flag outputs 18 of the error detection circuit 14.
28 The error location circuit 15 is coupled to the data register 17 and 29 s operative to correct a single error in the code word. If the rror detection circuit 14 provides an error flag signifying a 31 andom double error or a plurality of errors in one group, the entir 32 ode word may be disregarded and eliminated from the data register 1 1 a d another co~e word m.~y b~ entered into the data register 17.
2l The check bit generator 12 is shown in greater detail 3 in Figure 2. In the preferred embodiment, the 8 check bits are broken down into groups of 4 bits each as shown in Table I. The 51 32 data bits, Bo - B31 are applied to EXCLUSIVE OR gates 20 - 27 6¦ to provide the check bits C0 - C7 in accordance with the al-7~ gorithm shown in Table III, above, which is based on the H matrix 8¦ in Table I. above. The EXCLUSIVE OR gates provide an odd parity 9¦ (the check bit is the binary sum digit of the input bits). For 101 example, the check bit Cl is the odd parity of data bits Bo~
11¦ B4, B8, Bg, Blo, Bll~ B12~ B13~ B14~ Bls~ 21' 28 12¦ The syndrome bit generator 13 is shown in detail in the 13 ¦block diagram of Figure 3. In the preferred embodiment, the 32 14 ¦data bits and the 8 check bits are transmitted through the modu-15 ¦lar memory channel 11 and applied to the 40 inputs of the syndrome 16 ¦ bit generator 13 as shown in Figure 3. The syndrome bit gener-17 ¦ ator includes EXCLUSIVE OR gates 30 through 37 for providing 18 ¦ the syndrome bits S0 -- S7 in accordance with the algorithm in 19 ¦ Table IV, above, based on the H matrix in Table I above. The 20 ¦ EXCLUSIVE OR gates 30 - 37 provide an odd parity of the input 2 ¦ data bits and check bits in accordance with the entry of an "X"
2321 in the associated row and column of the H matrix of Table I.
I For example, the syndrome bit Sl is the odd parity of data bits 24 ¦ 4 8 9 10' 11' B12' B13~ B14, B15, B21, B28, and C
25 ¦ The error detection circuit 14 includes first circuit 2271 means coupled to the output of the syndrome bit generator 13 for 281 generating an error signal if the informational content of the l syndrome bits indicates a detection of any error in the trans-291 mission of the code word. In the preferred embodiment, this is 301 shown as OR gate 40 having syndrome bits So-S7 applied thereto as 311 shown in Figure 4. The introduction of either correctable or un-3 1 correctable errors in the code word produces a non-zero syndrome 1 bit among the syndrome bits S0 - S7 which is detected by the OR
2 ¦ circuit 40 to provide a signal on output terminal 18a.
3 Second circuit means is provided in the error detec-4 tion circuit 14 and being coupled to the output of the syndrome bit generator means 13 for generating an error signal if the in-6 formational content of the syndrome bits indicates detection of 7 a random double error or an even number of errors in a group in 8 the code word. In the preferred embodiment, this is shown as 9 EXCLUSIVE OR gate 41 having inputs S0 - S7. The output of EXCLUSIVE OR gate 41 is coupled to the input of an inverter 42 11 which in turn is coupled to the input of AND gate 43 A second 12 input to AND gate 43 is coupled to the output of OR gate 40.
13 ¦ The second circuit means including EXCLUSIVE OR gate 41, invert-14 er 42, and AND gate 43 together with the OR gate 40, provide a check for uncorrectable errors due to either random double errors, 16 double errors in a group, or quadruple errors in a group, all of 17 which are indicated by an even number of true syndrome bits among 18 the pattern of syndrome bits S0 - S7. This type of error is in-19 dicated by an output from the AND gate 43 to the input of OR
gate 48 to output terminal 18b to provide an error signal to in-1 dicate that the data received by the receiving means is unusable.
22 ~Third circuit means is coupled to the output of the 23 syndrome bit generator 13 for generating a signal if the infor-24 mational content of the syndrome bits indicates a detection of a plurality of errors in the same group of the code word. In the 26 preferred embodiment, the third circuit means provides detection 27 of three errors. However, the teachings of the present invention 28 enable one skilled in the art to adapt the third circuit means to 29 provide detection of an odd number of errors greater than one in 3 the same group of bits of a code word having groups with any de-sired number of bits in each group.
32 In the preferred embodiment, the third circuit means io749~9 includes AND ~ates 44a, 44h, 44c and 44d with the out~ut of the AND gates 44a - ll4d being coupled to the input of OR gate 45.
The third circuit ~eans also includes AND gates 46a, 46b, 46c and 46d having out~uts coupled to the input of OR gate 47. The out-pu-t of OR gate 47 is applied to an input of OR gate 48.
The third circuit means including the AND gates 44a, through 44d and the OR ~ate 45 detect three errors in a group of data bits or a group of check bits which is indicated by having three or five true syndrome bits with three true syndrome bits located in the first four syndrome positions (S0, Sl, S2, S3).
Similarly, the AND gates 46a - 46d in combination with OR gate 47 provide a detection of three errors in any data group or in any check bit group which is indicated by having three or five true syndrome bits with three true syndrome bits located in the last four syndrome positions, (S4, S5, S6, and S7). Three errors in any one group is uncorrectable by the present invention and an output from the OR gate 45 or OR gate 47 as well as an output from AND
gate 43 is transmitted through OR gate 48 to output terminal 18b to indicate that the data received by the receiving means is un-usable. If an error is detected by an output signal on errorflag signal terminal 18a but not on the error flag signal termi-nal 18b, a correctable single error is indicated. The inverter 49 then provides a control signal to enable the error location circuit 15 shown in greater detail in Figure 5. .
The error location circuit 15 includes a plurality of AND gates 50 each of which corresponds to one of the 32 data bits, Bo - B31, and a second plurality of AND gates 52 each cor-responding to one of the check bits C0 through C7. In addition, a pair of AND gates 51 have inputs coupled to the negation syn-drome bits. The output terminal 18c is coupled to each input of the AND gates 50 and 52. If an uncorrectable random double error is detected or a plurality of errors in any group of bits of the 107491g code word is detected, ~the AND gates sn and 52 are disenabled and the data in the code word is considered unusable.
If an error ~i~nal is ;ndicated by an output on termi-nal l~a but not by any signal on terminal l~b, a single error is indicated. The inverter 49 provides an output signal to enable the AND gate 50 and 52 of the error location circuit.
A single error correction is possible since the failure of a bit would result in a syndrome pattern coincidental with a particular column in the Tl matrix. If the single error occurs in a data bit, three syndrome bits will be true. For example, the failure of bit Bo would be indicated by a syndrome pattern, S0 S
S2 S3 S~ S5 S6 S7 11000010. Referring to the error location circuit in Figure 5, the first AND gate of the plurality of AND
gates 50 matches this syndrome pattern, i.e., So= Sl= S6-~This would provide a correction:signal to the data register to reverse the polarity of data bit Bo which has been identified as being in error.
Correspondingly, if a single error occurs in one of the check bits C0 - C7, only one syndrome bit is true. The plurality of AND gates 51 and the plurality of AND gates 52 providela logic function to identify the incorrect check bit and send a correc-tion signal to the data register 17 to reverse the polarity of the check bit which is in error. The outputs of the error loca-tion circuit 15 thereby correct a single error in the code word in the data register 17.
According to the syndrome pattern of the present inven-tion the error detection circuit thereby permits utilization of the received data if no error is detected or enables the error location circuit 15 to provide for single error Crrection in the data register if a single error is detected. The invention fur-ther provides an error flag signal on error flag output terminal 18b to prohibit utilization of the received code word which in-:~ff7~ L9 cludes the data worcl if any random douhle error or a plurality of errors in the same r~roup oF b;.ts are c3etected.
Obviously, many moclifications and variations of the present ;nvention are possible in light of the above teachings.
It is therefore to be understood that wi.thin the scope of the appended claims, the invention can be practi.ced otherwise than as specifically described.
1 code word.
2l Means for receiving the code word is provided which 3~ includes means for providing the error checking and correcting func-4 tion. The means for receiving the code word, in the preferred em-5 bodiment, includes syndrome bit generator means 13, error detection 6 circuit 14 and error location circuit 15. The means for receiving q the code word also includes a data register 17 for registering the 8 received data.
9 The received code word in the preferred embodiment having 10 32 da-ta bits and 8 check bits is applied to the syndrome bit gen-11 erator 13 and the data register 17.
12 The syndrome bit generator 13 generates a plurality of 13 syndrome bits in accordance with the algorithm shown in Table IV, 14¦ above, which was derived from the H matrix shown in Table I. The 5¦ syndrome bit generator provides the syndrome bits for use by the 6¦ error detection circuit 14 and the error location circuits lS to 7¦ perform the functions of SEC, DED, and GED.
8¦ The error detection circuit 14 includes means for gen-19 ¦erating error signals which includes error flags 18 which signal a 20 ¦detection of either a single error or the detection of a random 21 ¦double error or a plurality of errors in any one group of bits in 22 ¦the code word.
23 ¦ The error location circuit means 15 is coupled to the 24 ~utput of the syndrome bit generator and receives the syndrome bits.
251 The error location circuit means 15 is further coupled to the output 26 of the error detection circuit means 14 and receives error flag sig-27 nals from error flag outputs 18 of the error detection circuit 14.
28 The error location circuit 15 is coupled to the data register 17 and 29 s operative to correct a single error in the code word. If the rror detection circuit 14 provides an error flag signifying a 31 andom double error or a plurality of errors in one group, the entir 32 ode word may be disregarded and eliminated from the data register 1 1 a d another co~e word m.~y b~ entered into the data register 17.
2l The check bit generator 12 is shown in greater detail 3 in Figure 2. In the preferred embodiment, the 8 check bits are broken down into groups of 4 bits each as shown in Table I. The 51 32 data bits, Bo - B31 are applied to EXCLUSIVE OR gates 20 - 27 6¦ to provide the check bits C0 - C7 in accordance with the al-7~ gorithm shown in Table III, above, which is based on the H matrix 8¦ in Table I. above. The EXCLUSIVE OR gates provide an odd parity 9¦ (the check bit is the binary sum digit of the input bits). For 101 example, the check bit Cl is the odd parity of data bits Bo~
11¦ B4, B8, Bg, Blo, Bll~ B12~ B13~ B14~ Bls~ 21' 28 12¦ The syndrome bit generator 13 is shown in detail in the 13 ¦block diagram of Figure 3. In the preferred embodiment, the 32 14 ¦data bits and the 8 check bits are transmitted through the modu-15 ¦lar memory channel 11 and applied to the 40 inputs of the syndrome 16 ¦ bit generator 13 as shown in Figure 3. The syndrome bit gener-17 ¦ ator includes EXCLUSIVE OR gates 30 through 37 for providing 18 ¦ the syndrome bits S0 -- S7 in accordance with the algorithm in 19 ¦ Table IV, above, based on the H matrix in Table I above. The 20 ¦ EXCLUSIVE OR gates 30 - 37 provide an odd parity of the input 2 ¦ data bits and check bits in accordance with the entry of an "X"
2321 in the associated row and column of the H matrix of Table I.
I For example, the syndrome bit Sl is the odd parity of data bits 24 ¦ 4 8 9 10' 11' B12' B13~ B14, B15, B21, B28, and C
25 ¦ The error detection circuit 14 includes first circuit 2271 means coupled to the output of the syndrome bit generator 13 for 281 generating an error signal if the informational content of the l syndrome bits indicates a detection of any error in the trans-291 mission of the code word. In the preferred embodiment, this is 301 shown as OR gate 40 having syndrome bits So-S7 applied thereto as 311 shown in Figure 4. The introduction of either correctable or un-3 1 correctable errors in the code word produces a non-zero syndrome 1 bit among the syndrome bits S0 - S7 which is detected by the OR
2 ¦ circuit 40 to provide a signal on output terminal 18a.
3 Second circuit means is provided in the error detec-4 tion circuit 14 and being coupled to the output of the syndrome bit generator means 13 for generating an error signal if the in-6 formational content of the syndrome bits indicates detection of 7 a random double error or an even number of errors in a group in 8 the code word. In the preferred embodiment, this is shown as 9 EXCLUSIVE OR gate 41 having inputs S0 - S7. The output of EXCLUSIVE OR gate 41 is coupled to the input of an inverter 42 11 which in turn is coupled to the input of AND gate 43 A second 12 input to AND gate 43 is coupled to the output of OR gate 40.
13 ¦ The second circuit means including EXCLUSIVE OR gate 41, invert-14 er 42, and AND gate 43 together with the OR gate 40, provide a check for uncorrectable errors due to either random double errors, 16 double errors in a group, or quadruple errors in a group, all of 17 which are indicated by an even number of true syndrome bits among 18 the pattern of syndrome bits S0 - S7. This type of error is in-19 dicated by an output from the AND gate 43 to the input of OR
gate 48 to output terminal 18b to provide an error signal to in-1 dicate that the data received by the receiving means is unusable.
22 ~Third circuit means is coupled to the output of the 23 syndrome bit generator 13 for generating a signal if the infor-24 mational content of the syndrome bits indicates a detection of a plurality of errors in the same group of the code word. In the 26 preferred embodiment, the third circuit means provides detection 27 of three errors. However, the teachings of the present invention 28 enable one skilled in the art to adapt the third circuit means to 29 provide detection of an odd number of errors greater than one in 3 the same group of bits of a code word having groups with any de-sired number of bits in each group.
32 In the preferred embodiment, the third circuit means io749~9 includes AND ~ates 44a, 44h, 44c and 44d with the out~ut of the AND gates 44a - ll4d being coupled to the input of OR gate 45.
The third circuit ~eans also includes AND gates 46a, 46b, 46c and 46d having out~uts coupled to the input of OR gate 47. The out-pu-t of OR gate 47 is applied to an input of OR gate 48.
The third circuit means including the AND gates 44a, through 44d and the OR ~ate 45 detect three errors in a group of data bits or a group of check bits which is indicated by having three or five true syndrome bits with three true syndrome bits located in the first four syndrome positions (S0, Sl, S2, S3).
Similarly, the AND gates 46a - 46d in combination with OR gate 47 provide a detection of three errors in any data group or in any check bit group which is indicated by having three or five true syndrome bits with three true syndrome bits located in the last four syndrome positions, (S4, S5, S6, and S7). Three errors in any one group is uncorrectable by the present invention and an output from the OR gate 45 or OR gate 47 as well as an output from AND
gate 43 is transmitted through OR gate 48 to output terminal 18b to indicate that the data received by the receiving means is un-usable. If an error is detected by an output signal on errorflag signal terminal 18a but not on the error flag signal termi-nal 18b, a correctable single error is indicated. The inverter 49 then provides a control signal to enable the error location circuit 15 shown in greater detail in Figure 5. .
The error location circuit 15 includes a plurality of AND gates 50 each of which corresponds to one of the 32 data bits, Bo - B31, and a second plurality of AND gates 52 each cor-responding to one of the check bits C0 through C7. In addition, a pair of AND gates 51 have inputs coupled to the negation syn-drome bits. The output terminal 18c is coupled to each input of the AND gates 50 and 52. If an uncorrectable random double error is detected or a plurality of errors in any group of bits of the 107491g code word is detected, ~the AND gates sn and 52 are disenabled and the data in the code word is considered unusable.
If an error ~i~nal is ;ndicated by an output on termi-nal l~a but not by any signal on terminal l~b, a single error is indicated. The inverter 49 provides an output signal to enable the AND gate 50 and 52 of the error location circuit.
A single error correction is possible since the failure of a bit would result in a syndrome pattern coincidental with a particular column in the Tl matrix. If the single error occurs in a data bit, three syndrome bits will be true. For example, the failure of bit Bo would be indicated by a syndrome pattern, S0 S
S2 S3 S~ S5 S6 S7 11000010. Referring to the error location circuit in Figure 5, the first AND gate of the plurality of AND
gates 50 matches this syndrome pattern, i.e., So= Sl= S6-~This would provide a correction:signal to the data register to reverse the polarity of data bit Bo which has been identified as being in error.
Correspondingly, if a single error occurs in one of the check bits C0 - C7, only one syndrome bit is true. The plurality of AND gates 51 and the plurality of AND gates 52 providela logic function to identify the incorrect check bit and send a correc-tion signal to the data register 17 to reverse the polarity of the check bit which is in error. The outputs of the error loca-tion circuit 15 thereby correct a single error in the code word in the data register 17.
According to the syndrome pattern of the present inven-tion the error detection circuit thereby permits utilization of the received data if no error is detected or enables the error location circuit 15 to provide for single error Crrection in the data register if a single error is detected. The invention fur-ther provides an error flag signal on error flag output terminal 18b to prohibit utilization of the received code word which in-:~ff7~ L9 cludes the data worcl if any random douhle error or a plurality of errors in the same r~roup oF b;.ts are c3etected.
Obviously, many moclifications and variations of the present ;nvention are possible in light of the above teachings.
It is therefore to be understood that wi.thin the scope of the appended claims, the invention can be practi.ced otherwise than as specifically described.
Claims (10)
1. A system for providing single error correction, double error detection, and group error detection in a code word having plural groups of information and check bits, which comprises:
generator means receiving said code word for generating a plural-ity of syndrome bits, first circuit means coupled to the output of said generator means for generating a first error signal if the informational content of said syndrome bits indicates a de-tection of any error in the transmission of said code word, sec-ond circuit means coupled to the output of said generator means for generating a second error signal if the informational content of said syndrome bits indicates a detection of two random errors in said code word or an even number of errors in one of said plural groups, third circuit means coupled to the output of said generator means for generating a third error signal if the in-formational content of said syndrome bits indicates a detection of an odd number of errors greater than one in one of said plural groups, and error location circuit means in electrical communi-cation with said generator means and said first, said second, and said third circuit means for providing an error correction in response to the detection of a single error in said code word.
generator means receiving said code word for generating a plural-ity of syndrome bits, first circuit means coupled to the output of said generator means for generating a first error signal if the informational content of said syndrome bits indicates a de-tection of any error in the transmission of said code word, sec-ond circuit means coupled to the output of said generator means for generating a second error signal if the informational content of said syndrome bits indicates a detection of two random errors in said code word or an even number of errors in one of said plural groups, third circuit means coupled to the output of said generator means for generating a third error signal if the in-formational content of said syndrome bits indicates a detection of an odd number of errors greater than one in one of said plural groups, and error location circuit means in electrical communi-cation with said generator means and said first, said second, and said third circuit means for providing an error correction in response to the detection of a single error in said code word.
2. The system as described in claim 1 and wherein said first circuit means includes OR gate means coupled to the output of said generator means for generating said first error signal.
3. The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal.
4. The system as described in claim 1 and wherein said 4 (concluded) third circuit means includes AND gate means and OR gate means, said AND gate means having inputs coupled to said generator means and having outputs coupled to said OR gate means, said OR
gate means having first and second outputs with said first out-put for providing said third error signal and said second output being coupled to said error location circuit means for disabling said error location circuit means in response to said third er-ror signal.
gate means having first and second outputs with said first out-put for providing said third error signal and said second output being coupled to said error location circuit means for disabling said error location circuit means in response to said third er-ror signal.
5. The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal, and said third circuit means includes AND gate means and OR gate means, said AND gate means and said EXCLUSIVE
OR gate means having outputs coupled to the inputs of said OR
gate means, said OR gate means having first and second outputs with said first output for providing an error signal if the in-formational content of said syndrome bits indicates a detection of said two random errors or a plurality of errors in one of said plural groups and said second output being coupled to said error location circuit means for disabling said error location circuit means if said two random errors or said plurality of errors are detected.
OR gate means having outputs coupled to the inputs of said OR
gate means, said OR gate means having first and second outputs with said first output for providing an error signal if the in-formational content of said syndrome bits indicates a detection of said two random errors or a plurality of errors in one of said plural groups and said second output being coupled to said error location circuit means for disabling said error location circuit means if said two random errors or said plurality of errors are detected.
6. The system as described in claim 1, and further in-cluding OR gate means in electrical communication with said third circuit means and said error location circuit means, said OR gate means having first and second outputs with said first output for providing said third error signal and said second out-put for disabling said error location circuit means in response to said third error signal.
7. The system as described in claim 1 and wherein said second circuit means includes EXCLUSIVE OR gate means coupled to the output of said generator means for generating said second error signal, and OR gate means coupled to the output of said second circuit means and to the output of said third circuit means, said OR gate means having first and second outputs with said first output for providing an error indication if the in-formational content of said syndrome bits indicates a detection of said two random errors or a plurality of errors in one of said plural groups and said second output being inverted and coupled to said error location circuit means for disabling said error location circuit means in response to said error indica-tion.
8. An error detection and correction system, which com-prises: a. first generator means receiving an information bit stream for providing check bits to form a code word of plural bit groups in accordance with an H-matrix, said H-matrix having a bit structure partitioned to correspond with the boundaries of said plural bit groups and patterned to accommodate the correc-tion of said code word if the presence of only one error is de-tected and to accommodate the detection of two random errors in said code word and plural errors occurring in one of said plural bit groups; b. second generator means in electrical communica-tion with said first generator means for operating upon said code word in accordance with said H-matrix to provide syndrome bits; and c. logic means responsive to said syndrome bits and in electrical communication with said first generator means for cor-recting said one error and signalling the occurrence of said plural errors and said two random errors.
9. The system as described in claim 8 and wherein said first generator means includes a plurality of EXCLUSIVE OR gates 9 (concluded) for providing check bits by odd parity binary addition of a pre-determined combination of information bits in accordance with said H-matrix.
10. The system as described in claim 8 and wherein said second generator means includes a plurality of EXCLUSIVE OR
gates for providing syndrome bits by odd parity binary addition of a predetermined combination of information bits and check bits in accordance with said H-matrix.
gates for providing syndrome bits by odd parity binary addition of a predetermined combination of information bits and check bits in accordance with said H-matrix.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/695,494 US4077028A (en) | 1976-06-14 | 1976-06-14 | Error checking and correcting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1074919A true CA1074919A (en) | 1980-04-01 |
Family
ID=24793230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA276,907A Expired CA1074919A (en) | 1976-06-14 | 1977-04-25 | Error checking and correcting device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4077028A (en) |
| JP (1) | JPS6041770B2 (en) |
| CA (1) | CA1074919A (en) |
| DE (1) | DE2724409C2 (en) |
| FR (1) | FR2375658A1 (en) |
| GB (1) | GB1576627A (en) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142105A (en) * | 1977-05-18 | 1978-12-11 | Sony Corp | Code transmission system |
| JPS5848939B2 (en) * | 1977-12-23 | 1983-11-01 | 富士通株式会社 | error correction processing device |
| US4163147A (en) * | 1978-01-20 | 1979-07-31 | Sperry Rand Corporation | Double bit error correction using double bit complementing |
| US4191970A (en) * | 1978-05-15 | 1980-03-04 | Bell Telephone Laboratories, Incorporated | Interframe coder for video signals |
| US4236247A (en) * | 1979-01-15 | 1980-11-25 | Organisation Europeene De Recherches Spatiales | Apparatus for correcting multiple errors in data words read from a memory |
| US4277844A (en) * | 1979-07-26 | 1981-07-07 | Storage Technology Corporation | Method of detecting and correcting errors in digital data storage systems |
| US4355391A (en) * | 1980-03-31 | 1982-10-19 | Texas Instruments Incorporated | Apparatus and method of error detection and/or correction in a data set |
| US4335459A (en) * | 1980-05-20 | 1982-06-15 | Miller Richard L | Single chip random access memory with increased yield and reliability |
| US4345328A (en) * | 1980-06-30 | 1982-08-17 | Sperry Corporation | ECC Check bit generation using through checking parity bits |
| US4384353A (en) * | 1981-02-19 | 1983-05-17 | Fairchild Camera And Instrument Corp. | Method and means for internal error check in a digital memory |
| US4417339A (en) * | 1981-06-22 | 1983-11-22 | Burroughs Corporation | Fault tolerant error correction circuit |
| NL8104342A (en) * | 1981-09-21 | 1983-04-18 | Philips Nv | CALCULATOR SYSTEM, BASED ON A SYMBOL-CORRECTING CODE WITH TWO WORKING MODES. |
| JPS5878241A (en) * | 1981-11-04 | 1983-05-11 | Nippon Telegr & Teleph Corp <Ntt> | Error detecting and correcting system for coded data |
| WO1983002345A1 (en) * | 1981-12-30 | 1983-07-07 | Chen, Chin-Long | Two bit per symbol sec/ded code |
| US4464753A (en) * | 1981-12-30 | 1984-08-07 | International Business Machines Corporation | Two bit symbol SEC/DED code |
| US4531213A (en) * | 1982-03-03 | 1985-07-23 | Sperry Corporation | Memory through checking system with comparison of data word parity before and after ECC processing |
| FR2528613B1 (en) * | 1982-06-09 | 1991-09-20 | Hitachi Ltd | SEMICONDUCTOR MEMORY |
| US4509172A (en) * | 1982-09-28 | 1985-04-02 | International Business Machines Corporation | Double error correction - triple error detection code |
| NL8403147A (en) * | 1984-10-16 | 1986-05-16 | Philips Nv | DATA PROCESSING SYSTEM CONSTRUCTED FROM THREE DATA PROCESSING MODULES. |
| JPH0760394B2 (en) * | 1986-12-18 | 1995-06-28 | 株式会社日立製作所 | Error correction / detection method |
| JPH0821238B2 (en) * | 1987-11-12 | 1996-03-04 | 三菱電機株式会社 | Semiconductor memory device |
| US4918695A (en) * | 1988-08-30 | 1990-04-17 | Unisys Corporation | Failure detection for partial write operations for memories |
| US5014273A (en) * | 1989-01-27 | 1991-05-07 | Digital Equipment Corporation | Bad data algorithm |
| US5291498A (en) * | 1991-01-29 | 1994-03-01 | Convex Computer Corporation | Error detecting method and apparatus for computer memory having multi-bit output memory circuits |
| DE4300025C1 (en) * | 1993-01-02 | 1994-01-27 | Macrotek Ges Fuer Integrierte | Error coding data transmission method - recognising and/or correcting one and more bit errors and involves division of data word and test word into four bit wide part words |
| US5592404A (en) * | 1993-11-04 | 1997-01-07 | Cirrus Logic, Inc. | Versatile error correction system |
| US5481566A (en) * | 1993-12-29 | 1996-01-02 | At&T Corp. | Method and apparatus to increase efficiency of systematic codes |
| US5754563A (en) * | 1995-09-11 | 1998-05-19 | Ecc Technologies, Inc. | Byte-parallel system for implementing reed-solomon error-correcting codes |
| SG76501A1 (en) * | 1996-02-28 | 2000-11-21 | Sun Microsystems Inc | Error detection and correction method and apparatus for computer memory |
| US6308295B1 (en) | 1996-10-08 | 2001-10-23 | Arizona Board Of Regents | Parallel spectral reed-solomon encoder and decoder |
| US6119248A (en) * | 1998-01-26 | 2000-09-12 | Dell Usa L.P. | Operating system notification of correctable error in computer information |
| US6134684A (en) * | 1998-02-25 | 2000-10-17 | International Business Machines Corporation | Method and system for error detection in test units utilizing pseudo-random data |
| US6738942B1 (en) | 2000-06-02 | 2004-05-18 | Vitesse Semiconductor Corporation | Product code based forward error correction system |
| US6694476B1 (en) | 2000-06-02 | 2004-02-17 | Vitesse Semiconductor Corporation | Reed-solomon encoder and decoder |
| JP2006179131A (en) * | 2004-12-22 | 2006-07-06 | Fujitsu Ltd | Memory system and semiconductor storage device |
| US7653862B2 (en) * | 2005-06-15 | 2010-01-26 | Hitachi Global Storage Technologies Netherlands B.V. | Error detection and correction for encoded data |
| US20070050668A1 (en) * | 2005-09-01 | 2007-03-01 | Micron Technology, Inc. | Test mode to force generation of all possible correction codes in an ECC memory |
| US7702988B2 (en) | 2005-10-24 | 2010-04-20 | Platform Computing Corporation | Systems and methods for message encoding and decoding |
| US7751486B2 (en) * | 2006-05-19 | 2010-07-06 | Platform Computing Corporation | Systems and methods for transmitting data |
| US7949931B2 (en) * | 2007-01-02 | 2011-05-24 | International Business Machines Corporation | Systems and methods for error detection in a memory system |
| CN101442319B (en) * | 2008-11-25 | 2011-04-06 | 西安电子科技大学 | Encoder based on dual-diagonal quasi cyclic shift LDPC code check matrix |
| US8255773B2 (en) * | 2009-06-29 | 2012-08-28 | Sandisk Technologies Inc. | System and method of tracking error data within a storage device |
| JP5581969B2 (en) * | 2010-10-27 | 2014-09-03 | ソニー株式会社 | Decoding apparatus and method, and program |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3562709A (en) * | 1968-09-12 | 1971-02-09 | Rca Corp | Correction of block errors in transmission of data |
| US3697948A (en) * | 1970-12-18 | 1972-10-10 | Ibm | Apparatus for correcting two groups of multiple errors |
| US3745525A (en) * | 1971-12-15 | 1973-07-10 | Ibm | Error correcting system |
| US3745526A (en) * | 1971-12-20 | 1973-07-10 | Ibm | Shift register error correcting system |
| US3893071A (en) * | 1974-08-19 | 1975-07-01 | Ibm | Multi level error correction system for high density memory |
-
1976
- 1976-06-14 US US05/695,494 patent/US4077028A/en not_active Expired - Lifetime
-
1977
- 1977-04-25 CA CA276,907A patent/CA1074919A/en not_active Expired
- 1977-05-25 GB GB22039/77A patent/GB1576627A/en not_active Expired
- 1977-05-28 DE DE2724409A patent/DE2724409C2/en not_active Expired
- 1977-06-03 JP JP52064968A patent/JPS6041770B2/en not_active Expired
- 1977-06-14 FR FR7718162A patent/FR2375658A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| US4077028A (en) | 1978-02-28 |
| FR2375658B1 (en) | 1982-10-22 |
| GB1576627A (en) | 1980-10-08 |
| DE2724409A1 (en) | 1977-12-22 |
| JPS5325330A (en) | 1978-03-09 |
| JPS6041770B2 (en) | 1985-09-18 |
| FR2375658A1 (en) | 1978-07-21 |
| DE2724409C2 (en) | 1986-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1074919A (en) | Error checking and correcting device | |
| US6799287B1 (en) | Method and apparatus for verifying error correcting codes | |
| US7149947B1 (en) | Method of and system for validating an error correction code and parity information associated with a data word | |
| US6301680B1 (en) | Technique for correcting single-bit errors and detecting paired double-bit errors | |
| US5631915A (en) | Method of correcting single errors | |
| GB2216690A (en) | Error detecting/correction | |
| EP0692167B1 (en) | Apparatus and method for transmitting information between dual redundant components utilizing four signal paths | |
| US4388684A (en) | Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources | |
| US3541507A (en) | Error checked selection circuit | |
| US4236247A (en) | Apparatus for correcting multiple errors in data words read from a memory | |
| US5535227A (en) | Digital information error correcting apparatus for single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC) | |
| CA1267460A (en) | Parity detection system for wide bus circuitry | |
| US5491702A (en) | Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word | |
| EP0130429B1 (en) | Failure detection apparatus | |
| EP0310220B1 (en) | An apparatus useful for correction of single bit errors and detection of double bit errors in the transmission of data | |
| US4723245A (en) | IC chip error detecting and correcting method including automatic self-checking of chip operation | |
| US4739506A (en) | IC chip error detecting and correcting apparatus | |
| US4739505A (en) | IC chip error detecting and correcting apparatus with automatic self-checking of chip operation | |
| US6027243A (en) | Parity check circuit | |
| CA2021834C (en) | Personal computer memory bank parity error indicator | |
| EP0257414A2 (en) | Fast error detection/correction for command signals | |
| JP2864611B2 (en) | Semiconductor memory | |
| SU783782A2 (en) | Device for exchange of information of control computer with control objects | |
| SU786037A1 (en) | Error detecting and correcting device | |
| SU840912A1 (en) | Device for detecting and correcting errors in computer units |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |