CA1059638A - Fail soft memory - Google Patents

Fail soft memory

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Publication number
CA1059638A
CA1059638A CA244,779A CA244779A CA1059638A CA 1059638 A CA1059638 A CA 1059638A CA 244779 A CA244779 A CA 244779A CA 1059638 A CA1059638 A CA 1059638A
Authority
CA
Canada
Prior art keywords
address
control block
interrupt
addressing
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA244,779A
Other languages
French (fr)
Inventor
Jaime Calle
Garvin W. Patterson
Marion G. Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1059638A publication Critical patent/CA1059638A/en
Expired legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications

Abstract

ABSTRACT OF THE DISCLOSURE

A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or system interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or system interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Description

9~38 BAcKGnoullD OF THE INV~NTION

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This invention relates to data processing systems and more particularly to a general purpose computer system having alter-nate paths for addressing data in memory wherein one path is for normal addressing and the other is for automatic use in the - event of memory failure.
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Descri~tion of the Prior Art As data processing systems have become more complex the size and number of processors, main memories and peripheral units has gro~m. It has therefore become imperative that communication links between pro~essor, peripherals and main mem-ory ~e maintained. Because of the high cost of providing re-dundant processors for controlling communications between peri-pheral units an input/output exchange was utilized for coupling l a plurality of peripheral units to central processing unit.
When this input/output exchan~e failed, access to the central processing unit by all ~eripheral units coupled to that input/
outnut exahange was blocked. One answer tc this dilemma was to provide redundant paths by providing at least one additlonal out-put exchange, to whicll all the peripheral controllers and peri~
pheral units are conneatedO (See U. S, Paten~ Number 3,792,448 issued February 12, 1974 to Bennett et al and entitled ~iFail Soft Peripheral Exchange".) Thls did not ~olve the problem, however, where a peri~heral itself such as a main memory faiied. If, for example, ~here were a failure in one module or portion of main memory whid _3_ ~ >

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; stored the ba3e addresse~ of routines or program3 ~tored in the good portion of th~ main memory or module, these routines or programs in the good portion of the module would not automatically be accessible to the processox.
What i~ needed therefore is a mechanism ~or au~omatically providing an alternate addressing path to the good portion of memorv.
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OBJECTS OF THE IWVENTION
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- It is an object of the invention to provide an improved memory addressing mechanism for an automatic data processing system.
It is anotiler objeot o~ the invention to provide at least two addressing paths to data stored in a memory of a general - purpose computer system.
It is still ano~her object of the invention to provide a mechanism for detecting a memory failure in a general purpose computer system and automatically switching to an alternate ~, memory.
Yet another object of t~e invention is ~o store addressing data in at least two different portions or moduleq of main mem-ory and automatically utilizing the second module only wnen a failure is detected in the first module.

SU~RY OF ~HE INVENTION
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In accordance with the above and other objects of the in-vention, a firmware/hardware mechanism in a general purpose com-puter system automatically provides an alternate addressing path to a good portion of main memory when a failed memory ~`~

; portion is detected, Two types of memory failures are detected `:
and an alternate addressing path t;o a good memory is automati-cally provided for each type of failure. The first type is a failure in a memory which is not detected by the memory hardware or the system interface unit SIU hardware; such a failure is handled by an exception proc~ssing mechanism to automatically provide an alternate addressing path to a good portion of main memory. The second type of failure is detected by memory or SIU
hardware; such a failure is handled by an interrupt processing mechanism to automatically provide an alternate path to a good portion of main memory.
A primary and secondary con~rol block base CBB register provides the redundant addressing. If the primary control block in memory cannot be accessed by utilizing the primar~ control block base CBB, ~irmware utilizing the secondary CBB automatical-ly locates an interrupt or exception control block ICB or ECB re-spectively in another memory module which is utilized to initiate first an error routine to locate the error in the failed memory, ?`~1 and secondly a processing routine to provide the processing requested.
According to the presen~ invention, there is provided a fail soft mechanism in a general purpose computer system having at least one processor9 said fail soft mechanism for automatical-ly providing an alternate addressing path for addressin~ data in a second portion of main memory when a failure is detected in a ~irst portion of main memory, said mechanism comprising:
a~ ~irst means for addressing a ~irst control block means in a first portion of main memory of said computer system, said first means further comprising:
1. a firs~ interrupt con~rol block addressing means for storing signals indicating a firs~ part of the address of the first control block means in said first portion of said main . , . ~ ' .
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memory;
2. a first control block addressing means for storing signals indicating a second part of the address of said first control block means in said ~irst portion of said main memory;
and, .. ~. a first combining means coupled to be responsive to said first interrupt control block addressing means and to said ~irst control block addressing means for combining the first ;
: part and second part of the address of said ~irst control block means; b. second means coupled to be responsive to said first means, for detecting a failure in the first portion of main memory addressed by said first means; and, c third means~
coupled to be responsive to said second mea~s, ~or automatically ~;
providing an alternate path to a second portion of main memory upon detection of a failure in said first portion o~ main memory~
said third means further comprising;
1. a second interrupt control block addressing means for storing signals indicating a first pa~t of the address of a --second interrupt control block means in said seco~d portion of said main memory;
2. a second control block addressing means for storing signals indicati~g a second part of the address of the second interrupt control block means in said second portion of said main : memory; andj :
3. second combi~lng means coupled to be responsive to said second interrupt cvntrol block addressing means and to said .~ second control block addressing means, for combining the ~irst and second part of the address of the second interrupt control block means in said second portion of said main memory.
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Figure 1 is a schematic block diagram of a typical computer system utilizing the invention~

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Figures 2A through 2M are data structure diagrams of various registers utilized by the invention. ,~
Figure 3 i5 a block diagram of a processor in accor- ~
dance with the inven~ion. :

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_ 5b -~ S96315 . DESCRIPTION OF THL~ ~

,., l~eferring now to Figure 1 there is shown a typical computer system utilizing the invention. The System Interface Unit (SIU~
100, containing the priority interrupt and dispatcher unit mech anisms 101 and 102 respective~y, provides connections between the elements of the computer proce~sing system. In addition to prov~ding for access of local or remote memory 121, 122 and 122a, 123 respectively by the active module processors 103-106, con-figuration panel 124 etc., the SIU 100 provides for direct addressing of the high and low speed multiplexors 107 and 112, 113 respectively and control adapters 108, 109, 134, and 135 by the processors 103-106.
The interrupt unit 101 and the dispatcher unit 102, are more fully described in references B and C above; they control the interrupt discipline and perform processor dispatching as required.
Each processor designated IOP/P 103-106 typically contains 16 registers 130-133 for each level of priority assigned to a process or a total of 128 registers per processor capable of storing 128 words. mese registers 130-133 are sometimes re-ferred to in this specification as the scratchpad memory and are more fully described infra. Each processor IOP/P is a general purpose computer processor with a conventional complement of register-register, register-memoryl i~mediate, branch, bit field and shift instructions. These processors may be used as input~
output processors ~IOP) whose functions include initiation and termination of I/Oicommand sequences~ fetching, checking and s translating channel programs, and direct control of low speed peripheral devices such as unit record and data communications equipment. Proces~ors 103-106 are attached t~ and communicate ~, .
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1C~5~3163~3 with the SIU 10~ via ports H, G, F, and ~ respectively.
The processor loaal memor~ 12~, 12~ interface with the SIU and the processors 103-106 via ports LMo and ~ 1 and H-E
respectively. Each of the local memories 121, 122 is organized as a read-write store 136, 137 respectively, plus read only memory ROM 138, 139 with an optional cache memory 140, 141.
Width of the local memory interface ~lo , LMl is 3Ç bit~ plus
4 bits for parity. Local memory size is typically 256K or 512K
; bytes wherein each K is equal to 1024 bytesO
The remote memory adapters 122a, 123 are utilized when the SIU with its processors and peripherals is part of a larger general purnose computer system. ~he Remote ~emory Adapters (RE~A) 122a, 123 then provide a means of exch~nging control and data transfers between tlle processors 103-106 and remote memories 122b and 123b, of another general Purpose computer system designated 6XXX (not ~hown herein). Up to 2 ports ~ , ~and ~ ~for each of the REMA units 122, 123 respectively are pxovided, each port having a 40-bit data path for input and for output between the computer system shown and de~cribed herein and a large computer sys~em not shown herein. The R~MA units 122a, 123 are connected and communicate w.ith the SIU 100 via ports RMo and ~1 . Note that primary and secondary control blocks tto be more fully described infra) are stored in the local memories 121, 122 and remote memories 122b, 123b respe~tively.
A high speed multiplexor 107 provides direct control of data transfers between high speed peripheral devices (disk drive 110, tape drive 111) and central or local memory 121, 122~ ~he high speed multiplexor 107 inter~aces between the SIU and the peri-pherals via port A.
Each low speed multiplexor 112, 113 permits direct control by a processor 103-106 o~ a low-speed de~ice such as card punch . ' : , : I . . .
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': 118, printer 119 and console 120, via ports J and K and device adapter inter~ace unit D~I 115, 116 and 117 respectively.
Referring now to Figures 2A-2L the general visible registers 2A are those processor registers which can ~e acceqsed witn pro-cessor software instructions. The following constitute the ~, visible registers of each procassor IOP/P:
a. Process State ~egister (PSR) b, Instruction Counter (IC) - c. Page Table Base Register (PTBR~
d. General Registers (GR's) e. Control Block Base Register (CBB~) f. Process Control Register (PCR) The PSR, IC, PTBR and GR's are held in scratchpad 32~ of sixteen 36-bit registers and are assigned as shown in ~ig. 2A.
Process State Register (PSR~ Fig. 2B - The Process State Register holds information essential to the control of the cur-rent process. It has the format of Fig. 2~:
Ste~ring Bits (0-7) - Steering inserted to identify interrupt source.
P (Bit B) - Privilege. Master ~0) or Slave (1) Mode.
R (Bit 9) - External Register. Certain predetermined non-IOP/P registers cannot be altered if this bit is set.
A (Bit 10) - Address Mode. Absolute (O) or Paged (1) Mode.
CC (~its 11-12) - Condition Code~ Meaning of the condition code is given for each IOP/P instruction.
In general, corrRspondence is:
Result - O CC ~- O
Resul~ C o CC ~ 1 ~ Result ~ O CC ~- 2 ,i Overflvw CC C 3 C (Bit 13) - Carry bit out of adder. Carry (1) or No Carry (0) resulting from execution of instructions using arithmetic functions of the adder. (Adds, substr~cts, multiply, divide, compare and ne~ate.) Process Timer (Bit 14-35) - A timer which i8 decremented periodically while this process is active.
A process timer runout exception occurs when the timer value reaches zero. The timer is decremented once every 512 pro-'10 cessor cycles. For a cycle time of 80 nonoseconds, this results in a minimum value of about 40 microseconds, and a maximum value of 2.67 minutes.
Due to the frequency of acces9 to the PSR, either for modification or reference, the actual value for the current pro-cess is held in a special register outside the general register scratchpad (not shown). For performance reasons, changes in the r~gister are not reflected in general register GRo. This scratchpad location assigned to the PSR is used only to sa~estore the current PSR value in the event of an interrupt.
All instructions which specify GRo as a destinatlon operand will cause the result to be stored in the special register used to hold the PSR, and GRo will not be changed. A special instruction copies the PS~ to a GR so that it may be used as an ! 25 operand.
Instruction Counter (IC) ~ig. 2C - The Instruction Counter holds the address of the current instruction. Since instruction~
mu~t be half-word aligned, the least significant bit is always ; zero. The IC is held in general register GR , and it has the ;, 3 format of Fig. 2C: 1 J

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L/R (Bit 0) - Local/Remote (0) Specifies Local memory 121, 122; (1~ Speci~ies Remote memory 122b, 123b.
S (Bits 1-3) - Steering. Specifies which remote memory for remote memory re~erences.
RFU (Bit~ 4-8) - Reserved for Future Use.
IC (Bits 9-35) - The (byta~ address of the current in-struction.

Page Table Base Register (PTBR) Fig. 2D - The Page Table Base Register points to the page table used to provide paged address relocation for the current process. It may be loaded only in master mode. The PTBR is held in GR15, and it has the format of Fig. 2D:

L/R (Bit 0) - Local/Remote.
S (Bits 1-33 - Steering.

Prog. # (Bits 4-8) - Program Number. A field which may be used by software to carry additional program identi~ication. q~his field is ignored by the processor hardw re.
Page Table ~ase (Bits 9-29) - This is the absolute address - of the base of the table of Page Table Words for this process. Sinca the addre~s is filled to 27 bits by add-ing six zeros at the right, page table addresses must be congruent to 0 mod 64 ~bytes)~
Key (Bits 30-35)- The key is a process identifier used to associate Page Table Words with processes ., General Registers (GR) - The remaining 13 registers GR2 ~ GR14 of visible registers Fig. 2A a~re general registers.
The e may be used aq source or destination operands, or as ~5~638 first or second-level address modi~iers.
- Control Block Base Register ~CBBR) Fig. 2E - The Control Block Base (CBB) Figs. 2F-2G i~ an absolute address which points to the base address in memory of the Exception Control Block (ECB) Fig. 2J and Interrupt Control Block (ICB) Fig. 2J tables.
The Control Block ~ase Rlegister is actually held in the scratchpad location assigned to GRo for the highest priority process level. Two CBB values, a primary and a ~econdary are held in the register, which has the format of Fig. 2E.
The Primary CBB Fig. 2F is used for all exceptions, and for all interrupts except those associated with local memo~y errors.
When used, the primary CBB is aligned as shown on Fig. 2F.
This alignment permi~s the location of bases of the ECB and ICB tables on any 512-word boundary in any memory.
Referring to Fig. 2F:
L/R (Bit 0) - Local or Ramote memory (Same as Fig. 2C~.
S (Bits 1-3) - Same as Fig. 2C.
, RFU (Bits 4-8) - Same as Fig. 2C.
CBBl (Bit~ 9-24) - Address of primary Exception Control Block or primary Interrupt Control Block.
Bits 25-35 - Fill with zeros.
The secondary CBB Fig. 2G is invoked for interrupt~ due to local memory errors. When used, th~ secondary CBB is aligned as shown on Fig. 2G.
This alignment permits the location of the bases of the alternate ECB and ICB table~ on a 512-word boundary within the first 64K of any memory.
Referring to Fig. 2G:
~/R (Bit 0) - Local or Remote memory (Same as Fig. 2C).
S (Bits 1-3) - Steering. Same as Fig. 2C.

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11~591~i38 RFU (Bits 4-8) - Reserved fox future use.
Bits 9-17 - Fill with zeros.
CBB2 (Bits lB-24~ - Address of secondary Exception Con-trol Block or secondary Interrupt Con-trol Block.
The Exception Control Blocks and Interrupt Control Blocks are stored a~ shown on Fig. 2H with respect to the CBB~ Note for the address of Interrupt Control Blocks ICB's relative to the CBB, the relative address of the ICB'5 is added to,the CBB;
whereas for the address of exception control blocks ECB's, their relative address is subtracted from the CBB.
Process Control Register (PCR) - There is one ProcesS
Control Register (PCR) common to all levels. It has the format of Fig. 2I~
Exceptions (Bits 0-8) - Each bit indicates a non MME exception of a particular type.

Parity Errors (8its 9-15) - Identifies the point in the processor at which a parity error was detected.

LZ (Rit 16) - No responses to level zero~interrupt , present.
~, RFU ~Bit 17) - Reserved for future hardware use.
T&D (Bit 18) - T&D Mode ¦Test & Diagnostic) - ~alt instrustion StQpS processor with all interrupts ignored.
ROM (~it 19) - ROM bit. Controls acces~ to Read OnlY
Memory.
' RFU (Bits 20-22) - Reserved ~or future hardware usa.

PROC ~ ~ LEVEL (Bits 2 3-26 ) Processor number and priority lavel of proae6s.

INH ~Bit 27) - Interrupt inhibit bit.
INT. REQ. (Bits 28-35)- Inkerrupt request bits. Each bit set .

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'~ ~ indicates a software set interrupt at a level corresponding to the bit posi-tion, Request level 7 ~Bit 35) is always set. Processor set interrupts at levels 0-7 use ICB's 8~15 respectively.
Exceptions Exceptions are processor-detected conditions which cause automatic entry to an exception processing routine. Exception conditions may be created deliberately, or t~ey may be the re-sult of a programming error or a hardware error outside the pro-cessor. Exception conditions are defined as shown below. For - non-~E exceptions, correspondence is shown between type and bit positions of the PCR Fig. 2I~
PCR Bit of Fi~ 2I Exception Ty~e - O Operation not complete (ONC). No response on ARA
or ARDA from SIU. ARA - Active Request Accepted from SIU. SIU response to I~P/P cycle request.
ARDA - Accept Read Data from SIU.
1 Page address bounds fault (Key check).
2 Page access fault.
' 3 Page not resident in memory.
4 Illegal operation (invalid instruction, illegal slave instruction, or illegal slave operation).
Process Timer run out, 6 Overflow if PSR CC a 11~ Divide Check i~ PSR CC = 00.
7 Lockup fault (interrupts inhibited for more than 40 us), 8 Address misalignment~
~, 30 Exception conditions are identified by a four-bit exception number. For master mode entry exceptions, this number i5 taken from bits 10-14 of an instruction (not shown). In all other cases~ the exception number is zero. The exception number is .

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` ` 1~5i9~ii38 used as an ~xception Control Block Number (ECB ~) to identify a four-word Exception Control ~lock (ECB) which points to the exception processing routine. The byte address of an ECB is given by ECB address = Control Rlock Base - 16 (ECB # + 1).
The format of the ECB i8 shown on Fig. 2J. Referring to Fig. 2J, a PSR word Fig. 2B is held in the first word; an IC
word Fig. 2C is held in the second word; a Saving Area Pointer tSAP~ for processor pair 0 is held in the third word of ECB 0, and a S~P for processor pair 1 is held in the third word of ECB 1 Fig. 2H.
~efore an exception processing routine can be entered, essential information about the current process must be safe-~; stored. This is performed as a part of the processor response to an exception. Since occurrences of excaptions may be nested (i.e., a second exception may occur before completion of pro-cessing for the first), a stack is used to provide space for process safestore. The stack pointer is called the Saving Area Pointer ~SAP), and it is held in the third word o~ ECB 0. Multi-, 20 processor systems reyuire a second stack, and the SAP ~or the;, second processor is held in the third word of ECB 1.
, When an exception is detected~ the appropriate Saving Area - Pointer is retrieved, and information a~out the current process is safestored in the stack in the order shown on Fig. 2K where ADDRESS, IC, GR2-GR4, PCR, PTBR, PSR are dafined supra. The , Saving Area Pointer is updated accordingly.
The IC st~red in the stack Fig. ~K ~oints to the instruct-ion following the one in process at the time the exception was detected. The address stored in the last stack location is ~,~, 30 the last address o~ interest generated befoxe the exception wa~
detectedO It is primarily for exceptions involving addresses, ~14 , ` : ~(35963~
including operation not complete, bounds, acce~Y and missing page exceptionsr After this information about the current process has been safestored in the stack 2K, the PSR, IC, and PTBR are loaded from the appropriate Exception Control Block, and the address of the Saving Area Pointer used by this processor is loaded into GR2 . This completes the entry to the exception process-ing routine.
Upon completion, the exception processing routine issues a special instruction (RMM) (not shown~ to return to the pro-cess in which the exception was encountered. T~is instruction loads the PSR, IC, GR2, GR3, GR4 ~ and the PTBR from the stack, and decrement3 the Saving Araa Pointer. If exceptions and RMM instruct~ons do not occur in pairs~ the exception pro-cessing software must ensure that the stack is properly main-tained. There are no checks for errors in software manipulation of the stack pointer, or for stack overflow or underflow.

INTERRUPTS
Interrupts are events detected outside the processor which require a processor responsa. Interrupts in the IOP/P may be as~igned to one of eight priori~y levels. Level 0 is the highe~t priority level, and level 7, the lowest. In order to minimize the time required to answer an interrupt request, the IOP/P pro-vides a complete set of registers for each of the eight levels.
When an interrupt causes the initiation o~ a new process, the current process is left intact in the regist~rs assigned to the current level. Control may be returned to the interrupted pro-cess simply by reactivating that process level. The need to safestore and restore interrupted processes is eliminated, along with the accompanying overhead.

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The ~ixteen registers for each level are held in success-ive 16-register blocks in the 128~word IOP/P scratchpad 328.
Registers for level 0 are held in scratchpad locations 0-15~
Since the PSR for level 0 is never transferred to the scratchpad (level 0 cannot be interrupted), scratchpad location 0 is used to hold the Control Block Base although other registers at level ; O would be used. Communication between registers at different levels is possible only ~ia the master mode copy instructions (not shown~ which address the scratchpad.
The IOP System Interface Unit (SIU) const~ntly monitors both the current process level of the processor and requests for interrupts ~xom I/Q system modules. Each interrupt request specifies the number of the processor to ~e interrupted, the priority (level number) of the request, and steering to identify the interrupt requestor (see Interrupt word Fig. 2). This infor-mation is held in each module which may request interrupts, and for most modules it is set using programmable interface commandq.
~henever an int~rrupt re~ue~t is present at a level higher than the current processor leval~ the SIU raises a higher level interrupt present line to the processor by providing an inter-rupt signal ~see re~erence B supxa~. If several interrupt re-quests are present at the same le~el, the SIU determines which request is passed on to the proce~or on the basis of priorities established by port number.
If the current proces~ i~ not in`terrupt inhibited, an interrupt request causes tha IOP/P to suspend the current pro-cess and to ~ccept an interrupt word ~rom the SIU. ~e interrup~

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word has the format of Fig. 2L. Referring now to Fig. 2L:
N (Bit O) - New. This bit if set indicateq that the interrupt is a new one. ~f no~ set, the interrupt word specifies that of a previously interrupted process is to resume.
RFU ~Bits 1-17) - Reserved for future use. This field must be O but will not be checked to ascertain that the field is 0.
Bit 18 - Set to 0.
ICB # (Bits 19-26) - Interrupt Control Block Number.
STEERING (Bits 28-35) - Steering. This field identifies the interrupt requestor. Bits 2R to 31 are generated by the SIU and identify the 15 - source module (SIU port number) of the interrupt.
To initiate the interrupt processing routine, four registers are loaded from the interrupt control block Fig. 2M. When the PSR is loaded, the steering field from the interrupt word is in-serted into the steering ~ield of ~he PSR. The other registers, the IC, GR14, and PTBR, are loaded directly from suacessive words in the ICB Fig. 2~.
A release instruction ~not ~hown) (REL) i~ u~ed to exit processes entered as the result of an interrupt. After a REL
the SIU ~elects for execution the highest priority process wait-ing for the processor.
j This proce~s may be one that was previously interrupted, or a new prooeqs to be lnitiated as the result of an interrupt request. At the same prioxity level, previously interrupted pro-cesses have priority over new interrupt requests. Through hard-ware (see reference B supra) and software loading of the PCR, a ~05i9638 processor may prPsent to the SIU an interrup~ at any leve.l, 0-7. However, in order to provide a well-de~ined response to a REL executed at any level, the pCR bit requesting a level-seven interrupt is always set.
If a new process is to be entered as the result of a REL, the processor response is similar to that triggered by a nor-mal interrupt, including acceptance of an interrupt word from the SIU and access to an ICB. If a previously interrupted pro~

cess is to be re-entered, the SIU supplies only the level num-ber and the fact that an old process is to be re-entered. ,Since the process state at the time of its interruption is intact in the register scratchpad, this is the only information required to restart the process.

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General Description of Processor IOP/P:
Figure 3 is a block diagram o~-a processor in accordance with the present invention. Data and instructions from the sys-tem interface unit (SIU~ are provid~d at register 310 and pro-cessed data is provided to the SIU at data out register 312.

As data and instructions are clocked into ragister 310 a paritY

check is made and parity errors are noted.

Instructions are plaaed in a "look ahead" dual read-out register 314 which provides four words of buffering for instruct-ions. An 8-level control store address switch 316 (which may ' typically be a multiplexor) provid~es an address to control store 318. (Data Selectors, typically are multiplexors and are well known in the art and commercially available. See The Integrated Cirauits Catalog for Design Engineers published by Texas Instru-ments, pages 9-339 to 9-364.~ Two levels of the CSA switch 316 are provided by the instruction register 314 via pathfinder unit 317.
~! 30 Ths control store 318 contains the microinstructions which control ,.~

.,;, ' . ., .. , .. . , . . . , . . . .. .. ~ , : . . i, ~(~59~i315 data manipulations, and an addressed microinstruction is stored in corltrol store register 319.
Data from input register 310 is loaded into one level of the eight-level "B" swltch 320 (also commercially available~ which, along with two-level "A" switch 322 (commercially available), provides operands for the adder/shifter network 324. The "B"
switch 320 is controlled by a field in the control store regis-ter 319. "A" switch 322 provides inputs from the dual read-out working registers 326 or from general registers scratch pad 328 via SPB register 330. The dual read-out register 326 contains 3 working registers and an image of the instruction counter (IC) con-tained in the general register scratchpad 328. The WRR output from working register 326 is supplied to "A" switch 322, and the I~RP output from general register 326 is supplied to the general register scratch pad 328. A seven-bit address for the general register scratchpad is generated in a one of eight switcl (SPA) 332 (commercially available).
The adder/shifter network 324 which receives operands from "B" switch 320 and "A" switch 322 performs all of the arithmatic, logical, and shift operations required for addres3 development and instruction execution.
A page table word (PTW) scratchpad 334 provides storage o~
16 page table words for each of the 8 interrupt priority levels~
The four level address switch 336 (commercially available) con-catenates addxesses for either progr~ammable interface commands or read/write memory cycles (either paged or absolute).
Output from the adder/shifter network 324 may be supplied through a four-level result cros~bar (R-XBAR) 338 to data output register 312. The R-XBAR provides simultaneous transfer o~ its inputs to both the data output register 312 and the working , ~19-~596;~13 registers 326. The R-X~AR also receives i~puts from a process state register (PSR) 342, from a process control register (PCR) 344 through switch 346, from the general register scratchpad 328, and from the address switch 336.

General Register Scratchpad The General Register (GR) scratchpad 328 contai~s 128 forty bit registers. Each register consists of 4 nine bit bytes with a pari~y bit per byte. Data written into the scratchpad comes from one of the four working registers on the WRP output of the dual readout register bank used to implement the working registers~ Registers included in the scratchpad are a process state regis~er (PSR), an instruction counter (IC), a page table base register (PTBR), thirteen general registers (GR). The seven bit address ~or the scratchpad is generated in one of eight switch (SPA~ 332. The switch control inputs are wired directly to the Control Store Output register (CSR) 319. The most significank three bits of the address define one of eight levels and the least significant four bits define one of sixteen registers wi~hln the level. The level is supplied by Active Interrupt Level (AIL) lines (not shown) from the SIU for six of the eight posltions. The eight address sources are as follow~:
0) Seven bits of the constant fiald (2-8) of the CSR which allow9 addressing any register in any level.

1) The AIL lines and four bits of the CSR ~onstant field (5-8) which allows addressing any register in the current level.
2) The WRR output of the dual readout working registers bits 29-35. This allows a working register to provide the address for either initialization or software addressing (CSPG or CGSP).

. -2~-5963~
,, 3) The AIL lines and bits 19-22 of the current instruction.
This provides the XR2 read address for second level index-ing, 4) The AIL lines and bits 14-17 of the current instruction.
This provides the XRl read address for first level index-ing or the GR/GR2 read address for operand access.
5) The AIL lines and bits 9 12 of the current instruction.
This provides the GRl/GR read address for operand access.
6) The AIL lines and bits 0-2 of the Write Address tWA) registar 48 with the least significant bit wired to logi-cal one. This provides the odd address of an even odd pair read or write instruction.
7) The AIL lines and bits 0-3 of the WA register. This pro-vides the address for all software writes into a GR at the current level. This included GR loads and returning execu-tion results to the destination GR.
The output of the scratchpad goes to the one of two switch 330A into the SPB register 33~ which is a}so an input to the , Result Crossbar (R~XBAR) 340. ~e switch into SPB allows ~ operations on a GR and a working register or on two working registers by loading one into SPB. The switch 330A into SPB
330 is controlled by the SP control field in the CSR 319.
The Write Address (W~) register 348 can be loaded from either bits 9-12 or 14-17 of the current instruction (see refer-ence A supra). Thi~ provides the address for loading a General Register (GR) or returning a result to a GR. This is necessary since the GR address in tha instruation being executed is no longer available out of the dual readout InStruction register once the IC is updated. The GR addrass is therefore saved in 3~ WA and used for the write operation by setting a Write (W) flip/

' 1~i963~
flop (see ref. A supra) associated with WA. W resets on the first clock after it is set unless the WA control field in the CSR once again sets it (two word load of GR)~ A GR scratchpad write clock pulse is generated on all clocks occurring while W
is set unless WA=0 in any mode or ~A=15 or 1 in slave mode.
SPB register 330 is a forty bit register (four by~es with parity per byte). It provides buffering for words read out of the scratchpad and eliminate~ the scratchpad access time from the time requixed for an Adder/Shifter operation, Parity is checked on the data in the SPB register 330. The SPB load clock is c~ntrolled by the CSR SP control field 319.

A and B Operand Switches ~ ~he A and B operand ~witches provide the two operands ~or ; the Adder/Shifter network. A switch 322 sele~t~ either SPB or the WRR output of the dual readout working registers, The selec-tion is controlled by a bit in CSR 319. However, the control is forced to select WRR if W is~set and the address in WA is equal to XRl, Thi~ causes the ne~ ~alue of XRl or G~2 to be ~used i~
the previous instruction modifiçd them. The switc~ output i6 forced to logical zeros if the DL posi~ion is selected i~ B
switch 20 and no indexing is called for (XR l=Q~
switch 320 selection is controlled by a three bit field in CSR 319. However, the least significant bit i~ forced to logical one if the DL position is selected and second level~in dexing is required ~bit 18 of the I~struction = 1. See refer-ence A). The eight B switch positions are formatted as follows:
O) Eits 0-19 are equal to IRSW 319a bit 19. Bits 20-35 are wired to IRSW bits 20-35. This is the displacement ield for either first level or no indexing.
1) Bits 0-23 are equal to IRSW bit 23. Bits 24-35 ara wired , -22-~S9~;38 to IRSW bits 24-35, This is the displacement field for second level indexing.
2) Bits 0-30 are equal to IRSW bit 8. Bits 31-35 are wired to IRSW bits 9-13. T~lis is the short immediate value~
3) Bits 0-17 are equal to IRSW bit 8. Bits 18-35 are wired to IRSW bits lB-35. This is the long immediate value.
4) This position selects the WRR output of th,~ dual readout working registers 322. -5) Bits 0-31 are equal to logical zero~ Bit 32 is equal to the most significant bit of the CSR constant field. This provides the number 8 for incrementing the instruction counter IC to point to the next even/odd Instruction pair (8 bytes) in memory. Bits 33 and 34 are equal to the word length in bytes of the current instruction if the , ~ 15 two most significant bits of the CSR constant field are -~ zero (10 for word and 01 for half word). B~t 35 is equal to the carry bit in the process state register PSR if the l next o most significant bit of the control store register ;, CSR constant field is one.
6) Bits 0-26 are equal to zeroO Bits 27-35 are wired to the CSR constant field.
7) miS position selects the SIU Data In (DI~ register.
, .

Adder/Shifter Network A detailed block diagram o~ the Adder/Shifter network is shown in Figure 4 in the application of reference A supra. The Adder-Logical Unit (A~U? executes 36 bit arithmetic and logical ~, operatlons. It also provideQ the transfer path for~ither the A or B operands to the R-XBAR at 338. me ALU operations are controlled by the ALU/Shift input ~its in the CSR 319. The ALU
mode is controlled by the leas~ significant bit of the PSR/PCR
control bits in the CSR.

~q~5~3~
PTW Scratchpad -; me Page Table Word (PTW) scratchpad 334 provides stor-age for 16 PTW'~ ~or each of the eight levels (128 PTW's~ The output of the B operand switch 320 provides the write data into the scratchpad and the write c:Lock is controlled by a bit-in the CSR.
The PTW scratahpad addrPsEi i8 generated from either the least significant 7 bits of the ~RP output of the working regis-ter 326, or the level and bits 21 24 of the WRP output. The ~irst position is for initialization and general register GR
: to PTW transfer. The second position is for reading/loading PTWts while paging addresses and loading missing PTW~s. The address selection is controlled by a bit in the CSR.
Each byte of the PTW output is parity checked. The PTW
scratchpad output provides input data to two of the four address switch positions. If the PTW output is selected by the Paged~
position of the Address switch the following checks are made to determine if the ~TW i9 valid (the priority of the checks for declaring faults is in the order shown):
1) Bit~ 30-35 of the PTW are compared to a Key ragi~ter 372.
(The Key register identifies the proce~s with which the PTW is associated and is loaded with bits 30-35 of WRP
each time GR 15 is loaded.) 2) Bits 27-29 of the PTW are compared with blts 18-20 o~ WRP.
This is to verify that the correct PTW is resident in this PTW Scratchpad location. (0, 16, 32, etc. all reside in the same ~cratchpad locationO) 3) The next check is to see if the page is re~ident in read/
write R/W memory 122b, 123b. A zero in PTW bitr6 indicatas that the page is not resident in memory.

5963~
4) If the first three checks pass, bits 4-5 of the PTW are compared with the type of operation being initiated. A
data read is always legal. An Instruction fetch requires bit 4 while a write requires bit 5.
If the PTI~ in the scratchpad fails any of the above checks, it will be accessed from the Page Table in R/W memory and checked again prior to causing an exception.
The address word for either R/W memory or the Programmable Interface is generated in the Address switch 336. The switch is controlled by the Address switch control bits in the CSR.

If the paged position is selected and the PSR reflects the absolute address mode, the absolute position of the switch will be forced so that paging is bypassed. Tlle four positions are as follows:
0) This position generates the paged address to R/W memoryO

; Bit 0 equal to zero defines a R/W addressO Bits 1-3 are provided by the ZAC bits in CSR. Bit 4 is equal to zero.
Bits 5-8 are th0 zone bits and are generated as a function of the R/W memory oparation. Reads cause zeros, word or double word writes cause ones, and byte writes cause a one in the byte position to be written. Bits 9-24 are equal to PTW scratchpad 9-24 which i9 the page base addreæs. Bits 2S-35 are equal to WRP 25-35 which i6 the page relative addres~. When this position is selected, the WRP output of the working registers must reflect the unpaged address.

l~ mis position generates the R/W memory address when no paging is required. It can be selected hy the CSR or will be forced if position 0 is selected and the PSR reflects the absolute address mode. Bits 0~8 are the same aR position -25~ ' :. . . . . . .. . . . .

/'~ 5963~f - O. Bits 9-35 are equal to WRP 9-35 which must be equal to the absolute memory address when this pof~ition is selected.
2) This position generates a Pr.ogrammable Interface (PI) S command word. Bit 0 equal to one defines a PI command word. ~it 1 is supplied by the CSR ZAC field. Bit 2 is equal to bit 9 of the PSR and defines whether the curxent program can alter certain external register~. ~it 3 is equal to the processor n~mber supplied by the SIU. Bit 4 is equal to zero. Bits S-8 are equal to PSR bits 4-7 : and define the port within the multiplexer. Bits ~-35 are equal to WRP 9-35 and must be equal to the absolute address generated for either RDEX or WREX.

3) This po~ition provides the path for reading a PTW from the scratchpad.

Bits 0-2 of the address switch 336 are modified to reflect the R/W memory steering during loading of absolute addresses into GR. This requires bib 0-2 to reflect PTW saratchpad 0-2 if paged and WRP 0-2 if absolute address mode. This would be enabled due to position 0 of the address switch being i selected and no R/W memory cycle being initiated by the CSR

SIU request type control bits.
The ffteering switch provide~ the SIU steering or aither a R/W memory cycle or a Programmable Interface command. It is controlled by the Addre~s switch control bits in the CSR.
e steering is generated for R/W memory aq ~ollow~:
Bit 0 This bit equals 0 for R/W memory Bit 1 This bit de~ines local or remote memory. It is equal to PTW bit 0 if paged or WRP bit 0 if absolute.
Bits 2-4 'Thase bits are the memory steering bits. me initial value is equal to PTW bi~s 1-3 if paged or WRP bits 1-3 if abso:Lute. Tl~ is also the final value i~ bit 1 ., , ,, " , ~ , , , ,; ~. . . .. .

defines remote memory. When bit 1 defines local memory, bits 2 and 3 define the local memory port and steer addresses to the ROM in the local memory controller. Bit 2 is equal to the Exclusive OR of the initial valua and the Local Memory Port Specifier (LMPS) line from the SIU. Bit 3 is equal to the ~xclusive OR of the PCR ROM bit if the initial value is zero.

~it 5 This bit defines a single or double word memory cycle.
It is equal to bit 1 of the CSR ZAC field.

~it 6 This bit defines a read or write cycle. It is equal to bit 0 of the CSR ZAC field.
m e ste~ring is generated for a PI command as follows:

Bit 0 mi5 bit equal~ 1 for a PI command Bits 1-4 These bits define the SIU port to which the PI command is directed and equal bits 0-3 of PSR.
Bits 5-6 These bits are the same as for a R/W memory cycle and are generated in the same way.

The outputs of the steering switch are clocked into the steering register at the SIU interface each time a memory cycle or PI

command is initiated.
Result-X~AR
The Result Crossbar (R-XBAR) 338 provides simultaneous transfer of its inputs to both the Data Out and Working registers 312 and 326 respectively. A third output is wired to a display panel ~not showII) and provides the path to display most of the IOPP registers. Xhe output to the working register is oontrolled by the WR Write Addres~ bits in the CSR and can select any of the four inputs. The output to the DO register 312 is controlled by -27~

l¢~S963l~

the DO Write Address bit in the CSR and can select either the ALU/Shifter Output 324 the ~ddress switch 336. However, : this position is forced to select the PSR/PCR input if the DPCR
line (not shown) from the SIU is activatedO
S O) ALU/Shifter Output switch l) Address Switch 2) PSR/PCR Switch 3) SPB Input Switch Working RegistsrS
The four working registers are contained in the dual readout register bank 326. Register 0 contains the current InStruCtion . Counter (IC). (The IC is also maintained in the current level's GRl of the GR scratchpad). Registers l, 2 and 3 are working registers for instruction execution. They are labeled Rl, R2 and R3.
m e two Working register outputs are labeled WRP and nRR.
WRP is used to access PTWIs from the PTW scratchpad, R/W me ry ,~ address generation and supplies the Working register input to both the GR scratchpad 328 and the SPB register 330. The register enabled out of WRP is controlled by the WRP bits in the CSR 314. WRR is used to provide operands to the A and B
operand switches 322 ,and 3~0 respectively and the input to both the PSR and PCR registers~ The register enabled out of WRR i~
controlled by the WRR bits in the CSR.
The Working registers can be loaded from any of the XBAR
inputs. The register to be loaded and the write ~lock is controlled by the WR write address and.Write WR bits in the CSR.
There is no restriction on the registers selected for the ~, 30 read and write operations. It can be three di~ferent registers or they can all be the same one.

.. ,- j . .. .. ` - .: , , ~

r ~I ID59638 PSR/PCR
The Process Sta-te register (PSR) 342 is kept outside the GR scratchpad since it is continuously monitored and updated.
It is loaded from the WRR output of the Working registers 326~
A write clock is generated for the PSR each time a master mode program loads GR0 (GR0 written using the WA address) or the PSR/PCR control bits in the CSR define a write P5R operation.
The entire PSR is loaded during a master mode load of GR0, execution of an Exception from the ECB, or the execution of a DSIP, MME, RMM or REL instruction (see reference A supra).
When an interrupt ~is executed, the steering from the Interrupt data word is inserted into the PSR data from the ICB prior to loading.
A condition code (cc), carry (c) and process timer are continuously updated. Th~ cc is loaded each time an instruction is executed requiring a cc update. C is loaded with the carry out of the arithmetic and logic unit ALU each time the cc is - loaded and the ALU is the arithmetic mode. The process timer is decremented each time a Timer Ticker (not shown) rolls over. The Timer Ticker is an eight bit counter whi~h counts on all system clocks (controlied clocks in step mode). The Timer Ticker is also used to detec~ an operation not complete or lock up exception as described in the section on excaptions.
The Process Control register (PCR) 344 is common to all levels. It is loaded from the WRR output of the working registers (not all bits are loadable). A write clock is generated for the loadable bits when the PSR~PCR control bits in the CSR define a write PCR operation.

2~

., .

.

. , 5963~3 Bi~s 18-19 and 28-34 are loadable. Bits 0-16 set when the defined condition occurs and are reset by the set/reset bit control in the CSR. Bits 23-26 are provided for software to read.
The PSR/PCR switch into the R-XBAR selects the corresponding register to be loaded into one of the working registers. This switch is controlled by the PSR/PCR control bits in the CSR
but is forced to select PCR if the DPCR line (not shown) from khe SIU is activated D
The dual readout register bank 314 provides four words of buffering for instructions. The current instruction read output (CIR) 380 and next instruction read output (NIR) 380a provide access to the entire instruction independent of the instruction length and address. This is provided through the 1-5 Instruction register switch (IRSW) 319a. The CIR address is equal to the current Instruction Counter ~IC) bits 32 and 33 which points to one of the ~our words. The NIR address is generated to point to the following word. IRSW 319a is con~
trolled by the current bit 34 of the instruction counter IC
which defines whether the instruction starts on a word or half word address. The two IRSW positions are there~ore (0~ CIR
bits 0-35 and (1) CIR bits 18-35, NIR bits 0-17. IRSW bits 0-17 will reflect a half word instruation and IRSW bits 0-35 will reflect a full word instruction. The CIR and NIR addresses are updated each time the working register instruction counter IC
is updated. A11 fields of the Instruction word must kherefore be used prior to updating the IC.

., ~ . . . . . . . . - , ~ . , , , ~ ., .~S9638 Th0 IR 314 is loaded each time a new value is loaded into the IC due to an interrupt, exception, branch, etc. or each time x CIR address crosses over a two word boundary when tha IC is updated by the current instruction length. The instruction access control is described helow for the two conditions 1) enter new procedure and 2) incrementing through current procedure. In~both cases the instruction fetches are double precision memory cycles and the addresses are paged unless the PSR defines ab~olute mode.
1) The double word instruction fetch is initiated and the IR write address loaded on the clock that pages (if required) the new value of IC. The IR write address is loaded with 00 if IC bit 32=0 or 10 if IC bit 32-1. (The CIR and NIR addresses are loaded when the new IC value is loaded). When the ir~t word is available from memory, it is written into IR and the least significant bit of the write address is set. ~hi~ causes the next memory word to be written into the second word of the pair (01 or 11~.
The IC value plus eight tbytes) is then used to initiate another double precision memory read using the paged (if required~ address. The IR write addres~ is updated to the next two words (10 i~ IC bit 32=0 or 00 if IC bit 32=1 and a test is made to see if instruction execution can begin or if execution must wait for the memory cycle to complete. The test is on bit 33 of the IC. If the test indicates the new procedure is being entered at the last half word of a two word pair t33 = 1), the instruction ;l execution must be delayed until the data is available from the second double preci~ion cycle to guarantee IR contains -~, a full instruction word.

i .~

1~59638 2) The execution of each instruction includes an update of the IC by that instruction's length. If this update causes the IC to pass over a two word boundary (old IC
32 ~ new IC 32), the two word-area of the IR that was just finished (old IC 32 value) can be loaded with new instructions. The new IC value plus eight (bytes) is then used to initiate a double precision memory read using the paged (if required) address. ~he IR write address is updated to point to the IR area available. T~en the two words are received, they are written into the two word area as described above.
Control Store Addressing and Sequencing The Control Store Address i~ generated in the CSA switch 316. The ~irst four positions o~ the CSA switch are controlled by the CSA switch control field in the CSR 319~ The CSA switch control 316 can select the Next address register (~A) 382, the Return address register (RA) 384, the Execution address reqister (XA) 386, or the Standard Sequence output of the path finder (SS) 3881 The Exception/Interrupt position is forced when either of these two conditions existO The Exception addre~s is reflected unless an Interrupt is being executad. The two PTW mis~ positions are forced when an PTW mis~ is detected. The constant position is selected when the Branch control field in the CSR calls for a branch to the constant addre~s~
~A 382 is loaded on each execution cloc~ by the sum of the CSA switch 316 output plus one plus a aonditional skip constant 390. If no skip is called for by the CSR skip aon~rol field, NA
is loaded wi.th the address of the microinstruction immediately following the one being accessed (i.e., the clock that loads the microins~ruc~ion at address M into tha CSR loads the address M+l into NA). X~ a number of microinstructions are to be conditionally : skipped, the CSR skip field can speoify that a skip be executed 1~5~i3~3 with the CSR constant field defining the condition to be tested and the number (1 through 7) of microinstructions to ~e skipped. The ~equence for a skip is as follows~ microinstruction at M calls for a conditional skip, the execution of this micro-instruction loads M+l into the CSR and load~ the address of M+l+l+SKP into NA. M is a location-in Control Store 318.
SKP=0 if the skip is not satisfied and equal~ the sklp count defined in the least significant three bit~ of the CSR constant - field if satisfied. The skip i~ inhibited if position 4, 5 or 0 6 i5 selected in the ~SA switch.
The conditions that can be tested for skip execution are defined by bits 3-5 of the CSR con~tant field. WRR 35, WRR 0, WRR 33 and the carry bit in PSR need to be tested for zero or one. The PSR cc field will be tested for zero, one, two or three. Bits 1-2 of the constant field are used to define the test. The conditions to be tested are as follows:
0) WRR 35=K2 if Kl=l (K0-K8 are equal to b~ts 36-44 of SR 319).
WRR 0=K2 if Kl-0 1) Carry bit in PSR=K2 2~ WRR 33-34=Kl-2 3) Address ~yllable (AS) with IRSW 18=0 4) PSR cc ~ield ha~ corresponding bit i~ IRSW CF field ` 5) PSR cc field=Kl-2 6) IRSW 7=WRRO if Kl=0 IRSW 7=K2 if Kl=l 7) Higher Level Interrupt or Level Zero Pre~ent line from SIU if K2=0. Level Zero Interrupt Present line from SIU i~ K2=1.

. :

~l~?5~63l~
The RA register 384 is loaded from ~he NA register 382 whenever the Load RA bit is on in the CSR.
The XA register 386 is loaded with the Pathfinder 3]7 output each time the SS position is selected in the CSA switch. The use of the Pathfinder will be described below~ Its output is 2 control bits and 16 address bit:s. The address is used to address the upper 256 words of Control Store (address bit zero is forced to 1 in the XA position of the CSA switch).
The execution of a software instruction is in two phases.
The first phase is a microinstruction sequence common to a group of instructions. The second phase is a microinstruction sequence (which is only one microinstruction in most cases ?
unique to the specific software instruction being executed.
After completing the second phase, the common phase of the next instruction would be entered (in some cases, the second phasP may return to the first phase via RA register 384 for a few additional common steps prior to entering the next instructions common phase).
The operation code of IR5W 219a provides the Pathfinder address. The Standard Sequence output of the pathfinder is the Control Store address of the start of the microinstruction sequence common to the group of instructions containing thls one~ (This sequence is referred to as a standard sequence SS). SS is the Standard Sequence output 388 of th~ pathfinder. The location ~5 in the Pathfinder addressed by the operation code contains the SS
address and the address in Control Store where the unique~sequence , for this instruction starts. The instruction is then executed by : branching to the Standard Sequence addres~, executing the~common .

, i9gi38 steps, branching to the unique sequence address in XA register 386, executing the unique steps, updating the In~truction Count (IC) so that the next instructions operation code is enabled out of IRSW and repeating the above sequence by branching to the new Standard Sequence.
The interrupt answering~ exception processing and PTW
missing sequences are entered by forcing the corresponding position to be selected in the CSA switch 316. Interrupts are executed at the completion of software instructions. If the Higher Level Interrupt Present (not inhibited~ or the Level Zero Present lines from the SIU are active when~the SS
position of the CSA switch is selected by the CSA switch control bits in the CSR, the CSA switch control logic is forced to select the Exception/Interrupt position. This causes the interrupt answering sequence to be entered rather than the next instructions standard sequence. (The Exception/Interrupt position reflects the address of the interrupt answering sequence at this time).
Missing Page Table Words (P~W) cause immediate entry into the PTW missing sequences. Either the operand or instruction missing position i5 forced by the CSA switch 316 control-logic during the clock period lmmediately following the paging step~
; The return from either sa~uence is to the standard sequence decoded from IRSW 3i9a. This causes the instruation that was being executed to be started over again. Therefore, the microprogram will not do anything Prior to the PT~ missing detection that can't be done again. A 1ip/flop (not shown) is set when the PTW miss is detected that stays set until the address is once again paged. A miss the second time through causes an exception as defined below.

-35;

59Ç~38 The exceptions fall into two categories. The first type causes an immediate entry into the exception processing sequence.
The second type does not affect the CSA switch 316 control logic until the next instructions qtandard sequence is entered. Both types cause the Exception~Interrupt position in the CSA ~.witch 316 to be selected and set the corresponding bit in the PCR
; register 344.
The first category of exceptions are operations not complete, Page faults, Page not resident, and illegal instructions. They all must be serviced as soon as they are detected since continuation of instruction execution is impossible. The second category is process timer run outr overflow, lockup fault and address mis alignment. Divide check is handled by a test and branch if divisor is zero. They all indicate faults but do not need to be immediately serviced and can wait until the start of the next instruction.
Control Store Output Register e Control Store Output registex (CSR~ 319 contains the misroinstruction being executed. Provision is made for a remote CSR register, as indicated.
There is a one of four position switch 394 supplying the input to CSR. The four positions on the CSR input switch are `i as follows:
O), 1) These positions are the inputs from the ROM c~.ips on the Control Store substrates.
2) This position is the input from the maintenance-panel.
3~ This po~itlon re1ects the local CSR. It is used to reload the remote CSR bits when the maintenance panel switches axe used to display data.
, ~ . . .. . . . . . . .............. .

, . . . . , ,. ~ . , : . , .

f~
~l~S963E~
Data is displayed in the I/Q System by simulating CSR
with maintenance panel switches. When the switches are enabled out of the CSR input switch 394, a signal is generated causing the remote CSR bits to be loaded with the microinstruction simulated by the switches. The old contents must be reloaded when the display of the registers is completed. This is accomplished by selecting position 3 for one clock prior to switching back to position 0 and reloading the remote CSR bits during the one clock period. ~A block diagram of the input to the local and remote CSR is shown in United States Patent No.
3,976,977 (reference A supra) in Figure 3 with the timing dia-gram for reloading the remote CSR after using the maintenance panel switches for display).
The format of CSR is as follows:
Bit 0 Clock NA into RA
Bit 1 Execute SKIP ~Kl-2=test, K3-5=condition, k6-a-skip count) Bit ~ Branch to K0-8 Bits 3-4 WR write address 00=write IC (Load WA if Write WR) 01=write Rl (set W if Write WR and CSA=SS) 10=write R2 ll=write R3 ;
Bit 5 Wait for Accept Read Data from SIU
Bits 6-7 X-BAR address for WRW output Q0=AdderlShifter Output Switch Ql=Address switch 10=PSR/PCR switch ll=SP Output switch .:

... . . .

~5~3~3 Bits 8-9 Condition Code (CC) Control O O=~IOP
O 1=hoad Arithmetic 10=Load Logic ll=Load Parity of SPB Least Significant Byte Bit 10 Write PTW Scratchpad Bits 11-13 ZAC for R/W memory cycle 5bits 1~ 3 o:E R/W
address switch positions O and 1) OXX=Read I XX=Write XO~=Single precision XIX=Double precision Bit 14 Set/Reset bit defined by CSR41-44 Bits 15-17 SIU Request Type OOO=NOP
OOl=Interrupt Data O10=Release and Interrupt Data O 11=Memory or Programmable Interface Data (PI if 19-20=10) 100=Byte Read to Write (Byte address, R/W Zone i f wri te) * 101=Instruction ~etch * llO=Instruction Fetch if CIRO=I~WO
** lll=Instruction Fetch if SKIP test satisfied or if CSRl=O
*These codes cause an instruction PTW missing sequence if a page fault is detected.
**This code cause~ an operand PTW misslng sequence if a page fault is detected.

-38- .

l~S9638 si~ lB P1~ Scra~chpad address 0=Extended Read/Write from WRP
l=Current level PTW Read/Wr.ite from Effective Address.
Bits 19-20 Address Switch Control 00-Paged address (control logic forces 01 if PSR 10=1) 01=Absolute address 10=PI address ll=PTW scratchpad 0-35 Bit 21 Write WR
Bits 22-23 CSA switch control (first four positions) 00=Next Address register (NA) 01=Return Address register (RA) ~5 10=Execution Address register (XA) ll=Standard Sequence Address Bits 24-25 WRR read address , Bits 26-27 WRP read address 00=IC
01=Rl 10=R2 ll=R3 Bit 28 A operand Switch 0=SPB
l=WRR
Bits 29-30 PSR/PCR control ~ ALU Mode 00=Read PSR or Logical Mode 01=~ead PCR or Arithmetic Mode 10=Write PSR
ll=Write PCR

~ ~a9S96;~13 Bits 31-32 Adder/Shifter Output switch 00=Shifter 01=ALU
10=Store 32 ll=Load 32 Bits 33-35 B Operand switch 000=DL
001=DS
010=IS
011=IL
100=WRR
101=8, Word length~ or Carry 110=Constant K0-8 lll=DI
15. Bits 36-44 Constant K0-8 This field is also used for mutually exclusive control.
Bits 36-37 8/WL/CY control 00, 8/W~/CY=IRSW Instruction word length 01, 8/WL/CY=PSR Carry Bit 10, 8/WL/CY=8 Bits 36-38 Shift Count Swltch control 000 Left shift 001 Right shift 010 CSR Shift Count (39-44) 011 Instruction Fl field 100 Instruction F2 field 101 Instruction F3 field . 110 Byte load 111 Byte Store .. , . , , . . ,, ~ , ... .

59~i38 Bits 39-44 CSR Shift Count Bits 36-44 CSA switch branch address Bits 37-38 SKIP test value for conditions tested for multiple values Bits 38 WA input switeh Control (0=GRl 1=GR2) Bits 39-41 SKIP test condition 000 WRR35=CSR38 if CSR 37=1 WRR0=CSR38 if CSR 37=0 ~; 001 PSR 13 (carry)=CSR38 010 WRR33=CSR 38 011 IRSW 14-35 Contains Address syllable and bit 18-0 100 BRAC CF field has bit corresponding to PSR CC if CSR 38=1 BRAC CR field does not have bit corresponding to PSR CC if CSR3R=0 101 PSR CC field=CSR37=38 110 IRSW7=WRR0 if CSR37=0 IRSW7=CSR38 if CSR37=1 111 SIU HLIP line active and not inhibitsd or LZP active.
Bits 42-44 SKIP count - Bits 38-44 GR scratchpad total address Bits 41-44 GR scratchpad address per level S~ 38 .~
: Bits 41-44 Set/Reset bit address 0000 Reset llalt Mode :- 0001 Set Halt mode 0010 Rese~ Inhibit Interrupt mode .. 5 0011 Set Inhibit Interrupt mode 0100/0101 Rese~ PCR Exception Storage 0110/0111 Not Defin~d 1000/1001 Invert D0, Steering, and interrupt Data Parity . 10 1010/1011 Inver~ GR Parity & inhibit GR SP
write clock conditi~nally 1100/1101 Inhibit GR SP write Clock conditionally 1110/1111 S~t Measure F/F
Bits 45-48 ALU Control/Shift Input switches Control Bits 45-48 ALU operation (CSR 30=mode) Bits 45-46 Left Shift Input switch 00 A Operand switch , 01 Sign of Rl~ht Shift Input Switch ,1 10 Zeros 11 Ones . Bits 47-48 Right Shift Input switch 0X Zeroes 10 B Operand switch 11 A Operand switch , 25 Bits 49-50 GR Scratchpad Control i 00=NOP
! 01-Write GR ~cratchpad ~, 10=Load SPB from GR scratchpad ll=Load 5PB from WRP

, , ~42-.

~59~;~

Bits 51-53 GR Scratchpad Address ~ 000=CSR Scratchpad total address (CSR38-44) - 001=CSR scratchpad address per level (AIL, CSR41-44) 010=E~tended Read-Write address from WRR
011=Current level XR2 100=Current level XRl 101=Current level GRl 110=Odd register of pair addressed by WA in current level lll=WA address in current level Control Store The control store 318 is a typical prior art read only memory ~OM well known in the art. The theory; construc~ion and use of ROM's is detailed in a book by Samir S. Husson entitled, "Microprogramming Principles and Practices" published by Prentice Hall in 1970. The microprogram which resides in the control store 318 and controls the operations of the invention is included on pages 37 to 43 of this specification. When the control store 318 is micropro~rammed as shownr it is termed the firmware of the invention. The firmt~are differs from a software program in that an actual physical operation is performed on the ROM chip, and removal from the computer or loss of power does not alter the microprogram; this is akin to hardwiring the program in the computer. ~owever, with software programming there is no physica~alteration of memory - merely electrical, hence loss of powex or removal of the memory from the computer destroys the programr there is no kinship to hardware logic.
OPERATION OF THE INVENTION
Basically there ar two failures where the fail soft memory invention is utilized. The first are processor detected conditions ~ . . .

ii3~
which are herein termed exception conditions and cause an automatic retry to an exception processing routine. The second type of failures are events detected outside the processor which require a processor response and are herein termed interrupts. Exception conditions have been discussed supra under exceptions and interrupts are discussed in detai:L in the U. S. Patent No. 4,001,783 (reference B supra). Once an exception or interrupt condition has been identified each is handled by a combination of hardware/
firmware in almost identical fashion. The main difference in handling aside from the nomenclature is that in address formation for tha interrupt control block ICB relative to the control block base CBB the interrupt control block number ICBN is added to the CBB address; whereas in address formation for the exception control block ECB the exception control block ~umber ECBN is subtracted from the CBB address. (See Figure 2~ and also discussion supra under the sections on Exceptions and Interrupts).
For purposes of illustration as to the operation of the invention, assume that an interrupt has been generated by the SIU. (See reference B supra for such generation).
2a The SIU constantly monitors both the current process level of the processor and requests for interrupts from the I/O
system modules. Each interrupt request specifies the number of the processor to be interrupted, the priority (level number) of the request and the steering to identify the interrupt re~uestor. This information is held in each module which may request interrupts, and fo~ the most modules it is set by .,~,.. ...
using pro~rammablè interface commands. (See U.S. Patent No.
4,006,466 (reference D supra), Programmable Interface Apparatus by G. Wesley Patterson, Michael Monahan t W. Shelly and Jaime Calle, issued February 1, 1977,,and assigned to the same assignee as the instant application.J Whenever an interrupt request is present at A

, ~ -4~-~.~5~1fi313 level higher than the level of the current processor, the SIU
raises a higher level interrupt present line to the processor by providing an interrupt signal. If several interrupt requests are present at the same level, the SIU determines which request ; 5 is passed on to the processor on the basis of priorities established by port numberO If the current process is not interrupt inhibited, an interrupt request causes the IOP/P to suspend the current process and to accept an interrupt word, Figure 2L, from the SIU. Among other pi.eces of information the interrupt word supplies is an interrupt control block number ICBN
at bit positions 19-26. This is the number that is added to the CBBl address if the primary control base CBB to obtain an interrupt control block ICB address. If this were an exception instead of an interrupt, the exception control block number ECBN is then ; 15 subtracted from the CBBl address of the primary control block base CBB. The address is formed by hardware under firmware control.
Interrupt processing firmware causes the access of the CBB1 address stored in the primary CBB in general register GR0 of 1 and 0 lalthough any other level could be utilized for the purposes of this invention). The firmware will then cause the primary control block base to be shifted left by 11 bits so as the format of Figure 2F is obtained. The ICBN
bits 19-26 of interrupt word Figure 2L are added to the CBBl address of primary CBB Figure 2F to obtain the address of the interrupt control block ICBB. A double word request is then made by the firmware to access the first two words in the interrupt control~lock Figure 2~. Following the access of the first two words in the interrupt control block, the operation : 1~59~3~
not complete ONC bit (which is bit 0 of the PCR~ is tested to see whether or not the prior operat:ion was completed or not.
If the prior operation was completed and the ONC bit is not set, then the normal interrupt pxocessing routine is initiated by loading the process registers with the four registers from the t~terrupt control block. When the PSR is loaded, the steering field from the interrupt word is inserted into the steering field of the PSR. The other registers, the IC, the GR14 and PTBR are loaded directly from successi~e words in the ICB.
Assuming however that the ONC bit, bit 0 of PCR~ is set, then there is an indication that there is a malfunction in memory and an alternate memory should be used. Accordingly, the interrupt processing firmware once again causes the access of the CBB from GR0 of 1 and 0 in the scratchpad 328. However, this'time the secondary control block base is formed and CBB2 which uses an alternate memory is utilized to access another interrupt control block ICB to handle the memory fault in the primary memory. The address of the secondary 1nterrupt control block ICB is formed undar firmware control by taking the bits 0-3 of CBBR and place them in bits 0-3 of working register 326. Also bits 4-10 of the CBBR are placed in bit positions 18-24 of the working register. This forms the secondary CBB of Figure 2G. By using the CBB2 address and the new port identified by the steering and adding it to the interrupt control block number, an alternate interrupt control block can then be accessed and the system does not fail.
The microinstructions for t~e firmware for performing th~se processes are shown on pages 37 to 43 herein. In order to further illustrate their use in greater detail, the exception processing which is similar to the interrupt processing above will now be -1~596;~
, described. An exception is caused as previously described herein under the section on ~xceptions. Exceptions are recognized by the processor and identified by a four bit exception number~
~ For master mode entry exceptions, the exception number is taken ; 5 from bits 10-14 of an instruction (not shown herein). In all other cases, the exception number is 0. The exception number is used as an axception control block number ECBN to identify a ~ four-word exception control block ECB Figure 2J. As previously -~ described under the section on Exceptions, this ECBN is subtracted - 10 from the CBB address to obtain the ECB address.
Before an exception processing routine can be entered, essential information about the current process must be safe stored. This is performed as part of the processor response to an exception. Since occurrences of exceptions may be nested a stack, 15 Figure 2K, is used to provide space for process safe store. In the exception control block ECB there is stored a saving area pointer SAP which points to the stack used to provide space for safe storing information about the current process. ~ccordingly, the firmware is entered at address 200 on page 43 supra.
(Note that these are octal addresses). From address 200 on page 43 there is a branch to address 435 on page 56 of the Appendi~
herein. At address 435 there is the microinstruction which is a call to form the address in order to get the SAP. There is then a branch to address 100 on page 37 where there is a microinstruction which tests the processor nu~beE to see whether a saving area pointer for processor pair P0 o~ processor pair Pl is required.

~ ` ` "

1~59~38 ~ (See reference B supra for description of processor - pair P0 and processor pair Pl). The alignment of the CBB is effected by a microinstruction at octal address 103 on page 37. This instruction controls the alignment of the primary CBB by causing a left shift of 11 bits to give the ~ormat of the primary CBB Figure 2F~ Microinstruction at octal address 106 causes a read of the saving area pointer SAP addressed.
Following the access of the SAP, the ONC bit in the PCR is tested to see whether or not the access was completed. The test for the operation not complete at the completion of a memory cycle is performed under control of microinstruction at octal address 110. If the operation was completed, it indicates that there was no timing out or failure of memory and accordlngly a normal exception procedure is entered under control of microinstructions 111 and 112. However, if the ONC bit is set, it indicates that the operation was not completed due to a memory time out or some other malfunction and microinstruction at octal address 112 is skipped and microinstruction at octal address 113 on page 38 supra is executed. The secondary control block base CBB2 is then generated from the control block base register CBBR, Figure 2E, under control of firmware microinstructions at octal addresses 113, 114, 115, 116,117 and 120 also ~ound on page 38 supra. Utilizing this secondary control block base CBB2 a second address in another memory for the exception control block is generated utilizing the principles of address formation~
Accordingly, the system is not s~ut down because of a memory failure.

. i .

~ . .

1~5~63~3 ~ Iaving shown and described a preferred embodiment of the invention, those skilled in the art will realize that many - variations and modifications may be made to affect the described invention and still be within the scope of the claimed invention. Thus, many o the elements indicated above may be altered or replaced by different elements which will provide the same result and fall within the spirit of the claimed invention. It is the intention, therefore, to limit the invention only as indicated by the scope of the claims.
What is claimed is:

. ::

_~9_ ~

..... .....

Claims (15)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A fail soft mechanism in a general purpose computer system having at least one processor, said fail soft mechanism for automatically providing an alternate addressing path for addressing data in a second portion of main memory when a failure is detected in a first portion of main memory, said mechanism comprising: a. first means for addressing a first control block means in a first portion of main memory of said computer system, said first means further comprising:
1. a first interrupt control block addressing means for storing signals indicating a first part of the address of the first control block means in said first portion of said main memory;
2. a first control block addressing means for storing signals indicating a second part of the address of said first control block means in said first portion of said main memory;
and, 3. a first combining means coupled to be responsive to said first interrupt control block addressing means and to said first control block addressing means for combining the first part and second part of the address of said first control block means; b. second means coupled to be responsive to said first means, for detecting a failure in the first portion of main mem-ory addressed by said first means; and, c. third means, coupled to be responsive to said second means, for automatically provid-ing an alternate path to a second portion of main memory upon detection of a failure in said first portion of main memory, said third means further comprising;
1. a second interrupt control block addressing means for storing signals indicating a first part of the address of a second interrupt control block means in said second portion of said main memory;
2. a second control block addressing means for storing signals indicating a second part of the address of the second interrupt control block means in said second portion of said main memory; and, 3. second combining means coupled to be responsive to said second interrupt control block addressing means and to said second control block addressing means, for combining the first and second part of the address of the second interrupt control block means in said second portion of said main memory.
2. The fail soft mechanism as recited in claim 1 wherein said processor is executing instructions of a current process and further including fourth means coupled to said second means for generating signals interrupting said processor when a failure in the first portion of main memory addressed by said first means is detected.
3. The fail soft mechanism as recited in claim 2 including fifth means responsive to said second combining means for gener-ating signals for developing in said main memory a stack address, said stack for storing information about the currently executing process to permit returning to the currently executing process upon the termination of the interruption of said processor.
4. In a data processing system having at least one proces-sor sequentially executing instructions of a first one of a plurality of processes each of said processes having a priority level based on the relative importance to the other of said pro-cesses, and with any of said processes requesting control of said processor, said data processing system having at least one local random access memory and one random access main memory, a fail soft mechanism for automatically providing an addressing path to said main memory when a failure is detected in said local memory, said fail soft mechanism comprising: a. first means for providing an interrupt signal when a higher priority process than said first one of said plurality of processes requests con-trol of said processor; b. second means, coupled to be respon-sive to said first means, for detecting said interrupt signal;
c. third means, coupled to be responsive to said second means for addressing a first predetermined portion within the local memory of said computer system said third means further compris-ing;
1. a first interrupt control block addressing means for storing signals indicating a first part of the address of said first predetermined portion of said local memory;
2. a first control block addressing means for storing signals indicating a second park of the address of said first predetermined portion of said local memory; and, 3. first combining means coupled to be responsive to said first interrupt control block addressing means and to said first control block addressing means for combining said first and second part of the address; d. fourth means, coupled to be res-ponsive to said third means, for detecting a failure in said local memory; and, e. fifth means, coupled to be responsive to said fourth means, for automatically providing an alternate ad-dressing path to said main memory, said alternate addressing path comprising;
1. a second interrupt control block addressing means for storing signals indicating a first part of the address of a predetermined portion of said main memory;
2. a second control block addressing means for storing signals indicating a second part of the address of said predeter-mined portion of said main memory; and, 3. second combining means coupled to be responsive to said second interrupt control block addressing means and to said sec-ond control block addressing means for combining the first and second part of the address of said predetermined portion of main memory.
5. In a data processing system having at least one pro-cessor sequentially executing instructions of a first one of a plurality of processes each of said processes having a priority level based on the relative importance to the other of said processors, and with any of said processes requesting control of said processor, said data processing system having at least one local random access memory and at least one random access main memory, said at least one local random access memory having a first predetermined portion for storing instructions of a pre-determined second process of said group of processes, and said at least one random access main memory having a second predetermined portion for storing instructions of said predetermined second process of said group of processes, said second process stored in said local and main memory for handling exceptions detected by said processor, a fail soft mechanism comprising: a. a first addressing path further comprising;
1. first means for storing first coded signals represent-ing the absolute address, within said local memory, of a third portion of local memory, said third portion of local memory for storing a plurality of groups of second coded signals, a prede-termined first group of said group of second coded signals for indicating the address of said first predetermined portion of said local random access memory;
2. second means for storing third coded signals represent-ing the relative address within said third portion of local mem-ory of said predetermined first group of said group of second coded signals within said third portion of local memory; and, 3. third means coupled for being responsive to said first and second means for combining the first and third coded signals whereby the absolute address within said local memory of the predetermined one of said plurality of second coded signals is generated; b. a second addressing path comprising;
1. fourth means for storing fourth coded signals repre-senting the absolute address, within said main memory, of a fourth portion of said main memory, said fourth portion of main memory for storing a plurality of groups of fifth coded signals, a predetermined first group of said group of fifth coded signals for indicating the address of said second portion of said main memory;
2. fifth means for storing sixth coded signals represent-ing the relative address within said fourth portion of main mem-ory of said predetermined first group of said plurality of groups of fifth coded signals within said fourth portion of main memory;
and, 3. sixth means coupled for being responsive to said fourth and fifth means for combining the fourth and sixth coded signals whereby the absolute address within said main memory of the pre-determined one of said plurality of fifth coded signals is gen-erated; c. seventh means coupled to be responsive in said third means for storing coded signals for indicating said second ad-dressing path is to be utilized when said first addressing path is defective.
6. The fail soft mechanism as recited in claim 5 includ-ing eighth means coupled to be responsive to said seventh means for generating a first sequence of signals for causing said sec-ond addressing path to be used in accessing instructions in said second process.
7. The fail soft mechanism as recited in claim 6 wherein a fifth portion of said main memory stores coded signals indica-tive of the status of said first one of said plurality of pro-cesses when it is interrupted, and further including ninth means addressed by said fourth means for storing coded signals for indicating the address of said fifth portion of main memory.
8. The fail soft mechanism as recited in claim 7 includ-ing tenth means coupled to be responsive to said seventh means for generating a second sequence of signals for causing signals representing the status of said first one of said plurality of processes to be safe-stored in said fifth portion of main memory.
9. In a data processing system having a plurality of pro-cessors coupled to an interface unit via predetermined processor communication channels each processor being selectively control-led by selected ones of a first group of processes, each proces-sor having a plurality of registers accessible to any of the processes, each processor further having at least one local memory, said data processing system also having a plurality of main memories coupled to said interface unit via predetermined memory communication channels for communicating with each other and with said processors, each communication channel having an address identified by a predetermined steering code, each pro-cess and each peripheral channel being associated with a pre-determined level of priority, said system interface unit having an interrupt mechanism for interrupting said selected ones of said first group of processes, said data processing system fur-ther having monitoring means for monitoring interrupt request signals from a plurality of a second group of processes request-ing control of said processors, a fail soft mechanism compris-ing: a. a first addressing path further comprising;
1. a first interrupt control block in a first one of said main memories, said first interrupt control block for storing first coded signals indicating the address of first interrupt handling process in said main memory;

2. a first interrupt register for storing second coded signals indicating a first partial address of said first inter-rupt control block in said first one of said main memories;
3. a first primary control block register for storing third coded signals indicating a second partial address of said first interrupt control block in said first one of said main memories;
4. a first combining means coupled to be responsive to said first interrupt register and to said first primary control block register for combining the second and third coded signals, whereby the whole address of said first interrupt control block in said first one of said main memory is generated; b. a second addressing path further comprising;
1. a second interrupt control block in a second one of said local memories, said second interrupt control block for storing fourth coded signals indicating the address of a second interrupt handling process in said local memory;
2. a second interrupt register for storing fifth coded signals indicating a first partial address of said second inter-rupt control block in said second one of said local memories;
3. a second primary control block register for storing sixth coded signals indicating a second partial address of said second interrupt control block in said second one of said local memories;
4. a second combining means coupled to be responsive to said second interrupt register and to said second primary control block register for combining the fifth and sixth coded signals whereby the whole address of said second interrupt control block in said second one of said local memories is generated; c. first means is said first addressing path for storing seventh coded signals indicating whether or not said first addressing path is defective.
10. The fail soft mechanism as recited in claim 9 includ-ing second means coupled for being responsive to said first means for generating first control signals causing said first addressing path to be utilized in addressing said first inter-rupt handling process, when said seventh coded signals indicate said first address path is not defective.
11. The fail soft mechanism as recited in claim 10 includ-ing third means in said first interrupt control block for stor-ing eighth coded signals indicating the address in said first one of said main memories of a first stack.
12. The fail soft mechanism as recited in claim 11 includ-ing fifth means responsive to said second means for generating second control signals causing predetermined information pertin-ent to said selected one of said first group of processes to be stored in said first stack.
13. The fail soft mechanism as recited in claim 9 includ-ing sixth means coupled for being responsive to said first means for generating third control signals causing said second addres-sing path to be utilized in addressing said second interrupt handling process, when said seventh coded signals indicate said first addressing path is defective.
14. The fail soft mechanism as recited in claim 13 includ-ing seventh means in said second interrupt control block for storing ninth coded signals indicating the address in said sec-ond one of said local memories of a second stack in said second one of said local memories.
15. The fail soft mechanism as recited in claim 14 includ-ing eighth means responsive to said second means for generating fourth control signals causing predetermined information pertin-ent to said selected one of said first group of processes to be stored in said second stack.
CA244,779A 1975-03-26 1976-02-02 Fail soft memory Expired CA1059638A (en)

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US4010450A (en) 1977-03-01
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GB1547386A (en) 1979-06-20
DE2612034A1 (en) 1976-10-14

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