CA1038498A - Minutiae recognition system with means to detect merger of lines only once - Google Patents
Minutiae recognition system with means to detect merger of lines only onceInfo
- Publication number
- CA1038498A CA1038498A CA203,050A CA203050A CA1038498A CA 1038498 A CA1038498 A CA 1038498A CA 203050 A CA203050 A CA 203050A CA 1038498 A CA1038498 A CA 1038498A
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- Prior art keywords
- lines
- signal
- logic
- circuit
- merger
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/1347—Preprocessing; Feature extraction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/40—Extraction of image or video features
- G06V10/44—Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
- G06V10/457—Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components by analysing connectivity, e.g. edge linking, connected component analysis or slices
Abstract
IMPROVED MINUTIAE RECOGNITION SYSTEM
Abstract of the Disclosure A system for detecting bifurcations and ridge endings (minutiae) in a fingerprint or on similar patterns in which two lines merge into one. The print is optically scanned, converted into electrical signals and entered into a novel continuity logic network. The presence of a bifurcation in the network results in three distinct outputs on the peri-phery of the network from at least two sides. The split in the bifurca-tion may also be detected by reversing the polarity of the electrical signals and detecting a single output. Means are also provided for ensuring that a single bifurcation is detected only once. Ridge endings are treated as reverse-polarity bifurcations and can be detected by the same system elements.
Abstract of the Disclosure A system for detecting bifurcations and ridge endings (minutiae) in a fingerprint or on similar patterns in which two lines merge into one. The print is optically scanned, converted into electrical signals and entered into a novel continuity logic network. The presence of a bifurcation in the network results in three distinct outputs on the peri-phery of the network from at least two sides. The split in the bifurca-tion may also be detected by reversing the polarity of the electrical signals and detecting a single output. Means are also provided for ensuring that a single bifurcation is detected only once. Ridge endings are treated as reverse-polarity bifurcations and can be detected by the same system elements.
Description
: `
'' .~038~W
1 Cross Reference to a Related Application This application is related to U.S. patent 3,893,080 A.P. Ho and H.T. Lee, entitled Minutiae Recognition System and assigned to the same assignee as the present application.
Back~round of the Invention Field of the Invention This invention relates to the detection of the merger of lines in -~
a pattern of lines and spaces. More particularly, the invention relates to the detection of minutiae in a fingerprint.
Description of the Prior Art The importance of accurate and automated fingerprint identification and vertification requires no extended discussion. Law enforcement agencies such as the Federal Bureau of Investigation have been encour-aglng and soliciting the electronics industry to develop an automatic fingerprint identification processor. The broad details of such a pro-cessing system are well known and many facets of such a system are well - -within today's technology. The most widely accepted system comprises optically scanning a fingerprint or a transparency thereof, converting it into electrical signals, detecting and storing the unique character-istics of the given fingerprint whereby it may be compared to informa-tion already in storage and the results of the comparison retrieved from storage for identification or verification purposes.
Within the last few years, many researchers in this field have settled on the detection and location of ridge endings and bifurcations in the fingerprint as the most likely way to succeed. It has been demonstrated that these so-called minutiae afford positive identifica-tion. In practice, minutiae recognition is quite difficult. The pri-mary difficulty is that the quality of the fingerprints varies greatly in contrast and clarity. In addition, the width of the ridges and valleys, i.e., the distance between ridge centres, varies widely. Vari-; ous proposals to solve this problem have been suggested and many have been implemented with varying degrees of success. Many of these systems ~1.038498 1 appear in the patent literature and are familiar to those of skill in theart. Hence extended discussion is deemed unnecessary. Suffice it to say that to our knowledge none of the prior art systems have been used suc-cessfully in field operations of law enforcement agencies or by others who would use such a system, as for example, issuers of credit cards.
; Summary of the Inv_ntio_ It is therefore an object of the present invention to improve the recognition of minutiae in patterns such as fingerprints.
It is another object of this invention to do so efficiently, using electronic equipment and circuits which are commercially available.
It is yet another object of our invention to provide circuits for accurately determining the presence of minutiae in a fingerprint.
These and other objects and advantages are provided by impressing digital electrical representations of areas of the fingerprint on a first continuity logic network for recognizing bifurcations and ridge endings.
For a bifurcation, the network generates three positive output signals.
Ridge endings may be detected by inverting the input signals from the print. This reversal causes the network to also generate a positive output signal for a ridge ending.
In the preferred embodiment of the invention, a second continuity logic network is provided which has impressed thereon the reversal of the electrical signals to detect the split in the bifurcation or the area around the ridge endings.
Novel decision circuits are provided for determining the existence of bifurcations, splits, ridge endngs and the area around the ridge endings.
Means are also provided to inhibit the recognition of the same minutia twice.
The present system is applicable generally to the identification of any pattern which consists of contrasting lines and spaces and where two lines merge into one. For example, the testing and classification of conductive lines on printed circuits could also be accomplished with . ~ . . ~ ., ~ .............. . . .
; : : . ~ . .
1~384~8 1 the present invention. The conductive lines are highly reflective in comparison with the substrate on which the lines are deposited.
Brief Description of the Drawings FIG. 1 is a block diagram of the preferred embodiment of a bifurca-; tion recognition system.
FIGS. 2 and 3 are illustrations of the continuity logic network14 and 14' each respectively having electrical representations of a bifurcation and of a split impressed thereon.
FIG. 4 is an electrical circuit diagram illustrating the detailed - 10 construction of individual points in networks 14 and 14'.
FIG. 5 is an illustration of the circuit diagram in FIG. 4 com-prising field effect transistors.
FIG. 6 is a detailed diagram of tri-leg decision logic circuit 18.
FIG. 7 is a timing diagram illustrating the timing relationship of pertinent signals within logic block 18.
FIG. 8 is a detailed diagram of split decision logic block 16 illustrated in FIG. 1.
FIG. 9 is a timing diagram illustrating the timing relationship of pertinent signals within logic block 16.
FIG. 10 is a detailed diagram of coordinate discriminator 19 illustrated in FIG. 1 and its connection to selected points in con-tinuity logic network 14.
FIG. 11 illustrates the operation of coordinate discriminator 19. ;~
Description of the Preferred Embodiment The following description is with respect to the detection of bi-furcations and splits in bifurcations only. A bifurcation is the merger of two ridges into a single ridge. A ridge ending is the termination of a ridge in the fingerprint and appears as a negative of a bifurca-tion. Therefore, the present system can be used to detect ridge endings merely by inverting the polarity of the Yideo signals. Therefore, a detailed discussion of the system with respect to bifurcations and splits is all that is necessary to encompass minutiae detection in :~ :
:`
1 general. 1~38498 With reference to the overall system illustrated in FIG. 1, a fingerprint 2, which is suitably illuminated, is scanned by scanner 3 .
which generates video signals representative of the ridges and spaces within fingerprint 2. The analog signals are transmitted to enhancer 4 before being converted to binary signals by digitizer 5.
The elements just described have been used in various fingerprint systems and comprise no part of the present invention. Fingerprint 2 may be an actual print impressed on a prism or may be a transparency of a print suitably illuminated so that it can be scanned by scanner 3 which typically would be a flying spot scanner, a TV camera i or Vidicon, all of which are commercially available to generate a video ; signal. Enhancer 4 acts as a ridge-valley filter to accentuate the dif-ference in contrast between the ridges of the print and the valleys between the ridges. Various types of enhancement techniques could be used for taking into account the gradual gradations in lighting over the surface of the fingerprint. One such circuit is described by W.K.
Rackl in a publication entitled "Dynamic Threshold Circuit", IBM
Technical Disclosure Bulletin Volume 15, No. 4 September 1972 pp. 1138-1139. Other enhancement techniques for filling in small breaks and ridges, separating blurred valleys and editing blank or heavily smeared , areas have also been developed. These techniques may be applied to the transparency of the print itself prior to entry into the recognition sytem or in an on-line device as illustrated.
The analog signal in.dicative of the pattern at a selected position on the print is quantized into binary signals by digitizer 5. Digitizer 5 is preferably an Analog-Digital Converter of standard design capable of ~-sampling the video signal at a 1 MHz rate resulting in a matrix of 350 X 262 points representative of point 2. The binary signals are then transmitted to temporary memory 8 which comprises a plurality of digital shift registers 8A, 8B, ... 8L accessed in parallel. In the present embodiment each shift register has N = 350 individual locations ~ - .
and there are twelve such shift registers, thereby proYiding temporary storage for 4200 bits of information at any given instant, or twelve video lines.
After the 4200 bits of information have been stored in temporary storage 8 they are transmitted seriatim to a set of 12-bit shift regis-ters 9 and through inverters 10 to a corresponding set of 12-bit shift registers 12.
Each set of shift registers 9 and 12 comprise twelve individual shift registers, thereby providing simultaneous indications of 144 bits 10 of information to continuity logic networks 14 and 14', respectively.
Networks 14 and 14' will be described in greater detail in later sections of this specification. In general, they serve as storage means for the digital representations of a particular section of fingerprint 2 which has been scanned and digitized. It is from this digital repre-sentation that the detection of a bifurcation in electrical form is accomplished.
The periphery of networks 14 and 14' have output lines connected to the inputs of parallel-to-serial converters 15 and 17, respectively.
Thus, the periphery of network 14 which in a 12 X 12 matrix, comprises 44 circuits, are connected to converter 15 through cables 73, 74, 75 and 76 as indicated in FIG. 1. Similarly, the 44 peripheral circuits of matrix 14' are connected to the inputs of converter 17 through cables 54, 55, 56 and 57. Converters 15 and 17 are clocked at 44 MHz to syn-chronize their operation with the rest of the system.
Network 14' indicates whether there are three legs of a bifurca-tion present. The peripheral outputs stored in converter 17 are trans-mitted to a TRI-LEG decision logic circuit 18 which determines the existence of three legs. A positive output from logic circuit 18 via connection 82 is transmitted to AND circuit 21.
Network 14 serves to identify the split in the bifurcation noted in network 14'. SPLIT decision logic circuit 16 generates a positive output on connection 80 to AND circuit 21 if a split is found.
1(~3849~3 1 Certain of the circuits at the center of network 14 haYe outputs on cable 77 to COORDINATE DISCRIMINATOR 19. In addition, outputs 79 from logic circuit 16 have inputs to discriminator 19. As will be more fully described in a later section of this specification, discriminator 19 serves to block the recognition of the same bifurcation more than once.
The output from discriminator 19 is also transmitted to AND circuit 21 through connection 81. The coincidence of outputs from logic circuits 18, 16 and 19 at AND gate 21 generate an output indicative of a bifurca-tion.
When the criteria of a bifurcation are satisfied, the coordinates of this point on the fingerprint are stored in a suitable memory (not shown). In addition, the point may be superimposed on a bright spot on the print as viewed from a TV monitor.
FIG. 2 illustrates the presence of an exemplary bifurcation which -is impressed on continuity logic network 14'. Network 14' comprises a source of potential, +V, at the centre of a 12 X 12 matrix. The +V
source functions as a continuity signal. Each matrix point is a logic circuit which functions to generate an output upon the coincidence of a signal from its corresponding storage location in shift register 12 and a signal from one of the four matrix points located adjacent and orthogonal to it. For example, an input to circuit 5-4 of network 14' -from its associated position in the shift register array 12 plus an input received from either one of circuits 5-3, 5-5, 4-4, or 6-4 causes circuit 5-4 to generate an output. In similar fashion, peri-pheral circuit 1-2 is associated with three circuits: 1-1, 1-3 and 2-2.
An output signal from one such circuit is transmitted to the inputs of the adjacent, orthogonal matrix points. Thus, there is a two-way path between a circuit at any given matrix point and its adjacent, orthogonal circuits, whereby any such circuit can energize or become energized by `--the adjacent, orthogonal circuits in conjunction with signals received ~ -from shift registers 12. -As illustrated by the heavy shaded lines in FIG. 2, a bifurcation . 10;~8498 1 is represented by three distinct sets of grouped output signals from the +V source to the periphery of the matrix. A continuous output from ~V to one of the peripheral output lines is indicated by a logical '1' in FIG. 2; and an output which is not connected to the +V source is indicated by a logical 'O'. Only a single such conductive path from +V to the periphery is necessary to constitute a leg of a bifurca-tion. The logical 'O' signals on the periphery serve to separate the individual legs of the bifurcation. For a continuity path to be established, it is necessary that at least one of four elements 6-6, ; 10 6-7, 7-6 or 7-7 receive a signal from shift register 9.
FIG. 3 illustrates an exemplary illustration of the split in the bifurcation illustrated in FIG. 2. As previously noted with respect to FIG. 1 the binary signals from the print are transmitted to network 14 in their 'true' (logical '1') form whereas the signals transmitted to network 14' are inverted (logical 'O'). The legs of a bifurcation on a fingerprint appear as blank or white video dots and the split appears as a black video dot, the latter being represented by a logical '1' in the system.
As shown in heavy lines in FIG. 3, the split in the bifurcation is represented by a single set of grouped output potentials from +V to the periphery of the matrix. As with the bifurcations in FIG. 2, it is necessary that continuity exist from the centre of the matrix having the potential of +V to the periphery without any open connections for the split to be detected. Thus, there are other points in the matrix which receive signals from their corresponding storage locations in shift registers 9 such as point 1-1; but no output will be generated at the periphery of the matrix because there is no continuous conductive path from the potential source +V to that point.
The recognition of both the bifurcation as well as the split in the bifurcation is necessary due to the noise level caused by the video portion of the system. Without the noise problem only matrix 14' would be necessary.
1(~384C~8 1 An alternate technique for determining the existence of the three legs and the split in the bifurcation is to use an alternate-polarity systern. In such a system, a polarity control gate would be inserted between temporary memory 8 and shift registers 9. Network 14' shift registers 12 and inverters 10 would be eliminated. However, this type of system requires that the polarity of the video signal change with each video line, increasing the complexity of the system.
Turning now to FIG. 4 there is shown a submatri,~ of logic gates : . :
which comprise the matrix of logic networks 14 and 14'. Each circuit enclosed by dotted lines corresponds to one element in the matrix.
Referring to circuit 1-1 as being exemplary of the 144 circuits in a 12 X 12 matrix, it comprises AND gate 120 having a pair of inputs 201 and 121a plus a ~ input. Wire 201 emanates from storage location 1 in shift register 9A of the shift register array 9. Input connection ; 121a is the output from OR gate 121. The reset line is ordinarily at a logical '1' level during the gating time and is actuated in conjunc-tion with all other reset lines so as to clear the matrix between cycles.
The inputs to OR gate 129 are received from the outputs of the AND gates of the circuits which are adjacent and orthogonally located with respect to circuit 2-2, i.e., 1-2, 2-1, 3-2 and 2-3. In similar fashion the sin-gle output from AND gate 128 is connected to the inputs of each of the four adjacent and orthogonally placed logic circuits. Thus, in general, each circuit in continuity logic network 14 and 14' both: (1) addresses and (2) is addressed by the four circuits associated with it.
An understanding of the operation of the circuit in FIG. 4 results in a better understanding of the operation of networks 14 and 14'.
Assume that logical '1' signals are stored in the locations of shift register 12 associated with circuits 1-2, 2-2, 2-3 and 3-3. Logical 'O' signals are stored at the shift register locations associated with the remaining circuits 1-1, 1-3, 2-1, 3-1 and 3-2 in the submatrix.
If other circuits in the matrix are energized such that the potential source +V is propagated to line 142a, then a logical !1l (+V) will be .
.
10384~8 1 generated on line 54b at the periphery of the matrix. Because line 142a is at a '1' level, the output line 137a of OR gate 137 is also at a '1' level. Input 227 is at a '1' level as previously indicated; and gate 136 generates a logical '1' output. A logical '1' output from gate 136 is fed via lines 136a and 136c to the inputs of circuits 2-3 and 3-2, respectively. However, only circuit 2-3 can generate an out-put because the AND gate 130 is rendered inactive due to the logical 'O' signals on lines 226. The logical '1' signal on line 136a is gated through OR circuit 135 on line 135a to generate a logical '1' in conjunction with the logical '1' on input 215 from AND gate 134.
Circuit 2-2 is gated in similar fashion so that the signal on line 128a is a logical '1'. This signal then gates circuit 1-2 to generate an output at peripheral connection 54b. No outputs are generated on the other peripheral lines.
FIG. 5 illustrates the circuits which comprise the continuity logic network fabricated in the form of field effect transistors. Field effect transistors are chosen as the preferred embodiment of these matrix cir-cuit elements because of their relatively small cost, ease of fabrication in integrated circuit form and noise immunity. It will be clear to those of skill in this art that other types of circuits could be used to per-form the same function. For example, bipolar transistors configured as TTL circuits or current switch emitter follower circuits can per-form the same functions. At the present state of the art the configura-tion of these circuits into AND and OR gates are quite well known and no further description is required.
For brevity and ease of illustration, only circuits 1-1, 1-2 and
'' .~038~W
1 Cross Reference to a Related Application This application is related to U.S. patent 3,893,080 A.P. Ho and H.T. Lee, entitled Minutiae Recognition System and assigned to the same assignee as the present application.
Back~round of the Invention Field of the Invention This invention relates to the detection of the merger of lines in -~
a pattern of lines and spaces. More particularly, the invention relates to the detection of minutiae in a fingerprint.
Description of the Prior Art The importance of accurate and automated fingerprint identification and vertification requires no extended discussion. Law enforcement agencies such as the Federal Bureau of Investigation have been encour-aglng and soliciting the electronics industry to develop an automatic fingerprint identification processor. The broad details of such a pro-cessing system are well known and many facets of such a system are well - -within today's technology. The most widely accepted system comprises optically scanning a fingerprint or a transparency thereof, converting it into electrical signals, detecting and storing the unique character-istics of the given fingerprint whereby it may be compared to informa-tion already in storage and the results of the comparison retrieved from storage for identification or verification purposes.
Within the last few years, many researchers in this field have settled on the detection and location of ridge endings and bifurcations in the fingerprint as the most likely way to succeed. It has been demonstrated that these so-called minutiae afford positive identifica-tion. In practice, minutiae recognition is quite difficult. The pri-mary difficulty is that the quality of the fingerprints varies greatly in contrast and clarity. In addition, the width of the ridges and valleys, i.e., the distance between ridge centres, varies widely. Vari-; ous proposals to solve this problem have been suggested and many have been implemented with varying degrees of success. Many of these systems ~1.038498 1 appear in the patent literature and are familiar to those of skill in theart. Hence extended discussion is deemed unnecessary. Suffice it to say that to our knowledge none of the prior art systems have been used suc-cessfully in field operations of law enforcement agencies or by others who would use such a system, as for example, issuers of credit cards.
; Summary of the Inv_ntio_ It is therefore an object of the present invention to improve the recognition of minutiae in patterns such as fingerprints.
It is another object of this invention to do so efficiently, using electronic equipment and circuits which are commercially available.
It is yet another object of our invention to provide circuits for accurately determining the presence of minutiae in a fingerprint.
These and other objects and advantages are provided by impressing digital electrical representations of areas of the fingerprint on a first continuity logic network for recognizing bifurcations and ridge endings.
For a bifurcation, the network generates three positive output signals.
Ridge endings may be detected by inverting the input signals from the print. This reversal causes the network to also generate a positive output signal for a ridge ending.
In the preferred embodiment of the invention, a second continuity logic network is provided which has impressed thereon the reversal of the electrical signals to detect the split in the bifurcation or the area around the ridge endings.
Novel decision circuits are provided for determining the existence of bifurcations, splits, ridge endngs and the area around the ridge endings.
Means are also provided to inhibit the recognition of the same minutia twice.
The present system is applicable generally to the identification of any pattern which consists of contrasting lines and spaces and where two lines merge into one. For example, the testing and classification of conductive lines on printed circuits could also be accomplished with . ~ . . ~ ., ~ .............. . . .
; : : . ~ . .
1~384~8 1 the present invention. The conductive lines are highly reflective in comparison with the substrate on which the lines are deposited.
Brief Description of the Drawings FIG. 1 is a block diagram of the preferred embodiment of a bifurca-; tion recognition system.
FIGS. 2 and 3 are illustrations of the continuity logic network14 and 14' each respectively having electrical representations of a bifurcation and of a split impressed thereon.
FIG. 4 is an electrical circuit diagram illustrating the detailed - 10 construction of individual points in networks 14 and 14'.
FIG. 5 is an illustration of the circuit diagram in FIG. 4 com-prising field effect transistors.
FIG. 6 is a detailed diagram of tri-leg decision logic circuit 18.
FIG. 7 is a timing diagram illustrating the timing relationship of pertinent signals within logic block 18.
FIG. 8 is a detailed diagram of split decision logic block 16 illustrated in FIG. 1.
FIG. 9 is a timing diagram illustrating the timing relationship of pertinent signals within logic block 16.
FIG. 10 is a detailed diagram of coordinate discriminator 19 illustrated in FIG. 1 and its connection to selected points in con-tinuity logic network 14.
FIG. 11 illustrates the operation of coordinate discriminator 19. ;~
Description of the Preferred Embodiment The following description is with respect to the detection of bi-furcations and splits in bifurcations only. A bifurcation is the merger of two ridges into a single ridge. A ridge ending is the termination of a ridge in the fingerprint and appears as a negative of a bifurca-tion. Therefore, the present system can be used to detect ridge endings merely by inverting the polarity of the Yideo signals. Therefore, a detailed discussion of the system with respect to bifurcations and splits is all that is necessary to encompass minutiae detection in :~ :
:`
1 general. 1~38498 With reference to the overall system illustrated in FIG. 1, a fingerprint 2, which is suitably illuminated, is scanned by scanner 3 .
which generates video signals representative of the ridges and spaces within fingerprint 2. The analog signals are transmitted to enhancer 4 before being converted to binary signals by digitizer 5.
The elements just described have been used in various fingerprint systems and comprise no part of the present invention. Fingerprint 2 may be an actual print impressed on a prism or may be a transparency of a print suitably illuminated so that it can be scanned by scanner 3 which typically would be a flying spot scanner, a TV camera i or Vidicon, all of which are commercially available to generate a video ; signal. Enhancer 4 acts as a ridge-valley filter to accentuate the dif-ference in contrast between the ridges of the print and the valleys between the ridges. Various types of enhancement techniques could be used for taking into account the gradual gradations in lighting over the surface of the fingerprint. One such circuit is described by W.K.
Rackl in a publication entitled "Dynamic Threshold Circuit", IBM
Technical Disclosure Bulletin Volume 15, No. 4 September 1972 pp. 1138-1139. Other enhancement techniques for filling in small breaks and ridges, separating blurred valleys and editing blank or heavily smeared , areas have also been developed. These techniques may be applied to the transparency of the print itself prior to entry into the recognition sytem or in an on-line device as illustrated.
The analog signal in.dicative of the pattern at a selected position on the print is quantized into binary signals by digitizer 5. Digitizer 5 is preferably an Analog-Digital Converter of standard design capable of ~-sampling the video signal at a 1 MHz rate resulting in a matrix of 350 X 262 points representative of point 2. The binary signals are then transmitted to temporary memory 8 which comprises a plurality of digital shift registers 8A, 8B, ... 8L accessed in parallel. In the present embodiment each shift register has N = 350 individual locations ~ - .
and there are twelve such shift registers, thereby proYiding temporary storage for 4200 bits of information at any given instant, or twelve video lines.
After the 4200 bits of information have been stored in temporary storage 8 they are transmitted seriatim to a set of 12-bit shift regis-ters 9 and through inverters 10 to a corresponding set of 12-bit shift registers 12.
Each set of shift registers 9 and 12 comprise twelve individual shift registers, thereby providing simultaneous indications of 144 bits 10 of information to continuity logic networks 14 and 14', respectively.
Networks 14 and 14' will be described in greater detail in later sections of this specification. In general, they serve as storage means for the digital representations of a particular section of fingerprint 2 which has been scanned and digitized. It is from this digital repre-sentation that the detection of a bifurcation in electrical form is accomplished.
The periphery of networks 14 and 14' have output lines connected to the inputs of parallel-to-serial converters 15 and 17, respectively.
Thus, the periphery of network 14 which in a 12 X 12 matrix, comprises 44 circuits, are connected to converter 15 through cables 73, 74, 75 and 76 as indicated in FIG. 1. Similarly, the 44 peripheral circuits of matrix 14' are connected to the inputs of converter 17 through cables 54, 55, 56 and 57. Converters 15 and 17 are clocked at 44 MHz to syn-chronize their operation with the rest of the system.
Network 14' indicates whether there are three legs of a bifurca-tion present. The peripheral outputs stored in converter 17 are trans-mitted to a TRI-LEG decision logic circuit 18 which determines the existence of three legs. A positive output from logic circuit 18 via connection 82 is transmitted to AND circuit 21.
Network 14 serves to identify the split in the bifurcation noted in network 14'. SPLIT decision logic circuit 16 generates a positive output on connection 80 to AND circuit 21 if a split is found.
1(~3849~3 1 Certain of the circuits at the center of network 14 haYe outputs on cable 77 to COORDINATE DISCRIMINATOR 19. In addition, outputs 79 from logic circuit 16 have inputs to discriminator 19. As will be more fully described in a later section of this specification, discriminator 19 serves to block the recognition of the same bifurcation more than once.
The output from discriminator 19 is also transmitted to AND circuit 21 through connection 81. The coincidence of outputs from logic circuits 18, 16 and 19 at AND gate 21 generate an output indicative of a bifurca-tion.
When the criteria of a bifurcation are satisfied, the coordinates of this point on the fingerprint are stored in a suitable memory (not shown). In addition, the point may be superimposed on a bright spot on the print as viewed from a TV monitor.
FIG. 2 illustrates the presence of an exemplary bifurcation which -is impressed on continuity logic network 14'. Network 14' comprises a source of potential, +V, at the centre of a 12 X 12 matrix. The +V
source functions as a continuity signal. Each matrix point is a logic circuit which functions to generate an output upon the coincidence of a signal from its corresponding storage location in shift register 12 and a signal from one of the four matrix points located adjacent and orthogonal to it. For example, an input to circuit 5-4 of network 14' -from its associated position in the shift register array 12 plus an input received from either one of circuits 5-3, 5-5, 4-4, or 6-4 causes circuit 5-4 to generate an output. In similar fashion, peri-pheral circuit 1-2 is associated with three circuits: 1-1, 1-3 and 2-2.
An output signal from one such circuit is transmitted to the inputs of the adjacent, orthogonal matrix points. Thus, there is a two-way path between a circuit at any given matrix point and its adjacent, orthogonal circuits, whereby any such circuit can energize or become energized by `--the adjacent, orthogonal circuits in conjunction with signals received ~ -from shift registers 12. -As illustrated by the heavy shaded lines in FIG. 2, a bifurcation . 10;~8498 1 is represented by three distinct sets of grouped output signals from the +V source to the periphery of the matrix. A continuous output from ~V to one of the peripheral output lines is indicated by a logical '1' in FIG. 2; and an output which is not connected to the +V source is indicated by a logical 'O'. Only a single such conductive path from +V to the periphery is necessary to constitute a leg of a bifurca-tion. The logical 'O' signals on the periphery serve to separate the individual legs of the bifurcation. For a continuity path to be established, it is necessary that at least one of four elements 6-6, ; 10 6-7, 7-6 or 7-7 receive a signal from shift register 9.
FIG. 3 illustrates an exemplary illustration of the split in the bifurcation illustrated in FIG. 2. As previously noted with respect to FIG. 1 the binary signals from the print are transmitted to network 14 in their 'true' (logical '1') form whereas the signals transmitted to network 14' are inverted (logical 'O'). The legs of a bifurcation on a fingerprint appear as blank or white video dots and the split appears as a black video dot, the latter being represented by a logical '1' in the system.
As shown in heavy lines in FIG. 3, the split in the bifurcation is represented by a single set of grouped output potentials from +V to the periphery of the matrix. As with the bifurcations in FIG. 2, it is necessary that continuity exist from the centre of the matrix having the potential of +V to the periphery without any open connections for the split to be detected. Thus, there are other points in the matrix which receive signals from their corresponding storage locations in shift registers 9 such as point 1-1; but no output will be generated at the periphery of the matrix because there is no continuous conductive path from the potential source +V to that point.
The recognition of both the bifurcation as well as the split in the bifurcation is necessary due to the noise level caused by the video portion of the system. Without the noise problem only matrix 14' would be necessary.
1(~384C~8 1 An alternate technique for determining the existence of the three legs and the split in the bifurcation is to use an alternate-polarity systern. In such a system, a polarity control gate would be inserted between temporary memory 8 and shift registers 9. Network 14' shift registers 12 and inverters 10 would be eliminated. However, this type of system requires that the polarity of the video signal change with each video line, increasing the complexity of the system.
Turning now to FIG. 4 there is shown a submatri,~ of logic gates : . :
which comprise the matrix of logic networks 14 and 14'. Each circuit enclosed by dotted lines corresponds to one element in the matrix.
Referring to circuit 1-1 as being exemplary of the 144 circuits in a 12 X 12 matrix, it comprises AND gate 120 having a pair of inputs 201 and 121a plus a ~ input. Wire 201 emanates from storage location 1 in shift register 9A of the shift register array 9. Input connection ; 121a is the output from OR gate 121. The reset line is ordinarily at a logical '1' level during the gating time and is actuated in conjunc-tion with all other reset lines so as to clear the matrix between cycles.
The inputs to OR gate 129 are received from the outputs of the AND gates of the circuits which are adjacent and orthogonally located with respect to circuit 2-2, i.e., 1-2, 2-1, 3-2 and 2-3. In similar fashion the sin-gle output from AND gate 128 is connected to the inputs of each of the four adjacent and orthogonally placed logic circuits. Thus, in general, each circuit in continuity logic network 14 and 14' both: (1) addresses and (2) is addressed by the four circuits associated with it.
An understanding of the operation of the circuit in FIG. 4 results in a better understanding of the operation of networks 14 and 14'.
Assume that logical '1' signals are stored in the locations of shift register 12 associated with circuits 1-2, 2-2, 2-3 and 3-3. Logical 'O' signals are stored at the shift register locations associated with the remaining circuits 1-1, 1-3, 2-1, 3-1 and 3-2 in the submatrix.
If other circuits in the matrix are energized such that the potential source +V is propagated to line 142a, then a logical !1l (+V) will be .
.
10384~8 1 generated on line 54b at the periphery of the matrix. Because line 142a is at a '1' level, the output line 137a of OR gate 137 is also at a '1' level. Input 227 is at a '1' level as previously indicated; and gate 136 generates a logical '1' output. A logical '1' output from gate 136 is fed via lines 136a and 136c to the inputs of circuits 2-3 and 3-2, respectively. However, only circuit 2-3 can generate an out-put because the AND gate 130 is rendered inactive due to the logical 'O' signals on lines 226. The logical '1' signal on line 136a is gated through OR circuit 135 on line 135a to generate a logical '1' in conjunction with the logical '1' on input 215 from AND gate 134.
Circuit 2-2 is gated in similar fashion so that the signal on line 128a is a logical '1'. This signal then gates circuit 1-2 to generate an output at peripheral connection 54b. No outputs are generated on the other peripheral lines.
FIG. 5 illustrates the circuits which comprise the continuity logic network fabricated in the form of field effect transistors. Field effect transistors are chosen as the preferred embodiment of these matrix cir-cuit elements because of their relatively small cost, ease of fabrication in integrated circuit form and noise immunity. It will be clear to those of skill in this art that other types of circuits could be used to per-form the same function. For example, bipolar transistors configured as TTL circuits or current switch emitter follower circuits can per-form the same functions. At the present state of the art the configura-tion of these circuits into AND and OR gates are quite well known and no further description is required.
For brevity and ease of illustration, only circuits 1-1, 1-2 and
2-1 are illustrated in FIG. 5. All of the remaining circuits in the matrix would be constructed in the same fashion as one of these circuits and further illustration would be redundant.
Upon examination of FIG. 5, it will be readily apparent that the field effect transistors in each circuit element have a common input line at their gate electrodes. For purposes of the present system, the lQ38498 1 field effect transistors are enhancement mode N channel devices and the standard terminology of gate, source, and drain is used for descriptive purposes. As is well known to those of skill in the art, the difference between the source and drain of modern field effect transistors does not lie in the structure of the transistor itself but merely in the manner of biasing. In N channel device termino10gy the source is generally connected to the positive bias and the drain is generally connected to ~ ~ -a lower potential.
The correlation between the field effect transistor circuit in FIG. 5 and the logic circuit of FIG. 4 can be appreciated by referring specifically, for example, to circuit 2-2, as this represents the most complicated circuit in the matrix of logic circuits which comprise the continuity logic network.
The numbered inputs to OR gate 129 in FIG. 4 correspond to the identically numbered inputs to the source regions of transistors 306, 307, 308 and 309. The numbered outputs from AND gate 128 in FIG. 4 also correspond to the identically numbered outputs from the source regions.
Thus the source regions form a two way link between associated circuits.
There is one field effect transistor for each circuit which is associated with the circuit under consideration. Thus, circuit 2-2, --which has four circuits located adjacent and orthogonally with respect to it, contains four field effect transistorsi whereas circuits 1-2 and 1-1 contain three and two field effect transistors respectively because of their positions at the periphery of the matrix. The outputs at the periphery are taken from the common drain connections at circuits 1-1 -and 1-2 through load resistors 312 and 313, respectively, which have values of around 500 ohms. The resistors function to prevent the drain nodes from floating. In the operation of circuit 2-2, a positive sig-nal from shift register 12b on ljne 214 gates FET's 306-309. A posi-tive continuity signal ~V from one of the associated circuits 2-1, 1-3, 2-3 or 3-2 is then gated through the source of the associated FET 306, 307, 308 or 309, respectively. This signal is then available at the other .: .
1 FET sources to energize other circuits associated with circuit 2-2. If a signal is received by circuit 1-2 on line 202, the continuity signal from the +V continuity source appears at line 54b to be detected by logic circuit 18.
The FET configuration in FIG. S requires amplifier circuits at selected locations in the matrix to boost the signal level. However, their inclusion is a matter of design choice and is omitted for ease of illustration.
Turning now to FIG. 6 and 7, TRI-LEG decision logic circuit 18 is shown in more detail in conjunction with a timing diagram of waveforms generated within the circuit responsive to the outputs from continuity logic network 14'. As previously discussed, a bifurcation superimposed on network 14' generates a set of three distinct groups of logical '1' output signals. Each such group is separated by at least one logical '0' signal.
Circuit 18 performs two functions. Primarily it functions as a means for generating an output at line 82 indicative of the identifi-cation of three and only three distinct groups of signals indicative of a bifurcation. In addition, circuit 18 operates to reject any set of three groups in which any single group of signals contains more than a predetermined number of logical '1' signals. This latter function is a noise check to eliminate the results of a blurred impression or other imperfections generated from network 14'.
The primary three-leg identification function is performed by burst counter 31 and decoder 32. Counter 31 generates outputs in binary coded decimal form depending on the number of group of signals received from converter 17. Decoder 32 is responsive to the outputs from burst counter 31 and has a single operative output line which generates an output signal only upon the incidence a signal indicative of three groups of signals.
The aforementioned rejection feature is performed by N-count multi-vibrator 33 and gating elements which comprise inverters 34 and 37, AND
.
.
~0384~8 1 gate 35 and latch 36. In the present embodiment it is desired to reject a set in which any group contains more than five pulses. The cycle time ;
of decision circuit 18 is sufficiently long to receive the forty-four signals contained in converter 17 which stores the outputs of the peri-phery of network 14' and transmits the pulses in serial fashion along line 58 to logic circuit 18. Thus a CLOCK SET line is provided at latch j 36 to reset circuit 18 after 44 cycles. Converter 15 must be designed to operate at a much faster rate than the remainder of the system. In the preferred embodiment, the system clock operates at a 1 MHz rate and converter 15 operates at a 44 MHz rate.
It is noted at this point that each of the circuits illustrated in block 18 is well known to those of skill in the art and commercially available. The operation of the reject circuitry is illustrated by way of example in FIG. 7. A set of three groups of signals is trans-mitted from converter 17 to decision circuit 18. The groups contain four, five and six pulses respectively. As previously mentioned, it is desired to ignore more than five pulses in any group; therefore N-count multivibrator 36 is set to N = 5. Upon the receipt of a first pulse in the first group, multivibrator 33 generates five pulses irrespective of the number of pulses in the group at node A. Inverter 34 inverts the signal from multivibrator 33 as shown at node B. Because node B is at a down, or logical 'O' level, AND gate 35 generates a down level output at node C, thereby holding latch 36 to a negative level. The negative ~-~
level of latch 36 is inverted at inverter 38 to a true or logical '1' level. Upon the receipt of an indication of three distinct groups from decoder 32, AND gate 38 is activated and generates a logical '1' signal on line 82 during the clock cycle.
As shown in FIG. 7 a similar action occurs for the second group which consists of five signals from converter 17. The third group of pulses, however, contains six pulses which is one more than the maximum allowed. In this event there is a coincidence of logical '1' signals at AND gate 35, thereby setting latch 36 to an up or logical '1' level.
: :-.
. '' ' ' - ' : ~ ' : .
~0384~8 1 Inverter 37 inverts the signal to a down level or logical '0', causing the output from AND gate 38 to become a logical '0' during the 1 micro-` second clock cyc1e. This causes the output on line 82 to AND gate 21 to be a logical '0' and results in the rejection of the false impression of a bifurcation.
A Decision at gate 21 is made only at the end of each 44 subcycles.
Hence, the set of pulses from converter 17 would be rejected ln toto.
Referring now to FIGS. 8 and 9, SPLIT decision logic circuit 16 is illustrated in conjunction with a timing diagram of wave forms generated within the circuit responsive to the outputs from continuity logic net-work 14. Network 14 generates one distinct group of logical '1' out-put signals in response to a split of a bifurcation superimposed thereon.
The group of logical '1' signals is preceded and followed by logical - '0' signals.
Circuit 16 performs three functions, two of which are quite similar to that of circuit 18 previously discussed. Circuit 16 functions as a means for generating an output at line 80 indicative of the identifi-cation of one, and only one, distinct groups of signals indicative of a - split in a bifurcation. Secondly, circuit 16 operates to reject this group if it contains more than a predetermined number of logical '1' signals. Thirdly, the circuit functions to identify the particular quadrant of the periphery of matrix 14 from which the first signal in the group emanates.
The single leg identification function is performed by burst coun-ter 91 and decoder 92. Counter 91 generates an output in binary coded decimal form indicative of the number of groups of signals received from converter 15. Decoder 92 is responsive to outputs from burst counter 31. It has a single operative output line which generates an output signal only upon the incidence of a signal indicative of one group of signals.
The rejection feature is performed by M-count multivibrator 93 and gating elements which comprise inverters 94 and 97, AND gate 95 and FI9-73-060 - 13 - :
: . . . .. . . .. .
1038~98 , 1 latch 96. In the present embodiment it is desired to reject a group ofsignals which contains more than five pulses. This number of signals is selected to be the same as the number in N-count multivibrator 33 of FIG. 6. The number is more or less arbitrary and could be greater or lower depending upon the particular system involved. The cycle time of decision circuit 16 is sufficiently long to receive the forty-four sig-nals contained in converter 15 which stores the outputs of the peri-phery of network 14 and transmits the pulses in serial fashion along line 59 to logic circuit 16. Thus, a CLOCK SET line is provided at latch 36 to reset circuit 16 after 44 cycles. As with the clock of logic circuit 18 the system clock operates at a 1 MHz rate and converter 15 operates at a 44 MHz rate.
The quadrant identification function is performed by detector 98, counter 100 and decoder 101. Simultaneous signals received from detector 98 and decoder 101 at one of the four AND gates denoted by numeral 102 generate a signal indicative of the quadrant in which the split is ~ ;
located on one of lines T, S, R or Q.
The operation of SPLIT decision circuit 16 is illustrated by way of example in FIG. 9. Nodes E, F, G and H correspond to nodes A, B, C and D of the circuit in FIG. 6 and their associated circuits function in the same fashion. Node I at the output of leading edge d~tector 98 generates a pulse in response to the first of the pulse group of logical '1' signals received from converter 15. Divide-by-ll counter 100 generates an output to decoder 101 after each 11 signals from the 44 MHz clock. Thus the output of decoder 101 at nodes J, K, L and P
define a particular one of the four sides of quadrants of the periphery of network 14. The coincidence of a signal at node I and an output from decoder 101 gates one of the AND circuits 102 and thereby identifies the particular quadrant at which the split is located.
FIG. 9 illustrates two distinct cycles, each of which are one microsecond in length and each of which is divided into 44 subcycles con-trolled by the 44 MHz clock. In the first cycle a group of signals , . , . ~ .
1~38~9B
1 containing seven pulses is received from conyerter 15. As it is desired ~' to ignore more than five pulses in any group, ~-count multivibrator 93 is set to M=5. Upon the receipt of a first pulse in the group, multi-vibrator 93 generates five pulses, irrespective of the number of pulses in the group at node E. Inverter 94 inVerts the signal from multivi-brator 93 as shown at node F. Because the group of pulses contains seven pulses which is two more than the maximum allowed, there is a coincidence of logical '1' signals at AND gate 95, resulting in a posi-tive pulse at node G. Latch 96 is set to a logical '1' level, which is inverted by inverter 37 to a logical '0'. This causes the output from AND gate 99 to become a logical '0' during the one microsecond clock cycle. This causes the output on line 80 to AND gate 21 to be a logical '0', resulting in the rejection of the false impression of a split in a bifurcation.
During the operation of this first cycle an output pulse from leading edge detector 98 at node I coincides with the 1/4 microsecond pulse (11 subcycles) at node K from decoder 101 to generate an output pulse at line R. This pulse is transmitted via cable 79 to coordinate dis-criminator 19, the operation of which will be described more fully in a later section of this specification.
FIG. 9 also illustrates a second one microsecond interval in which ; a pulse group of four pulses is received from converter 15 which results in the generation of a positive output on line 80 to AND gate 21 and a second pulse on line R to discriminator 19. A more detailed descrip-tion of this cycle is considered to be unnecessary to those who have : read the preceding sections of this specification.
FIG. 10 shows the operative relationship between network 14 and discriminator 19. Discriminator 19 functions to insure that a parti-cular bifurcation will be detected in the system only once. Without discriminator 19 the same bifurcation could generate more than one signal from AND gate 21. In general, the continuity logic network -operates during each successive scanning interval to generate a signal . .
~038498 1 if the requisites of a bifurcation are met, i.e., three indiyidual paths between the source ~V and the periphery of the matrix. It will often happen that the bifurcation will be detected during a number of different scanning intervals due to the nature of the bifurcation sig-nal itself.
Referring specifically to FIG. 10, selected circuits of network 14 have outputs connected through cable 77 to OR gates which operate as inputs to discriminator 19. The outputs on cable 77 emanate from the AND gates of the circuits and are in addition to the outputs of ~he net-work previously described. These output lines form a cross pattern about the voltage source +V at the centre of the matrix 14 and, in conjunction with discriminator 1, function to block the recognition ~ -of a split in the bifurcation more than once.
The output pattern is divided into two separate columns and rows, each of which is connected to an individual one of OR gates 320-323.
The outputs of the OR gates are connected to inverters 325-328, respec-tively. AND gates 330-333 function to gate a signal from its associated inverter when a quadrant detect signal is received from logic circuit 16 on cabling 79. An output signal from one of the AND gates is fed to latch 336 where it is held in the logical '1' position and terminated at AND gate 21 in combination with the signals from logic circuits 16 and 18.
The operation of discriminator 19 can best be appreciated by referring to FIGS. lla, llb and llc, in conjunction with FIG. 10.
The figures illustrate the appearance of a split in the bifurca- :
tion at succeeding scan intervals on a network 14. The cross pattern - formed by the outputs to discriminator 19 is shown in dotted lines by numeral 13. It will be recalled at this point that the TV raster encom-- passes 350 dots and temporary memory 8 in FIG. 1 comprises 12 shift registers of 350 bits in length. Thus each scanning interYal is 350 microseconds.
In FIG. lla, a split in a bifurcation appears at the upper right .
:
103849~
1 hand corner of network 14 as illustrated by the ~illed in ~ots. ~owever, the split is not detected at this point because there is no connection between potential source +V at the centre of network 14 to the inputs received from shift registers 9. For a split to be detected, at least one of the matrix points adjacent to source +V must be energized by a signal from its associated location in shift register 9.
In FIG. llb the inputs from shift register 9 have been displaced one column to the left of the matrix, and the presence of the split is indi-cated by the logical '1' signals at the outputs on the upper right hand portion of network 14. Because the number of logical 'l's in that group does not exceed five, the presence of the split will be indicated by an output from split decision logic circuits 16 along line 80 to AND gate - 21 (FIG. 1). Logic circuit 16 also indicates to discriminator circuit 19 that the split is located in the upper portion of matrix 14 by gating AND gate 332 on line R of cable 79. Simultaneously OR gates 323 and 321 are activated because of the signals at their corresponding circuit locations in matrix 14. OR gates 320 and 322 are held at a 'O' level because there is no signal at their column and row outputs. The posi-tive signals at gates 321 and 323 are inverted by inverters 326 and 328 respectively to zero and the zero outputs from OR gates 320 and 322 are inverted to logical '1' signals. Because an indication of a shift has : been received at AND gate 332 on line R the signal from inverter 327 is gated through AND gate 322 through OR gate 335 to actuate latch 336 to a logical '1' output. Thus, at this point AND gate 21 receives an indi-cation of a bifurcation from discriminator 19 as well as from logic circuit 16.
In FIG. llc during the succeeding scanning interval the same ~ -split is superimposed on network 14 as indicated by the logical '1' outputs at the upper right hand portion of the matrix. However, the pattern at outputs to coordinate discr1minator 19 serves to block recog-nition of this split, because the output of OR gate 322 becomes a logical '1'. This signal is inverted to a logical 'O' in inverter 327 and - , , . - . . . , . ::: ,~
1 prevents the operation of AND gate 332. The split signals are shifted one column position in FIG. llc from that in FIG. llb. Thus, OR gate 322, which in the previous scan was not activated, is now activated to generate a '1' output to inverter 3?7. Inverter 327 generates an 'O' ,~
output to AND gate 322. Thus the signal on line R is not gated through gate 322 and the output from discriminator 19 is at a logical 'O' level.
This operation occurs irrespective of the quadrant on the matrix in which the split occurs due to the symmetry of pattern 13 and the circuits in discriminator 19.
. 10 In summary, we have invented a system which is capable of identify-ing the merger of lines. The specific embodiment described is for detecting bifurcations in fingerprints and is compatible with overall fingerprint identification or verification networks which involve cen-tral processing and storage units and data communication lines. The system features novel decision and recognition circuits. The basic building blocks of the circuits are constructed from commercially available components, many of which are presently available in inte-grated circuit for ease of fabrication, reliability and relatively low cost.
As previously noted, the system is also adaptable for recogniz-ing ridge endings as well as bifurcations. Ridge endings appear to the system as the negative of a bifurcation. Therefore, in adapting the system for this purpose, it is necessary only that the binary sig-nals be inverted before being processed, for example, between digitizer 5 and memory 8 in FIG. 1.
Although the invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example and that numerous changes in the details - of construction, the combination and arrangement of parts, may be made without departing from the spirit and the scope of the invention as hereinafter claimed.
For example, the coordinate discriminator pattern in FIG. 10 .
~3849B
1 comprises two rows and two columns of eight logic elements each, for defining the four quadrants of the matrix. However, fewer elements could be used depending on the sensitivity required. In a 12 x 12 continuity logic network, we have found that the eight-element cross pattern affords best results. This pattern operates to suppress bifur-cation indications in scanning intervals both preceding and succeeding the particular interval in which an output is generated from the discriminator to A;D gate 21.
- .. , . . : :- ........... , : ......... .
~. :: . . .: .'
Upon examination of FIG. 5, it will be readily apparent that the field effect transistors in each circuit element have a common input line at their gate electrodes. For purposes of the present system, the lQ38498 1 field effect transistors are enhancement mode N channel devices and the standard terminology of gate, source, and drain is used for descriptive purposes. As is well known to those of skill in the art, the difference between the source and drain of modern field effect transistors does not lie in the structure of the transistor itself but merely in the manner of biasing. In N channel device termino10gy the source is generally connected to the positive bias and the drain is generally connected to ~ ~ -a lower potential.
The correlation between the field effect transistor circuit in FIG. 5 and the logic circuit of FIG. 4 can be appreciated by referring specifically, for example, to circuit 2-2, as this represents the most complicated circuit in the matrix of logic circuits which comprise the continuity logic network.
The numbered inputs to OR gate 129 in FIG. 4 correspond to the identically numbered inputs to the source regions of transistors 306, 307, 308 and 309. The numbered outputs from AND gate 128 in FIG. 4 also correspond to the identically numbered outputs from the source regions.
Thus the source regions form a two way link between associated circuits.
There is one field effect transistor for each circuit which is associated with the circuit under consideration. Thus, circuit 2-2, --which has four circuits located adjacent and orthogonally with respect to it, contains four field effect transistorsi whereas circuits 1-2 and 1-1 contain three and two field effect transistors respectively because of their positions at the periphery of the matrix. The outputs at the periphery are taken from the common drain connections at circuits 1-1 -and 1-2 through load resistors 312 and 313, respectively, which have values of around 500 ohms. The resistors function to prevent the drain nodes from floating. In the operation of circuit 2-2, a positive sig-nal from shift register 12b on ljne 214 gates FET's 306-309. A posi-tive continuity signal ~V from one of the associated circuits 2-1, 1-3, 2-3 or 3-2 is then gated through the source of the associated FET 306, 307, 308 or 309, respectively. This signal is then available at the other .: .
1 FET sources to energize other circuits associated with circuit 2-2. If a signal is received by circuit 1-2 on line 202, the continuity signal from the +V continuity source appears at line 54b to be detected by logic circuit 18.
The FET configuration in FIG. S requires amplifier circuits at selected locations in the matrix to boost the signal level. However, their inclusion is a matter of design choice and is omitted for ease of illustration.
Turning now to FIG. 6 and 7, TRI-LEG decision logic circuit 18 is shown in more detail in conjunction with a timing diagram of waveforms generated within the circuit responsive to the outputs from continuity logic network 14'. As previously discussed, a bifurcation superimposed on network 14' generates a set of three distinct groups of logical '1' output signals. Each such group is separated by at least one logical '0' signal.
Circuit 18 performs two functions. Primarily it functions as a means for generating an output at line 82 indicative of the identifi-cation of three and only three distinct groups of signals indicative of a bifurcation. In addition, circuit 18 operates to reject any set of three groups in which any single group of signals contains more than a predetermined number of logical '1' signals. This latter function is a noise check to eliminate the results of a blurred impression or other imperfections generated from network 14'.
The primary three-leg identification function is performed by burst counter 31 and decoder 32. Counter 31 generates outputs in binary coded decimal form depending on the number of group of signals received from converter 17. Decoder 32 is responsive to the outputs from burst counter 31 and has a single operative output line which generates an output signal only upon the incidence a signal indicative of three groups of signals.
The aforementioned rejection feature is performed by N-count multi-vibrator 33 and gating elements which comprise inverters 34 and 37, AND
.
.
~0384~8 1 gate 35 and latch 36. In the present embodiment it is desired to reject a set in which any group contains more than five pulses. The cycle time ;
of decision circuit 18 is sufficiently long to receive the forty-four signals contained in converter 17 which stores the outputs of the peri-phery of network 14' and transmits the pulses in serial fashion along line 58 to logic circuit 18. Thus a CLOCK SET line is provided at latch j 36 to reset circuit 18 after 44 cycles. Converter 15 must be designed to operate at a much faster rate than the remainder of the system. In the preferred embodiment, the system clock operates at a 1 MHz rate and converter 15 operates at a 44 MHz rate.
It is noted at this point that each of the circuits illustrated in block 18 is well known to those of skill in the art and commercially available. The operation of the reject circuitry is illustrated by way of example in FIG. 7. A set of three groups of signals is trans-mitted from converter 17 to decision circuit 18. The groups contain four, five and six pulses respectively. As previously mentioned, it is desired to ignore more than five pulses in any group; therefore N-count multivibrator 36 is set to N = 5. Upon the receipt of a first pulse in the first group, multivibrator 33 generates five pulses irrespective of the number of pulses in the group at node A. Inverter 34 inverts the signal from multivibrator 33 as shown at node B. Because node B is at a down, or logical 'O' level, AND gate 35 generates a down level output at node C, thereby holding latch 36 to a negative level. The negative ~-~
level of latch 36 is inverted at inverter 38 to a true or logical '1' level. Upon the receipt of an indication of three distinct groups from decoder 32, AND gate 38 is activated and generates a logical '1' signal on line 82 during the clock cycle.
As shown in FIG. 7 a similar action occurs for the second group which consists of five signals from converter 17. The third group of pulses, however, contains six pulses which is one more than the maximum allowed. In this event there is a coincidence of logical '1' signals at AND gate 35, thereby setting latch 36 to an up or logical '1' level.
: :-.
. '' ' ' - ' : ~ ' : .
~0384~8 1 Inverter 37 inverts the signal to a down level or logical '0', causing the output from AND gate 38 to become a logical '0' during the 1 micro-` second clock cyc1e. This causes the output on line 82 to AND gate 21 to be a logical '0' and results in the rejection of the false impression of a bifurcation.
A Decision at gate 21 is made only at the end of each 44 subcycles.
Hence, the set of pulses from converter 17 would be rejected ln toto.
Referring now to FIGS. 8 and 9, SPLIT decision logic circuit 16 is illustrated in conjunction with a timing diagram of wave forms generated within the circuit responsive to the outputs from continuity logic net-work 14. Network 14 generates one distinct group of logical '1' out-put signals in response to a split of a bifurcation superimposed thereon.
The group of logical '1' signals is preceded and followed by logical - '0' signals.
Circuit 16 performs three functions, two of which are quite similar to that of circuit 18 previously discussed. Circuit 16 functions as a means for generating an output at line 80 indicative of the identifi-cation of one, and only one, distinct groups of signals indicative of a - split in a bifurcation. Secondly, circuit 16 operates to reject this group if it contains more than a predetermined number of logical '1' signals. Thirdly, the circuit functions to identify the particular quadrant of the periphery of matrix 14 from which the first signal in the group emanates.
The single leg identification function is performed by burst coun-ter 91 and decoder 92. Counter 91 generates an output in binary coded decimal form indicative of the number of groups of signals received from converter 15. Decoder 92 is responsive to outputs from burst counter 31. It has a single operative output line which generates an output signal only upon the incidence of a signal indicative of one group of signals.
The rejection feature is performed by M-count multivibrator 93 and gating elements which comprise inverters 94 and 97, AND gate 95 and FI9-73-060 - 13 - :
: . . . .. . . .. .
1038~98 , 1 latch 96. In the present embodiment it is desired to reject a group ofsignals which contains more than five pulses. This number of signals is selected to be the same as the number in N-count multivibrator 33 of FIG. 6. The number is more or less arbitrary and could be greater or lower depending upon the particular system involved. The cycle time of decision circuit 16 is sufficiently long to receive the forty-four sig-nals contained in converter 15 which stores the outputs of the peri-phery of network 14 and transmits the pulses in serial fashion along line 59 to logic circuit 16. Thus, a CLOCK SET line is provided at latch 36 to reset circuit 16 after 44 cycles. As with the clock of logic circuit 18 the system clock operates at a 1 MHz rate and converter 15 operates at a 44 MHz rate.
The quadrant identification function is performed by detector 98, counter 100 and decoder 101. Simultaneous signals received from detector 98 and decoder 101 at one of the four AND gates denoted by numeral 102 generate a signal indicative of the quadrant in which the split is ~ ;
located on one of lines T, S, R or Q.
The operation of SPLIT decision circuit 16 is illustrated by way of example in FIG. 9. Nodes E, F, G and H correspond to nodes A, B, C and D of the circuit in FIG. 6 and their associated circuits function in the same fashion. Node I at the output of leading edge d~tector 98 generates a pulse in response to the first of the pulse group of logical '1' signals received from converter 15. Divide-by-ll counter 100 generates an output to decoder 101 after each 11 signals from the 44 MHz clock. Thus the output of decoder 101 at nodes J, K, L and P
define a particular one of the four sides of quadrants of the periphery of network 14. The coincidence of a signal at node I and an output from decoder 101 gates one of the AND circuits 102 and thereby identifies the particular quadrant at which the split is located.
FIG. 9 illustrates two distinct cycles, each of which are one microsecond in length and each of which is divided into 44 subcycles con-trolled by the 44 MHz clock. In the first cycle a group of signals , . , . ~ .
1~38~9B
1 containing seven pulses is received from conyerter 15. As it is desired ~' to ignore more than five pulses in any group, ~-count multivibrator 93 is set to M=5. Upon the receipt of a first pulse in the group, multi-vibrator 93 generates five pulses, irrespective of the number of pulses in the group at node E. Inverter 94 inVerts the signal from multivi-brator 93 as shown at node F. Because the group of pulses contains seven pulses which is two more than the maximum allowed, there is a coincidence of logical '1' signals at AND gate 95, resulting in a posi-tive pulse at node G. Latch 96 is set to a logical '1' level, which is inverted by inverter 37 to a logical '0'. This causes the output from AND gate 99 to become a logical '0' during the one microsecond clock cycle. This causes the output on line 80 to AND gate 21 to be a logical '0', resulting in the rejection of the false impression of a split in a bifurcation.
During the operation of this first cycle an output pulse from leading edge detector 98 at node I coincides with the 1/4 microsecond pulse (11 subcycles) at node K from decoder 101 to generate an output pulse at line R. This pulse is transmitted via cable 79 to coordinate dis-criminator 19, the operation of which will be described more fully in a later section of this specification.
FIG. 9 also illustrates a second one microsecond interval in which ; a pulse group of four pulses is received from converter 15 which results in the generation of a positive output on line 80 to AND gate 21 and a second pulse on line R to discriminator 19. A more detailed descrip-tion of this cycle is considered to be unnecessary to those who have : read the preceding sections of this specification.
FIG. 10 shows the operative relationship between network 14 and discriminator 19. Discriminator 19 functions to insure that a parti-cular bifurcation will be detected in the system only once. Without discriminator 19 the same bifurcation could generate more than one signal from AND gate 21. In general, the continuity logic network -operates during each successive scanning interval to generate a signal . .
~038498 1 if the requisites of a bifurcation are met, i.e., three indiyidual paths between the source ~V and the periphery of the matrix. It will often happen that the bifurcation will be detected during a number of different scanning intervals due to the nature of the bifurcation sig-nal itself.
Referring specifically to FIG. 10, selected circuits of network 14 have outputs connected through cable 77 to OR gates which operate as inputs to discriminator 19. The outputs on cable 77 emanate from the AND gates of the circuits and are in addition to the outputs of ~he net-work previously described. These output lines form a cross pattern about the voltage source +V at the centre of the matrix 14 and, in conjunction with discriminator 1, function to block the recognition ~ -of a split in the bifurcation more than once.
The output pattern is divided into two separate columns and rows, each of which is connected to an individual one of OR gates 320-323.
The outputs of the OR gates are connected to inverters 325-328, respec-tively. AND gates 330-333 function to gate a signal from its associated inverter when a quadrant detect signal is received from logic circuit 16 on cabling 79. An output signal from one of the AND gates is fed to latch 336 where it is held in the logical '1' position and terminated at AND gate 21 in combination with the signals from logic circuits 16 and 18.
The operation of discriminator 19 can best be appreciated by referring to FIGS. lla, llb and llc, in conjunction with FIG. 10.
The figures illustrate the appearance of a split in the bifurca- :
tion at succeeding scan intervals on a network 14. The cross pattern - formed by the outputs to discriminator 19 is shown in dotted lines by numeral 13. It will be recalled at this point that the TV raster encom-- passes 350 dots and temporary memory 8 in FIG. 1 comprises 12 shift registers of 350 bits in length. Thus each scanning interYal is 350 microseconds.
In FIG. lla, a split in a bifurcation appears at the upper right .
:
103849~
1 hand corner of network 14 as illustrated by the ~illed in ~ots. ~owever, the split is not detected at this point because there is no connection between potential source +V at the centre of network 14 to the inputs received from shift registers 9. For a split to be detected, at least one of the matrix points adjacent to source +V must be energized by a signal from its associated location in shift register 9.
In FIG. llb the inputs from shift register 9 have been displaced one column to the left of the matrix, and the presence of the split is indi-cated by the logical '1' signals at the outputs on the upper right hand portion of network 14. Because the number of logical 'l's in that group does not exceed five, the presence of the split will be indicated by an output from split decision logic circuits 16 along line 80 to AND gate - 21 (FIG. 1). Logic circuit 16 also indicates to discriminator circuit 19 that the split is located in the upper portion of matrix 14 by gating AND gate 332 on line R of cable 79. Simultaneously OR gates 323 and 321 are activated because of the signals at their corresponding circuit locations in matrix 14. OR gates 320 and 322 are held at a 'O' level because there is no signal at their column and row outputs. The posi-tive signals at gates 321 and 323 are inverted by inverters 326 and 328 respectively to zero and the zero outputs from OR gates 320 and 322 are inverted to logical '1' signals. Because an indication of a shift has : been received at AND gate 332 on line R the signal from inverter 327 is gated through AND gate 322 through OR gate 335 to actuate latch 336 to a logical '1' output. Thus, at this point AND gate 21 receives an indi-cation of a bifurcation from discriminator 19 as well as from logic circuit 16.
In FIG. llc during the succeeding scanning interval the same ~ -split is superimposed on network 14 as indicated by the logical '1' outputs at the upper right hand portion of the matrix. However, the pattern at outputs to coordinate discr1minator 19 serves to block recog-nition of this split, because the output of OR gate 322 becomes a logical '1'. This signal is inverted to a logical 'O' in inverter 327 and - , , . - . . . , . ::: ,~
1 prevents the operation of AND gate 332. The split signals are shifted one column position in FIG. llc from that in FIG. llb. Thus, OR gate 322, which in the previous scan was not activated, is now activated to generate a '1' output to inverter 3?7. Inverter 327 generates an 'O' ,~
output to AND gate 322. Thus the signal on line R is not gated through gate 322 and the output from discriminator 19 is at a logical 'O' level.
This operation occurs irrespective of the quadrant on the matrix in which the split occurs due to the symmetry of pattern 13 and the circuits in discriminator 19.
. 10 In summary, we have invented a system which is capable of identify-ing the merger of lines. The specific embodiment described is for detecting bifurcations in fingerprints and is compatible with overall fingerprint identification or verification networks which involve cen-tral processing and storage units and data communication lines. The system features novel decision and recognition circuits. The basic building blocks of the circuits are constructed from commercially available components, many of which are presently available in inte-grated circuit for ease of fabrication, reliability and relatively low cost.
As previously noted, the system is also adaptable for recogniz-ing ridge endings as well as bifurcations. Ridge endings appear to the system as the negative of a bifurcation. Therefore, in adapting the system for this purpose, it is necessary only that the binary sig-nals be inverted before being processed, for example, between digitizer 5 and memory 8 in FIG. 1.
Although the invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example and that numerous changes in the details - of construction, the combination and arrangement of parts, may be made without departing from the spirit and the scope of the invention as hereinafter claimed.
For example, the coordinate discriminator pattern in FIG. 10 .
~3849B
1 comprises two rows and two columns of eight logic elements each, for defining the four quadrants of the matrix. However, fewer elements could be used depending on the sensitivity required. In a 12 x 12 continuity logic network, we have found that the eight-element cross pattern affords best results. This pattern operates to suppress bifur-cation indications in scanning intervals both preceding and succeeding the particular interval in which an output is generated from the discriminator to A;D gate 21.
- .. , . . : :- ........... , : ......... .
~. :: . . .: .'
Claims (4)
1. A system for recognizing the merger of two lines in a pattern consisting of lines and spaces between lines comprising:
scanning means for scanning said pattern;
means for converting the output of said scanning means into binary signals representative of the contrast between said lines and said spaces;
continuity logic means including a matrix of logic elements operative in response to said binary signals for forming conductive paths corres-ponding to the contrast between said lines and spaces;
means connected to said continuity logic means and responsive to said conductive paths for providing an indication of a merger of two lines;
and discriminator means connected to said con-tinuity logic means for ensuring that a particular merger is identified only once.
scanning means for scanning said pattern;
means for converting the output of said scanning means into binary signals representative of the contrast between said lines and said spaces;
continuity logic means including a matrix of logic elements operative in response to said binary signals for forming conductive paths corres-ponding to the contrast between said lines and spaces;
means connected to said continuity logic means and responsive to said conductive paths for providing an indication of a merger of two lines;
and discriminator means connected to said con-tinuity logic means for ensuring that a particular merger is identified only once.
2. A system as in Claim 1 wherein said discriminator means is connected to the outputs of selected ones of said logic elements and is operative during each scanning interval for suppressing an indication of a merger sensed by said indication means during another scanning interval.
3. A system as in Claim 2 further including:
a source of a continuity signal connected to the inputs of the four logic elements which comprise the center of said matrix; and wherein said selected ones of logic elements include said centrally located elements.
a source of a continuity signal connected to the inputs of the four logic elements which comprise the center of said matrix; and wherein said selected ones of logic elements include said centrally located elements.
4. A system as in Claim 3 further comprising:
means for identifying the quadrant location of a particular merger in said matrix; and wherein said discriminator means comprises;
first gating means connected to said selected logic elements for transmitting a signal indicative of a conductive path during a scanning interval and for blocking said conductive path signal during other scanning intervals; and second gating means responsive to the coinci-dence of said quadrant identifying signal and a conductive path signal from said first gating means for gating only one signal for each particular merger.
means for identifying the quadrant location of a particular merger in said matrix; and wherein said discriminator means comprises;
first gating means connected to said selected logic elements for transmitting a signal indicative of a conductive path during a scanning interval and for blocking said conductive path signal during other scanning intervals; and second gating means responsive to the coinci-dence of said quadrant identifying signal and a conductive path signal from said first gating means for gating only one signal for each particular merger.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US375191A US3859633A (en) | 1973-06-29 | 1973-06-29 | Minutiae recognition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1038498A true CA1038498A (en) | 1978-09-12 |
Family
ID=23479872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA203,050A Expired CA1038498A (en) | 1973-06-29 | 1974-06-21 | Minutiae recognition system with means to detect merger of lines only once |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US3859633A (en) |
| CA (1) | CA1038498A (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4210899A (en) * | 1975-06-23 | 1980-07-01 | Fingermatrix, Inc. | Fingerprint-based access control and identification apparatus |
| US4083035A (en) * | 1976-09-10 | 1978-04-04 | Rockwell International Corporation | Binary image minutiae detector |
| SE425704B (en) * | 1981-03-18 | 1982-10-25 | Loefberg Bo | DATABERARE |
| US4541113A (en) * | 1983-01-19 | 1985-09-10 | Seufert Wolf D | Apparatus and method of line pattern analysis |
| US4547898A (en) * | 1983-03-11 | 1985-10-15 | Siemens Corporate Research & Support, Inc. | Apparatus for determining the two-dimensional connectivity of a prescribed binary variable associated with a surface |
| US5878158A (en) * | 1995-05-10 | 1999-03-02 | Ferris; Stephen G. | Ridge-valley minutia associator for fingerprints |
| US6049620A (en) | 1995-12-15 | 2000-04-11 | Veridicom, Inc. | Capacitive fingerprint sensor with adjustable gain |
| US5841888A (en) | 1996-01-23 | 1998-11-24 | Harris Corporation | Method for fingerprint indexing and searching |
| US5963679A (en) * | 1996-01-26 | 1999-10-05 | Harris Corporation | Electric field fingerprint sensor apparatus and related methods |
| US5828773A (en) * | 1996-01-26 | 1998-10-27 | Harris Corporation | Fingerprint sensing method with finger position indication |
| US5956415A (en) * | 1996-01-26 | 1999-09-21 | Harris Corporation | Enhanced security fingerprint sensor package and related methods |
| KR100323679B1 (en) * | 1999-03-26 | 2002-02-07 | 구자홍 | Apparatus and Method for auto channel serching of TV |
| US6785408B1 (en) | 1999-05-11 | 2004-08-31 | Authentic, Inc. | Fingerprint segment area processing method and associated apparatus |
| US7284266B1 (en) * | 2000-03-21 | 2007-10-16 | Broadcom Corporation | System and method for secure biometric identification |
| US6910132B1 (en) | 2000-09-15 | 2005-06-21 | Matsushita Electric Industrial Co., Ltd. | Secure system and method for accessing files in computers using fingerprints |
| KR100432491B1 (en) | 2001-08-31 | 2004-05-22 | (주)니트 젠 | Method of extracting fingerprint features using ridge direction model |
| US7321667B2 (en) * | 2002-01-18 | 2008-01-22 | Digimarc Corporation | Data hiding through arrangement of objects |
| US20050063562A1 (en) * | 2003-08-07 | 2005-03-24 | Brunk Hugh L. | Conveying fingerprint minutiae with digital watermarks |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2952181A (en) * | 1956-12-31 | 1960-09-13 | Jr John Andrew Maurer | Method of and apparatus for automatic identification of finger prints |
| DE1065198B (en) * | 1957-04-17 | 1959-09-10 | Standard Elektrik Lorenz Aktiengesellschaft, Stuttgart-Zuflenhausen | Method and arrangement for the automatic recognition of characters, in particular characters (digits, letters, etc.) |
| US3248552A (en) * | 1962-09-25 | 1966-04-26 | Philco Corp | Photosensitive optical logic unit for use in a computer system |
| US3558864A (en) * | 1965-12-29 | 1971-01-26 | Ibm | Reference point determining system |
| US3511571A (en) * | 1966-02-28 | 1970-05-12 | Hugh Malcolm Ogle | Method and apparatus for comparing patterns |
| US3588818A (en) * | 1967-07-07 | 1971-06-28 | Ncr Co | Character recognition system employing continuity detection and registration means |
| US3611290A (en) * | 1968-06-03 | 1971-10-05 | North American Rockwell | Fingerprint minutiae reading device |
| US3613080A (en) * | 1968-11-08 | 1971-10-12 | Scan Data Corp | Character recognition system utilizing feature extraction |
| US3537070A (en) * | 1969-03-04 | 1970-10-27 | Ibm | Apparatus for pattern recognition |
| US3582889A (en) * | 1969-09-04 | 1971-06-01 | Cit Alcatel | Device for identifying a fingerprint pattern |
| US3699519A (en) * | 1971-04-30 | 1972-10-17 | North American Rockwell | Fingerprint analysis device |
-
1973
- 1973-06-29 US US375191A patent/US3859633A/en not_active Expired - Lifetime
-
1974
- 1974-06-21 CA CA203,050A patent/CA1038498A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3859633A (en) | 1975-01-07 |
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